From 31b934e2ed174e56ebfde0638d644226369120bf Mon Sep 17 00:00:00 2001 From: CarolineConcatto Date: Tue, 20 Oct 2026 13:55:50 +0000 Subject: [PATCH 1/2] Add ACLE intrinsics for non-temporal pair loads/stores Add ACLE intrinsics for: LDNP[1]/STNP[2] non-temporal pairs. These instructions are not part of FEAT_LSUI. The 128-bit instruction forms are proposed using Neon vector types because there are no scalar arithmetic instructions with a 128-bit scalar data type. A scalar 128-bit floating-point type is not consistently available across AArch64 targets. For example, long double is 64-bit on Darwin and Windows AArch64 targets. References: [1]https://support.arm.com/documentation/ddi0602/2026-09/SIMD-FP-Instructions/LDNP--SIMD-FP---Load-pair-of-SIMD-FP-registers--with-non-temporal-hint-?lang=en [2]https://support.arm.com/documentation/ddi0602/2026-09/SIMD-FP-Instructions/STNP--SIMD-FP---Store-pair-of-SIMD-FP-registers--with-non-temporal-hint-?lang=en --- neon_intrinsics/advsimd.md | 51 +++++++++++++++++++ neon_intrinsics/advsimd.template.md | 1 + tools/intrinsic_db/advsimd.csv | 39 ++++++++++++++ tools/intrinsic_db/advsimd_classification.csv | 38 ++++++++++++++ 4 files changed, 129 insertions(+) diff --git a/neon_intrinsics/advsimd.md b/neon_intrinsics/advsimd.md index b44f4769..68209659 100644 --- a/neon_intrinsics/advsimd.md +++ b/neon_intrinsics/advsimd.md @@ -118,6 +118,7 @@ See [Changelog for year 2026](#changelog-for-year-2026). ### Changelog for year 2026 +* Added proposed support for LDNP/STNP intrinsics. * Added support for FEAT_F16F32DOT * Added support for FEAT_F16F32MM and FEAT_F16MM * Renamed vmmlaq_f16_f16 to vmmlaq_f16 @@ -3829,6 +3830,31 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``. ### Load +#### Non-temporal pair + + +| Intrinsic | Argument preparation | AArch64 Instruction | Result | Supported architectures | +|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------|---------------------------------|---------------------------------------------------------------------------------------------------------------------|---------------------------| +| int32x2_t vldn_s32_x2(
     int32_t const *ptr) | `ptr -> Xn` | `LDNP Wt1,Wt2,[Xn]` | `Wt1/Wt2 -> result[0]/result[1]` | `A64` | +| uint32x2_t vldn_u32_x2(
     uint32_t const *ptr) | `ptr -> Xn` | `LDNP Wt1,Wt2,[Xn]` | `Wt1/Wt2 -> result[0]/result[1]` | `A64` | +| float32x2_t vldn_f32_x2(
     float32_t const *ptr) | `ptr -> Xn` | `LDNP Wt1,Wt2,[Xn]` | `Wt1/Wt2 -> result[0]/result[1]` | `A64` | +| int64x2_t vldn_s64_x2(
     int64_t const *ptr) | `ptr -> Xn` | `LDNP Xt1,Xt2,[Xn]` | `Xt1/Xt2 -> result[0]/result[1]` | `A64` | +| uint64x2_t vldn_u64_x2(
     uint64_t const *ptr) | `ptr -> Xn` | `LDNP Xt1,Xt2,[Xn]` | `Xt1/Xt2 -> result[0]/result[1]` | `A64` | +| float64x2_t vldn_f64_x2(
     float64_t const *ptr) | `ptr -> Xn` | `LDNP Xt1,Xt2,[Xn]` | `Xt1/Xt2 -> result[0]/result[1]` | `A64` | +| int8x16x2_t vldnq_s8_x2(
     int8_t const *ptr) | `ptr -> Xn` | `LDNP Qt1,Qt2,[Xn]` | `Qt1/Qt2 -> result.val[0]/result.val[1]` | `A64` | +| int16x8x2_t vldnq_s16_x2(
     int16_t const *ptr) | `ptr -> Xn` | `LDNP Qt1,Qt2,[Xn]` | `Qt1/Qt2 -> result.val[0]/result.val[1]` | `A64` | +| int32x4x2_t vldnq_s32_x2(
     int32_t const *ptr) | `ptr -> Xn` | `LDNP Qt1,Qt2,[Xn]` | `Qt1/Qt2 -> result.val[0]/result.val[1]` | `A64` | +| int64x2x2_t vldnq_s64_x2(
     int64_t const *ptr) | `ptr -> Xn` | `LDNP Qt1,Qt2,[Xn]` | `Qt1/Qt2 -> result.val[0]/result.val[1]` | `A64` | +| uint8x16x2_t vldnq_u8_x2(
     uint8_t const *ptr) | `ptr -> Xn` | `LDNP Qt1,Qt2,[Xn]` | `Qt1/Qt2 -> result.val[0]/result.val[1]` | `A64` | +| uint16x8x2_t vldnq_u16_x2(
     uint16_t const *ptr) | `ptr -> Xn` | `LDNP Qt1,Qt2,[Xn]` | `Qt1/Qt2 -> result.val[0]/result.val[1]` | `A64` | +| uint32x4x2_t vldnq_u32_x2(
     uint32_t const *ptr) | `ptr -> Xn` | `LDNP Qt1,Qt2,[Xn]` | `Qt1/Qt2 -> result.val[0]/result.val[1]` | `A64` | +| uint64x2x2_t vldnq_u64_x2(
     uint64_t const *ptr) | `ptr -> Xn` | `LDNP Qt1,Qt2,[Xn]` | `Qt1/Qt2 -> result.val[0]/result.val[1]` | `A64` | +| float16x8x2_t vldnq_f16_x2(
     float16_t const *ptr) | `ptr -> Xn` | `LDNP Qt1,Qt2,[Xn]` | `Qt1/Qt2 -> result.val[0]/result.val[1]` | `A64` | +| bfloat16x8x2_t vldnq_bf16_x2(
     bfloat16_t const *ptr) | `ptr -> Xn` | `LDNP Qt1,Qt2,[Xn]` | `Qt1/Qt2 -> result.val[0]/result.val[1]` | `A64` | +| float32x4x2_t vldnq_f32_x2(
     float32_t const *ptr) | `ptr -> Xn` | `LDNP Qt1,Qt2,[Xn]` | `Qt1/Qt2 -> result.val[0]/result.val[1]` | `A64` | +| float64x2x2_t vldnq_f64_x2(
     float64_t const *ptr) | `ptr -> Xn` | `LDNP Qt1,Qt2,[Xn]` | `Qt1/Qt2 -> result.val[0]/result.val[1]` | `A64` | +| mfloat8x16x2_t vldnq_mf8_x2(
     mfloat8_t const *ptr) | `ptr -> Xn` | `LDNP Qt1,Qt2,[Xn]` | `Qt1/Qt2 -> result.val[0]/result.val[1]` | `A64` | + #### Stride | Intrinsic | Argument preparation | AArch64 Instruction | Result | Supported architectures | @@ -4308,6 +4334,31 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``. ### Store +#### Non-temporal pair + +| Intrinsic | Argument preparation | AArch64 Instruction | Result | Supported architectures | +|-----------|----------------------|---------------------|--------|-------------------------| +| void vstn_s32_x2(
     int32_t *ptr,
     int32x2_t val) | `val[0]/val[1] -> Wt1/Wt2`
`ptr -> Xn` | `STNP Wt1,Wt2,[Xn]` | | `A64` | +| void vstn_u32_x2(
     uint32_t *ptr,
     uint32x2_t val) | `val[0]/val[1] -> Wt1/Wt2`
`ptr -> Xn` | `STNP Wt1,Wt2,[Xn]` | | `A64` | +| void vstn_f32_x2(
     float32_t *ptr,
     float32x2_t val) | `val[0]/val[1] -> Wt1/Wt2`
`ptr -> Xn` | `STNP Wt1,Wt2,[Xn]` | | `A64` | +| void vstn_s64_x2(
     int64_t *ptr,
     int64x2_t val) | `val[0]/val[1] -> Xt1/Xt2`
`ptr -> Xn` | `STNP Xt1,Xt2,[Xn]` | | `A64` | +| void vstn_u64_x2(
     uint64_t *ptr,
     uint64x2_t val) | `val[0]/val[1] -> Xt1/Xt2`
`ptr -> Xn` | `STNP Xt1,Xt2,[Xn]` | | `A64` | +| void vstn_f64_x2(
     float64_t *ptr,
     float64x2_t val) | `val[0]/val[1] -> Xt1/Xt2`
`ptr -> Xn` | `STNP Xt1,Xt2,[Xn]` | | `A64` | +| void vstnq_s8_x2(
     int8_t *ptr,
     int8x16x2_t val) | `val.val[0]/val.val[1] -> Qt1/Qt2`
`ptr -> Xn` | `STNP Qt1,Qt2,[Xn]` | | `A64` | +| void vstnq_s16_x2(
     int16_t *ptr,
     int16x8x2_t val) | `val.val[0]/val.val[1] -> Qt1/Qt2`
`ptr -> Xn` | `STNP Qt1,Qt2,[Xn]` | | `A64` | +| void vstnq_s32_x2(
     int32_t *ptr,
     int32x4x2_t val) | `val.val[0]/val.val[1] -> Qt1/Qt2`
`ptr -> Xn` | `STNP Qt1,Qt2,[Xn]` | | `A64` | +| void vstnq_s64_x2(
     int64_t *ptr,
     int64x2x2_t val) | `val.val[0]/val.val[1] -> Qt1/Qt2`
`ptr -> Xn` | `STNP Qt1,Qt2,[Xn]` | | `A64` | +| void vstnq_u8_x2(
     uint8_t *ptr,
     uint8x16x2_t val) | `val.val[0]/val.val[1] -> Qt1/Qt2`
`ptr -> Xn` | `STNP Qt1,Qt2,[Xn]` | | `A64` | +| void vstnq_u16_x2(
     uint16_t *ptr,
     uint16x8x2_t val) | `val.val[0]/val.val[1] -> Qt1/Qt2`
`ptr -> Xn` | `STNP Qt1,Qt2,[Xn]` | | `A64` | +| void vstnq_u32_x2(
     uint32_t *ptr,
     uint32x4x2_t val) | `val.val[0]/val.val[1] -> Qt1/Qt2`
`ptr -> Xn` | `STNP Qt1,Qt2,[Xn]` | | `A64` | +| void vstnq_u64_x2(
     uint64_t *ptr,
     uint64x2x2_t val) | `val.val[0]/val.val[1] -> Qt1/Qt2`
`ptr -> Xn` | `STNP Qt1,Qt2,[Xn]` | | `A64` | +| void vstnq_f16_x2(
     float16_t *ptr,
     float16x8x2_t val) | `val.val[0]/val.val[1] -> Qt1/Qt2`
`ptr -> Xn` | `STNP Qt1,Qt2,[Xn]` | | `A64` | +| void vstnq_bf16_x2(
     bfloat16_t *ptr,
     bfloat16x8x2_t val) | `val.val[0]/val.val[1] -> Qt1/Qt2`
`ptr -> Xn` | `STNP Qt1,Qt2,[Xn]` | | `A64` | +| void vstnq_f32_x2(
     float32_t *ptr,
     float32x4x2_t val) | `val.val[0]/val.val[1] -> Qt1/Qt2`
`ptr -> Xn` | `STNP Qt1,Qt2,[Xn]` | | `A64` | +| void vstnq_f64_x2(
     float64_t *ptr,
     float64x2x2_t val) | `val.val[0]/val.val[1] -> Qt1/Qt2`
`ptr -> Xn` | `STNP Qt1,Qt2,[Xn]` | | `A64` | +| void vstnq_mf8_x2(
     mfloat8_t *ptr,
     mfloat8x16x2_t val) | `val.val[0]/val.val[1] -> Qt1/Qt2`
`ptr -> Xn` | `STNP Qt1,Qt2,[Xn]` | | `A64` | + + #### Stride | Intrinsic | Argument preparation | AArch64 Instruction | Result | Supported architectures | diff --git a/neon_intrinsics/advsimd.template.md b/neon_intrinsics/advsimd.template.md index 45fee375..5df0afbb 100644 --- a/neon_intrinsics/advsimd.template.md +++ b/neon_intrinsics/advsimd.template.md @@ -118,6 +118,7 @@ See [Changelog for year 2026](#changelog-for-year-2026). ### Changelog for year 2026 +* Added proposed support for LDNP/STNP intrinsics. * Added support for FEAT_F16F32DOT * Added support for FEAT_F16F32MM and FEAT_F16MM * Renamed vmmlaq_f16_f16 to vmmlaq_f16 diff --git a/tools/intrinsic_db/advsimd.csv b/tools/intrinsic_db/advsimd.csv index d5bac768..cf81a1b9 100644 --- a/tools/intrinsic_db/advsimd.csv +++ b/tools/intrinsic_db/advsimd.csv @@ -4863,3 +4863,42 @@ float32x4_t vmmlaq_f32_f16(float32x4_t r, float16x8_t a, float16x8_t b) r -> Vd.
Non-widening half-precision matrix multiply instruction. Requires the +f16mm architecture extension. float16x8_t vmmlaq_f16(float16x8_t r, float16x8_t a, float16x8_t b) r -> Vd.8H;a -> Vn.8H;b -> Vm.8H FMMLA Vd.8H, Vn.8H, Vm.8H Vd.8H -> result A64 +
Non-temporal pair load and store intrinsics +int32x2_t vldn_s32_x2(int32_t const *ptr) ptr -> Xn LDNP Wt1,Wt2,[Xn] Wt2 -> result[1];Wt1 -> result[0] A64 +uint32x2_t vldn_u32_x2(uint32_t const *ptr) ptr -> Xn LDNP Wt1,Wt2,[Xn] Wt2 -> result[1];Wt1 -> result[0] A64 +float32x2_t vldn_f32_x2(float32_t const *ptr) ptr -> Xn LDNP Wt1,Wt2,[Xn] Wt2 -> result[1];Wt1 -> result[0] A64 +int64x2_t vldn_s64_x2(int64_t const *ptr) ptr -> Xn LDNP Xt1,Xt2,[Xn] Xt2 -> result[1];Xt1 -> result[0] A64 +uint64x2_t vldn_u64_x2(uint64_t const *ptr) ptr -> Xn LDNP Xt1,Xt2,[Xn] Xt2 -> result[1];Xt1 -> result[0] A64 +float64x2_t vldn_f64_x2(float64_t const *ptr) ptr -> Xn LDNP Xt1,Xt2,[Xn] Xt2 -> result[1];Xt1 -> result[0] A64 +int8x16x2_t vldnq_s8_x2(int8_t const *ptr) ptr -> Xn LDNP Qt1,Qt2,[Xn] Qt2 -> result.val[1];Qt1 -> result.val[0] A64 +int16x8x2_t vldnq_s16_x2(int16_t const *ptr) ptr -> Xn LDNP Qt1,Qt2,[Xn] Qt2 -> result.val[1];Qt1 -> result.val[0] A64 +int32x4x2_t vldnq_s32_x2(int32_t const *ptr) ptr -> Xn LDNP Qt1,Qt2,[Xn] Qt2 -> result.val[1];Qt1 -> result.val[0] A64 +int64x2x2_t vldnq_s64_x2(int64_t const *ptr) ptr -> Xn LDNP Qt1,Qt2,[Xn] Qt2 -> result.val[1];Qt1 -> result.val[0] A64 +uint8x16x2_t vldnq_u8_x2(uint8_t const *ptr) ptr -> Xn LDNP Qt1,Qt2,[Xn] Qt2 -> result.val[1];Qt1 -> result.val[0] A64 +uint16x8x2_t vldnq_u16_x2(uint16_t const *ptr) ptr -> Xn LDNP Qt1,Qt2,[Xn] Qt2 -> result.val[1];Qt1 -> result.val[0] A64 +uint32x4x2_t vldnq_u32_x2(uint32_t const *ptr) ptr -> Xn LDNP Qt1,Qt2,[Xn] Qt2 -> result.val[1];Qt1 -> result.val[0] A64 +uint64x2x2_t vldnq_u64_x2(uint64_t const *ptr) ptr -> Xn LDNP Qt1,Qt2,[Xn] Qt2 -> result.val[1];Qt1 -> result.val[0] A64 +float16x8x2_t vldnq_f16_x2(float16_t const *ptr) ptr -> Xn LDNP Qt1,Qt2,[Xn] Qt2 -> result.val[1];Qt1 -> result.val[0] A64 +bfloat16x8x2_t vldnq_bf16_x2(bfloat16_t const *ptr) ptr -> Xn LDNP Qt1,Qt2,[Xn] Qt2 -> result.val[1];Qt1 -> result.val[0] A64 +float32x4x2_t vldnq_f32_x2(float32_t const *ptr) ptr -> Xn LDNP Qt1,Qt2,[Xn] Qt2 -> result.val[1];Qt1 -> result.val[0] A64 +float64x2x2_t vldnq_f64_x2(float64_t const *ptr) ptr -> Xn LDNP Qt1,Qt2,[Xn] Qt2 -> result.val[1];Qt1 -> result.val[0] A64 +mfloat8x16x2_t vldnq_mf8_x2(mfloat8_t const *ptr) ptr -> Xn LDNP Qt1,Qt2,[Xn] Qt2 -> result.val[1];Qt1 -> result.val[0] A64 +void vstn_s32_x2(int32_t *ptr, int32x2_t val) val.val[1] -> Wt2;val.val[0] -> Wt1;ptr -> Xn STNP Wt1,Wt2,[Xn] A64 +void vstn_u32_x2(uint32_t *ptr, uint32x2_t val) val.val[1] -> Wt2;val.val[0] -> Wt1;ptr -> Xn STNP Wt1,Wt2,[Xn] A64 +void vstn_f32_x2(float32_t *ptr, float32x2_t val) val.val[1] -> Wt2;val.val[0] -> Wt1;ptr -> Xn STNP Wt1,Wt2,[Xn] A64 +void vstn_s64_x2(int64_t *ptr, int64x2_t val) val.val[1] -> Xt2;val.val[0] -> Xt1;ptr -> Xn STNP Xt1,Xt2,[Xn] A64 +void vstn_u64_x2(uint64_t *ptr, uint64x2_t val) val.val[1] -> Xt2;val.val[0] -> Xt1;ptr -> Xn STNP Xt1,Xt2,[Xn] A64 +void vstn_f64_x2(float64_t *ptr, float64x2_t val) val.val[1] -> Xt2;val.val[0] -> Xt1;ptr -> Xn STNP Xt1,Xt2,[Xn] A64 +void vstnq_s8_x2(int8_t *ptr, int8x16x2_t val) val.val[1] -> Qt2;val.val[0] -> Qt1;ptr -> Xn STNP Qt1,Qt2,[Xn] A64 +void vstnq_s16_x2(int16_t *ptr, int16x8x2_t val) val.val[1] -> Qt2;val.val[0] -> Qt1;ptr -> Xn STNP Qt1,Qt2,[Xn] A64 +void vstnq_s32_x2(int32_t *ptr, int32x4x2_t val) val.val[1] -> Qt2;val.val[0] -> Qt1;ptr -> Xn STNP Qt1,Qt2,[Xn] A64 +void vstnq_s64_x2(int64_t *ptr, int64x2x2_t val) val.val[1] -> Qt2;val.val[0] -> Qt1;ptr -> Xn STNP Qt1,Qt2,[Xn] A64 +void vstnq_u8_x2(uint8_t *ptr, uint8x16x2_t val) val.val[1] -> Qt2;val.val[0] -> Qt1;ptr -> Xn STNP Qt1,Qt2,[Xn] A64 +void vstnq_u16_x2(uint16_t *ptr, uint16x8x2_t val) val.val[1] -> Qt2;val.val[0] -> Qt1;ptr -> Xn STNP Qt1,Qt2,[Xn] A64 +void vstnq_u32_x2(uint32_t *ptr, uint32x4x2_t val) val.val[1] -> Qt2;val.val[0] -> Qt1;ptr -> Xn STNP Qt1,Qt2,[Xn] A64 +void vstnq_u64_x2(uint64_t *ptr, uint64x2x2_t val) val.val[1] -> Qt2;val.val[0] -> Qt1;ptr -> Xn STNP Qt1,Qt2,[Xn] A64 +void vstnq_f16_x2(float16_t *ptr, float16x8x2_t val) val.val[1] -> Qt2;val.val[0] -> Qt1;ptr -> Xn STNP Qt1,Qt2,[Xn] A64 +void vstnq_bf16_x2(bfloat16_t *ptr, bfloat16x8x2_t val) val.val[1] -> Qt2;val.val[0] -> Qt1;ptr -> Xn STNP Qt1,Qt2,[Xn] A64 +void vstnq_f32_x2(float32_t *ptr, float32x4x2_t val) val.val[1] -> Qt2;val.val[0] -> Qt1;ptr -> Xn STNP Qt1,Qt2,[Xn] A64 +void vstnq_f64_x2(float64_t *ptr, float64x2x2_t val) val.val[1] -> Qt2;val.val[0] -> Qt1;ptr -> Xn STNP Qt1,Qt2,[Xn] A64 +void vstnq_mf8_x2(mfloat8_t *ptr, mfloat8x16x2_t val) val.val[1] -> Qt2;val.val[0] -> Qt1;ptr -> Xn STNP Qt1,Qt2,[Xn] A64 diff --git a/tools/intrinsic_db/advsimd_classification.csv b/tools/intrinsic_db/advsimd_classification.csv index 312f9b05..eb915b2d 100644 --- a/tools/intrinsic_db/advsimd_classification.csv +++ b/tools/intrinsic_db/advsimd_classification.csv @@ -4745,3 +4745,41 @@ vdot_laneq_f32_f16 Vector arithmetic|Dot product vdotq_lane_f32_f16 Vector arithmetic|Dot product vmmlaq_f32_f16 Vector arithmetic|Matrix multiply vmmlaq_f16 Vector arithmetic|Matrix multiply +vldn_s32_x2 Load|Stride +vldn_u32_x2 Load|Stride +vldn_f32_x2 Load|Stride +vldn_s64_x2 Load|Stride +vldn_u64_x2 Load|Stride +vldn_f64_x2 Load|Stride +vldnq_s8_x2 Load|Stride +vldnq_s16_x2 Load|Stride +vldnq_s32_x2 Load|Stride +vldnq_s64_x2 Load|Stride +vldnq_u8_x2 Load|Stride +vldnq_u16_x2 Load|Stride +vldnq_u32_x2 Load|Stride +vldnq_u64_x2 Load|Stride +vldnq_f16_x2 Load|Stride +vldnq_bf16_x2 Load|Stride +vldnq_f32_x2 Load|Stride +vldnq_f64_x2 Load|Stride +vldnq_mf8_x2 Load|Stride +vstn_s32_x2 Store|Stride +vstn_u32_x2 Store|Stride +vstn_f32_x2 Store|Stride +vstn_s64_x2 Store|Stride +vstn_u64_x2 Store|Stride +vstn_f64_x2 Store|Stride +vstnq_s8_x2 Store|Stride +vstnq_s16_x2 Store|Stride +vstnq_s32_x2 Store|Stride +vstnq_s64_x2 Store|Stride +vstnq_u8_x2 Store|Stride +vstnq_u16_x2 Store|Stride +vstnq_u32_x2 Store|Stride +vstnq_u64_x2 Store|Stride +vstnq_f16_x2 Store|Stride +vstnq_bf16_x2 Store|Stride +vstnq_f32_x2 Store|Stride +vstnq_f64_x2 Store|Stride +vstnq_mf8_x2 Store|Stride From a2f5c30ebf1bca7fe3b560da9b12daaa26e02d89 Mon Sep 17 00:00:00 2001 From: CarolineConcatto Date: Mon, 2 Nov 2026 09:35:25 +0000 Subject: [PATCH 2/2] Remove 32 and 64 bits intructions --- neon_intrinsics/advsimd.md | 12 ------------ tools/intrinsic_db/advsimd.csv | 12 ------------ tools/intrinsic_db/advsimd_classification.csv | 12 ------------ 3 files changed, 36 deletions(-) diff --git a/neon_intrinsics/advsimd.md b/neon_intrinsics/advsimd.md index 68209659..ab9b4318 100644 --- a/neon_intrinsics/advsimd.md +++ b/neon_intrinsics/advsimd.md @@ -3835,12 +3835,6 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``. | Intrinsic | Argument preparation | AArch64 Instruction | Result | Supported architectures | |------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------|---------------------------------|---------------------------------------------------------------------------------------------------------------------|---------------------------| -| int32x2_t vldn_s32_x2(
     int32_t const *ptr) | `ptr -> Xn` | `LDNP Wt1,Wt2,[Xn]` | `Wt1/Wt2 -> result[0]/result[1]` | `A64` | -| uint32x2_t vldn_u32_x2(
     uint32_t const *ptr) | `ptr -> Xn` | `LDNP Wt1,Wt2,[Xn]` | `Wt1/Wt2 -> result[0]/result[1]` | `A64` | -| float32x2_t vldn_f32_x2(
     float32_t const *ptr) | `ptr -> Xn` | `LDNP Wt1,Wt2,[Xn]` | `Wt1/Wt2 -> result[0]/result[1]` | `A64` | -| int64x2_t vldn_s64_x2(
     int64_t const *ptr) | `ptr -> Xn` | `LDNP Xt1,Xt2,[Xn]` | `Xt1/Xt2 -> result[0]/result[1]` | `A64` | -| uint64x2_t vldn_u64_x2(
     uint64_t const *ptr) | `ptr -> Xn` | `LDNP Xt1,Xt2,[Xn]` | `Xt1/Xt2 -> result[0]/result[1]` | `A64` | -| float64x2_t vldn_f64_x2(
     float64_t const *ptr) | `ptr -> Xn` | `LDNP Xt1,Xt2,[Xn]` | `Xt1/Xt2 -> result[0]/result[1]` | `A64` | | int8x16x2_t vldnq_s8_x2(
     int8_t const *ptr) | `ptr -> Xn` | `LDNP Qt1,Qt2,[Xn]` | `Qt1/Qt2 -> result.val[0]/result.val[1]` | `A64` | | int16x8x2_t vldnq_s16_x2(
     int16_t const *ptr) | `ptr -> Xn` | `LDNP Qt1,Qt2,[Xn]` | `Qt1/Qt2 -> result.val[0]/result.val[1]` | `A64` | | int32x4x2_t vldnq_s32_x2(
     int32_t const *ptr) | `ptr -> Xn` | `LDNP Qt1,Qt2,[Xn]` | `Qt1/Qt2 -> result.val[0]/result.val[1]` | `A64` | @@ -4338,12 +4332,6 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``. | Intrinsic | Argument preparation | AArch64 Instruction | Result | Supported architectures | |-----------|----------------------|---------------------|--------|-------------------------| -| void vstn_s32_x2(
     int32_t *ptr,
     int32x2_t val) | `val[0]/val[1] -> Wt1/Wt2`
`ptr -> Xn` | `STNP Wt1,Wt2,[Xn]` | | `A64` | -| void vstn_u32_x2(
     uint32_t *ptr,
     uint32x2_t val) | `val[0]/val[1] -> Wt1/Wt2`
`ptr -> Xn` | `STNP Wt1,Wt2,[Xn]` | | `A64` | -| void vstn_f32_x2(
     float32_t *ptr,
     float32x2_t val) | `val[0]/val[1] -> Wt1/Wt2`
`ptr -> Xn` | `STNP Wt1,Wt2,[Xn]` | | `A64` | -| void vstn_s64_x2(
     int64_t *ptr,
     int64x2_t val) | `val[0]/val[1] -> Xt1/Xt2`
`ptr -> Xn` | `STNP Xt1,Xt2,[Xn]` | | `A64` | -| void vstn_u64_x2(
     uint64_t *ptr,
     uint64x2_t val) | `val[0]/val[1] -> Xt1/Xt2`
`ptr -> Xn` | `STNP Xt1,Xt2,[Xn]` | | `A64` | -| void vstn_f64_x2(
     float64_t *ptr,
     float64x2_t val) | `val[0]/val[1] -> Xt1/Xt2`
`ptr -> Xn` | `STNP Xt1,Xt2,[Xn]` | | `A64` | | void vstnq_s8_x2(
     int8_t *ptr,
     int8x16x2_t val) | `val.val[0]/val.val[1] -> Qt1/Qt2`
`ptr -> Xn` | `STNP Qt1,Qt2,[Xn]` | | `A64` | | void vstnq_s16_x2(
     int16_t *ptr,
     int16x8x2_t val) | `val.val[0]/val.val[1] -> Qt1/Qt2`
`ptr -> Xn` | `STNP Qt1,Qt2,[Xn]` | | `A64` | | void vstnq_s32_x2(
     int32_t *ptr,
     int32x4x2_t val) | `val.val[0]/val.val[1] -> Qt1/Qt2`
`ptr -> Xn` | `STNP Qt1,Qt2,[Xn]` | | `A64` | diff --git a/tools/intrinsic_db/advsimd.csv b/tools/intrinsic_db/advsimd.csv index cf81a1b9..25aa0df3 100644 --- a/tools/intrinsic_db/advsimd.csv +++ b/tools/intrinsic_db/advsimd.csv @@ -4864,12 +4864,6 @@ float32x4_t vmmlaq_f32_f16(float32x4_t r, float16x8_t a, float16x8_t b) r -> Vd.
Non-widening half-precision matrix multiply instruction. Requires the +f16mm architecture extension. float16x8_t vmmlaq_f16(float16x8_t r, float16x8_t a, float16x8_t b) r -> Vd.8H;a -> Vn.8H;b -> Vm.8H FMMLA Vd.8H, Vn.8H, Vm.8H Vd.8H -> result A64
Non-temporal pair load and store intrinsics -int32x2_t vldn_s32_x2(int32_t const *ptr) ptr -> Xn LDNP Wt1,Wt2,[Xn] Wt2 -> result[1];Wt1 -> result[0] A64 -uint32x2_t vldn_u32_x2(uint32_t const *ptr) ptr -> Xn LDNP Wt1,Wt2,[Xn] Wt2 -> result[1];Wt1 -> result[0] A64 -float32x2_t vldn_f32_x2(float32_t const *ptr) ptr -> Xn LDNP Wt1,Wt2,[Xn] Wt2 -> result[1];Wt1 -> result[0] A64 -int64x2_t vldn_s64_x2(int64_t const *ptr) ptr -> Xn LDNP Xt1,Xt2,[Xn] Xt2 -> result[1];Xt1 -> result[0] A64 -uint64x2_t vldn_u64_x2(uint64_t const *ptr) ptr -> Xn LDNP Xt1,Xt2,[Xn] Xt2 -> result[1];Xt1 -> result[0] A64 -float64x2_t vldn_f64_x2(float64_t const *ptr) ptr -> Xn LDNP Xt1,Xt2,[Xn] Xt2 -> result[1];Xt1 -> result[0] A64 int8x16x2_t vldnq_s8_x2(int8_t const *ptr) ptr -> Xn LDNP Qt1,Qt2,[Xn] Qt2 -> result.val[1];Qt1 -> result.val[0] A64 int16x8x2_t vldnq_s16_x2(int16_t const *ptr) ptr -> Xn LDNP Qt1,Qt2,[Xn] Qt2 -> result.val[1];Qt1 -> result.val[0] A64 int32x4x2_t vldnq_s32_x2(int32_t const *ptr) ptr -> Xn LDNP Qt1,Qt2,[Xn] Qt2 -> result.val[1];Qt1 -> result.val[0] A64 @@ -4883,12 +4877,6 @@ bfloat16x8x2_t vldnq_bf16_x2(bfloat16_t const *ptr) ptr -> Xn LDNP Qt1,Qt2,[Xn] float32x4x2_t vldnq_f32_x2(float32_t const *ptr) ptr -> Xn LDNP Qt1,Qt2,[Xn] Qt2 -> result.val[1];Qt1 -> result.val[0] A64 float64x2x2_t vldnq_f64_x2(float64_t const *ptr) ptr -> Xn LDNP Qt1,Qt2,[Xn] Qt2 -> result.val[1];Qt1 -> result.val[0] A64 mfloat8x16x2_t vldnq_mf8_x2(mfloat8_t const *ptr) ptr -> Xn LDNP Qt1,Qt2,[Xn] Qt2 -> result.val[1];Qt1 -> result.val[0] A64 -void vstn_s32_x2(int32_t *ptr, int32x2_t val) val.val[1] -> Wt2;val.val[0] -> Wt1;ptr -> Xn STNP Wt1,Wt2,[Xn] A64 -void vstn_u32_x2(uint32_t *ptr, uint32x2_t val) val.val[1] -> Wt2;val.val[0] -> Wt1;ptr -> Xn STNP Wt1,Wt2,[Xn] A64 -void vstn_f32_x2(float32_t *ptr, float32x2_t val) val.val[1] -> Wt2;val.val[0] -> Wt1;ptr -> Xn STNP Wt1,Wt2,[Xn] A64 -void vstn_s64_x2(int64_t *ptr, int64x2_t val) val.val[1] -> Xt2;val.val[0] -> Xt1;ptr -> Xn STNP Xt1,Xt2,[Xn] A64 -void vstn_u64_x2(uint64_t *ptr, uint64x2_t val) val.val[1] -> Xt2;val.val[0] -> Xt1;ptr -> Xn STNP Xt1,Xt2,[Xn] A64 -void vstn_f64_x2(float64_t *ptr, float64x2_t val) val.val[1] -> Xt2;val.val[0] -> Xt1;ptr -> Xn STNP Xt1,Xt2,[Xn] A64 void vstnq_s8_x2(int8_t *ptr, int8x16x2_t val) val.val[1] -> Qt2;val.val[0] -> Qt1;ptr -> Xn STNP Qt1,Qt2,[Xn] A64 void vstnq_s16_x2(int16_t *ptr, int16x8x2_t val) val.val[1] -> Qt2;val.val[0] -> Qt1;ptr -> Xn STNP Qt1,Qt2,[Xn] A64 void vstnq_s32_x2(int32_t *ptr, int32x4x2_t val) val.val[1] -> Qt2;val.val[0] -> Qt1;ptr -> Xn STNP Qt1,Qt2,[Xn] A64 diff --git a/tools/intrinsic_db/advsimd_classification.csv b/tools/intrinsic_db/advsimd_classification.csv index eb915b2d..9e4d0731 100644 --- a/tools/intrinsic_db/advsimd_classification.csv +++ b/tools/intrinsic_db/advsimd_classification.csv @@ -4745,12 +4745,6 @@ vdot_laneq_f32_f16 Vector arithmetic|Dot product vdotq_lane_f32_f16 Vector arithmetic|Dot product vmmlaq_f32_f16 Vector arithmetic|Matrix multiply vmmlaq_f16 Vector arithmetic|Matrix multiply -vldn_s32_x2 Load|Stride -vldn_u32_x2 Load|Stride -vldn_f32_x2 Load|Stride -vldn_s64_x2 Load|Stride -vldn_u64_x2 Load|Stride -vldn_f64_x2 Load|Stride vldnq_s8_x2 Load|Stride vldnq_s16_x2 Load|Stride vldnq_s32_x2 Load|Stride @@ -4764,12 +4758,6 @@ vldnq_bf16_x2 Load|Stride vldnq_f32_x2 Load|Stride vldnq_f64_x2 Load|Stride vldnq_mf8_x2 Load|Stride -vstn_s32_x2 Store|Stride -vstn_u32_x2 Store|Stride -vstn_f32_x2 Store|Stride -vstn_s64_x2 Store|Stride -vstn_u64_x2 Store|Stride -vstn_f64_x2 Store|Stride vstnq_s8_x2 Store|Stride vstnq_s16_x2 Store|Stride vstnq_s32_x2 Store|Stride