diff --git a/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/Board_HP-U85.clayer.yml b/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/Board_HP-U85.clayer.yml index 1482341..897d2a8 100644 --- a/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/Board_HP-U85.clayer.yml +++ b/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/Board_HP-U85.clayer.yml @@ -33,7 +33,7 @@ layer: # List the packs used in the layer. packs: - - pack: AlifSemiconductor::Ensemble@^2.2.0-0 + - pack: AlifSemiconductor::Ensemble@^2.2.1-0 - pack: ARM::CMSIS@^6.2.0 - pack: ARM::CMSIS-Compiler@^2.1.0 - pack: ARM::CMSIS-Driver@^2.10.0 diff --git a/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/Board_HP.clayer.yml b/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/Board_HP.clayer.yml index d13d8dc..c929da3 100644 --- a/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/Board_HP.clayer.yml +++ b/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/Board_HP.clayer.yml @@ -41,7 +41,7 @@ layer: # List the packs used in the layer. packs: - - pack: AlifSemiconductor::Ensemble@^2.2.0-0 + - pack: AlifSemiconductor::Ensemble@^2.2.1-0 - pack: ARM::CMSIS@^6.2.0 - pack: ARM::CMSIS-Compiler@^2.1.0 - pack: ARM::CMSIS-Driver@^2.10.0 diff --git a/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/RTE_Device.h b/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/RTE_Device.h index 531af63..6502c56 100644 --- a/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/RTE_Device.h +++ b/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/RTE_Device.h @@ -374,89 +374,22 @@ // Default: 0 #define RTE_ISP_IRQ_PRIORITY 0 -// ISP Enable AE Module +// ISP Binning Enable // <0=> disable // <1=> enable -// defines if AE Module is enabled or not +// Enable binning processing in ISP // default: false -#define RTE_ISP_AE_MODULE 1 +#define RTE_ISP_BINNING_ENABLE 0 -// ISP Enable BLS Module -// <0=> disable -// <1=> enable -// defines if Black Level Subtraction Module is enabled or not -// default: false -#define RTE_ISP_BLS_MODULE 1 - -// ISP Enable DMSC Module -// <0=> disable -// <1=> enable -// defines if Demosaic Module is enabled or not -// default: false -#define RTE_ISP_DMSC_MODULE 1 - -// ISP Enable FLT Module -// <0=> disable -// <1=> enable -// defines if Noise/Sharpening-Filter Module is enabled or not -// default: false -#define RTE_ISP_FLT_MODULE 1 - -// ISP Enable CCM Module -// <0=> disable -// <1=> enable -// defines if Color Correction Matrix Module is enabled or not -// default: false -#define RTE_ISP_CCM_MODULE 1 - -// ISP Enable CSM Module -// <0=> disable -// <1=> enable -// defines if Color Space Conversion Module is enabled or not -// default: false -#define RTE_ISP_CSM_MODULE 1 - -// ISP Enable WB Module -// <0=> disable -// <1=> enable -// defines if White Balancing Module is enabled or not -// default: false -#define RTE_ISP_WB_MODULE 1 - -// ISP Enable EXPM Module -// <0=> disable -// <1=> enable -// defines if Auto-Exposure Statistics Module is enabled or not -// default: false -#define RTE_ISP_EXPM_MODULE 1 - -// ISP Enable Gamma-out Module -// <0=> disable -// <1=> enable -// defines if Gamma-out Module is enabled or not -// default: false -#define RTE_ISP_GAMMAOUT_MODULE 1 - -// ISP Enable WBM Module -// <0=> disable -// <1=> enable -// defines if White-Balancing Statistics Module is enabled or not -// default: false -#define RTE_ISP_WBM_MODULE 1 - -// ISP Enable Binning Module -// <0=> disable -// <1=> enable -// defines if Binning Module is enabled or not -// default: false -#define RTE_ISP_BINNING_MODULE 1 +// ISP Binning Horizontal Step <0-255> +// Horizontal binning step size +// default: 0 +#define RTE_ISP_BINNING_HSTEP 0 -// ISP Enable Scaling Module -// <0=> disable -// <1=> enable -// defines if scaling Module is enabled or not -// default: true -#define RTE_ISP_SCALAR_MODULE 1 +// ISP Binning Vertical Step <0-255> +// Vertical binning step size +// default: 0 +#define RTE_ISP_BINNING_VSTEP 0 // ISP log level // <0=> NONE @@ -498,36 +431,48 @@ // Height in pixels of the ISP scaler output (after scaling from sensor dimensions). #define RTE_ISP_OUTPUT_HEIGHT 480 -// ISP Sensor Input Width -// Width in pixels of the sensor input to the ISP pipeline. -// Default: MT9M114 sensor resolution (1280). Change for different sensors. -#define RTE_ISP_SENSOR_INPUT_WIDTH RTE_MT9M114_CAMERA_SENSOR_FRAME_WIDTH +#endif +// ISP (ISP) [Driver_ISP] -// ISP Sensor Input Height -// Height in pixels of the sensor input to the ISP pipeline. -// Default: MT9M114 sensor resolution (720). Change for different sensors. -#define RTE_ISP_SENSOR_INPUT_HEIGHT RTE_MT9M114_CAMERA_SENSOR_FRAME_HEIGHT +// JPEG (JPEG) [Driver_JPEG] +// Configuration settings for Driver_JPEG in component ::Drivers:JPEG +#define RTE_JPEG 1 +#if RTE_JPEG -// ISP Crop Top offset <0-4095> -// Top offset in pixels for the cropped output window -#define RTE_ISP_CROP_TOP 0 +// JPEG IRQ priority <0-255> +// Defines Interrupt priority for JPEG. +// Default: 0 +#define RTE_JPEG_IRQ_PRIORITY 0 -// ISP Crop Left offset <0-4095> -// Left offset in pixels for the cropped output window -#define RTE_ISP_CROP_LEFT 0 +// JPEG Encoding Mode +// <0=> 4:2:0(4lum+2chrblocks/MCU) +// Defines encoding mode for JPEG. +// Default: 0 +#define RTE_JPEG_MODE 0 -// ISP Crop Width <1-4095> -// Width in pixels of the cropped output window. -// Default: full sensor input (no crop). Override with smaller value to crop. -#define RTE_ISP_CROP_WIDTH RTE_ISP_SENSOR_INPUT_WIDTH +// JPEG Encoding Mode +// <0=> JPEGENC_420_MODE +// Defines encoding mode for JPEG. +// Default: 0 +#define RTE_JPEG_CODING_MODE 0 -// ISP Crop Height <1-4095> -// Height in pixels of the cropped output window. -// Default: full sensor input (no crop). Override with smaller value to crop. -#define RTE_ISP_CROP_HEIGHT RTE_ISP_SENSOR_INPUT_HEIGHT +// JPEG AXI Burst Length +// AXI burst length for JPEG. +// Default: 64 +#define RTE_JPEG_AXI_BURST_LENGTH 64 + +// JPEG AXI write outstanding number +// AXI write outstanding number for JPEG. +// Default: 64 +#define RTE_AXI_WRITE_OUTSTANDING_NUM 64 + +// JPEG AXI read outstanding number +// AXI read outstanding number for JPEG. +// Default: 64 +#define RTE_AXI_READ_OUTSTANDING_NUM 64 #endif -// ISP (ISP) [Driver_ISP] +// JPEG (JPEG) [Driver_JPEG] // MIPI_CSI2 (mipi csi2) [Driver_MIPI_CSI2] // Configuration settings for Driver_MIPI_CSI2 in component ::Drivers:MIPI_CSI2 @@ -1000,6 +945,27 @@ // Default: 1 #define RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG 3 +// MT9M114 MIPI frame width and height(derived from IMAGE_CONFIG) +// defines MT9M114 MIPI frame width & height +// default: 1280x720 +#if (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 0) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 1288 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 728 +#elif (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 1) || \ + (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 2) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 1280 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 720 +#elif (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 3) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 640 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 480 +#elif (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 4) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 320 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 240 +#elif (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 5) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 320 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 320 +#endif + // select MT9M114 MIPI number of lanes in DPHY // defines select MT9M114 MIPI number of lanes in DPHY. // default: 1 one lane @@ -1238,15 +1204,39 @@ // default: 2 (IPI-16 RAW 8) #define RTE_OV5675_CAMERA_SENSOR_CPI_COLOR_MODE 2 -// select OV5675 frame height -// defines select OV5675 frame height. +// Select OV5675 image configuration +// <0=> 1296x972_RAW10 +// <1=> 1920x1080_RAW10 +// <2=> 1280x720_RAW10 +// <3=> 640x480_RAW10 +// Default: 0 +#define RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG 0 + +// OV5675 frame height (derived from IMAGE_CONFIG) +// defines OV5675 frame height. // default: 972 +#if (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 1) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 1080 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 2) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 720 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 3) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 480 +#else #define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 972 +#endif -// select OV5675 frame width -// defines select OV5675 frame width. +// OV5675 frame width (derived from IMAGE_CONFIG) +// defines OV5675 frame width. // default: 1296 +#if (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 1) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 1920 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 2) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 1280 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 3) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 640 +#else #define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 1296 +#endif // Select camera sensor OV5675 i2c instance // Defines camera sensor OV5675 i2c instance @@ -8180,6 +8170,29 @@ // Default: ENABLE #define RTE_ADC120_COMPARATOR_BIAS 2 +// ADC120 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for ADC120 (StartN buffered mode) +// Default: DISABLE +#define RTE_ADC120_DMA_ENABLE 0 + +// ADC120 DMA Selection +// <0=> DMA2 (M55-HE) +// <1=> DMA0 +// Default: DMA0 +#define RTE_ADC120_SELECT_DMA0 1 + +// ADC120 DMA IRQ priority <0-255> +// Defines ADC120 DMA interrupt priority +// Default: 0 +#define RTE_ADC120_DMA_IRQ_PRI 0 + +// ADC120 DMA mcode buffer size (bytes) <256-16384:64> +// Larger buffer -> fewer DMA interrupts at high sample rates. +// Default: 256 +#define RTE_ADC120_DMA_MCODE_SIZE 256 + #endif // ADC120 (Analog to Digital Converter 0) [Driver_ADC120] @@ -8282,6 +8295,29 @@ // Default: ENABLE #define RTE_ADC121_COMPARATOR_BIAS 2 +// ADC121 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for ADC121 (StartN buffered mode) +// Default: DISABLE +#define RTE_ADC121_DMA_ENABLE 0 + +// ADC121 DMA Selection +// <0=> DMA2 (M55-HE) +// <1=> DMA0 +// Default: DMA0 +#define RTE_ADC121_SELECT_DMA0 1 + +// ADC121 DMA IRQ priority <0-255> +// Defines ADC121 DMA interrupt priority +// Default: 0 +#define RTE_ADC121_DMA_IRQ_PRI 0 + +// ADC121 DMA mcode buffer size (bytes) <256-16384:64> +// Larger buffer -> fewer DMA interrupts at high sample rates. +// Default: 256 +#define RTE_ADC121_DMA_MCODE_SIZE 256 + #endif // ADC121 (Analog to Digital Converter 1) [Driver_ADC121] @@ -8384,6 +8420,29 @@ // Default: ENABLE #define RTE_ADC122_COMPARATOR_BIAS 2 +// ADC122 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for ADC122 (StartN buffered mode) +// Default: DISABLE +#define RTE_ADC122_DMA_ENABLE 0 + +// ADC122 DMA Selection +// <0=> DMA2 (M55-HE) +// <1=> DMA0 +// Default: DMA0 +#define RTE_ADC122_SELECT_DMA0 1 + +// ADC122 DMA IRQ priority <0-255> +// Defines ADC122 DMA interrupt priority +// Default: 0 +#define RTE_ADC122_DMA_IRQ_PRI 0 + +// ADC122 DMA mcode buffer size (bytes) <256-16384:64> +// Larger buffer -> fewer DMA interrupts at high sample rates. +// Default: 256 +#define RTE_ADC122_DMA_MCODE_SIZE 256 + #endif // ADC122 (Analog to Digital Converter 2) [Driver_ADC122] @@ -8478,6 +8537,29 @@ // Default: 3 #define RTE_ADC24_BIAS (3) +// ADC24 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for ADC24 (StartN buffered mode) +// Default: DISABLE +#define RTE_ADC24_DMA_ENABLE 0 + +// ADC24 DMA Selection +// <0=> DMA2 (M55-HE) +// <1=> DMA0 +// Default: DMA0 +#define RTE_ADC24_SELECT_DMA0 1 + +// ADC24 DMA IRQ priority <0-255> +// Defines ADC24 DMA interrupt priority +// Default: 0 +#define RTE_ADC24_DMA_IRQ_PRI 0 + +// ADC24 DMA mcode buffer size (bytes) <256-16384:64> +// Larger buffer -> fewer DMA interrupts at high sample rates. +// Default: 256 +#define RTE_ADC24_DMA_MCODE_SIZE 256 + #endif // ADC24 (Analog to Digital Converter 0) [Driver_ADC24] // ADC (Analog to Digital Converter) @@ -9018,6 +9100,16 @@ // Default: 0 #define RTE_I2C0_RX_FIFO_THRESHOLD 0 +// I2C0 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C0_SCL_STUCK_LOW_TIMEOUT 1000000 + +// I2C0 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C0_SDA_STUCK_LOW_TIMEOUT 1000000 + // I2C0 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -9030,6 +9122,12 @@ // Defines I2C0 DMA Interrupt priority // Default: 0 #define RTE_I2C0_DMA_IRQ_PRI 0 + +// I2C0 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_I2C0_DMA_SCRATCH_SIZE 256 #endif #endif @@ -9055,6 +9153,16 @@ // Default: 0 #define RTE_I2C1_RX_FIFO_THRESHOLD 0 +// I2C1 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C1_SCL_STUCK_LOW_TIMEOUT 1000000 + +// I2C1 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C1_SDA_STUCK_LOW_TIMEOUT 1000000 + // I2C1 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -9067,6 +9175,12 @@ // Defines I2C1 DMA Interrupt priority // Default: 0 #define RTE_I2C1_DMA_IRQ_PRI 0 + +// I2C1 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_I2C1_DMA_SCRATCH_SIZE 256 #endif #endif @@ -9092,6 +9206,16 @@ // Default: 0 #define RTE_I2C2_RX_FIFO_THRESHOLD 0 +// I2C2 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C2_SCL_STUCK_LOW_TIMEOUT 1000000 + +// I2C2 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C2_SDA_STUCK_LOW_TIMEOUT 1000000 + // I2C2 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -9104,6 +9228,12 @@ // Defines I2C2 DMA Interrupt priority // Default: 0 #define RTE_I2C2_DMA_IRQ_PRI 0 + +// I2C2 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_I2C2_DMA_SCRATCH_SIZE 256 #endif #endif @@ -9130,6 +9260,16 @@ // Default: 0 #define RTE_I2C3_RX_FIFO_THRESHOLD 0 +// I2C3 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C3_SCL_STUCK_LOW_TIMEOUT 1000000 + +// I2C3 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C3_SDA_STUCK_LOW_TIMEOUT 1000000 + // I2C3 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -9142,6 +9282,12 @@ // Defines I2C3 DMA Interrupt priority // Default: 0 #define RTE_I2C3_DMA_IRQ_PRI 0 + +// I2C3 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_I2C3_DMA_SCRATCH_SIZE 256 #endif #endif @@ -9187,6 +9333,16 @@ // Default: 0 #define RTE_LPI2C1_RX_FIFO_THRESHOLD 0 +// LPI2C1 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 160MHz) +#define RTE_LPI2C1_SCL_STUCK_LOW_TIMEOUT 1600000 + +// LPI2C1 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 160MHz) +#define RTE_LPI2C1_SDA_STUCK_LOW_TIMEOUT 1600000 + // LPI2C1 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -9199,6 +9355,12 @@ // Defines LPI2C1 DMA Interrupt priority // Default: 0 #define RTE_LPI2C1_DMA_IRQ_PRI 0 + +// LPI2C1 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_LPI2C1_DMA_SCRATCH_SIZE 256 #endif #endif @@ -10786,17 +10948,18 @@ // SDC BUS WIDTH SELECT // <0=> BUS_WIDTH_1BIT // <1=> BUS_WIDTH_4BIT +// <2=> BUS_WIDTH_8BIT // Defines SDC0 size of bus width // Default: BUS_WIDTH_4BIT #define RTE_SDC_BUS_WIDTH 1 -// SDC CLOCK SELECT -// <0=> SDC_12_5MHz -// <1=> SDC_25MHz -// <2=> SDC_50MHz -// Defines SDC0 Clock select +// SDC CLOCK SELECT (Hz) +// <12500000=> 12.5MHz +// <25000000=> 25MHz +// <50000000=> 50MHz +// Defines SDC0 Clock frequency in Hz // Default: 25MHz -#define RTE_SDC_CLOCK_SELECT 1 +#define RTE_SDC_CLOCK_SELECT 25000000 // SDC DMA SELECT // <0=> SDMA diff --git a/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/RTE_Device.h.base@2.2.0 b/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/RTE_Device.h.base@2.5.0 similarity index 94% rename from RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/RTE_Device.h.base@2.2.0 rename to RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/RTE_Device.h.base@2.5.0 index c08e58c..0903f32 100644 --- a/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/RTE_Device.h.base@2.2.0 +++ b/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/RTE_Device.h.base@2.5.0 @@ -374,83 +374,6 @@ // Default: 0 #define RTE_ISP_IRQ_PRIORITY 0 -// ISP Enable AE Module -// <0=> disable -// <1=> enable -// defines if AE Module is enabled or not -// default: false -#define RTE_ISP_AE_MODULE 1 - -// ISP Enable BLS Module -// <0=> disable -// <1=> enable -// defines if Black Level Subtraction Module is enabled or not -// default: false -#define RTE_ISP_BLS_MODULE 1 - -// ISP Enable DMSC Module -// <0=> disable -// <1=> enable -// defines if Demosaic Module is enabled or not -// default: false -#define RTE_ISP_DMSC_MODULE 1 - -// ISP Enable FLT Module -// <0=> disable -// <1=> enable -// defines if Noise/Sharpening-Filter Module is enabled or not -// default: false -#define RTE_ISP_FLT_MODULE 1 - -// ISP Enable CCM Module -// <0=> disable -// <1=> enable -// defines if Color Correction Matrix Module is enabled or not -// default: false -#define RTE_ISP_CCM_MODULE 1 - -// ISP Enable CSM Module -// <0=> disable -// <1=> enable -// defines if Color Space Conversion Module is enabled or not -// default: false -#define RTE_ISP_CSM_MODULE 1 - -// ISP Enable WB Module -// <0=> disable -// <1=> enable -// defines if White Balancing Module is enabled or not -// default: false -#define RTE_ISP_WB_MODULE 1 - -// ISP Enable EXPM Module -// <0=> disable -// <1=> enable -// defines if Auto-Exposure Statistics Module is enabled or not -// default: false -#define RTE_ISP_EXPM_MODULE 1 - -// ISP Enable Gamma-out Module -// <0=> disable -// <1=> enable -// defines if Gamma-out Module is enabled or not -// default: false -#define RTE_ISP_GAMMAOUT_MODULE 1 - -// ISP Enable WBM Module -// <0=> disable -// <1=> enable -// defines if White-Balancing Statistics Module is enabled or not -// default: false -#define RTE_ISP_WBM_MODULE 1 - -// ISP Enable Binning Module -// <0=> disable -// <1=> enable -// defines if Binning Module is enabled or not -// default: false -#define RTE_ISP_BINNING_MODULE 1 - // ISP Binning Enable // <0=> disable // <1=> enable @@ -468,13 +391,6 @@ // default: 0 #define RTE_ISP_BINNING_VSTEP 0 -// ISP Enable Scaling Module -// <0=> disable -// <1=> enable -// defines if scaling Module is enabled or not -// default: true -#define RTE_ISP_SCALAR_MODULE 1 - // ISP log level // <0=> NONE // <1 => Logs all fatal errors. @@ -515,35 +431,6 @@ // Height in pixels of the ISP scaler output (after scaling from sensor dimensions). #define RTE_ISP_OUTPUT_HEIGHT 480 -// ISP Sensor Input Width -// Width in pixels of the sensor input to the ISP pipeline. -// Default: MT9M114 sensor resolution (1280). Change for different sensors. -#define RTE_ISP_SENSOR_INPUT_WIDTH RTE_MT9M114_CAMERA_SENSOR_FRAME_WIDTH - - -// ISP Sensor Input Height -// Height in pixels of the sensor input to the ISP pipeline. -// Default: MT9M114 sensor resolution (720). Change for different sensors. -#define RTE_ISP_SENSOR_INPUT_HEIGHT RTE_MT9M114_CAMERA_SENSOR_FRAME_HEIGHT - -// ISP Crop Top offset <0-4095> -// Top offset in pixels for the cropped output window -#define RTE_ISP_CROP_TOP 0 - -// ISP Crop Left offset <0-4095> -// Left offset in pixels for the cropped output window -#define RTE_ISP_CROP_LEFT 0 - -// ISP Crop Width <1-4095> -// Width in pixels of the cropped output window. -// Default: full sensor input (no crop). Override with smaller value to crop. -#define RTE_ISP_CROP_WIDTH RTE_ISP_SENSOR_INPUT_WIDTH - -// ISP Crop Height <1-4095> -// Height in pixels of the cropped output window. -// Default: full sensor input (no crop). Override with smaller value to crop. -#define RTE_ISP_CROP_HEIGHT RTE_ISP_SENSOR_INPUT_HEIGHT - #endif // ISP (ISP) [Driver_ISP] @@ -1058,6 +945,27 @@ // Default: 1 #define RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG 1 +// MT9M114 MIPI frame width and height(derived from IMAGE_CONFIG) +// defines MT9M114 MIPI frame width & height +// default: 1280x720 +#if (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 0) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 1288 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 728 +#elif (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 1) || \ + (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 2) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 1280 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 720 +#elif (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 3) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 640 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 480 +#elif (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 4) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 320 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 240 +#elif (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG == 5) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_WIDTH 320 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_FRAME_HEIGHT 320 +#endif + // select MT9M114 MIPI number of lanes in DPHY // defines select MT9M114 MIPI number of lanes in DPHY. // default: 1 one lane @@ -8262,6 +8170,29 @@ // Default: ENABLE #define RTE_ADC120_COMPARATOR_BIAS 2 +// ADC120 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for ADC120 (StartN buffered mode) +// Default: DISABLE +#define RTE_ADC120_DMA_ENABLE 0 + +// ADC120 DMA Selection +// <0=> DMA2 (M55-HE) +// <1=> DMA0 +// Default: DMA0 +#define RTE_ADC120_SELECT_DMA0 1 + +// ADC120 DMA IRQ priority <0-255> +// Defines ADC120 DMA interrupt priority +// Default: 0 +#define RTE_ADC120_DMA_IRQ_PRI 0 + +// ADC120 DMA mcode buffer size (bytes) <256-16384:64> +// Larger buffer -> fewer DMA interrupts at high sample rates. +// Default: 256 +#define RTE_ADC120_DMA_MCODE_SIZE 256 + #endif // ADC120 (Analog to Digital Converter 0) [Driver_ADC120] @@ -8364,6 +8295,29 @@ // Default: ENABLE #define RTE_ADC121_COMPARATOR_BIAS 2 +// ADC121 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for ADC121 (StartN buffered mode) +// Default: DISABLE +#define RTE_ADC121_DMA_ENABLE 0 + +// ADC121 DMA Selection +// <0=> DMA2 (M55-HE) +// <1=> DMA0 +// Default: DMA0 +#define RTE_ADC121_SELECT_DMA0 1 + +// ADC121 DMA IRQ priority <0-255> +// Defines ADC121 DMA interrupt priority +// Default: 0 +#define RTE_ADC121_DMA_IRQ_PRI 0 + +// ADC121 DMA mcode buffer size (bytes) <256-16384:64> +// Larger buffer -> fewer DMA interrupts at high sample rates. +// Default: 256 +#define RTE_ADC121_DMA_MCODE_SIZE 256 + #endif // ADC121 (Analog to Digital Converter 1) [Driver_ADC121] @@ -8466,6 +8420,29 @@ // Default: ENABLE #define RTE_ADC122_COMPARATOR_BIAS 2 +// ADC122 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for ADC122 (StartN buffered mode) +// Default: DISABLE +#define RTE_ADC122_DMA_ENABLE 0 + +// ADC122 DMA Selection +// <0=> DMA2 (M55-HE) +// <1=> DMA0 +// Default: DMA0 +#define RTE_ADC122_SELECT_DMA0 1 + +// ADC122 DMA IRQ priority <0-255> +// Defines ADC122 DMA interrupt priority +// Default: 0 +#define RTE_ADC122_DMA_IRQ_PRI 0 + +// ADC122 DMA mcode buffer size (bytes) <256-16384:64> +// Larger buffer -> fewer DMA interrupts at high sample rates. +// Default: 256 +#define RTE_ADC122_DMA_MCODE_SIZE 256 + #endif // ADC122 (Analog to Digital Converter 2) [Driver_ADC122] @@ -8560,6 +8537,29 @@ // Default: 3 #define RTE_ADC24_BIAS (3) +// ADC24 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for ADC24 (StartN buffered mode) +// Default: DISABLE +#define RTE_ADC24_DMA_ENABLE 0 + +// ADC24 DMA Selection +// <0=> DMA2 (M55-HE) +// <1=> DMA0 +// Default: DMA0 +#define RTE_ADC24_SELECT_DMA0 1 + +// ADC24 DMA IRQ priority <0-255> +// Defines ADC24 DMA interrupt priority +// Default: 0 +#define RTE_ADC24_DMA_IRQ_PRI 0 + +// ADC24 DMA mcode buffer size (bytes) <256-16384:64> +// Larger buffer -> fewer DMA interrupts at high sample rates. +// Default: 256 +#define RTE_ADC24_DMA_MCODE_SIZE 256 + #endif // ADC24 (Analog to Digital Converter 0) [Driver_ADC24] // ADC (Analog to Digital Converter) @@ -9100,6 +9100,16 @@ // Default: 0 #define RTE_I2C0_RX_FIFO_THRESHOLD 0 +// I2C0 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C0_SCL_STUCK_LOW_TIMEOUT 1000000 + +// I2C0 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C0_SDA_STUCK_LOW_TIMEOUT 1000000 + // I2C0 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -9112,6 +9122,12 @@ // Defines I2C0 DMA Interrupt priority // Default: 0 #define RTE_I2C0_DMA_IRQ_PRI 0 + +// I2C0 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_I2C0_DMA_SCRATCH_SIZE 256 #endif #endif @@ -9137,6 +9153,16 @@ // Default: 0 #define RTE_I2C1_RX_FIFO_THRESHOLD 0 +// I2C1 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C1_SCL_STUCK_LOW_TIMEOUT 1000000 + +// I2C1 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C1_SDA_STUCK_LOW_TIMEOUT 1000000 + // I2C1 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -9149,6 +9175,12 @@ // Defines I2C1 DMA Interrupt priority // Default: 0 #define RTE_I2C1_DMA_IRQ_PRI 0 + +// I2C1 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_I2C1_DMA_SCRATCH_SIZE 256 #endif #endif @@ -9174,6 +9206,16 @@ // Default: 0 #define RTE_I2C2_RX_FIFO_THRESHOLD 0 +// I2C2 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C2_SCL_STUCK_LOW_TIMEOUT 1000000 + +// I2C2 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C2_SDA_STUCK_LOW_TIMEOUT 1000000 + // I2C2 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -9186,6 +9228,12 @@ // Defines I2C2 DMA Interrupt priority // Default: 0 #define RTE_I2C2_DMA_IRQ_PRI 0 + +// I2C2 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_I2C2_DMA_SCRATCH_SIZE 256 #endif #endif @@ -9212,6 +9260,16 @@ // Default: 0 #define RTE_I2C3_RX_FIFO_THRESHOLD 0 +// I2C3 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C3_SCL_STUCK_LOW_TIMEOUT 1000000 + +// I2C3 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 100MHz) +#define RTE_I2C3_SDA_STUCK_LOW_TIMEOUT 1000000 + // I2C3 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -9224,6 +9282,12 @@ // Defines I2C3 DMA Interrupt priority // Default: 0 #define RTE_I2C3_DMA_IRQ_PRI 0 + +// I2C3 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_I2C3_DMA_SCRATCH_SIZE 256 #endif #endif @@ -9269,6 +9333,16 @@ // Default: 0 #define RTE_LPI2C1_RX_FIFO_THRESHOLD 0 +// LPI2C1 SCL Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SCL stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 160MHz) +#define RTE_LPI2C1_SCL_STUCK_LOW_TIMEOUT 1600000 + +// LPI2C1 SDA Stuck at Low Timeout <0x00000000-0xFFFFFFFF> +// Defines SDA stuck-at-low timeout (in ic_clk cycles). +// Default: 10ms (Considered the input clock as 160MHz) +#define RTE_LPI2C1_SDA_STUCK_LOW_TIMEOUT 1600000 + // LPI2C1 DMA ENABLE // <0=> DISABLE // <1=> ENABLE @@ -9281,6 +9355,12 @@ // Defines LPI2C1 DMA Interrupt priority // Default: 0 #define RTE_LPI2C1_DMA_IRQ_PRI 0 + +// LPI2C1 DMA scratch buffer size (entries) <32-256:8> +// Per-instance 16-bit DMA scratch buffer; sized in DATA_CMD entries. +// Caps the per-chunk DMA transfer (max 256). +// Default: 256 +#define RTE_LPI2C1_DMA_SCRATCH_SIZE 256 #endif #endif @@ -10868,6 +10948,7 @@ // SDC BUS WIDTH SELECT // <0=> BUS_WIDTH_1BIT // <1=> BUS_WIDTH_4BIT +// <2=> BUS_WIDTH_8BIT // Defines SDC0 size of bus width // Default: BUS_WIDTH_4BIT #define RTE_SDC_BUS_WIDTH 1 diff --git a/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_mram.sct b/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_mram.sct index b1f7c16..427dfa4 100644 --- a/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_mram.sct +++ b/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_mram.sct @@ -4,7 +4,7 @@ #include "app_mem_regions.h" #define __ROM_BASE APP_MRAM_HP_BASE -#define __ROM_SIZE APP_MRAM_HP_SIZE +#define __ROM_SIZE APP_CODE_MRAM_SIZE #define __ITCM_BASE APP_ITCM_BASE #define __ITCM_SIZE APP_HP_ITCM_SIZE @@ -18,14 +18,14 @@ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition -*----------------------------------------------------------------------------*/ + *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ #define __APP_HEAP_BASE (AlignExpr(+0, 8)) /* starts after HEAP, 8 byte aligned */ /*---------------------------------------------------------------------------- Scatter File Definitions definition -*----------------------------------------------------------------------------*/ + *----------------------------------------------------------------------------*/ #define __RW_BASE __RAM_BASE #define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __APP_HEAP_SIZE) @@ -65,14 +65,14 @@ LR_ROM __ROM_BASE NOCOMPRESS __ROM_SIZE { ; load region size_region } /*--------------------------------------------------------------------------*/ - /* DTCM – SMALL, EXPLICIT, SAFE */ + /* DTCM - SMALL, EXPLICIT, SAFE */ /*--------------------------------------------------------------------------*/ RW_RAM __RW_BASE __RW_SIZE { /* Explicit DTCM placement only */ * (.*dtcm*) - } + } NS_REGION_0 (AlignExpr(+0, TGU_BLOCK_SIZE)) { ; Non secure region 0 * (eth_buf) @@ -99,7 +99,7 @@ LR_ROM __ROM_BASE NOCOMPRESS __ROM_SIZE { ; load region size_region #if (SRAM0_SRAM1_COMBINED == 1) /*--------------------------------------------------------------------------*/ - /* Combined SRAM – ALL LARGE & GENERAL DATA */ + /* Combined SRAM - ALL LARGE & GENERAL DATA */ /*--------------------------------------------------------------------------*/ RW_SRAM APP_SRAM_BASE APP_SRAM_SIZE { @@ -120,4 +120,4 @@ LR_ROM __ROM_BASE NOCOMPRESS __ROM_SIZE { ; load region size_region PADDING +0 OVERLAY ALIGN 16 FILL 0 16 { } -} \ No newline at end of file +} diff --git a/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_mram.sct.base@2.2.0 b/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_mram.sct.base@2.2.1 similarity index 95% rename from RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_mram.sct.base@2.2.0 rename to RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_mram.sct.base@2.2.1 index 06436a6..2551ba1 100644 --- a/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_mram.sct.base@2.2.0 +++ b/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_mram.sct.base@2.2.1 @@ -99,6 +99,7 @@ LR_ROM __ROM_BASE NOCOMPRESS __ROM_SIZE { ; load region size_region * (.bss.lcd_frame_buf) ; LCD frame Buffer. * (.bss.camera_frame_buf) ; Camera Frame Buffer * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + * (.data.audio_samples) ; Audio sample data } /* diff --git a/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_ospi_boot.sct b/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_ospi_boot.sct index b32496e..1e5e3f4 100644 --- a/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_ospi_boot.sct +++ b/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_ospi_boot.sct @@ -94,6 +94,7 @@ LR_ROM __ROM_BASE NOCOMPRESS __ROM_SIZE { ; load region size_region * (.bss.lcd_frame_buf) ; LCD frame Buffer. * (.bss.camera_frame_buf) ; Camera Frame Buffer * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + * (.data.audio_samples) ; Audio sample data } /* diff --git a/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_ospi_boot.sct.base@2.1.0 b/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_ospi_boot.sct.base@2.1.1 similarity index 95% rename from RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_ospi_boot.sct.base@2.1.0 rename to RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_ospi_boot.sct.base@2.1.1 index b32496e..4ab9387 100644 --- a/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_ospi_boot.sct.base@2.1.0 +++ b/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_ospi_boot.sct.base@2.1.1 @@ -94,6 +94,7 @@ LR_ROM __ROM_BASE NOCOMPRESS __ROM_SIZE { ; load region size_region * (.bss.lcd_frame_buf) ; LCD frame Buffer. * (.bss.camera_frame_buf) ; Camera Frame Buffer * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + * (.data.audio_samples) ; Audio sample data } /* diff --git a/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_tcm.sct b/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_tcm.sct index 446f7fa..d0d7ae2 100644 --- a/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_tcm.sct +++ b/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_tcm.sct @@ -18,7 +18,7 @@ *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ -#define __APP_HEAP_BASE (AlignExpr(+0, 8)) /* starts after HEAP, 8 byte aligned */ +#define __APP_HEAP_BASE (AlignExpr(+0, 8)) /* starts after HEAP, 8 byte aligned */ /*---------------------------------------------------------------------------- @@ -97,6 +97,7 @@ LR_ROM __ROM_BASE __ROM_SIZE { ; load region size_region * (.bss.lcd_frame_buf) ; LCD frame Buffer. * (.bss.camera_frame_buf) ; Camera Frame Buffer * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + * (.data.audio_samples) ; Audio sample data * (.bss.*) } diff --git a/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_tcm.sct.base@2.1.0 b/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_tcm.sct.base@2.1.1 similarity index 95% rename from RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_tcm.sct.base@2.1.0 rename to RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_tcm.sct.base@2.1.1 index 4a8f9d6..7b685e3 100644 --- a/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_tcm.sct.base@2.1.0 +++ b/RockPaperScissors/AppKit-E8_USB/Board/AppKit-E8_M55_HP/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_tcm.sct.base@2.1.1 @@ -93,6 +93,7 @@ LR_ROM __ROM_BASE __ROM_SIZE { ; load region size_region * (.bss.lcd_frame_buf) ; LCD frame Buffer. * (.bss.camera_frame_buf) ; Camera Frame Buffer * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + * (.data.audio_samples) ; Audio sample data } /* diff --git a/RockPaperScissors/AppKit-E8_USB/README.md b/RockPaperScissors/AppKit-E8_USB/README.md index dcffec6..3d37c76 100644 --- a/RockPaperScissors/AppKit-E8_USB/README.md +++ b/RockPaperScissors/AppKit-E8_USB/README.md @@ -14,8 +14,10 @@ To run this example: - `https://github.com/ARM-software/SDS-Framework/releases` - Setup the [Python environment](https://arm-software.github.io/SDS-Framework/main/utilities.html#setup) for running the SDS Utilities. -- Install Alif Ensemble CMSIS DFP pack v2.2.0 or later with: - - `cpackget add AlifSemiconductor::Ensemble@2.2.0` +- Install ExecuTorch pack v1.5.1 or later with: + - `cpackget add PyTorch::ExecuTorch@1.5.1` +- Install Alif Ensemble CMSIS DFP pack v2.2.1 or later with: + - `cpackget add AlifSemiconductor::Ensemble@2.2.1` ## Alif AppKit-E8-AIML diff --git a/RockPaperScissors/AppKit-E8_USB/SDS.cbuild-pack.yml b/RockPaperScissors/AppKit-E8_USB/SDS.cbuild-pack.yml deleted file mode 100644 index 7096d28..0000000 --- a/RockPaperScissors/AppKit-E8_USB/SDS.cbuild-pack.yml +++ /dev/null @@ -1,43 +0,0 @@ -cbuild-pack: - resolved-packs: - - resolved-pack: ARM::CMSIS@6.3.0 - selected-by-pack: - - ARM::CMSIS@^6.2.0 - - ARM::CMSIS@^6.3.0 - - resolved-pack: ARM::CMSIS-Compiler@2.3.0 - selected-by-pack: - - ARM::CMSIS-Compiler@^2.1.0 - - resolved-pack: ARM::CMSIS-Driver@2.10.0 - selected-by-pack: - - ARM::CMSIS-Driver@^2.10.0 - - resolved-pack: ARM::CMSIS-NN@7.0.0 - selected-by-pack: - - ARM::CMSIS-NN@^7.0.0 - - resolved-pack: ARM::CMSIS-RTX@5.9.1 - selected-by-pack: - - ARM::CMSIS-RTX@^5.9.1 - - resolved-pack: ARM::SDS@3.1.0 - selected-by-pack: - - ARM::SDS@^3.1.0-0 - - resolved-pack: ARM::SSE_320_BSP@1.1.0 - selected-by-pack: - - ARM::SSE_320_BSP@1.1.0 - - resolved-pack: ARM::ethos-u-core-driver@1.26.2 - selected-by-pack: - - ARM::ethos-u-core-driver@^1.26.2 - - resolved-pack: AlifSemiconductor::Ensemble@2.2.0 - selected-by-pack: - - AlifSemiconductor::Ensemble@^2.2.0-0 - - resolved-pack: Keil::MDK-Middleware@8.3.0 - selected-by-pack: - - Keil::MDK-Middleware@^8.0.0 - - resolved-pack: PyTorch::ExecuTorch@1.4.1 - selected-by-pack: - - PyTorch::ExecuTorch - - PyTorch::ExecuTorch@1.4.1 - - resolved-pack: SEGGER::RTT@8.58.0 - selected-by-pack: - - SEGGER::RTT@^8.58.0 - - resolved-pack: SEGGER::SystemView@4.12.0 - selected-by-pack: - - SEGGER::SystemView@^4.12.0 diff --git a/RockPaperScissors/AppKit-E8_USB/SDS.csolution.yml b/RockPaperScissors/AppKit-E8_USB/SDS.csolution.yml index defc67d..4c2cc74 100644 --- a/RockPaperScissors/AppKit-E8_USB/SDS.csolution.yml +++ b/RockPaperScissors/AppKit-E8_USB/SDS.csolution.yml @@ -16,7 +16,7 @@ solution: packs: - pack: ARM::SDS@^3.1.0-0 - - pack: AlifSemiconductor::Ensemble@^2.2.0-0 + - pack: AlifSemiconductor::Ensemble@^2.2.1-0 - pack: ARM::SSE_320_BSP@1.1.0 # List different hardware targets that are used to deploy the solution. diff --git a/RockPaperScissors/AppKit-E8_USB/algorithm/ML/ai_layer/ai_layer.clayer.yml b/RockPaperScissors/AppKit-E8_USB/algorithm/ML/ai_layer/ai_layer.clayer.yml index f62d8f8..0c7c815 100644 --- a/RockPaperScissors/AppKit-E8_USB/algorithm/ML/ai_layer/ai_layer.clayer.yml +++ b/RockPaperScissors/AppKit-E8_USB/algorithm/ML/ai_layer/ai_layer.clayer.yml @@ -3,7 +3,7 @@ layer: description: Machine Learning layer for the Rock-Paper-Scissors game, utilizing a pre-trained model for inference on an Ethos-U NPU. packs: - - pack: PyTorch::ExecuTorch@1.4.1 + - pack: PyTorch::ExecuTorch@^1.5.1 define: - ET_LOG_ENABLED : 0