From e8ad43d2c59c6a107e2b112683c7fca9f821aef7 Mon Sep 17 00:00:00 2001
From: Dmitry Ilyin <6576495+widgetii@users.noreply.github.com>
Date: Sat, 17 Oct 2026 13:34:38 +0300
Subject: [PATCH] ARM: dts: hi3536dv100: give the hibvt i2c controller its
 interrupt

i2c@120c0000 has no interrupts property, so i2c-hibvt runs in polling
mode, and a transfer that never completes spins udelay(50) up to 0x10000
times -- 3.3 s per transfer on the SoC's only core -- before "wait idle
timeout". An NVR has nothing on that bus: one ipctool report issued 38
such transfers and the board stopped answering the network for two
minutes.

The Hi3536DV100 data sheet lists I2C as interrupt bit 42, which is SPI 10.
Checked on a lab NVR: setting the controller's INTR_EN made GICD_ISPENDR1
bit 10 (ID 42) pending, and clearing it cleared the bit. The same change on
hi3516cv500/hi3516dv300 was run on a Hi3516AV300, where the sensor works
over i2c in interrupt mode.
---
 arch/arm/boot/dts/hi3536dv100.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/hi3536dv100.dtsi b/arch/arm/boot/dts/hi3536dv100.dtsi
index 968d91db45f..cdd965cf56a 100644
--- a/arch/arm/boot/dts/hi3536dv100.dtsi
+++ b/arch/arm/boot/dts/hi3536dv100.dtsi
@@ -170,6 +170,7 @@
 			compatible = "hisilicon,hi3536dv100-i2c",
 					"hisilicon,hibvt-i2c";
 			reg = <0x120c0000 0x1000>;
+			interrupts = <0 10 4>;
 			clocks = <&clock HI3536DV100_SYSAPB_CLK>;
 			status = "disabled";
 		};