From dedd1d196b0642e2b9938e00be23f5261e9d912c Mon Sep 17 00:00:00 2001 From: Minxing Chu Date: Mon, 26 Oct 2026 01:59:22 -0400 Subject: [PATCH] Add Code Behind the Layout benchmark: generator-edit agents on SKY130 Code and frozen configurations for E1 (action level), E2 (evaluation fidelity), E3 (family test rules), E4 (point/family SFT and DPO) and E5 (cost). Frozen task packets and the E4 training set are fetched with scripts/fetch_data.sh. --- benchmarks/code_behind_layout/.gitignore | 12 + benchmarks/code_behind_layout/README.md | 95 + .../e2_four_source_statistics_v1.json | 94 + .../c01_collection_final_preparation.json | 1715 +++ .../c01_collection_preparation.json | 1715 +++ .../c01_collection_v2_preparation.json | 117 + ...ilure_minimal_gpt_teacher_preparation.json | 107 + .../c01_family/configurations.json | 233 + .../c01_family/contracts/anchor.json | 74 + .../c01_family/contracts/dev_l120.json | 74 + .../c01_family/contracts/dev_nf1_l030.json | 74 + .../c01_family/contracts/dev_nf2_l060.json | 74 + .../c01_family/contracts/dev_nf3_l045.json | 74 + .../c01_family/contracts/dev_nf6_l060.json | 74 + .../c01_family/contracts/dev_nf8_l090.json | 74 + .../c01_family/contracts/dev_w075_l045.json | 74 + .../c01_family/contracts/dev_w100_l060.json | 74 + .../c01_family/references/anchor.spice | 10 + .../c01_family/references/dev_l120.spice | 10 + .../c01_family/references/dev_nf1_l030.spice | 4 + .../c01_family/references/dev_nf2_l060.spice | 6 + .../c01_family/references/dev_nf3_l045.spice | 8 + .../c01_family/references/dev_nf6_l060.spice | 14 + .../c01_family/references/dev_nf8_l090.spice | 18 + .../c01_family/references/dev_w075_l045.spice | 10 + .../c01_family/references/dev_w100_l060.spice | 10 + .../c01_gpt_teacher_frozen_manifest.json | 152 + .../circuit_input.json | 62 + .../configurations.json | 215 + .../contracts/anchor.json | 99 + .../contracts/dev_nf2_l030.json | 99 + .../contracts/dev_nf2_l060.json | 99 + .../contracts/dev_nf2_l090.json | 99 + .../contracts/dev_nf4_l030.json | 99 + .../contracts/dev_nf4_l090.json | 99 + .../contracts/dev_nf6_l030.json | 99 + .../contracts/dev_nf6_l060.json | 99 + .../contracts/dev_nf6_l090.json | 99 + .../qualification_commands.json | 204 + .../references/anchor.spice | 10 + .../references/dev_nf2_l030.spice | 6 + .../references/dev_nf2_l060.spice | 6 + .../references/dev_nf2_l090.spice | 6 + .../references/dev_nf4_l030.spice | 10 + .../references/dev_nf4_l090.spice | 10 + .../references/dev_nf6_l030.spice | 14 + .../references/dev_nf6_l060.spice | 14 + .../references/dev_nf6_l090.spice | 14 + .../circuit_input.json | 62 + .../configurations.json | 275 + .../contracts/anchor.json | 105 + .../contracts/dev_n2_2.json | 105 + .../contracts/dev_n2_4.json | 105 + .../contracts/dev_n2_6.json | 105 + .../contracts/dev_n4_2.json | 105 + .../contracts/dev_n4_6.json | 105 + .../contracts/dev_n6_2.json | 105 + .../contracts/dev_n6_4.json | 105 + .../contracts/dev_n6_6.json | 105 + .../qualification_commands.json | 204 + .../references/anchor.spice | 10 + .../references/dev_n2_2.spice | 6 + .../references/dev_n2_4.spice | 8 + .../references/dev_n2_6.spice | 10 + .../references/dev_n4_2.spice | 8 + .../references/dev_n4_6.spice | 12 + .../references/dev_n6_2.spice | 10 + .../references/dev_n6_4.spice | 12 + .../references/dev_n6_6.spice | 14 + .../circuit_input.json | 62 + .../configurations.json | 302 + .../contracts/long_anchor.json | 106 + .../contracts/long_dev_n2_2.json | 106 + .../contracts/long_dev_n2_4.json | 106 + .../contracts/long_dev_n2_6.json | 106 + .../contracts/long_dev_n4_2.json | 106 + .../contracts/long_dev_n4_6.json | 106 + .../contracts/long_dev_n6_2.json | 106 + .../contracts/long_dev_n6_4.json | 106 + .../contracts/long_dev_n6_6.json | 106 + .../references/long_anchor.spice | 10 + .../references/long_dev_n2_2.spice | 6 + .../references/long_dev_n2_4.spice | 8 + .../references/long_dev_n2_6.spice | 10 + .../references/long_dev_n4_2.spice | 8 + .../references/long_dev_n4_6.spice | 12 + .../references/long_dev_n6_2.spice | 10 + .../references/long_dev_n6_4.spice | 12 + .../references/long_dev_n6_6.spice | 14 + .../circuit_input.json | 62 + .../configurations.json | 276 + .../contracts/wide_anchor.json | 105 + .../contracts/wide_dev_n2_2.json | 105 + .../contracts/wide_dev_n2_4.json | 105 + .../contracts/wide_dev_n2_6.json | 105 + .../contracts/wide_dev_n4_2.json | 105 + .../contracts/wide_dev_n4_6.json | 105 + .../contracts/wide_dev_n6_2.json | 105 + .../contracts/wide_dev_n6_4.json | 105 + .../contracts/wide_dev_n6_6.json | 105 + .../qualification_commands.json | 248 + .../references/wide_anchor.spice | 10 + .../references/wide_dev_n2_2.spice | 6 + .../references/wide_dev_n2_4.spice | 8 + .../references/wide_dev_n2_6.spice | 10 + .../references/wide_dev_n4_2.spice | 8 + .../references/wide_dev_n4_6.spice | 12 + .../references/wide_dev_n6_2.spice | 10 + .../references/wide_dev_n6_4.spice | 12 + .../references/wide_dev_n6_6.spice | 14 + .../c01_rule_collection_preparation.json | 118 + .../development/c02_family/circuit_input.json | 86 + .../c02_family/configurations.json | 280 + .../c02_family/contracts/anchor.json | 87 + .../c02_family/contracts/dev_len045.json | 87 + .../c02_family/contracts/dev_len090.json | 87 + .../c02_family/contracts/dev_nf_1half.json | 87 + .../contracts/dev_nf_3quarters.json | 87 + .../c02_family/contracts/dev_nf_double.json | 87 + .../c02_family/contracts/dev_nf_half.json | 87 + .../c02_family/contracts/dev_unit075.json | 87 + .../c02_family/contracts/dev_unit100.json | 87 + .../c02_family/references/anchor.spice | 34 + .../c02_family/references/dev_len045.spice | 34 + .../c02_family/references/dev_len090.spice | 34 + .../c02_family/references/dev_nf_1half.spice | 50 + .../references/dev_nf_3quarters.spice | 26 + .../c02_family/references/dev_nf_double.spice | 66 + .../c02_family/references/dev_nf_half.spice | 18 + .../c02_family/references/dev_unit075.spice | 34 + .../c02_family/references/dev_unit100.spice | 34 + .../c03_cfg1_family/circuit_input.json | 76 + .../c03_cfg1_family/configurations.json | 248 + .../c03_cfg1_family/contracts/anchor.json | 100 + .../c03_cfg1_family/contracts/dev_len075.json | 100 + .../c03_cfg1_family/contracts/dev_len150.json | 100 + .../contracts/dev_nf_1half.json | 100 + .../contracts/dev_nf_3quarters.json | 100 + .../contracts/dev_nf_double.json | 100 + .../contracts/dev_nf_half.json | 100 + .../contracts/dev_unit075.json | 100 + .../contracts/dev_unit100.json | 100 + .../c03_cfg1_family/references/anchor.spice | 38 + .../references/dev_len075.spice | 38 + .../references/dev_len150.spice | 38 + .../references/dev_nf_1half.spice | 56 + .../references/dev_nf_3quarters.spice | 29 + .../references/dev_nf_double.spice | 74 + .../references/dev_nf_half.spice | 20 + .../references/dev_unit075.spice | 38 + .../references/dev_unit100.spice | 38 + .../c03_cfg2_family/circuit_input.json | 76 + .../c03_cfg2_family/configurations.json | 248 + .../c03_cfg2_family/contracts/anchor.json | 100 + .../c03_cfg2_family/contracts/dev_len075.json | 100 + .../c03_cfg2_family/contracts/dev_len150.json | 100 + .../c03_cfg2_family/contracts/dev_len200.json | 100 + .../contracts/dev_nf_1half.json | 100 + .../contracts/dev_nf_3quarters.json | 100 + .../contracts/dev_nf_double.json | 100 + .../contracts/dev_nf_half.json | 100 + .../contracts/dev_unit075.json | 100 + .../c03_cfg2_family/references/anchor.spice | 14 + .../references/dev_len075.spice | 14 + .../references/dev_len150.spice | 14 + .../references/dev_len200.spice | 14 + .../references/dev_nf_1half.spice | 20 + .../references/dev_nf_3quarters.spice | 11 + .../references/dev_nf_double.spice | 26 + .../references/dev_nf_half.spice | 8 + .../references/dev_unit075.spice | 14 + .../c03_cfg3_family/circuit_input.json | 76 + .../c03_cfg3_family/configurations.json | 248 + .../c03_cfg3_family/contracts/anchor.json | 100 + .../c03_cfg3_family/contracts/dev_len075.json | 100 + .../c03_cfg3_family/contracts/dev_len150.json | 100 + .../contracts/dev_nf_1half.json | 100 + .../contracts/dev_nf_3quarters.json | 100 + .../contracts/dev_nf_double.json | 100 + .../contracts/dev_nf_half.json | 100 + .../contracts/dev_unit075.json | 100 + .../contracts/dev_unit100.json | 100 + .../c03_cfg3_family/references/anchor.spice | 26 + .../references/dev_len075.spice | 26 + .../references/dev_len150.spice | 26 + .../references/dev_nf_1half.spice | 38 + .../references/dev_nf_3quarters.spice | 20 + .../references/dev_nf_double.spice | 50 + .../references/dev_nf_half.spice | 14 + .../references/dev_unit075.spice | 26 + .../references/dev_unit100.spice | 26 + .../development/c03_family/circuit_input.json | 76 + .../c03_family/configurations.json | 246 + .../c03_family/contracts/anchor.json | 100 + .../c03_family/contracts/dev_len075.json | 100 + .../c03_family/contracts/dev_len150.json | 100 + .../c03_family/contracts/dev_nf_1half.json | 100 + .../contracts/dev_nf_3quarters.json | 100 + .../c03_family/contracts/dev_nf_double.json | 100 + .../c03_family/contracts/dev_nf_half.json | 100 + .../c03_family/contracts/dev_unit075.json | 100 + .../c03_family/contracts/dev_unit100.json | 100 + .../c03_family/references/anchor.spice | 26 + .../c03_family/references/dev_len075.spice | 26 + .../c03_family/references/dev_len150.spice | 26 + .../c03_family/references/dev_nf_1half.spice | 38 + .../references/dev_nf_3quarters.spice | 20 + .../c03_family/references/dev_nf_double.spice | 50 + .../c03_family/references/dev_nf_half.spice | 14 + .../c03_family/references/dev_unit075.spice | 26 + .../c03_family/references/dev_unit100.spice | 26 + .../c04_cfg1_family/circuit_input.json | 64 + .../c04_cfg1_family/configurations.json | 203 + .../c04_cfg1_family/contracts/anchor.json | 93 + .../c04_cfg1_family/contracts/dev_len075.json | 93 + .../c04_cfg1_family/contracts/dev_len150.json | 93 + .../c04_cfg1_family/contracts/dev_len200.json | 93 + .../contracts/dev_nf_1half.json | 93 + .../contracts/dev_nf_double.json | 93 + .../contracts/dev_nf_half.json | 93 + .../contracts/dev_unit075.json | 93 + .../contracts/dev_unit100.json | 93 + .../c04_cfg1_family/references/anchor.spice | 20 + .../references/dev_len075.spice | 20 + .../references/dev_len150.spice | 20 + .../references/dev_len200.spice | 20 + .../references/dev_nf_1half.spice | 29 + .../references/dev_nf_double.spice | 38 + .../references/dev_nf_half.spice | 11 + .../references/dev_unit075.spice | 20 + .../references/dev_unit100.spice | 20 + .../c04_cfg2_family/circuit_input.json | 64 + .../c04_cfg2_family/configurations.json | 203 + .../c04_cfg2_family/contracts/anchor.json | 93 + .../c04_cfg2_family/contracts/dev_len075.json | 93 + .../c04_cfg2_family/contracts/dev_len150.json | 93 + .../c04_cfg2_family/contracts/dev_len200.json | 93 + .../contracts/dev_nf_1half.json | 93 + .../contracts/dev_nf_double.json | 93 + .../contracts/dev_nf_half.json | 93 + .../contracts/dev_nf_triple.json | 93 + .../contracts/dev_unit075.json | 93 + .../c04_cfg2_family/references/anchor.spice | 8 + .../references/dev_len075.spice | 8 + .../references/dev_len150.spice | 8 + .../references/dev_len200.spice | 8 + .../references/dev_nf_1half.spice | 11 + .../references/dev_nf_double.spice | 14 + .../references/dev_nf_half.spice | 5 + .../references/dev_nf_triple.spice | 20 + .../references/dev_unit075.spice | 8 + .../c04_cfg3_family/circuit_input.json | 64 + .../c04_cfg3_family/configurations.json | 203 + .../c04_cfg3_family/contracts/anchor.json | 93 + .../c04_cfg3_family/contracts/dev_len075.json | 93 + .../c04_cfg3_family/contracts/dev_len150.json | 93 + .../contracts/dev_nf_1half.json | 93 + .../contracts/dev_nf_3quarters.json | 93 + .../contracts/dev_nf_double.json | 93 + .../contracts/dev_nf_half.json | 93 + .../contracts/dev_unit075.json | 93 + .../contracts/dev_unit100.json | 93 + .../c04_cfg3_family/references/anchor.spice | 14 + .../references/dev_len075.spice | 14 + .../references/dev_len150.spice | 14 + .../references/dev_nf_1half.spice | 20 + .../references/dev_nf_3quarters.spice | 11 + .../references/dev_nf_double.spice | 26 + .../references/dev_nf_half.spice | 8 + .../references/dev_unit075.spice | 14 + .../references/dev_unit100.spice | 14 + .../development/c04_family/circuit_input.json | 64 + .../c04_family/configurations.json | 201 + .../c04_family/contracts/anchor.json | 93 + .../c04_family/contracts/dev_len075.json | 93 + .../c04_family/contracts/dev_len150.json | 93 + .../c04_family/contracts/dev_nf_1half.json | 93 + .../contracts/dev_nf_3quarters.json | 93 + .../c04_family/contracts/dev_nf_double.json | 93 + .../c04_family/contracts/dev_nf_half.json | 93 + .../c04_family/contracts/dev_unit075.json | 93 + .../c04_family/contracts/dev_unit100.json | 93 + .../c04_family/references/anchor.spice | 14 + .../c04_family/references/dev_len075.spice | 14 + .../c04_family/references/dev_len150.spice | 14 + .../c04_family/references/dev_nf_1half.spice | 20 + .../references/dev_nf_3quarters.spice | 11 + .../c04_family/references/dev_nf_double.spice | 26 + .../c04_family/references/dev_nf_half.spice | 8 + .../c04_family/references/dev_unit075.spice | 14 + .../c04_family/references/dev_unit100.spice | 14 + .../c05_collection_preparation.json | 1650 +++ .../c05_family/configurations.json | 189 + .../c05_family/contracts/anchor.json | 72 + .../c05_family/contracts/dev_len045.json | 72 + .../c05_family/contracts/dev_len060.json | 72 + .../c05_family/contracts/dev_nf_1half.json | 72 + .../contracts/dev_nf_3quarters.json | 72 + .../c05_family/contracts/dev_nf_double.json | 72 + .../c05_family/contracts/dev_nf_half.json | 72 + .../c05_family/contracts/dev_unit075.json | 72 + .../c05_family/contracts/dev_unit100.json | 72 + .../c05_family/references/anchor.spice | 14 + .../c05_family/references/dev_len045.spice | 14 + .../c05_family/references/dev_len060.spice | 14 + .../c05_family/references/dev_nf_1half.spice | 20 + .../references/dev_nf_3quarters.spice | 11 + .../c05_family/references/dev_nf_double.spice | 26 + .../c05_family/references/dev_nf_half.spice | 8 + .../c05_family/references/dev_unit075.spice | 14 + .../c05_family/references/dev_unit100.spice | 14 + .../c05_minimal_gpt_teacher_preparation.json | 75 + .../c05_observed_states_preparation.json | 14 + .../c05_rule_collection_preparation.json | 118 + .../c06_cfg1_family/circuit_input.json | 90 + .../c06_cfg1_family/configurations.json | 293 + .../c06_cfg1_family/contracts/anchor.json | 113 + .../c06_cfg1_family/contracts/dev_len075.json | 113 + .../c06_cfg1_family/contracts/dev_len150.json | 113 + .../c06_cfg1_family/contracts/dev_len200.json | 113 + .../contracts/dev_nf_1half.json | 113 + .../contracts/dev_nf_double.json | 113 + .../contracts/dev_nf_half.json | 113 + .../contracts/dev_unit075.json | 113 + .../contracts/dev_unit100.json | 113 + .../c06_cfg1_family/references/anchor.spice | 38 + .../references/dev_len075.spice | 38 + .../references/dev_len150.spice | 38 + .../references/dev_len200.spice | 38 + .../references/dev_nf_1half.spice | 56 + .../references/dev_nf_double.spice | 74 + .../references/dev_nf_half.spice | 20 + .../references/dev_unit075.spice | 38 + .../references/dev_unit100.spice | 38 + .../c06_cfg2_family/circuit_input.json | 90 + .../c06_cfg2_family/configurations.json | 293 + .../c06_cfg2_family/contracts/anchor.json | 113 + .../c06_cfg2_family/contracts/dev_len075.json | 113 + .../c06_cfg2_family/contracts/dev_len150.json | 113 + .../c06_cfg2_family/contracts/dev_len200.json | 113 + .../contracts/dev_nf_1half.json | 113 + .../contracts/dev_nf_double.json | 113 + .../contracts/dev_nf_half.json | 113 + .../contracts/dev_nf_triple.json | 113 + .../contracts/dev_unit075.json | 113 + .../c06_cfg2_family/references/anchor.spice | 14 + .../references/dev_len075.spice | 14 + .../references/dev_len150.spice | 14 + .../references/dev_len200.spice | 14 + .../references/dev_nf_1half.spice | 20 + .../references/dev_nf_double.spice | 26 + .../references/dev_nf_half.spice | 8 + .../references/dev_nf_triple.spice | 38 + .../references/dev_unit075.spice | 14 + .../c06_cfg3_family/circuit_input.json | 90 + .../c06_cfg3_family/configurations.json | 293 + .../c06_cfg3_family/contracts/anchor.json | 113 + .../c06_cfg3_family/contracts/dev_len075.json | 113 + .../c06_cfg3_family/contracts/dev_len150.json | 113 + .../contracts/dev_nf_1half.json | 113 + .../contracts/dev_nf_3quarters.json | 113 + .../contracts/dev_nf_double.json | 113 + .../contracts/dev_nf_half.json | 113 + .../contracts/dev_unit075.json | 113 + .../contracts/dev_unit100.json | 113 + .../c06_cfg3_family/references/anchor.spice | 26 + .../references/dev_len075.spice | 26 + .../references/dev_len150.spice | 26 + .../references/dev_nf_1half.spice | 38 + .../references/dev_nf_3quarters.spice | 20 + .../references/dev_nf_double.spice | 50 + .../references/dev_nf_half.spice | 14 + .../references/dev_unit075.spice | 26 + .../references/dev_unit100.spice | 26 + .../development/c06_family/circuit_input.json | 90 + .../c06_family/configurations.json | 291 + .../c06_family/contracts/anchor.json | 113 + .../c06_family/contracts/dev_len075.json | 113 + .../c06_family/contracts/dev_len150.json | 113 + .../c06_family/contracts/dev_nf_1half.json | 113 + .../contracts/dev_nf_3quarters.json | 113 + .../c06_family/contracts/dev_nf_double.json | 113 + .../c06_family/contracts/dev_nf_half.json | 113 + .../c06_family/contracts/dev_unit075.json | 113 + .../c06_family/contracts/dev_unit100.json | 113 + .../c06_family/references/anchor.spice | 26 + .../c06_family/references/dev_len075.spice | 26 + .../c06_family/references/dev_len150.spice | 26 + .../c06_family/references/dev_nf_1half.spice | 38 + .../references/dev_nf_3quarters.spice | 20 + .../c06_family/references/dev_nf_double.spice | 50 + .../c06_family/references/dev_nf_half.spice | 14 + .../c06_family/references/dev_unit075.spice | 26 + .../c06_family/references/dev_unit100.spice | 26 + .../development/c07_family/circuit_input.json | 93 + .../c07_family/configurations.json | 280 + .../c07_family/contracts/anchor.json | 84 + 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908 ++ .../fvf/task_packet.json | 478 + .../index.json | 91 + .../legacy_miller/task.json | 1016 ++ .../legacy_miller/task_packet.json | 498 + .../configs/training/backbone_cache.json | 89 + ...claude_span_20261023T104641Z_physical.json | 28 + ...claude_span_20261023T115051Z_physical.json | 28 + ...claude_span_20261023T133414Z_physical.json | 28 + ...claude_span_20261024T090302Z_physical.json | 46 + ...tbook_claude_span_round2a_v1_physical.json | 28 + .../textbook_claude_span_v1_physical_v2.json | 64 + .../training/e4_pools_20261024T172052Z.json | 2760 ++++ .../configs/training/environment.lock.json | 51 + .../configs/training/formal_16k.json | 61 + .../configs/training/manifest.draft.json | 17 + .../configs/training/pilot.json | 25 + .../manifests/c01_collection_v1/backup.json | 6 + .../c01_collection_v1/collection.json | 52 + .../c01_collection_v1/freeze_identity.json | 6 + .../c01_collection_v1/label_rule.json | 16 + .../manifests/c01_collection_v2/backup.json | 6 + .../c01_collection_v2/collection.json | 129 + .../c01_collection_v2/freeze_identity.json | 8 + .../c01_collection_v2/label_rule.json | 16 + .../teacher_context_preflight.json | 32 + .../manifests/c01_gpt_teacher_v1/backup.json | 6 + .../c01_gpt_teacher_v1/collection.json | 152 + .../c01_gpt_teacher_v1/freeze_identity.json | 8 + .../c01_gpt_teacher_v1/label_rule.json | 16 + .../teacher_context_preflight.json | 12 + .../data/manifests/c01_rules_v1/backup.json | 6 + .../manifests/c01_rules_v1/collection.json | 57 + .../c01_rules_v1/freeze_identity.json | 9 + .../manifests/c01_rules_v1/label_rule.json | 16 + .../manifests/c05_collection_v1/backup.json | 6 + .../c05_collection_v1/calibration.json | 27 + .../c05_collection_v1/collection.json | 57 + .../c05_collection_v1/freeze_identity.json | 9 + .../c05_collection_v1/label_rule.json | 16 + .../data/manifests/c05_rules_v1/backup.json | 6 + .../manifests/c05_rules_v1/calibration.json | 27 + .../manifests/c05_rules_v1/collection.json | 57 + .../c05_rules_v1/freeze_identity.json | 10 + .../manifests/c05_rules_v1/label_rule.json | 16 + .../manifests/c08_collection_v1/backup.json | 6 + .../c08_collection_v1/calibration.json | 27 + .../c08_collection_v1/collection.json | 57 + .../c08_collection_v1/freeze_identity.json | 9 + .../c08_collection_v1/label_rule.json | 16 + .../data/manifests/c08_rules_v1/backup.json | 6 + .../manifests/c08_rules_v1/calibration.json | 27 + .../manifests/c08_rules_v1/collection.json | 57 + .../c08_rules_v1/freeze_identity.json | 10 + .../manifests/c08_rules_v1/label_rule.json | 16 + .../data/splits/registry.json | 2448 ++++ .../data/splits/registry.v2.proposal.json | 2159 +++ .../code_behind_layout/docs/e1_protocol.md | 27 + .../code_behind_layout/docs/e3_protocol.md | 108 + .../docs/measurement_interface.md | 31 + .../code_behind_layout/docs/protocol.md | 68 + .../docs/protocol_amendments.md | 74 + .../reproducibility/glayout_fixes.patch | 345 + .../code_behind_layout/requirements.txt | 41 + .../e3_fidelity_control_20261019/controls.py | 67 + .../qualified_default_fullflow_v5.py | 334 + .../scripts/account_recorded_resources.py | 94 + .../code_behind_layout/scripts/analyze_e1.py | 58 + .../scripts/analyze_e1_partial_interface.py | 192 + .../scripts/analyze_e1_scope.py | 31 + .../scripts/analyze_e2_development.py | 74 + .../code_behind_layout/scripts/analyze_e3.py | 33 + .../scripts/analyze_e3_qor_supplement.py | 35 + .../code_behind_layout/scripts/analyze_e4.py | 43 + .../scripts/analyze_e5_costs.py | 214 + .../scripts/analyze_phase0.py | 76 + .../scripts/analyze_protocol_results.py | 192 + .../scripts/archive_e1_episode.py | 118 + .../scripts/archive_e2_run.py | 117 + .../scripts/archive_e3_evidence.py | 268 + .../scripts/assemble_e4_methods_draft.py | 42 + .../scripts/audit_e4_cold_run.py | 319 + .../scripts/audit_matched_T0_increment.py | 136 + .../scripts/audit_ota_analyses.py | 44 + .../scripts/audit_textbook_pin_order.py | 43 + .../scripts/audit_train_device_intent.py | 50 + .../scripts/audit_train_pair_nf_rc.py | 115 + .../scripts/backup_completed_phase0.py | 53 + .../scripts/backup_sealed_e2_development.py | 48 + .../scripts/bind_local_trajectory_drafts.py | 110 + .../scripts/build_e3_risk_model.py | 166 + .../code_behind_layout/scripts/build_magic.py | 33 + .../scripts/build_promotion_calibration.py | 108 + .../scripts/c01_collection_evaluator.py | 40 + .../calibrate_ordinary_inference_memory.py | 160 + .../scripts/calibrate_policy_state.py | 43 + .../scripts/collect_matched_t0_proposals.py | 106 + .../scripts/collect_planning_trajectories.py | 474 + .../scripts/collect_textbook_opus_spans.py | 134 + .../scripts/collect_train_span_proposals.py | 139 + .../scripts/collect_training.py | 467 + .../scripts/collect_training_v2.py | 471 + .../scripts/common_source_probe.py | 124 + .../scripts/compact_feedback_calibration.py | 128 + .../scripts/compare_research_sources.py | 54 + .../scripts/component_oracle_geometry.py | 18 + .../scripts/component_oracle_witness.py | 57 + .../scripts/component_state_qualification.py | 60 + .../scripts/component_task_baseline.py | 171 + .../scripts/component_task_evaluator.py | 105 + .../corpus_additional_capsule_smoke.py | 77 + .../corpus_additional_collection_evaluator.py | 34 + .../corpus_additional_domain_summary.py | 32 + .../scripts/corpus_c01_nf_domain_queue.py | 63 + .../scripts/corpus_c02_nf_followup_queue.py | 58 + .../corpus_component_collection_evaluator.py | 47 + .../scripts/corpus_component_domain_queue.py | 54 + .../corpus_component_domain_summary.py | 38 + .../corpus_component_recovery_queue.py | 83 + .../scripts/corpus_component_train_pilot.py | 49 + .../scripts/corpus_family_batch.py | 41 + .../scripts/corpus_family_summary.py | 23 + .../scripts/corpus_family_yield_summary.py | 73 + .../corpus_gpt_action_teacher_service.py | 113 + .../corpus_gpt_planning_teacher_service.py | 114 + .../scripts/corpus_gpt_teacher_service.py | 131 + .../scripts/corpus_isolated_evaluate.py | 155 + .../scripts/corpus_long_nf_ideal.py | 58 + .../scripts/corpus_matched_pair_ideal.py | 76 + .../scripts/corpus_measure_existing.py | 24 + .../scripts/corpus_model_candidates.py | 103 + .../scripts/corpus_nf_ideal_control.py | 52 + .../scripts/corpus_patch_audit.py | 24 + .../scripts/corpus_rule_proposer.py | 45 + .../scripts/corpus_rule_proposer_v2.py | 41 + .../corpus_textbook_collection_evaluator.py | 46 + .../scripts/corpus_textbook_domain_queue.py | 73 + .../scripts/corpus_textbook_domain_summary.py | 37 + .../scripts/corpus_textbook_train_pilot.py | 53 + .../corpus_wide_nf_qualification_queue.py | 43 + .../scripts/corpus_yield_pilot.py | 284 + .../scripts/custom_ota_build.py | 42 + .../scripts/custom_ota_miller_build.py | 47 + .../scripts/custom_ota_miller_schematic.py | 153 + .../scripts/custom_ota_schematic.py | 174 + .../scripts/declare_e4_pools.py | 78 + .../scripts/dedup_run_sources.py | 53 + .../scripts/derive_training_selection_v2.py | 149 + .../scripts/device_full_flow.py | 95 + .../scripts/device_port_inventory.py | 8 + .../scripts/device_reextract.py | 63 + .../scripts/diagnose_e3_patch_rejection.py | 118 + .../scripts/direct_drc_probe.py | 17 + .../scripts/domain_smoke.py | 171 + .../scripts/drc_parser_calibration.py | 25 + .../scripts/e1_development_pilot.py | 327 + .../scripts/e1_engineering_source_control.py | 51 + .../scripts/e1_exact_grid_domain.py | 81 + .../scripts/e1_g2_composition_control.py | 38 + .../scripts/e1_matched_runner.py | 395 + .../scripts/e1_mechanical_smoke.py | 41 + .../scripts/e1_packet_preflight.py | 33 + .../scripts/e1_pcell_prepare.py | 72 + .../scripts/e1_primitive_handoff.py | 90 + .../scripts/e1_primitive_intent_audit.py | 30 + .../scripts/e1_schematic_feasibility.py | 159 + .../scripts/e1_schematic_parallel.py | 64 + .../scripts/e1_scope_history_preflight.py | 66 + .../scripts/e1_scope_pilot.py | 92 + .../scripts/e1_scope_proposal_preflight.py | 69 + .../scripts/e1_scope_runner.py | 211 + .../scripts/e1_trusted_evaluator.py | 139 + .../scripts/e2_apply_transient_completion.py | 69 + .../scripts/e2_cached_evaluator.py | 102 + .../scripts/e2_default_source_controls.py | 115 + .../scripts/e2_development_pilot.py | 569 + .../scripts/e2_execution.py | 432 + .../scripts/e2_execution_prepare.py | 196 + .../scripts/e2_four_source.py | 576 + .../scripts/e2_geometry_evaluator.py | 41 + .../scripts/e2_mask_geometry_smoke.py | 50 + .../scripts/e2_mask_stage.py | 55 + .../scripts/e2_nominal_bench.py | 121 + .../e2_sizing_physical_qualification.py | 157 + .../scripts/e2_sizing_prequalification.py | 200 + .../scripts/e2_spice_process_profile.py | 49 + .../scripts/e2_stage_prepare.py | 115 + .../scripts/e2_stage_smoke.py | 83 + .../scripts/e2_telescopic_adapter.py | 109 + .../scripts/e2_telescopic_frozen_bench.py | 155 + .../scripts/e2_telescopic_stage_smoke.py | 167 + .../scripts/e2_transient_completion.py | 240 + .../scripts/e3_anchor_qualify.py | 160 + .../scripts/e3_baseline_control.py | 167 + .../code_behind_layout/scripts/e3_episode.py | 555 + .../scripts/e3_expand_parameters.py | 72 + .../scripts/e3_fidelity_episode.py | 257 + .../scripts/e3_fidelity_point.py | 333 + .../scripts/e3_gateway_control.py | 68 + .../scripts/e3_generation_qualify.py | 121 + .../scripts/e3_history_preflight.py | 93 + .../scripts/e3_instance_episode.py | 655 + .../scripts/e3_nominal_objective.py | 38 + .../scripts/e3_original_baseline.py | 438 + .../scripts/e3_parameter_binding_check.py | 70 + .../scripts/e3_parameter_episode.py | 437 + .../scripts/e3_physical_point.py | 92 + .../scripts/e3_remaining_ota_qualify.py | 172 + .../scripts/e3_summarize_qualification.py | 85 + .../scripts/e3_task_prepare.py | 225 + .../scripts/e3_trusted_objective.py | 39 + .../scripts/e4_checkpoint_validation.py | 59 + .../scripts/e4_validation_mirror_domain.py | 558 + .../scripts/evaluate_matched_t0_proposals.py | 628 + ...valuate_natural_terminal_span_proposals.py | 305 + .../scripts/evaluate_nf_joint_pool.py | 280 + .../scripts/evaluate_nf_span_proposals.py | 257 + .../scripts/evaluate_ratio_span_proposals.py | 298 + .../scripts/evaluate_textbook_opus_spans.py | 431 + .../evaluate_textbook_opus_spans_v2.py | 461 + .../scripts/evaluate_train_span_proposals.py | 447 + .../scripts/executor_smoke.py | 301 + .../code_behind_layout/scripts/fetch_data.sh | 7 + .../scripts/five_t_feedback_calibration.py | 128 + .../scripts/follower_characterization.py | 155 + .../freeze_action_teacher_collection.py | 53 + .../scripts/freeze_c01_collection_v2.py | 60 + .../freeze_c05_natural_action_teacher.py | 113 + .../freeze_component_action_collection.py | 177 + .../code_behind_layout/scripts/freeze_e1.py | 202 + .../scripts/freeze_e1_scope_cohort.py | 269 + .../code_behind_layout/scripts/freeze_e3.py | 545 + .../scripts/freeze_e3_fidelity.py | 173 + .../scripts/freeze_e4_cold_backups.py | 362 + .../scripts/freeze_e4_methods.py | 28 + .../scripts/freeze_e4_training_data.py | 191 + .../scripts/freeze_gpt_teacher_collection.py | 58 + .../scripts/freeze_matched_t0_proposals.py | 84 + .../freeze_minimal_teacher_collection.py | 52 + .../freeze_natural_terminal_span_teacher.py | 155 + .../scripts/freeze_nf_span_teacher.py | 143 + .../freeze_planning_trajectory_batch.py | 118 + .../scripts/freeze_ratio_span_teacher.py | 132 + .../freeze_textbook_multistate_collection.py | 97 + .../freeze_textbook_train_collection.py | 136 + .../scripts/freeze_train_domain_collection.py | 135 + .../scripts/freeze_train_span_teacher.py | 148 + .../scripts/freeze_training_collection.py | 120 + .../freeze_trajectory_teacher_collection.py | 70 + .../code_behind_layout/scripts/fvf_build.py | 43 + .../scripts/fvf_follower_flow.py | 101 + .../scripts/fvf_intent_reference.py | 68 + .../scripts/fvf_load_calibration.py | 57 + .../scripts/fvf_local_mirror_flow.py | 101 + .../scripts/fvf_local_mirror_ports.py | 14 + .../scripts/fvf_netlist_repaired.py | 310 + .../scripts/fvf_node_probe.py | 32 + .../code_behind_layout/scripts/fvf_plot.py | 29 + .../scripts/fvf_reference.py | 61 + .../scripts/fvf_supplement_episode.py | 437 + .../scripts/fvf_supplement_point.py | 228 + .../scripts/fvf_textbook_c08_electrical.py | 149 + .../fvf_textbook_cropped_source_smoke.py | 55 + .../scripts/fvf_textbook_geometry_pilot.py | 64 + .../code_behind_layout/scripts/fvf_tg_flow.py | 103 + .../scripts/fvf_trace_short.py | 60 + .../scripts/fvf_validate.py | 168 + .../scripts/gpt_adapter_smoke.py | 38 + .../scripts/gpt_teacher_transport_gate.py | 107 + .../scripts/gpu_context_calibration_queue.py | 131 + .../scripts/independent_characterization.py | 193 + .../scripts/independent_legacy_domain.py | 140 + .../independent_legacy_sizing_diagnostic.py | 126 + .../scripts/independent_task_baseline.py | 138 + .../scripts/independent_task_evaluator.py | 140 + .../scripts/independent_task_preflight.py | 33 + .../scripts/inspect_e1_packet_scope.py | 76 + .../inspect_training_queue_evidence.py | 70 + .../code_behind_layout/scripts/inventory.py | 68 + .../scripts/inventory_second_framework_pdk.py | 31 + .../scripts/lattice_signal_check.py | 24 + .../scripts/local_policy_smoke.py | 137 + .../make_promotion_calibration_figure.py | 60 + .../scripts/materialize_component_states.py | 66 + .../scripts/materialize_e1_packets.py | 257 + .../scripts/materialize_independent_tasks.py | 141 + .../scripts/materialize_ota_tasks.py | 464 + .../scripts/materialize_tasks.py | 379 + .../scripts/merge_e1_feasibility.py | 47 + .../scripts/mirror_characterization.py | 192 + .../scripts/mirror_task_evaluator.py | 73 + .../scripts/named_top_smoke.py | 36 + .../scripts/opus_cohort/__init__.py | 1 + .../scripts/opus_cohort/common.py | 210 + .../scripts/opus_cohort/common_v2.py | 69 + .../opus_cohort/count_e3c_sibling_failures.py | 112 + .../opus_cohort/e1_scope_runner_opus.py | 37 + .../opus_cohort/e1_scope_runner_opus_v2.py | 33 + .../scripts/opus_cohort/e3_episode_opus.py | 39 + .../opus_cohort/e3_parameter_episode_opus.py | 32 + .../opus_cohort/freeze_cohorts_opus.py | 255 + .../opus_cohort/freeze_cohorts_opus_v2.py | 165 + .../scripts/opus_cohort/pilot_opus_policy.py | 137 + .../opus_cohort/pilot_opus_policy_v2.py | 73 + .../opus_cohort/run_e1_scope_suite_opus.py | 140 + .../opus_cohort/run_e1_scope_suite_opus_v2.py | 141 + .../opus_cohort/run_e1c2_continuation.py | 139 + .../scripts/opus_cohort/run_e3_suite_opus.py | 31 + .../opus_cohort/summarize_e3_visible_stage.py | 160 + .../ordinary_inference_memory_operation.py | 225 + .../scripts/ota_anchor_cache_audit.py | 129 + .../scripts/ota_bias_load_pilot.py | 71 + .../scripts/ota_compensation_pilot.py | 49 + .../scripts/ota_convergence_calibration.py | 42 + .../scripts/ota_domain_qualification.py | 313 + .../scripts/ota_feedback_calibration.py | 67 + .../scripts/ota_frozen_bench.py | 224 + .../scripts/ota_klu_calibration.py | 28 + .../scripts/ota_mim_plate_probe.py | 12 + .../scripts/ota_pin_repair.py | 42 + .../scripts/ota_postlayout.py | 168 + .../scripts/ota_precision_calibration.py | 48 + .../scripts/ota_rc_calibration.py | 71 + .../scripts/ota_reference_probe.py | 114 + .../scripts/ota_serial_bench_prepare.py | 75 + .../scripts/ota_task_preflight.py | 76 + .../scripts/ota_validate_existing.py | 23 + .../scripts/ota_vendor_transport_smoke.py | 71 + .../scripts/pair_characterization.py | 166 + .../scripts/plot_development_evidence.py | 113 + .../scripts/plot_family_workflow.py | 111 + .../scripts/plot_formal_partial_evidence.py | 567 + .../scripts/plot_ota_debug.py | 30 + .../scripts/plot_preview_e4_transfer.py | 55 + .../prepare_action_teacher_collection.py | 64 + .../prepare_additional_observed_states.py | 57 + .../prepare_additional_train_collection.py | 52 + .../prepare_additional_train_domains.py | 47 + .../scripts/prepare_c01_collection.py | 40 + .../scripts/prepare_c01_collection_v2.py | 50 + .../prepare_c01_independent_finger_domain.py | 41 + .../prepare_c01_long_channel_domain.py | 50 + .../prepare_c01_natural_action_states.py | 39 + .../scripts/prepare_c01_observed_states.py | 58 + .../prepare_c01_per_device_finger_domain.py | 42 + .../scripts/prepare_c01_wide_finger_domain.py | 25 + .../prepare_c05_natural_repair_states.py | 74 + .../scripts/prepare_cascode_train_domain.py | 56 + .../prepare_component_train_collection.py | 82 + .../prepare_component_train_domains.py | 62 + .../scripts/prepare_e1_scope_cohort.py | 89 + .../scripts/prepare_e2_draft.py | 189 + .../prepare_enumeration_teacher_draft.py | 37 + .../scripts/prepare_fvf_search_supplement.py | 229 + .../scripts/prepare_fvf_supplement.py | 209 + .../scripts/prepare_gpt_teacher_collection.py | 42 + .../prepare_local_trajectory_drafts.py | 86 + .../prepare_minimal_teacher_collection.py | 84 + .../prepare_natural_terminal_baselines.py | 252 + .../scripts/prepare_nf_rule_proposals.py | 91 + .../scripts/prepare_nf_span_baselines.py | 158 + .../prepare_planning_trajectory_batch.py | 111 + .../prepare_ratio_source_train_baselines.py | 212 + .../prepare_ratio_source_train_domain.py | 58 + .../scripts/prepare_ratio_train_context.py | 51 + .../scripts/prepare_ratio_training_draft.py | 118 + .../scripts/prepare_research_task_states.py | 82 + .../scripts/prepare_rule_collection.py | 55 + .../scripts/prepare_student_data.py | 160 + .../scripts/prepare_telescopic_supplement.py | 200 + .../prepare_textbook_opus_span_collection.py | 93 + ...repare_textbook_opus_span_collection_v2.py | 100 + .../prepare_textbook_rule_collection.py | 55 + .../prepare_textbook_train_collection.py | 75 + .../scripts/prepare_textbook_train_domains.py | 175 + .../prepare_textbook_variant_states.py | 147 + .../scripts/prepare_tg_strength_domain.py | 30 + .../prepare_train_pair_nf_collection.py | 87 + .../scripts/prepare_train_pair_nf_domains.py | 91 + .../prepare_train_ugb_terminal_pilot.py | 181 + .../scripts/prepare_training.py | 368 + .../prepare_training_context_matrix.py | 169 + .../scripts/profile_probe.py | 36 + .../scripts/qualify_fvf_supplement.py | 197 + .../scripts/qualify_telescopic_supplement.py | 306 + .../qualify_telescopic_supplement_v2.py | 323 + .../scripts/quiesce_gpt_teacher_collection.py | 273 + .../quiesce_train_gate_current_boundary.py | 248 + .../ratio_source_ideal_qualification.py | 53 + .../scripts/ratio_source_pad_smoke.py | 58 + .../ratio_source_pad_then_qualification.py | 71 + .../scripts/ratio_source_physical_probe.py | 225 + .../ratio_source_physical_qualification.py | 195 + .../scripts/ratio_source_train_evaluator.py | 142 + .../scripts/rebind_e1_serial_benches.py | 71 + .../scripts/reconcile_completed_span16.py | 104 + .../scripts/recover_paused_rule_collection.py | 133 + .../scripts/rehearse_closed_c01_restore.py | 322 + .../scripts/release_e3_hidden.py | 157 + .../scripts/remote_mirror_pex.py | 56 + .../scripts/remote_mirror_spice.py | 73 + .../scripts/remote_smoke.py | 88 + .../scripts/render_telescopic_intent.py | 128 + .../scripts/request_frozen_policy.py | 69 + .../scripts/resistive_diff_probe.py | 126 + .../scripts/revise_e1_mirror_domain.py | 77 + .../scripts/run_e1_gpt_continuation_v2.py | 162 + .../scripts/run_e1_scope_continuation.py | 301 + .../scripts/run_e1_scope_suite.py | 138 + .../scripts/run_e1_suite.py | 167 + .../scripts/run_e3_evaluation.py | 237 + .../scripts/run_e3_suite.py | 358 + .../scripts/run_e4_dpo_training.sh | 43 + .../scripts/run_e4_freeze_and_serve_chain.sh | 30 + .../scripts/run_e4_post_sft_chain.sh | 33 + .../scripts/run_e4_selection_v2_chain.sh | 24 + .../scripts/run_e4_selection_v2_dpo_chain.sh | 18 + .../scripts/run_e4_sft_training.sh | 38 + .../scripts/run_e4_validation_selection.sh | 42 + .../scripts/run_eda_probe.py | 70 + .../scripts/run_frozen_training_collection.py | 43 + .../scripts/run_fvf_supplement_suite.py | 234 + .../run_independent_task_preflights.py | 28 + .../scripts/run_natural_terminal_baselines.py | 207 + .../scripts/run_nf_span_baselines.py | 177 + .../scripts/run_opus_repair_round.sh | 27 + .../scripts/run_opus_span_round.sh | 37 + .../run_parallel_train_qualification.py | 96 + .../run_ratio_source_train_baselines.py | 167 + .../scripts/run_textbook_rule_collections.py | 117 + .../run_textbook_variant_collections.py | 91 + .../run_train_ugb_terminal_baselines.py | 224 + .../scripts/seal_unusable_gpt_teacher.py | 66 + .../scripts/serve_checkpoint_policy.py | 295 + .../scripts/serve_frozen_policy.py | 270 + .../scripts/serve_local_policy.py | 224 + .../scripts/serve_matched_t0_proposals.py | 185 + .../scripts/serve_train_span_teacher.py | 99 + .../scripts/stacked_switch_probe.py | 124 + .../scripts/summarize_nf_ideal.py | 37 + .../scripts/task_source_surfaces.json | 204 + .../telescopic_ota_characterization.py | 231 + .../scripts/telescopic_ota_fullflow.py | 341 + .../telescopic_ota_generation_smoke.py | 38 + .../telescopic_sizing_qualification.py | 141 + .../scripts/tg_characterization.py | 144 + .../scripts/train_collection_queue.py | 244 + .../train_pair_nf_physical_qualification.py | 247 + .../scripts/train_policy.py | 346 + .../scripts/training_gpu_calibration.py | 175 + .../scripts/training_pilot_status.py | 288 + .../scripts/training_store_smoke.py | 74 + .../scripts/validation_budget_pilot.py | 253 + .../scripts/validation_mirror_probe.py | 65 + .../validation_ota_calibration_domain.py | 93 + .../scripts/validation_row_ota_probe.py | 140 + .../scripts/validation_task_evaluator.py | 93 + .../scripts/watch_student_readmission.py | 53 + .../scripts/write_paper_numbers.py | 239 + benchmarks/code_behind_layout/src/__init__.py | 1 + .../src/candidate_executor.py | 362 + .../src/corpus_component_benches.py | 156 + .../code_behind_layout/src/corpus_metrics.py | 43 + .../src/corpus_textbook_benches.py | 239 + .../code_behind_layout/src/device_intent.py | 116 + .../code_behind_layout/src/domain_runner.py | 470 + .../code_behind_layout/src/e1_analysis.py | 122 + .../code_behind_layout/src/e1_benchmarks.py | 52 + .../code_behind_layout/src/e1_packets.py | 176 + .../src/e2_mask_geometry.py | 66 + .../code_behind_layout/src/e3_analysis.py | 74 + .../code_behind_layout/src/e3_dispatch.py | 86 + .../src/e3_episode_state.py | 136 + .../code_behind_layout/src/e3_feedback.py | 57 + .../code_behind_layout/src/e3_parameters.py | 68 + .../src/e3_policy_models.py | 39 + .../src/e3_qor_supplement.py | 278 + .../code_behind_layout/src/e3_regression.py | 47 + .../code_behind_layout/src/e3_risk_model.py | 132 + .../code_behind_layout/src/e3_task_prepare.py | 239 + .../code_behind_layout/src/e4_analysis.py | 190 + .../code_behind_layout/src/e4_methods.py | 275 + .../code_behind_layout/src/e4_validation.py | 588 + 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benchmarks/code_behind_layout/configs/development/c02_family/references/dev_nf_3quarters.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c02_family/references/dev_nf_double.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c02_family/references/dev_nf_half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c02_family/references/dev_unit075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c02_family/references/dev_unit100.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg1_family/circuit_input.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg1_family/configurations.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/anchor.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_len075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_len150.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_nf_1half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_nf_3quarters.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_nf_double.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_nf_half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_unit075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_unit100.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/anchor.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_len075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_len150.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_nf_1half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_nf_3quarters.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_nf_double.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_nf_half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_unit075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_unit100.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg2_family/circuit_input.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg2_family/configurations.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/anchor.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_len075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_len150.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_len200.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_nf_1half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_nf_3quarters.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_nf_double.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_nf_half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_unit075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/anchor.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_len075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_len150.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_len200.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_nf_1half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_nf_3quarters.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_nf_double.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_nf_half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_unit075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg3_family/circuit_input.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg3_family/configurations.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/anchor.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_len075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_len150.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_nf_1half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_nf_3quarters.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_nf_double.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_nf_half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_unit075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_unit100.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/anchor.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_len075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_len150.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_nf_1half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_nf_3quarters.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_nf_double.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_nf_half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_unit075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_unit100.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_family/circuit_input.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_family/configurations.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_family/contracts/anchor.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_len075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_len150.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_nf_1half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_nf_3quarters.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_nf_double.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_nf_half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_unit075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_unit100.json create mode 100644 benchmarks/code_behind_layout/configs/development/c03_family/references/anchor.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_family/references/dev_len075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_family/references/dev_len150.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_family/references/dev_nf_1half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_family/references/dev_nf_3quarters.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_family/references/dev_nf_double.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_family/references/dev_nf_half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_family/references/dev_unit075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c03_family/references/dev_unit100.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg1_family/circuit_input.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg1_family/configurations.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/anchor.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_len075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_len150.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_len200.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_nf_1half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_nf_double.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_nf_half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_unit075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_unit100.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/anchor.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_len075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_len150.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_len200.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_nf_1half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_nf_double.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_nf_half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_unit075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_unit100.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg2_family/circuit_input.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg2_family/configurations.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/anchor.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_len075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_len150.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_len200.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_nf_1half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_nf_double.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_nf_half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_nf_triple.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_unit075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/anchor.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_len075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_len150.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_len200.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_nf_1half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_nf_double.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_nf_half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_nf_triple.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_unit075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg3_family/circuit_input.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg3_family/configurations.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/anchor.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_len075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_len150.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_nf_1half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_nf_3quarters.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_nf_double.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_nf_half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_unit075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_unit100.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/anchor.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_len075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_len150.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_nf_1half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_nf_3quarters.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_nf_double.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_nf_half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_unit075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_unit100.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_family/circuit_input.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_family/configurations.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_family/contracts/anchor.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_len075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_len150.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_nf_1half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_nf_3quarters.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_nf_double.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_nf_half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_unit075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_unit100.json create mode 100644 benchmarks/code_behind_layout/configs/development/c04_family/references/anchor.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_family/references/dev_len075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_family/references/dev_len150.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_family/references/dev_nf_1half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_family/references/dev_nf_3quarters.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_family/references/dev_nf_double.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_family/references/dev_nf_half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_family/references/dev_unit075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c04_family/references/dev_unit100.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c05_collection_preparation.json create mode 100644 benchmarks/code_behind_layout/configs/development/c05_family/configurations.json create mode 100644 benchmarks/code_behind_layout/configs/development/c05_family/contracts/anchor.json create mode 100644 benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_len045.json create mode 100644 benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_len060.json create mode 100644 benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_nf_1half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_nf_3quarters.json create mode 100644 benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_nf_double.json create mode 100644 benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_nf_half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_unit075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_unit100.json create mode 100644 benchmarks/code_behind_layout/configs/development/c05_family/references/anchor.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c05_family/references/dev_len045.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c05_family/references/dev_len060.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c05_family/references/dev_nf_1half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c05_family/references/dev_nf_3quarters.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c05_family/references/dev_nf_double.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c05_family/references/dev_nf_half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c05_family/references/dev_unit075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c05_family/references/dev_unit100.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c05_minimal_gpt_teacher_preparation.json create mode 100644 benchmarks/code_behind_layout/configs/development/c05_observed_states_preparation.json create mode 100644 benchmarks/code_behind_layout/configs/development/c05_rule_collection_preparation.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg1_family/circuit_input.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg1_family/configurations.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/anchor.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_len075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_len150.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_len200.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_nf_1half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_nf_double.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_nf_half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_unit075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_unit100.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/anchor.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_len075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_len150.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_len200.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_nf_1half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_nf_double.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_nf_half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_unit075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_unit100.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg2_family/circuit_input.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg2_family/configurations.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/anchor.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_len075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_len150.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_len200.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_nf_1half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_nf_double.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_nf_half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_nf_triple.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_unit075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/anchor.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_len075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_len150.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_len200.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_nf_1half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_nf_double.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_nf_half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_nf_triple.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_unit075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg3_family/circuit_input.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg3_family/configurations.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/anchor.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_len075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_len150.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_nf_1half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_nf_3quarters.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_nf_double.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_nf_half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_unit075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_unit100.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/anchor.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_len075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_len150.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_nf_1half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_nf_3quarters.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_nf_double.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_nf_half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_unit075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_unit100.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_family/circuit_input.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_family/configurations.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_family/contracts/anchor.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_len075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_len150.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_nf_1half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_nf_3quarters.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_nf_double.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_nf_half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_unit075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_unit100.json create mode 100644 benchmarks/code_behind_layout/configs/development/c06_family/references/anchor.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_family/references/dev_len075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_family/references/dev_len150.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_family/references/dev_nf_1half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_family/references/dev_nf_3quarters.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_family/references/dev_nf_double.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_family/references/dev_nf_half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_family/references/dev_unit075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c06_family/references/dev_unit100.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c07_family/circuit_input.json create mode 100644 benchmarks/code_behind_layout/configs/development/c07_family/configurations.json create mode 100644 benchmarks/code_behind_layout/configs/development/c07_family/contracts/anchor.json create mode 100644 benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_len045.json create mode 100644 benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_len060.json create mode 100644 benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_nf_1half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_nf_3quarters.json create mode 100644 benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_nf_double.json create mode 100644 benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_nf_half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_unit075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_unit100.json create mode 100644 benchmarks/code_behind_layout/configs/development/c07_family/references/anchor.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c07_family/references/dev_len045.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c07_family/references/dev_len060.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c07_family/references/dev_nf_1half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c07_family/references/dev_nf_3quarters.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c07_family/references/dev_nf_double.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c07_family/references/dev_nf_half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c07_family/references/dev_unit075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c07_family/references/dev_unit100.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c08_collection_preparation.json create mode 100644 benchmarks/code_behind_layout/configs/development/c08_family/configurations.json create mode 100644 benchmarks/code_behind_layout/configs/development/c08_family/contracts/anchor.json create mode 100644 benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_len045.json create mode 100644 benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_len060.json create mode 100644 benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_nf_1half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_nf_3quarters.json create mode 100644 benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_nf_double.json create mode 100644 benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_nf_half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_unit075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_unit100.json create mode 100644 benchmarks/code_behind_layout/configs/development/c08_family/references/anchor.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c08_family/references/dev_len045.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c08_family/references/dev_len060.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c08_family/references/dev_nf_1half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c08_family/references/dev_nf_3quarters.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c08_family/references/dev_nf_double.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c08_family/references/dev_nf_half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c08_family/references/dev_unit075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c08_family/references/dev_unit100.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c08_minimal_gpt_teacher_preparation.json create mode 100644 benchmarks/code_behind_layout/configs/development/c08_observed_states_preparation.json create mode 100644 benchmarks/code_behind_layout/configs/development/c08_rule_collection_preparation.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg1_family/circuit_input.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg1_family/configurations.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/anchor.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_len075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_len150.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_len200.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_nf_1half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_nf_double.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_nf_half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_unit075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_unit100.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/anchor.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_len075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_len150.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_len200.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_nf_1half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_nf_double.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_nf_half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_unit075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_unit100.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg2_family/circuit_input.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg2_family/configurations.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/anchor.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_len075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_len150.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_len200.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_nf_1half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_nf_double.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_nf_half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_nf_triple.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_unit075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/anchor.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_len075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_len150.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_len200.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_nf_1half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_nf_double.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_nf_half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_nf_triple.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_unit075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg3_family/circuit_input.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg3_family/configurations.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/anchor.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_len075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_len150.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_nf_1half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_nf_3quarters.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_nf_double.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_nf_half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_unit075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_unit100.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/anchor.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_len075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_len150.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_nf_1half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_nf_3quarters.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_nf_double.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_nf_half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_unit075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_unit100.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_family/circuit_input.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_family/configurations.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_family/contracts/anchor.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_len075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_len150.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_nf_1half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_nf_3quarters.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_nf_double.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_nf_half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_unit075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_unit100.json create mode 100644 benchmarks/code_behind_layout/configs/development/c12_family/references/anchor.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_family/references/dev_len075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_family/references/dev_len150.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_family/references/dev_nf_1half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_family/references/dev_nf_3quarters.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_family/references/dev_nf_double.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_family/references/dev_nf_half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_family/references/dev_unit075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c12_family/references/dev_unit100.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg1_family/circuit_input.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg1_family/configurations.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/anchor.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_len075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_len150.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_len200.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_nf_1half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_nf_double.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_nf_half.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_unit075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_unit100.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/anchor.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_len075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_len150.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_len200.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_nf_1half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_nf_double.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_nf_half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_unit075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_unit100.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg2_family/circuit_input.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg2_family/configurations.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/anchor.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_len075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_len150.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_len200.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_nf_double.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_nf_triple.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_unit075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_unit100.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_unit125.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/anchor.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_len075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_len150.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_len200.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_nf_double.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_nf_triple.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_unit075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_unit100.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_unit125.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg3_family/circuit_input.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg3_family/configurations.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/anchor.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_len075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_len150.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_len200.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_nf_double.json create mode 100644 benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_nf_triple.json create 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create mode 100644 benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/dev_unit075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/dev_unit125.spice create mode 100644 benchmarks/code_behind_layout/configs/development/c14_family/circuit_input.json create mode 100644 benchmarks/code_behind_layout/configs/development/c14_family/configurations.json create mode 100644 benchmarks/code_behind_layout/configs/development/c14_family/contracts/anchor.json create mode 100644 benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_len075.json create mode 100644 benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_len150.json create mode 100644 benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_len200.json create mode 100644 benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_nf_1half.json create mode 100644 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create mode 100644 benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/dev_unit075.json create mode 100644 benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/dev_unit100.json create mode 100644 benchmarks/code_behind_layout/configs/development/train_tg01_family/references/anchor.spice create mode 100644 benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_len045.spice create mode 100644 benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_len060.spice create mode 100644 benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_nf_1half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_nf_3quarters.spice create mode 100644 benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_nf_double.spice create mode 100644 benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_nf_half.spice create mode 100644 benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_unit075.spice create mode 100644 benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_unit100.spice create mode 100644 benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/circuit_input.json create mode 100644 benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/configurations.json create mode 100644 benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/anchor.json create mode 100644 benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/dev_len045.json create mode 100644 benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/dev_len060.json create mode 100644 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benchmarks/code_behind_layout/configs/development/validation_shared_budget_v3.json create mode 100644 benchmarks/code_behind_layout/configs/experiments/e2_four_source_prospective_v3.json create mode 100644 benchmarks/code_behind_layout/configs/experiments/e2_telescopic_draft.json create mode 100644 benchmarks/code_behind_layout/configs/experiments/e3_instance_arrivals_draft.json create mode 100644 benchmarks/code_behind_layout/configs/experiments/e3_matched_draft.json create mode 100644 benchmarks/code_behind_layout/configs/experiments/frozen/E1_20261019T0410Z.json create mode 100644 benchmarks/code_behind_layout/configs/experiments/frozen/E1_20261019T0449Z_permission_fix.json create mode 100644 benchmarks/code_behind_layout/configs/experiments/frozen/E1_scope_v2_16k.json create mode 100644 benchmarks/code_behind_layout/configs/experiments/frozen/E1_scope_v2_16k_claude.json create mode 100644 benchmarks/code_behind_layout/configs/experiments/frozen/E1_scope_v2_16k_claude_v2.json create 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benchmarks/code_behind_layout/configs/tasks/development_components_20261019T012723Z/follower/task_packet.json create mode 100644 benchmarks/code_behind_layout/configs/tasks/development_components_20261019T012723Z/mirror/task.json create mode 100644 benchmarks/code_behind_layout/configs/tasks/development_components_20261019T012723Z/mirror/task_packet.json create mode 100644 benchmarks/code_behind_layout/configs/tasks/development_components_20261019T012723Z/pair/task.json create mode 100644 benchmarks/code_behind_layout/configs/tasks/development_components_20261019T012723Z/pair/task_packet.json create mode 100644 benchmarks/code_behind_layout/configs/tasks/development_components_20261019T012723Z/tg/task.json create mode 100644 benchmarks/code_behind_layout/configs/tasks/development_components_20261019T012723Z/tg/task_packet.json create mode 100644 benchmarks/code_behind_layout/configs/tasks/development_independent_20261019T014450Z/cascode_mirror.json create mode 100644 benchmarks/code_behind_layout/configs/tasks/development_independent_20261019T014450Z/common_source_stage.json create mode 100644 benchmarks/code_behind_layout/configs/tasks/development_independent_20261019T014450Z/resistive_diff.json create mode 100644 benchmarks/code_behind_layout/configs/tasks/development_independent_20261019T014450Z/source_follower.json create mode 100644 benchmarks/code_behind_layout/configs/tasks/development_independent_20261019T014450Z/stacked_switch.json create mode 100644 benchmarks/code_behind_layout/configs/tasks/development_otas_20261019T022816Z/compact_miller/task.json create mode 100644 benchmarks/code_behind_layout/configs/tasks/development_otas_20261019T022816Z/compact_miller/task_packet.json create mode 100644 benchmarks/code_behind_layout/configs/tasks/development_otas_20261019T022816Z/context_calibration.json create mode 100644 benchmarks/code_behind_layout/configs/tasks/development_otas_20261019T022816Z/five_t/task.json create mode 100644 benchmarks/code_behind_layout/configs/tasks/development_otas_20261019T022816Z/five_t/task_packet.json create mode 100644 benchmarks/code_behind_layout/configs/tasks/development_otas_20261019T022816Z/fvf/task.json create mode 100644 benchmarks/code_behind_layout/configs/tasks/development_otas_20261019T022816Z/fvf/task_packet.json create mode 100644 benchmarks/code_behind_layout/configs/tasks/development_otas_20261019T022816Z/index.json create mode 100644 benchmarks/code_behind_layout/configs/tasks/development_otas_20261019T022816Z/legacy_miller/task.json create mode 100644 benchmarks/code_behind_layout/configs/tasks/development_otas_20261019T022816Z/legacy_miller/task_packet.json create mode 100644 benchmarks/code_behind_layout/configs/training/backbone_cache.json create mode 100644 benchmarks/code_behind_layout/configs/training/e4_pool_label_rules/textbook_claude_span_20261023T104641Z_physical.json create mode 100644 benchmarks/code_behind_layout/configs/training/e4_pool_label_rules/textbook_claude_span_20261023T115051Z_physical.json create mode 100644 benchmarks/code_behind_layout/configs/training/e4_pool_label_rules/textbook_claude_span_20261023T133414Z_physical.json create mode 100644 benchmarks/code_behind_layout/configs/training/e4_pool_label_rules/textbook_claude_span_20261024T090302Z_physical.json create mode 100644 benchmarks/code_behind_layout/configs/training/e4_pool_label_rules/textbook_claude_span_round2a_v1_physical.json create mode 100644 benchmarks/code_behind_layout/configs/training/e4_pool_label_rules/textbook_claude_span_v1_physical_v2.json create mode 100644 benchmarks/code_behind_layout/configs/training/e4_pools_20261024T172052Z.json create mode 100644 benchmarks/code_behind_layout/configs/training/environment.lock.json create mode 100644 benchmarks/code_behind_layout/configs/training/formal_16k.json create mode 100644 benchmarks/code_behind_layout/configs/training/manifest.draft.json create mode 100644 benchmarks/code_behind_layout/configs/training/pilot.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c01_collection_v1/backup.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c01_collection_v1/collection.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c01_collection_v1/freeze_identity.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c01_collection_v1/label_rule.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c01_collection_v2/backup.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c01_collection_v2/collection.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c01_collection_v2/freeze_identity.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c01_collection_v2/label_rule.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c01_collection_v2/teacher_context_preflight.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c01_gpt_teacher_v1/backup.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c01_gpt_teacher_v1/collection.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c01_gpt_teacher_v1/freeze_identity.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c01_gpt_teacher_v1/label_rule.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c01_gpt_teacher_v1/teacher_context_preflight.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c01_rules_v1/backup.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c01_rules_v1/collection.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c01_rules_v1/freeze_identity.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c01_rules_v1/label_rule.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c05_collection_v1/backup.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c05_collection_v1/calibration.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c05_collection_v1/collection.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c05_collection_v1/freeze_identity.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c05_collection_v1/label_rule.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c05_rules_v1/backup.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c05_rules_v1/calibration.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c05_rules_v1/collection.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c05_rules_v1/freeze_identity.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c05_rules_v1/label_rule.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c08_collection_v1/backup.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c08_collection_v1/calibration.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c08_collection_v1/collection.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c08_collection_v1/freeze_identity.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c08_collection_v1/label_rule.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c08_rules_v1/backup.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c08_rules_v1/calibration.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c08_rules_v1/collection.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c08_rules_v1/freeze_identity.json create mode 100644 benchmarks/code_behind_layout/data/manifests/c08_rules_v1/label_rule.json create mode 100644 benchmarks/code_behind_layout/data/splits/registry.json create mode 100644 benchmarks/code_behind_layout/data/splits/registry.v2.proposal.json create mode 100644 benchmarks/code_behind_layout/docs/e1_protocol.md create mode 100644 benchmarks/code_behind_layout/docs/e3_protocol.md create mode 100644 benchmarks/code_behind_layout/docs/measurement_interface.md create mode 100644 benchmarks/code_behind_layout/docs/protocol.md create mode 100644 benchmarks/code_behind_layout/docs/protocol_amendments.md create mode 100644 benchmarks/code_behind_layout/reproducibility/glayout_fixes.patch create mode 100644 benchmarks/code_behind_layout/requirements.txt create mode 100644 benchmarks/code_behind_layout/runtime/e3_fidelity_control_20261019/controls.py create mode 100644 benchmarks/code_behind_layout/runtime/telescopic_sizing_qualification_20261019/qualified_default_fullflow_v5.py create mode 100644 benchmarks/code_behind_layout/scripts/account_recorded_resources.py create mode 100644 benchmarks/code_behind_layout/scripts/analyze_e1.py create mode 100644 benchmarks/code_behind_layout/scripts/analyze_e1_partial_interface.py create mode 100644 benchmarks/code_behind_layout/scripts/analyze_e1_scope.py create mode 100644 benchmarks/code_behind_layout/scripts/analyze_e2_development.py create mode 100644 benchmarks/code_behind_layout/scripts/analyze_e3.py create mode 100644 benchmarks/code_behind_layout/scripts/analyze_e3_qor_supplement.py create mode 100644 benchmarks/code_behind_layout/scripts/analyze_e4.py create mode 100644 benchmarks/code_behind_layout/scripts/analyze_e5_costs.py create mode 100644 benchmarks/code_behind_layout/scripts/analyze_phase0.py create mode 100644 benchmarks/code_behind_layout/scripts/analyze_protocol_results.py create mode 100644 benchmarks/code_behind_layout/scripts/archive_e1_episode.py create mode 100644 benchmarks/code_behind_layout/scripts/archive_e2_run.py create mode 100644 benchmarks/code_behind_layout/scripts/archive_e3_evidence.py create mode 100644 benchmarks/code_behind_layout/scripts/assemble_e4_methods_draft.py create mode 100644 benchmarks/code_behind_layout/scripts/audit_e4_cold_run.py create mode 100644 benchmarks/code_behind_layout/scripts/audit_matched_T0_increment.py create mode 100644 benchmarks/code_behind_layout/scripts/audit_ota_analyses.py create mode 100644 benchmarks/code_behind_layout/scripts/audit_textbook_pin_order.py create mode 100644 benchmarks/code_behind_layout/scripts/audit_train_device_intent.py create mode 100644 benchmarks/code_behind_layout/scripts/audit_train_pair_nf_rc.py create mode 100644 benchmarks/code_behind_layout/scripts/backup_completed_phase0.py create mode 100644 benchmarks/code_behind_layout/scripts/backup_sealed_e2_development.py create mode 100644 benchmarks/code_behind_layout/scripts/bind_local_trajectory_drafts.py create mode 100644 benchmarks/code_behind_layout/scripts/build_e3_risk_model.py create mode 100644 benchmarks/code_behind_layout/scripts/build_magic.py create mode 100644 benchmarks/code_behind_layout/scripts/build_promotion_calibration.py create mode 100644 benchmarks/code_behind_layout/scripts/c01_collection_evaluator.py create mode 100644 benchmarks/code_behind_layout/scripts/calibrate_ordinary_inference_memory.py create mode 100644 benchmarks/code_behind_layout/scripts/calibrate_policy_state.py create mode 100644 benchmarks/code_behind_layout/scripts/collect_matched_t0_proposals.py create mode 100644 benchmarks/code_behind_layout/scripts/collect_planning_trajectories.py create mode 100644 benchmarks/code_behind_layout/scripts/collect_textbook_opus_spans.py create mode 100644 benchmarks/code_behind_layout/scripts/collect_train_span_proposals.py create mode 100644 benchmarks/code_behind_layout/scripts/collect_training.py create mode 100644 benchmarks/code_behind_layout/scripts/collect_training_v2.py create mode 100644 benchmarks/code_behind_layout/scripts/common_source_probe.py create mode 100644 benchmarks/code_behind_layout/scripts/compact_feedback_calibration.py create mode 100644 benchmarks/code_behind_layout/scripts/compare_research_sources.py create mode 100644 benchmarks/code_behind_layout/scripts/component_oracle_geometry.py create mode 100644 benchmarks/code_behind_layout/scripts/component_oracle_witness.py create mode 100644 benchmarks/code_behind_layout/scripts/component_state_qualification.py create mode 100644 benchmarks/code_behind_layout/scripts/component_task_baseline.py create mode 100644 benchmarks/code_behind_layout/scripts/component_task_evaluator.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_additional_capsule_smoke.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_additional_collection_evaluator.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_additional_domain_summary.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_c01_nf_domain_queue.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_c02_nf_followup_queue.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_component_collection_evaluator.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_component_domain_queue.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_component_domain_summary.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_component_recovery_queue.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_component_train_pilot.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_family_batch.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_family_summary.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_family_yield_summary.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_gpt_action_teacher_service.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_gpt_planning_teacher_service.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_gpt_teacher_service.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_isolated_evaluate.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_long_nf_ideal.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_matched_pair_ideal.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_measure_existing.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_model_candidates.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_nf_ideal_control.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_patch_audit.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_rule_proposer.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_rule_proposer_v2.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_textbook_collection_evaluator.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_textbook_domain_queue.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_textbook_domain_summary.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_textbook_train_pilot.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_wide_nf_qualification_queue.py create mode 100644 benchmarks/code_behind_layout/scripts/corpus_yield_pilot.py create mode 100644 benchmarks/code_behind_layout/scripts/custom_ota_build.py create mode 100644 benchmarks/code_behind_layout/scripts/custom_ota_miller_build.py create mode 100644 benchmarks/code_behind_layout/scripts/custom_ota_miller_schematic.py create mode 100644 benchmarks/code_behind_layout/scripts/custom_ota_schematic.py create mode 100644 benchmarks/code_behind_layout/scripts/declare_e4_pools.py create mode 100644 benchmarks/code_behind_layout/scripts/dedup_run_sources.py create mode 100644 benchmarks/code_behind_layout/scripts/derive_training_selection_v2.py create mode 100644 benchmarks/code_behind_layout/scripts/device_full_flow.py create mode 100644 benchmarks/code_behind_layout/scripts/device_port_inventory.py create mode 100644 benchmarks/code_behind_layout/scripts/device_reextract.py create mode 100644 benchmarks/code_behind_layout/scripts/diagnose_e3_patch_rejection.py create mode 100644 benchmarks/code_behind_layout/scripts/direct_drc_probe.py create mode 100644 benchmarks/code_behind_layout/scripts/domain_smoke.py create mode 100644 benchmarks/code_behind_layout/scripts/drc_parser_calibration.py create mode 100644 benchmarks/code_behind_layout/scripts/e1_development_pilot.py create mode 100644 benchmarks/code_behind_layout/scripts/e1_engineering_source_control.py create mode 100644 benchmarks/code_behind_layout/scripts/e1_exact_grid_domain.py create mode 100644 benchmarks/code_behind_layout/scripts/e1_g2_composition_control.py create mode 100644 benchmarks/code_behind_layout/scripts/e1_matched_runner.py create mode 100644 benchmarks/code_behind_layout/scripts/e1_mechanical_smoke.py create mode 100644 benchmarks/code_behind_layout/scripts/e1_packet_preflight.py create mode 100644 benchmarks/code_behind_layout/scripts/e1_pcell_prepare.py create mode 100644 benchmarks/code_behind_layout/scripts/e1_primitive_handoff.py create mode 100644 benchmarks/code_behind_layout/scripts/e1_primitive_intent_audit.py create mode 100644 benchmarks/code_behind_layout/scripts/e1_schematic_feasibility.py create mode 100644 benchmarks/code_behind_layout/scripts/e1_schematic_parallel.py create mode 100644 benchmarks/code_behind_layout/scripts/e1_scope_history_preflight.py create mode 100644 benchmarks/code_behind_layout/scripts/e1_scope_pilot.py create mode 100644 benchmarks/code_behind_layout/scripts/e1_scope_proposal_preflight.py create mode 100644 benchmarks/code_behind_layout/scripts/e1_scope_runner.py create mode 100644 benchmarks/code_behind_layout/scripts/e1_trusted_evaluator.py create mode 100644 benchmarks/code_behind_layout/scripts/e2_apply_transient_completion.py create mode 100644 benchmarks/code_behind_layout/scripts/e2_cached_evaluator.py create mode 100644 benchmarks/code_behind_layout/scripts/e2_default_source_controls.py create mode 100644 benchmarks/code_behind_layout/scripts/e2_development_pilot.py create mode 100644 benchmarks/code_behind_layout/scripts/e2_execution.py create mode 100644 benchmarks/code_behind_layout/scripts/e2_execution_prepare.py create mode 100644 benchmarks/code_behind_layout/scripts/e2_four_source.py create mode 100644 benchmarks/code_behind_layout/scripts/e2_geometry_evaluator.py create mode 100644 benchmarks/code_behind_layout/scripts/e2_mask_geometry_smoke.py create mode 100644 benchmarks/code_behind_layout/scripts/e2_mask_stage.py create mode 100644 benchmarks/code_behind_layout/scripts/e2_nominal_bench.py create mode 100644 benchmarks/code_behind_layout/scripts/e2_sizing_physical_qualification.py create mode 100644 benchmarks/code_behind_layout/scripts/e2_sizing_prequalification.py create mode 100644 benchmarks/code_behind_layout/scripts/e2_spice_process_profile.py create mode 100644 benchmarks/code_behind_layout/scripts/e2_stage_prepare.py create mode 100644 benchmarks/code_behind_layout/scripts/e2_stage_smoke.py create mode 100644 benchmarks/code_behind_layout/scripts/e2_telescopic_adapter.py create mode 100644 benchmarks/code_behind_layout/scripts/e2_telescopic_frozen_bench.py create mode 100644 benchmarks/code_behind_layout/scripts/e2_telescopic_stage_smoke.py create mode 100644 benchmarks/code_behind_layout/scripts/e2_transient_completion.py create mode 100644 benchmarks/code_behind_layout/scripts/e3_anchor_qualify.py create mode 100644 benchmarks/code_behind_layout/scripts/e3_baseline_control.py create mode 100644 benchmarks/code_behind_layout/scripts/e3_episode.py create mode 100644 benchmarks/code_behind_layout/scripts/e3_expand_parameters.py create mode 100644 benchmarks/code_behind_layout/scripts/e3_fidelity_episode.py create mode 100644 benchmarks/code_behind_layout/scripts/e3_fidelity_point.py create mode 100644 benchmarks/code_behind_layout/scripts/e3_gateway_control.py create mode 100644 benchmarks/code_behind_layout/scripts/e3_generation_qualify.py create mode 100644 benchmarks/code_behind_layout/scripts/e3_history_preflight.py create mode 100644 benchmarks/code_behind_layout/scripts/e3_instance_episode.py create mode 100644 benchmarks/code_behind_layout/scripts/e3_nominal_objective.py create mode 100644 benchmarks/code_behind_layout/scripts/e3_original_baseline.py create mode 100644 benchmarks/code_behind_layout/scripts/e3_parameter_binding_check.py create mode 100644 benchmarks/code_behind_layout/scripts/e3_parameter_episode.py create mode 100644 benchmarks/code_behind_layout/scripts/e3_physical_point.py create mode 100644 benchmarks/code_behind_layout/scripts/e3_remaining_ota_qualify.py create mode 100644 benchmarks/code_behind_layout/scripts/e3_summarize_qualification.py create mode 100644 benchmarks/code_behind_layout/scripts/e3_task_prepare.py create mode 100644 benchmarks/code_behind_layout/scripts/e3_trusted_objective.py create mode 100644 benchmarks/code_behind_layout/scripts/e4_checkpoint_validation.py create mode 100644 benchmarks/code_behind_layout/scripts/e4_validation_mirror_domain.py create mode 100644 benchmarks/code_behind_layout/scripts/evaluate_matched_t0_proposals.py create mode 100644 benchmarks/code_behind_layout/scripts/evaluate_natural_terminal_span_proposals.py create mode 100644 benchmarks/code_behind_layout/scripts/evaluate_nf_joint_pool.py create mode 100644 benchmarks/code_behind_layout/scripts/evaluate_nf_span_proposals.py create mode 100644 benchmarks/code_behind_layout/scripts/evaluate_ratio_span_proposals.py create mode 100644 benchmarks/code_behind_layout/scripts/evaluate_textbook_opus_spans.py create mode 100644 benchmarks/code_behind_layout/scripts/evaluate_textbook_opus_spans_v2.py create mode 100644 benchmarks/code_behind_layout/scripts/evaluate_train_span_proposals.py create mode 100644 benchmarks/code_behind_layout/scripts/executor_smoke.py create mode 100755 benchmarks/code_behind_layout/scripts/fetch_data.sh create mode 100644 benchmarks/code_behind_layout/scripts/five_t_feedback_calibration.py create mode 100644 benchmarks/code_behind_layout/scripts/follower_characterization.py create mode 100644 benchmarks/code_behind_layout/scripts/freeze_action_teacher_collection.py create mode 100644 benchmarks/code_behind_layout/scripts/freeze_c01_collection_v2.py create mode 100644 benchmarks/code_behind_layout/scripts/freeze_c05_natural_action_teacher.py create mode 100644 benchmarks/code_behind_layout/scripts/freeze_component_action_collection.py create mode 100644 benchmarks/code_behind_layout/scripts/freeze_e1.py create mode 100644 benchmarks/code_behind_layout/scripts/freeze_e1_scope_cohort.py create mode 100644 benchmarks/code_behind_layout/scripts/freeze_e3.py create mode 100644 benchmarks/code_behind_layout/scripts/freeze_e3_fidelity.py create mode 100644 benchmarks/code_behind_layout/scripts/freeze_e4_cold_backups.py create mode 100644 benchmarks/code_behind_layout/scripts/freeze_e4_methods.py create mode 100644 benchmarks/code_behind_layout/scripts/freeze_e4_training_data.py create mode 100644 benchmarks/code_behind_layout/scripts/freeze_gpt_teacher_collection.py create mode 100644 benchmarks/code_behind_layout/scripts/freeze_matched_t0_proposals.py create mode 100644 benchmarks/code_behind_layout/scripts/freeze_minimal_teacher_collection.py create mode 100644 benchmarks/code_behind_layout/scripts/freeze_natural_terminal_span_teacher.py create mode 100644 benchmarks/code_behind_layout/scripts/freeze_nf_span_teacher.py create mode 100644 benchmarks/code_behind_layout/scripts/freeze_planning_trajectory_batch.py create mode 100644 benchmarks/code_behind_layout/scripts/freeze_ratio_span_teacher.py create mode 100644 benchmarks/code_behind_layout/scripts/freeze_textbook_multistate_collection.py create mode 100644 benchmarks/code_behind_layout/scripts/freeze_textbook_train_collection.py create mode 100644 benchmarks/code_behind_layout/scripts/freeze_train_domain_collection.py create mode 100644 benchmarks/code_behind_layout/scripts/freeze_train_span_teacher.py create mode 100644 benchmarks/code_behind_layout/scripts/freeze_training_collection.py create mode 100644 benchmarks/code_behind_layout/scripts/freeze_trajectory_teacher_collection.py create mode 100644 benchmarks/code_behind_layout/scripts/fvf_build.py create mode 100644 benchmarks/code_behind_layout/scripts/fvf_follower_flow.py create mode 100644 benchmarks/code_behind_layout/scripts/fvf_intent_reference.py create mode 100644 benchmarks/code_behind_layout/scripts/fvf_load_calibration.py create mode 100644 benchmarks/code_behind_layout/scripts/fvf_local_mirror_flow.py create mode 100644 benchmarks/code_behind_layout/scripts/fvf_local_mirror_ports.py create mode 100644 benchmarks/code_behind_layout/scripts/fvf_netlist_repaired.py create mode 100644 benchmarks/code_behind_layout/scripts/fvf_node_probe.py create mode 100644 benchmarks/code_behind_layout/scripts/fvf_plot.py create mode 100644 benchmarks/code_behind_layout/scripts/fvf_reference.py create mode 100644 benchmarks/code_behind_layout/scripts/fvf_supplement_episode.py create mode 100644 benchmarks/code_behind_layout/scripts/fvf_supplement_point.py create mode 100644 benchmarks/code_behind_layout/scripts/fvf_textbook_c08_electrical.py create mode 100644 benchmarks/code_behind_layout/scripts/fvf_textbook_cropped_source_smoke.py create mode 100644 benchmarks/code_behind_layout/scripts/fvf_textbook_geometry_pilot.py create mode 100644 benchmarks/code_behind_layout/scripts/fvf_tg_flow.py create mode 100644 benchmarks/code_behind_layout/scripts/fvf_trace_short.py create mode 100644 benchmarks/code_behind_layout/scripts/fvf_validate.py create mode 100644 benchmarks/code_behind_layout/scripts/gpt_adapter_smoke.py create mode 100644 benchmarks/code_behind_layout/scripts/gpt_teacher_transport_gate.py create mode 100644 benchmarks/code_behind_layout/scripts/gpu_context_calibration_queue.py create mode 100644 benchmarks/code_behind_layout/scripts/independent_characterization.py create mode 100644 benchmarks/code_behind_layout/scripts/independent_legacy_domain.py create mode 100644 benchmarks/code_behind_layout/scripts/independent_legacy_sizing_diagnostic.py create mode 100644 benchmarks/code_behind_layout/scripts/independent_task_baseline.py create mode 100644 benchmarks/code_behind_layout/scripts/independent_task_evaluator.py create mode 100644 benchmarks/code_behind_layout/scripts/independent_task_preflight.py create mode 100644 benchmarks/code_behind_layout/scripts/inspect_e1_packet_scope.py create mode 100644 benchmarks/code_behind_layout/scripts/inspect_training_queue_evidence.py create mode 100644 benchmarks/code_behind_layout/scripts/inventory.py create mode 100644 benchmarks/code_behind_layout/scripts/inventory_second_framework_pdk.py create mode 100644 benchmarks/code_behind_layout/scripts/lattice_signal_check.py create mode 100644 benchmarks/code_behind_layout/scripts/local_policy_smoke.py create mode 100644 benchmarks/code_behind_layout/scripts/make_promotion_calibration_figure.py create mode 100644 benchmarks/code_behind_layout/scripts/materialize_component_states.py create mode 100644 benchmarks/code_behind_layout/scripts/materialize_e1_packets.py create mode 100644 benchmarks/code_behind_layout/scripts/materialize_independent_tasks.py create mode 100644 benchmarks/code_behind_layout/scripts/materialize_ota_tasks.py create mode 100644 benchmarks/code_behind_layout/scripts/materialize_tasks.py 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benchmarks/code_behind_layout/scripts/ordinary_inference_memory_operation.py create mode 100644 benchmarks/code_behind_layout/scripts/ota_anchor_cache_audit.py create mode 100644 benchmarks/code_behind_layout/scripts/ota_bias_load_pilot.py create mode 100644 benchmarks/code_behind_layout/scripts/ota_compensation_pilot.py create mode 100644 benchmarks/code_behind_layout/scripts/ota_convergence_calibration.py create mode 100644 benchmarks/code_behind_layout/scripts/ota_domain_qualification.py create mode 100644 benchmarks/code_behind_layout/scripts/ota_feedback_calibration.py create mode 100644 benchmarks/code_behind_layout/scripts/ota_frozen_bench.py create mode 100644 benchmarks/code_behind_layout/scripts/ota_klu_calibration.py create mode 100644 benchmarks/code_behind_layout/scripts/ota_mim_plate_probe.py create mode 100644 benchmarks/code_behind_layout/scripts/ota_pin_repair.py create mode 100644 benchmarks/code_behind_layout/scripts/ota_postlayout.py create mode 100644 benchmarks/code_behind_layout/scripts/ota_precision_calibration.py create mode 100644 benchmarks/code_behind_layout/scripts/ota_rc_calibration.py create mode 100644 benchmarks/code_behind_layout/scripts/ota_reference_probe.py create mode 100644 benchmarks/code_behind_layout/scripts/ota_serial_bench_prepare.py create mode 100644 benchmarks/code_behind_layout/scripts/ota_task_preflight.py create mode 100644 benchmarks/code_behind_layout/scripts/ota_validate_existing.py create mode 100644 benchmarks/code_behind_layout/scripts/ota_vendor_transport_smoke.py create mode 100644 benchmarks/code_behind_layout/scripts/pair_characterization.py create mode 100644 benchmarks/code_behind_layout/scripts/plot_development_evidence.py create mode 100644 benchmarks/code_behind_layout/scripts/plot_family_workflow.py create mode 100644 benchmarks/code_behind_layout/scripts/plot_formal_partial_evidence.py create mode 100644 benchmarks/code_behind_layout/scripts/plot_ota_debug.py create mode 100644 benchmarks/code_behind_layout/scripts/plot_preview_e4_transfer.py create mode 100644 benchmarks/code_behind_layout/scripts/prepare_action_teacher_collection.py create mode 100644 benchmarks/code_behind_layout/scripts/prepare_additional_observed_states.py create mode 100644 benchmarks/code_behind_layout/scripts/prepare_additional_train_collection.py create mode 100644 benchmarks/code_behind_layout/scripts/prepare_additional_train_domains.py create mode 100644 benchmarks/code_behind_layout/scripts/prepare_c01_collection.py create mode 100644 benchmarks/code_behind_layout/scripts/prepare_c01_collection_v2.py create mode 100644 benchmarks/code_behind_layout/scripts/prepare_c01_independent_finger_domain.py create mode 100644 benchmarks/code_behind_layout/scripts/prepare_c01_long_channel_domain.py create mode 100644 benchmarks/code_behind_layout/scripts/prepare_c01_natural_action_states.py create mode 100644 benchmarks/code_behind_layout/scripts/prepare_c01_observed_states.py create mode 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benchmarks/code_behind_layout/scripts/prepare_gpt_teacher_collection.py create mode 100644 benchmarks/code_behind_layout/scripts/prepare_local_trajectory_drafts.py create mode 100644 benchmarks/code_behind_layout/scripts/prepare_minimal_teacher_collection.py create mode 100644 benchmarks/code_behind_layout/scripts/prepare_natural_terminal_baselines.py create mode 100644 benchmarks/code_behind_layout/scripts/prepare_nf_rule_proposals.py create mode 100644 benchmarks/code_behind_layout/scripts/prepare_nf_span_baselines.py create mode 100644 benchmarks/code_behind_layout/scripts/prepare_planning_trajectory_batch.py create mode 100644 benchmarks/code_behind_layout/scripts/prepare_ratio_source_train_baselines.py create mode 100644 benchmarks/code_behind_layout/scripts/prepare_ratio_source_train_domain.py create mode 100644 benchmarks/code_behind_layout/scripts/prepare_ratio_train_context.py create mode 100644 benchmarks/code_behind_layout/scripts/prepare_ratio_training_draft.py create mode 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benchmarks/code_behind_layout/scripts/ratio_source_ideal_qualification.py create mode 100644 benchmarks/code_behind_layout/scripts/ratio_source_pad_smoke.py create mode 100644 benchmarks/code_behind_layout/scripts/ratio_source_pad_then_qualification.py create mode 100644 benchmarks/code_behind_layout/scripts/ratio_source_physical_probe.py create mode 100644 benchmarks/code_behind_layout/scripts/ratio_source_physical_qualification.py create mode 100644 benchmarks/code_behind_layout/scripts/ratio_source_train_evaluator.py create mode 100644 benchmarks/code_behind_layout/scripts/rebind_e1_serial_benches.py create mode 100644 benchmarks/code_behind_layout/scripts/reconcile_completed_span16.py create mode 100644 benchmarks/code_behind_layout/scripts/recover_paused_rule_collection.py create mode 100644 benchmarks/code_behind_layout/scripts/rehearse_closed_c01_restore.py create mode 100644 benchmarks/code_behind_layout/scripts/release_e3_hidden.py create mode 100644 benchmarks/code_behind_layout/scripts/remote_mirror_pex.py create mode 100644 benchmarks/code_behind_layout/scripts/remote_mirror_spice.py create mode 100644 benchmarks/code_behind_layout/scripts/remote_smoke.py create mode 100644 benchmarks/code_behind_layout/scripts/render_telescopic_intent.py create mode 100644 benchmarks/code_behind_layout/scripts/request_frozen_policy.py create mode 100644 benchmarks/code_behind_layout/scripts/resistive_diff_probe.py create mode 100644 benchmarks/code_behind_layout/scripts/revise_e1_mirror_domain.py create mode 100644 benchmarks/code_behind_layout/scripts/run_e1_gpt_continuation_v2.py create mode 100644 benchmarks/code_behind_layout/scripts/run_e1_scope_continuation.py create mode 100644 benchmarks/code_behind_layout/scripts/run_e1_scope_suite.py create mode 100644 benchmarks/code_behind_layout/scripts/run_e1_suite.py create mode 100644 benchmarks/code_behind_layout/scripts/run_e3_evaluation.py create mode 100644 benchmarks/code_behind_layout/scripts/run_e3_suite.py create mode 100644 benchmarks/code_behind_layout/scripts/run_e4_dpo_training.sh create mode 100755 benchmarks/code_behind_layout/scripts/run_e4_freeze_and_serve_chain.sh create mode 100755 benchmarks/code_behind_layout/scripts/run_e4_post_sft_chain.sh create mode 100755 benchmarks/code_behind_layout/scripts/run_e4_selection_v2_chain.sh create mode 100755 benchmarks/code_behind_layout/scripts/run_e4_selection_v2_dpo_chain.sh create mode 100644 benchmarks/code_behind_layout/scripts/run_e4_sft_training.sh create mode 100644 benchmarks/code_behind_layout/scripts/run_e4_validation_selection.sh create mode 100644 benchmarks/code_behind_layout/scripts/run_eda_probe.py create mode 100644 benchmarks/code_behind_layout/scripts/run_frozen_training_collection.py create mode 100644 benchmarks/code_behind_layout/scripts/run_fvf_supplement_suite.py create mode 100644 benchmarks/code_behind_layout/scripts/run_independent_task_preflights.py create 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benchmarks/code_behind_layout/scripts/serve_frozen_policy.py create mode 100644 benchmarks/code_behind_layout/scripts/serve_local_policy.py create mode 100644 benchmarks/code_behind_layout/scripts/serve_matched_t0_proposals.py create mode 100644 benchmarks/code_behind_layout/scripts/serve_train_span_teacher.py create mode 100644 benchmarks/code_behind_layout/scripts/stacked_switch_probe.py create mode 100644 benchmarks/code_behind_layout/scripts/summarize_nf_ideal.py create mode 100644 benchmarks/code_behind_layout/scripts/task_source_surfaces.json create mode 100644 benchmarks/code_behind_layout/scripts/telescopic_ota_characterization.py create mode 100644 benchmarks/code_behind_layout/scripts/telescopic_ota_fullflow.py create mode 100644 benchmarks/code_behind_layout/scripts/telescopic_ota_generation_smoke.py create mode 100644 benchmarks/code_behind_layout/scripts/telescopic_sizing_qualification.py create mode 100644 benchmarks/code_behind_layout/scripts/tg_characterization.py create mode 100644 benchmarks/code_behind_layout/scripts/train_collection_queue.py create mode 100644 benchmarks/code_behind_layout/scripts/train_pair_nf_physical_qualification.py create mode 100644 benchmarks/code_behind_layout/scripts/train_policy.py create mode 100644 benchmarks/code_behind_layout/scripts/training_gpu_calibration.py create mode 100644 benchmarks/code_behind_layout/scripts/training_pilot_status.py create mode 100644 benchmarks/code_behind_layout/scripts/training_store_smoke.py create mode 100644 benchmarks/code_behind_layout/scripts/validation_budget_pilot.py create mode 100644 benchmarks/code_behind_layout/scripts/validation_mirror_probe.py create mode 100644 benchmarks/code_behind_layout/scripts/validation_ota_calibration_domain.py create mode 100644 benchmarks/code_behind_layout/scripts/validation_row_ota_probe.py create mode 100644 benchmarks/code_behind_layout/scripts/validation_task_evaluator.py create mode 100644 benchmarks/code_behind_layout/scripts/watch_student_readmission.py create mode 100644 benchmarks/code_behind_layout/scripts/write_paper_numbers.py create mode 100644 benchmarks/code_behind_layout/src/__init__.py create mode 100644 benchmarks/code_behind_layout/src/candidate_executor.py create mode 100644 benchmarks/code_behind_layout/src/corpus_component_benches.py create mode 100644 benchmarks/code_behind_layout/src/corpus_metrics.py create mode 100644 benchmarks/code_behind_layout/src/corpus_textbook_benches.py create mode 100644 benchmarks/code_behind_layout/src/device_intent.py create mode 100644 benchmarks/code_behind_layout/src/domain_runner.py create mode 100644 benchmarks/code_behind_layout/src/e1_analysis.py create mode 100644 benchmarks/code_behind_layout/src/e1_benchmarks.py create mode 100644 benchmarks/code_behind_layout/src/e1_packets.py create mode 100644 benchmarks/code_behind_layout/src/e2_mask_geometry.py create mode 100644 benchmarks/code_behind_layout/src/e3_analysis.py create mode 100644 benchmarks/code_behind_layout/src/e3_dispatch.py create mode 100644 benchmarks/code_behind_layout/src/e3_episode_state.py create mode 100644 benchmarks/code_behind_layout/src/e3_feedback.py create mode 100644 benchmarks/code_behind_layout/src/e3_parameters.py create mode 100644 benchmarks/code_behind_layout/src/e3_policy_models.py create mode 100644 benchmarks/code_behind_layout/src/e3_qor_supplement.py create mode 100644 benchmarks/code_behind_layout/src/e3_regression.py create mode 100644 benchmarks/code_behind_layout/src/e3_risk_model.py create mode 100644 benchmarks/code_behind_layout/src/e3_task_prepare.py create mode 100644 benchmarks/code_behind_layout/src/e4_analysis.py create mode 100644 benchmarks/code_behind_layout/src/e4_methods.py create mode 100644 benchmarks/code_behind_layout/src/e4_validation.py create mode 100644 benchmarks/code_behind_layout/src/e5_costs.py create mode 100644 benchmarks/code_behind_layout/src/fidelity_analysis.py create mode 100644 benchmarks/code_behind_layout/src/generators/README.md create mode 100644 benchmarks/code_behind_layout/src/generators/__init__.py create mode 100644 benchmarks/code_behind_layout/src/generators/cascode_mirror.py create mode 100644 benchmarks/code_behind_layout/src/generators/cascode_mirror_reference.py create mode 100644 benchmarks/code_behind_layout/src/generators/common_source_reference.py create mode 100644 benchmarks/code_behind_layout/src/generators/common_source_stage.py create mode 100644 benchmarks/code_behind_layout/src/generators/compact_miller.py create mode 100644 benchmarks/code_behind_layout/src/generators/compact_miller_reference.py create mode 100644 benchmarks/code_behind_layout/src/generators/five_t.py create mode 100644 benchmarks/code_behind_layout/src/generators/five_t_reference.py create mode 100644 benchmarks/code_behind_layout/src/generators/resistive_diff.py create mode 100644 benchmarks/code_behind_layout/src/generators/resistive_diff_reference.py create mode 100644 benchmarks/code_behind_layout/src/generators/source_follower.py create mode 100644 benchmarks/code_behind_layout/src/generators/source_follower_reference.py create mode 100644 benchmarks/code_behind_layout/src/generators/stacked_switch.py create mode 100644 benchmarks/code_behind_layout/src/generators/stacked_switch_reference.py create mode 100644 benchmarks/code_behind_layout/src/generators/telescopic_ota.py create mode 100644 benchmarks/code_behind_layout/src/generators/telescopic_ota_reference.py create mode 100644 benchmarks/code_behind_layout/src/generators/terminal_access.py create mode 100644 benchmarks/code_behind_layout/src/generators/validation_mirror.py create mode 100644 benchmarks/code_behind_layout/src/generators/validation_row_ota.py create mode 100644 benchmarks/code_behind_layout/src/generators/validation_row_ota_reference.py create mode 100644 benchmarks/code_behind_layout/src/local_model_adapter.py create mode 100644 benchmarks/code_behind_layout/src/measurement.py create mode 100644 benchmarks/code_behind_layout/src/model_adapter.py create mode 100644 benchmarks/code_behind_layout/src/opus_cli_adapter.py create mode 100644 benchmarks/code_behind_layout/src/opus_cli_adapter_v2.py create mode 100644 benchmarks/code_behind_layout/src/physical_drc.py create mode 100644 benchmarks/code_behind_layout/src/policy_state.py create mode 100644 benchmarks/code_behind_layout/src/promotion_calibration.py create mode 100644 benchmarks/code_behind_layout/src/protocol_result_tables.py create mode 100644 benchmarks/code_behind_layout/src/regression_selector.py create mode 100644 benchmarks/code_behind_layout/src/report_parsers.py create mode 100644 benchmarks/code_behind_layout/src/spice_validation.py create mode 100644 benchmarks/code_behind_layout/src/student_interface.py create mode 100644 benchmarks/code_behind_layout/src/train_generators/__init__.py create mode 100644 benchmarks/code_behind_layout/src/train_generators/ratio_source.py create mode 100644 benchmarks/code_behind_layout/src/train_generators/ratio_source_bench.py create mode 100644 benchmarks/code_behind_layout/src/train_generators/ratio_source_intent.py create mode 100644 benchmarks/code_behind_layout/src/train_natural_terminal_span_bundle.py create mode 100644 benchmarks/code_behind_layout/src/train_nf_span_bundle.py create mode 100644 benchmarks/code_behind_layout/src/train_ratio_span_bundle.py create mode 100644 benchmarks/code_behind_layout/src/train_span_bundle.py create mode 100644 benchmarks/code_behind_layout/src/train_span_cli.py create mode 100644 benchmarks/code_behind_layout/src/train_span_opus_cli.py create mode 100644 benchmarks/code_behind_layout/src/train_span_proposer.py create mode 100644 benchmarks/code_behind_layout/src/training.py create mode 100644 benchmarks/code_behind_layout/src/training_selection_v2.py create mode 100644 benchmarks/code_behind_layout/tests/fixtures/device4_allnet_pex.spice create mode 100644 benchmarks/code_behind_layout/tests/fixtures/e1_scope_actual_bad_patches.json create mode 100644 benchmarks/code_behind_layout/tests/fixtures/known_underwidth_full_drc.rpt create mode 100644 benchmarks/code_behind_layout/tests/fixtures/ota_clean_drc.rpt create mode 100644 benchmarks/code_behind_layout/tests/fixtures/ota_legacy_disconnected_lvs.rpt create mode 100644 benchmarks/code_behind_layout/tests/fixtures/ota_repaired_lvs.rpt create mode 100644 benchmarks/code_behind_layout/tests/fixtures/train_pair_nf_parent_anchors.json create mode 100644 benchmarks/code_behind_layout/tests/test_archive_e3_evidence.py create mode 100644 benchmarks/code_behind_layout/tests/test_candidate_executor.py create mode 100644 benchmarks/code_behind_layout/tests/test_checkpoint_policy_service.py create mode 100644 benchmarks/code_behind_layout/tests/test_closed_c01_restore.py create mode 100644 benchmarks/code_behind_layout/tests/test_collection_runner.py create mode 100644 benchmarks/code_behind_layout/tests/test_current_train_gate_boundary.py create mode 100644 benchmarks/code_behind_layout/tests/test_device_intent.py create mode 100644 benchmarks/code_behind_layout/tests/test_domain_runner.py create mode 100644 benchmarks/code_behind_layout/tests/test_e1_analysis.py create mode 100644 benchmarks/code_behind_layout/tests/test_e1_archive.py create mode 100644 benchmarks/code_behind_layout/tests/test_e1_feedback.py create mode 100644 benchmarks/code_behind_layout/tests/test_e1_packets.py create mode 100644 benchmarks/code_behind_layout/tests/test_e1_partial_interface_analysis.py create mode 100644 benchmarks/code_behind_layout/tests/test_e1_runner.py create mode 100644 benchmarks/code_behind_layout/tests/test_e1_scope_cohort.py create mode 100644 benchmarks/code_behind_layout/tests/test_e1_scope_continuation.py create mode 100644 benchmarks/code_behind_layout/tests/test_e1_suite.py create mode 100644 benchmarks/code_behind_layout/tests/test_e2_archive.py create mode 100644 benchmarks/code_behind_layout/tests/test_e2_default_source_controls.py create mode 100644 benchmarks/code_behind_layout/tests/test_e2_four_source.py create mode 100644 benchmarks/code_behind_layout/tests/test_e2_promotions.py create mode 100644 benchmarks/code_behind_layout/tests/test_e2_telescopic_adapter.py create mode 100644 benchmarks/code_behind_layout/tests/test_e3_analysis.py create mode 100644 benchmarks/code_behind_layout/tests/test_e3_baseline_control.py create mode 100644 benchmarks/code_behind_layout/tests/test_e3_episode_state.py create mode 100644 benchmarks/code_behind_layout/tests/test_e3_feedback.py create mode 100644 benchmarks/code_behind_layout/tests/test_e3_fidelity_episode.py create mode 100644 benchmarks/code_behind_layout/tests/test_e3_fidelity_point.py create mode 100644 benchmarks/code_behind_layout/tests/test_e3_gateway.py create mode 100644 benchmarks/code_behind_layout/tests/test_e3_instance_episode.py create mode 100644 benchmarks/code_behind_layout/tests/test_e3_original_baseline.py create mode 100644 benchmarks/code_behind_layout/tests/test_e3_parameter_episode.py create mode 100644 benchmarks/code_behind_layout/tests/test_e3_parameters.py create mode 100644 benchmarks/code_behind_layout/tests/test_e3_patch_rejection_diagnosis.py create mode 100644 benchmarks/code_behind_layout/tests/test_e3_qor_supplement.py create mode 100644 benchmarks/code_behind_layout/tests/test_e3_qualification_summary.py create mode 100644 benchmarks/code_behind_layout/tests/test_e3_regression.py create mode 100644 benchmarks/code_behind_layout/tests/test_e3_remaining_ota_qualify.py create mode 100644 benchmarks/code_behind_layout/tests/test_e3_risk_model.py create mode 100644 benchmarks/code_behind_layout/tests/test_e3_task_prepare.py create mode 100644 benchmarks/code_behind_layout/tests/test_e4_analysis.py create mode 100644 benchmarks/code_behind_layout/tests/test_e4_checkpoint_validation.py create mode 100644 benchmarks/code_behind_layout/tests/test_e4_cold_backups.py create mode 100644 benchmarks/code_behind_layout/tests/test_e4_methods.py create mode 100644 benchmarks/code_behind_layout/tests/test_e5_costs.py create mode 100644 benchmarks/code_behind_layout/tests/test_fidelity_analysis.py create mode 100644 benchmarks/code_behind_layout/tests/test_freeze_e3.py create mode 100644 benchmarks/code_behind_layout/tests/test_frozen_collection_entrypoint.py create mode 100644 benchmarks/code_behind_layout/tests/test_fvf_control.py create mode 100644 benchmarks/code_behind_layout/tests/test_fvf_supplement.py create mode 100644 benchmarks/code_behind_layout/tests/test_fvf_supplement_episode.py create mode 100644 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100644 benchmarks/code_behind_layout/tests/test_nf_joint_pool.py create mode 100644 benchmarks/code_behind_layout/tests/test_nf_span_baselines.py create mode 100644 benchmarks/code_behind_layout/tests/test_nf_span_physical.py create mode 100644 benchmarks/code_behind_layout/tests/test_nf_span_teacher.py create mode 100644 benchmarks/code_behind_layout/tests/test_ordinary_inference_memory.py create mode 100644 benchmarks/code_behind_layout/tests/test_ordinary_inference_memory_operation.py create mode 100644 benchmarks/code_behind_layout/tests/test_phase0_backup.py create mode 100644 benchmarks/code_behind_layout/tests/test_planning_trajectory_interface.py create mode 100644 benchmarks/code_behind_layout/tests/test_policy_state.py create mode 100644 benchmarks/code_behind_layout/tests/test_promotion_calibration.py create mode 100644 benchmarks/code_behind_layout/tests/test_protocol_result_tables.py create mode 100644 benchmarks/code_behind_layout/tests/test_ratio_source_physical_qualification.py create mode 100644 benchmarks/code_behind_layout/tests/test_ratio_source_train_baselines.py create mode 100644 benchmarks/code_behind_layout/tests/test_ratio_source_train_domain.py create mode 100644 benchmarks/code_behind_layout/tests/test_ratio_span_collection.py create mode 100644 benchmarks/code_behind_layout/tests/test_regression_selector.py create mode 100644 benchmarks/code_behind_layout/tests/test_release_e3_hidden.py create mode 100644 benchmarks/code_behind_layout/tests/test_report_parsers.py create mode 100644 benchmarks/code_behind_layout/tests/test_request_frozen_policy.py create mode 100644 benchmarks/code_behind_layout/tests/test_resource_accounting.py create mode 100644 benchmarks/code_behind_layout/tests/test_run_e3_evaluation.py create mode 100644 benchmarks/code_behind_layout/tests/test_run_e3_suite.py create mode 100644 benchmarks/code_behind_layout/tests/test_serve_frozen_policy.py create mode 100644 benchmarks/code_behind_layout/tests/test_span16_reconciliation.py create mode 100644 benchmarks/code_behind_layout/tests/test_spice_validation.py create mode 100644 benchmarks/code_behind_layout/tests/test_student_interface.py create mode 100644 benchmarks/code_behind_layout/tests/test_student_readmission.py create mode 100644 benchmarks/code_behind_layout/tests/test_telescopic_fullflow.py create mode 100644 benchmarks/code_behind_layout/tests/test_telescopic_op_parser.py create mode 100644 benchmarks/code_behind_layout/tests/test_telescopic_supplement.py create mode 100644 benchmarks/code_behind_layout/tests/test_telescopic_supplement_v2.py create mode 100644 benchmarks/code_behind_layout/tests/test_train_pair_nf_collection.py create mode 100644 benchmarks/code_behind_layout/tests/test_train_pair_nf_domains.py create mode 100644 benchmarks/code_behind_layout/tests/test_train_pair_nf_physical.py create mode 100644 benchmarks/code_behind_layout/tests/test_train_pair_nf_rc.py create mode 100644 benchmarks/code_behind_layout/tests/test_train_span_physical_followup.py create mode 100644 benchmarks/code_behind_layout/tests/test_train_span_proposer.py create mode 100644 benchmarks/code_behind_layout/tests/test_train_ugb_terminal_preparation.py create mode 100644 benchmarks/code_behind_layout/tests/test_training.py create mode 100644 benchmarks/code_behind_layout/tests/test_training_physical_store.py create mode 100644 benchmarks/code_behind_layout/tests/test_training_pilot_status.py create mode 100644 benchmarks/code_behind_layout/tests/test_training_selection_v2.py diff --git a/benchmarks/code_behind_layout/.gitignore b/benchmarks/code_behind_layout/.gitignore new file mode 100644 index 00000000..f0db5081 --- /dev/null +++ b/benchmarks/code_behind_layout/.gitignore @@ -0,0 +1,12 @@ +__pycache__/ +*.py[cod] +.DS_Store +.venv/ +/checkpoints/ +/runs/ +/logs/ +/results/ +/tmp/ +/runtime/* +!/runtime/telescopic_sizing_qualification_20261019/ +!/runtime/e3_fidelity_control_20261019/ diff --git a/benchmarks/code_behind_layout/README.md b/benchmarks/code_behind_layout/README.md new file mode 100644 index 00000000..bbc63adf --- /dev/null +++ b/benchmarks/code_behind_layout/README.md @@ -0,0 +1,95 @@ +# The Code Behind the Layout + +Code and frozen configurations for *The Code Behind the Layout: AI Agents for Analog Layout Generators*. The study asks a single question: does one shared edit to a gLayout generator's source improve post-extraction performance across a declared family of parameter configurations, while every configuration that passed before still passes? Every candidate is checked on SKY130: GDS generation, DRC, LVS against an independent reference, RC extraction, and SPICE at the tt/ss/ff corners. + +Two frontier models act as the editing policy: Claude Opus 5.5 and GPT-6.1. A local Qwen2.5-Coder-32B-Instruct model is fine-tuned under point and family supervision, with SFT and DPO. + +## Experiments + +| | Question | Entry points | +| --- | --- | --- | +| E1 | Which action level works: geometry (G0), primitives (G1) or generator source (G2)? | `scripts/run_e1_scope_suite.py`, `scripts/opus_cohort/run_e1_scope_suite_opus_v2.py` | +| E2 | Which cheap signal ranks candidates before full evaluation: area, a geometric rule, extracted RC, or the calibrated interval F3? | `scripts/e2_four_source.py` | +| E3 | Which test rule finds family regressions within a fixed budget: A anchor, R random, B boundary or C risk? | `scripts/run_e3_suite.py`, `scripts/opus_cohort/run_e3_suite_opus.py` | +| E4 | Point vs. family supervision, SFT vs. DPO (T1–T4, seeds 41/73/109) | `scripts/train_policy.py`, `scripts/run_e4_*.sh`, `scripts/e4_checkpoint_validation.py` | +| E5 | Physical CPU, GPU and token cost per verified configuration | `scripts/analyze_e5_costs.py` | + +The protocol is in [docs/protocol.md](docs/protocol.md), [docs/e1_protocol.md](docs/e1_protocol.md) and [docs/e3_protocol.md](docs/e3_protocol.md). The amendments are in [docs/protocol_amendments.md](docs/protocol_amendments.md). The S0/S1/S2 measurement interface is in [docs/measurement_interface.md](docs/measurement_interface.md). + +## Layout + +- `src/` contains the libraries: measurement and S0/S1/S2 assessment, trusted physical store, policy adapters, student interface, training, checkpoint selection and analysis. +- `scripts/` contains the scripts for task preparation, collection, freezes, suite runners, training, analysis and figures. +- `scripts/opus_cohort/` runs the frozen E1/E3 suites with the Claude Opus 5.5 policy. +- `configs/` contains the study definition, model configs, task preparations, frozen experiment manifests (`configs/experiments/frozen/`), training configs and the E4 pool declaration. +- `data/splits/`, `data/manifests/` contain the source-grouped split registry and the collection manifests. +- `reproducibility/glayout_fixes.patch` contains the gLayout fixes used by the E1–E3 circuits. +- `runtime/` contains the two qualified flow modules that the E2/E3 code loads. The data bundle below also extracts here. +- `tests/` contains the unit tests. + +## Data bundle + +The frozen task packets and the E4 training set are distributed separately (`cbl-data-v1.tar.gz`, about 400 MB unpacked): + +```sh +bash scripts/fetch_data.sh +``` + +It extracts the following into this directory: + +- `runtime/protocol_freezes/`: the frozen E1, E2 and E3 manifests with their task packets, registries, model configs, qualification and baseline plans. This includes the private evaluator side (references, benches, hidden configurations). +- `runtime/e4_validation_preparation/`, `runtime/e4_validation_tasks/`: the E4 checkpoint-validation plan, budget and the nine-point validation task. +- `data/training/e4_textbook_v1/`: the E4 training set (see its README). + +## Environment + +- **Analysis and unit tests.** Python 3.12: + + ```sh + python3 -m pip install -r requirements.txt + python3 -m unittest discover -s tests -p 'test_*.py' + ``` + +- **Physical flow.** Runs on Linux with Magic, Netgen, ngspice and SKY130A. Two gLayout trees are used: + - For E1–E3: gLayout at upstream commit `5af536b` with `reproducibility/glayout_fixes.patch` applied. + - For the E4 textbook collections: the `glayout.sharing` module and the `textbook_sharing` benchmark from ReaLLMASIC/gLayout#127. +- **Training.** Needs one 80 GB GPU with PyTorch, Transformers, PEFT and bitsandbytes, and the base model `Qwen/Qwen2.5-Coder-32B-Instruct` at revision `381fc969f78efac66bc87ff7ddeadb7e73c218a7`. + +The scripts that drive the server from a workstation use these placeholders. Recorded paths in the manifests use the same ones. + +| Placeholder | Meaning | +| --- | --- | +| `cbl-server` | SSH host alias of the evaluation and training server (`~/.ssh/config`) | +| `~/.ssh/cbl_server_key` | SSH identity for that host | +| `/srv/code-behind-layout` | Location of this directory on the server | +| `GPT_CLI`, `CLAUDE_CLI` | Command-line clients for the two frontier policies (`src/model_adapter.py`, `src/opus_cli_adapter.py`) | + +## Reproducing + +**E1 and E3.** Run the suite runners against the frozen manifests: + +```sh +python3 scripts/run_e1_scope_suite.py --manifest runtime/protocol_freezes/E1_scope_v2_16k/manifest.json --output runs/E1_gpt +python3 scripts/opus_cohort/run_e1_scope_suite_opus_v2.py --manifest runtime/protocol_freezes/E1_scope_v2_16k_claude_v2/manifest.json --output runs/E1_opus +python3 scripts/run_e3_suite.py --part gpt --manifest runtime/protocol_freezes/E3_primary_v2/manifest.json --output runs/E3_gpt +python3 scripts/opus_cohort/run_e3_suite_opus.py --part gpt --manifest runtime/protocol_freezes/E3_primary_v2_claude/manifest.json --output runs/E3_opus +``` + +E3 parts are `gpt` (the manifest's frontier policy under rules A/R/B/C), `parameter`, `signals`, `fidelity` (F3, with `E3_F3_primary`), `local` and `instance`. Each runner checks its freeze's bound implementation files before dispatch and reserves a trial identity before launch. Failures are recorded, never retried in place. + +**E2.** + +```sh +python3 scripts/e2_four_source.py run --manifest runtime/protocol_freezes/E2_four_source_primary/manifest.json --output runs/E2 --method {full_oracle,fixed_area,adaptive_geometry,fixed_rc_product,f3_calibrated} [--pool-id ] +``` + +**E4.** + +```sh +python3 scripts/train_policy.py --manifest data/training/e4_textbook_v1/training_manifest.json --method T1 --seed 41 --output checkpoints/e4_textbook_v1/T1/seed-41 --validate-only +bash scripts/run_e4_sft_training.sh data/training/e4_textbook_v1 +bash scripts/run_e4_validation_selection.sh data/training/e4_textbook_v1 runtime/e4_validation_preparation/e4_textbook_v1_validation_plan_v2.json T1 41 runs/e4_validation_v2 +bash scripts/run_e4_dpo_training.sh data/training/e4_textbook_v1 runs/e4_validation_v2/e4_textbook_v1/T1 +``` + +`--validate-only` checks admission, the split registry and the samples without a GPU. T3/T4 use `training_manifest_dpo.json`. Checkpoints are selected by mean task S2 fraction on the nine validation points, with ties going to the earliest update; training loss is never used for selection. `scripts/assemble_e4_methods_draft.py` and `scripts/freeze_e4_methods.py` freeze the selected models, and `scripts/serve_frozen_policy.py` serves them to the E3 local-model part. diff --git a/benchmarks/code_behind_layout/configs/analysis/e2_four_source_statistics_v1.json b/benchmarks/code_behind_layout/configs/analysis/e2_four_source_statistics_v1.json new file mode 100644 index 00000000..13af2815 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/analysis/e2_four_source_statistics_v1.json @@ -0,0 +1,94 @@ +{ + "status": "FROZEN_E2_ANALYSIS_PLAN", + "sealed_at_utc": "2026-10-19T06:27:04.783292+00:00", + "activation_evidence": "results/derived/E2_actual_analysis_declaration_pause.json", + "activation_observation": "All five original coordinator parents were paused at 2026-10-19T06:25:05.885Z. Each had zero full, PEX and nominal acquisitions. No formal electrical outcomes were available or inspected for this declaration. Resume preserves all original sources, streams, budgets and records.", + "analysis_id": "E2_four_source_statistics_v1", + "drafted_at_utc": "2026-10-19T06:26:13Z", + "applies_to_backend_manifest": "/srv/code-behind-layout/runtime/protocol_freezes/E2_four_source_primary/manifest.json", + "scope": "Separate prospective statistics declaration. The original E2 freeze did not declare these rank/subset rules. This file does not amend execution, selection, circuits, budgets, or any original record.", + "activation": "Root must seal this declaration and the observed all-five-coordinators full=PEX=nominal=0 pause evidence before resuming. A DRAFT or unbound declaration is exploratory only.", + "candidate_denominator": 64, + "pool_rules": { + "pool_count": 12, + "source_families": 4, + "sizings_per_source": 3, + "generation_attempt_limit": 256, + "generation_failures_and_exact_mask_duplicates": "Keep every attempt and actual acquisition cost. Do not replace a later physical or electrical failure after a candidate is accepted.", + "incomplete_oracle": "Any unmeasured or unresolved accepted candidate keeps the 64-candidate oracle incomplete. No finite-pool regret or full-pool top-k recall is defined.", + "no_feasible_oracle": "Report zero verified feasible and null regret/top-k recall. Do not invent an objective for failed or unknown candidates." + }, + "objective": { + "name": "worst_ugb_Hz", + "unit": "Hz", + "direction": "max", + "feasible_selection_requires": "Complete original frozen physical, device-intent, analysis and electrical constraints over tt/ss/ff, with S2=true." + }, + "near_frontier": { + "fraction": 0.2, + "count": "ceil(fraction * accepted_pool_size); 13 for the declared 64", + "selection": "Ascending actual physical_mask_bbox_area_um2, then ascending stream_index", + "selection_timing": "Membership uses geometry only, before conditioning on any PEX, nominal or full electrical outcome. Do not select the subset using true UGB or S2.", + "report_with": "Broad-pool and near-frontier results, declared/matched/nonrankable/unknown counts, and original accepted candidate denominator." + }, + "numeric_ties": { + "prediction_absolute_tolerance": 0.0, + "actual_absolute_tolerance": 0.0, + "relative_tolerance": 0.0, + "primary": "Exact saved finite numeric values; Spearman average ranks and Kendall tau-b exact ties. Ranking cutoffs use ascending stream_index to select exactly k.", + "evidence": "results/derived/E2_actual_repeat_precision_evidence.json", + "evidence_limit": "Three same-PEX/same-original-TT-deck saved repetitions have identical decks and 9-significant-digit printed AC vectors, with observed maximum difference zero. This does not establish universally zero simulation noise." + }, + "precision_sensitivity": { + "method": "Propagate each of the two printed unity-crossing rows' 9-significant-digit half-ULP intervals through the unchanged frozen measurement interpolation. Effective pair reversal uses only pairs with nonoverlapping actual and predictor intervals.", + "eligibility": "Only intervals derived from the actual candidate's saved rows and exact frozen measurement rule; an absent/unverified interval yields UNAVAILABLE for this sensitivity, not an invented tolerance.", + "primary_results_unchanged": true + }, + "rank_tables": { + "same_objective_estimates": [ + "actually acquired nominal_tt_ugb_Hz", + "saved frozen-calibration prediction_ugb_Hz" + ], + "same_objective_metrics": [ + "Spearman", + "Kendall_tau_b", + "effective_pair_reversal_rate", + "top_k_recall" + ], + "descriptive_features": [ + "physical_mask_bbox_area_um2", + "union_rectilinear_proxy_um", + "R_sum_times_C_sum_s" + ], + "descriptive_feature_interpretation": "Negative feature score ranks smaller area/wire/RC ahead. Report rank association and top-k selection recall only; this is not calibrated UGB prediction or same-unit prediction-error/reversal evidence.", + "rank_eligibility": "Use matched finite actual UGB and actually acquired predictor/feature values. Full-pool primary tables require a complete oracle; explicitly labeled conditional measured-pair diagnostics may be shown for incomplete pools, with all exclusions counted. Never turn failed or unknown measurements into zero UGB." + }, + "top_k": { + "fraction": 0.2, + "predicted_count": "ceil(fraction * accepted_pool_size)", + "actual_target_count": "min(predicted_count, number of complete S2-feasible candidates)", + "actual_target": "Highest worst_ugb_Hz among complete S2-feasible candidates; stream_index breaks exact ties", + "recall": "Size of predicted top-k intersect actual target, divided by actual_target_count. All accepted candidates must have the declared score, and the finite-pool oracle must be complete; otherwise unavailable. Known infeasible candidates still consume predicted selection slots." + }, + "same_sized_netlist_prelayout": { + "rule": "One constant schematic benchmark per independently fixed N(z). It has no layout ranking or rank correlation. Do not rank the 64 layouts using repeated copies of the same prelayout value, and do not pool different sized netlists to manufacture a layout ranking." + }, + "selection_comparisons": { + "finite_pool_oracle": "Complete 64-candidate reference, identified separately from execution of every online strategy.", + "offline_replay": "Label any retrospective replay explicitly OFFLINE_ORACLE_REPLAY; account for the actual measurements used to construct it. It is not an online saving measurement.", + "real_online": "Use the independently executed method's actual ordered full_evaluations and all actual geometry/PEX/nominal acquisitions. No other method's labels entered its decisions.", + "join_requirement": "Same frozen pool/source/N/contract/deck/PDK/tool bindings and accepted stream indices, plus actual retained-GDS mask equality. IDs, bbox summaries or a declaration alone do not prove pool equality.", + "regret": "Oracle best feasible worst_ugb_Hz minus best actually delivered verified feasible worst_ugb_Hz, in Hz. Null if oracle incomplete/has no feasible candidate, or the online method has no verified feasible delivery." + }, + "budget_curves": { + "query_axis": "Actual full-query attempts in recorded order; retain physical failure and unknown attempts", + "time_axis": "Only actual recorded timestamps/costs. Missing timing remains unavailable. Do not infer wall or CPU from allocation, query number or theoretical simulator count.", + "costs": "Charge generation failures/duplicates and every actually acquired fidelity, host mask/controller work and queue/deployment work. Nested references to the same physical run are counted once; per-SPICE CPU is a component of trusted CPU, not added twice." + }, + "reporting_units": "Pool results remain separate by source and sized N; 64 layouts and three sizings are not independent circuits. Any cross-pool uncertainty resamples whole source-family clusters and states that there are four source families.", + "no_formal_results_read_for_this_draft": true, + "new_model_or_EDA_calls": 0, + "execution_freeze_id": "E2_four_source_primary", + "execution_manifest": "/srv/code-behind-layout/runtime/protocol_freezes/E2_four_source_primary/manifest.json", + "pause_evidence": "results/derived/E2_actual_analysis_declaration_pause.json" +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_collection_final_preparation.json b/benchmarks/code_behind_layout/configs/development/c01_collection_final_preparation.json new file mode 100644 index 00000000..7585ffbc --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_collection_final_preparation.json @@ -0,0 +1,1715 @@ +{ + "status": "DRAFT_READONLY_COLLECTION_CAPSULE_NOT_FROZEN", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "source_pack": "/srv/code-behind-layout/runtime/collection_preparation/c01_20261019T011833920147Z/source_pack", + "source_files": [ + "LICENSE", + "circuit_input.json", + "generator.py", + "glayout/__init__.py", + "glayout/backend/__init__.py", + "glayout/backend/_gdsfactory.py", + "glayout/backend/_gdstk.py", + "glayout/pdk/__init__.py", + "glayout/pdk/gf180_mapped/__init__.py", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x02p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x04p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x08p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x16p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_05p00x05p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_10p00x10p00.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_05p00x00p42.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_05p00x05p00.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_10p00x00p42.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_10p00x10p00.gds", + "glayout/pdk/gf180_mapped/gf180_grules.py", + "glayout/pdk/gf180_mapped/gf180_mapped.py", + "glayout/pdk/gf180_mapped/gf180mcu.drc", + "glayout/pdk/gf180_mapped/gf180mcu_drc.lydrc", + "glayout/pdk/gf180_mapped/gf180mcu_drc_wrapper.drc", + "glayout/pdk/gf180_mapped/gf180mcu_osu_sc_9T.spice", + "glayout/pdk/ihp130_mapped/__init__.py", + "glayout/pdk/ihp130_mapped/ihp130_drc.lydrc", + "glayout/pdk/ihp130_mapped/ihp130_grules.py", + "glayout/pdk/ihp130_mapped/ihp130_mapped.py", + "glayout/pdk/mappedpdk.py", + "glayout/pdk/sky130_mapped/__init__.py", + "glayout/pdk/sky130_mapped/sky130.lydrc", + "glayout/pdk/sky130_mapped/sky130_add_npc.py", + "glayout/pdk/sky130_mapped/sky130_fd_sc_hd.spice", + "glayout/pdk/sky130_mapped/sky130_grules.py", + "glayout/pdk/sky130_mapped/sky130_mapped.py", + "glayout/placement/__init__.py", + "glayout/placement/common_centroid_ab_ba.py", + "glayout/placement/four_transistor_interdigitized.py", + "glayout/placement/two_transistor_interdigitized.py", + "glayout/placement/two_transistor_place.py", + "glayout/primitives/__init__.py", + "glayout/primitives/bjt.py", + "glayout/primitives/fet.py", + "glayout/primitives/guardring.py", + "glayout/primitives/mimcap.py", + "glayout/primitives/resistor.py", + "glayout/primitives/via_gen.py", + "glayout/routing/L_route.py", + "glayout/routing/__init__.py", + "glayout/routing/c_route.py", + "glayout/routing/smart_route.py", + "glayout/routing/straight_route.py", + "glayout/sharing/README.md", + "glayout/sharing/__init__.py", + "glayout/sharing/enumeration.py", + "glayout/sharing/evidence.py", + "glayout/sharing/group.py", + "glayout/sharing/rules.py", + "glayout/sharing/spec.py", + "glayout/spice/__init__.py", + "glayout/spice/netlist.py", + "glayout/util/__init__.py", + "glayout/util/comp_utils.py", + "glayout/util/component_array_create.py", + "glayout/util/geometry.py", + "glayout/util/pattern.py", + "glayout/util/port_utils.py", + "glayout/util/print_rules.py", + "glayout/util/routing.py", + "glayout/util/snap_to_grid.py", + "sizing_input.json", + "textbook_sharing/__init__.py", + "textbook_sharing/assembly/__init__.py", + "textbook_sharing/assembly/adapters.py", + "textbook_sharing/assembly/engine.py", + "textbook_sharing/assembly/passives.py", + "textbook_sharing/assembly/pincell.py", + "textbook_sharing/layout.py", + "textbook_sharing/netlist.py" + ], + "editable_paths": [ + "textbook_sharing/layout.py", + "glayout/sharing/enumeration.py" + ], + "trusted_bundle": "/srv/code-behind-layout/runtime/collection_preparation/c01_20261019T011833920147Z/trusted", + "trusted_files": [ + "contracts/anchor.json", + "contracts/dev_l120.json", + "contracts/dev_nf1_l030.json", + "contracts/dev_nf2_l060.json", + "contracts/dev_nf3_l045.json", + "contracts/dev_nf6_l060.json", + "contracts/dev_nf8_l090.json", + "contracts/dev_w075_l045.json", + "contracts/dev_w100_l060.json", + "evaluate.py", + "physical.py", + "references/anchor.spice", + "references/dev_l120.spice", + "references/dev_nf1_l030.spice", + "references/dev_nf2_l060.spice", + "references/dev_nf3_l045.spice", + "references/dev_nf6_l060.spice", + "references/dev_nf8_l090.spice", + "references/dev_w075_l045.spice", + "references/dev_w100_l060.spice", + "run_pex.sh", + "src/__init__.py", + "src/corpus_metrics.py", + "src/measurement.py", + "src/physical_drc.py", + "src/report_parsers.py", + "src/spice_validation.py" + ], + "configurations": [ + { + "configuration_id": "anchor", + "parameters": { + "configuration_id": "anchor", + "circuit": { + "circuit_id": "C01", + "name": "basic_current_mirror", + "ports": [ + "VSS", + "IB1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IB1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "IOUT1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 726, + "files": [ + "Dataset/726/726.cir", + "Dataset/726/Port726.txt", + "Dataset/726/Pagenumber726.txt", + "Dataset/726/Book726.png", + "Dataset/726/Cadence726.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "305", + "device_name_map": { + "M1": "M3", + "M2": "M5" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/726/Book726.png", + "observation": "Johns p.305 scan: Q1 diode-connected NMOS, Q2 output NMOS gate tied through a long wire (bias-distribution figure); basic 1:1 mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M2": { + "w": 2.0, + "l": 0.6, + "nf": 4 + } + }, + "top_cell": "corpus_c01" + }, + "reference_id": "c01_anchor_independent_perfinger", + "contract": { + "task_id": "train_collection_c01", + "configuration_id": "anchor", + "reference_id": "c01_anchor_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ] + }, + "role": "anchor" + }, + { + "configuration_id": "dev_nf1_l030", + "parameters": { + "configuration_id": "dev_nf1_l030", + "circuit": { + "circuit_id": "C01", + "name": "basic_current_mirror", + "ports": [ + "VSS", + "IB1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IB1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "IOUT1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 726, + "files": [ + "Dataset/726/726.cir", + "Dataset/726/Port726.txt", + "Dataset/726/Pagenumber726.txt", + "Dataset/726/Book726.png", + "Dataset/726/Cadence726.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "305", + "device_name_map": { + "M1": "M3", + "M2": "M5" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/726/Book726.png", + "observation": "Johns p.305 scan: Q1 diode-connected NMOS, Q2 output NMOS gate tied through a long wire (bias-distribution figure); basic 1:1 mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 0.5, + "l": 0.3, + "nf": 1 + }, + "M2": { + "w": 0.5, + "l": 0.3, + "nf": 1 + } + }, + "top_cell": "corpus_c01" + }, + "reference_id": "c01_dev_nf1_l030_independent_perfinger", + "contract": { + "task_id": "train_collection_c01", + "configuration_id": "dev_nf1_l030", + "reference_id": "c01_dev_nf1_l030_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ] + }, + "role": "development" + }, + { + "configuration_id": "dev_nf2_l060", + "parameters": { + "configuration_id": "dev_nf2_l060", + "circuit": { + "circuit_id": "C01", + "name": "basic_current_mirror", + "ports": [ + "VSS", + "IB1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IB1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "IOUT1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 726, + "files": [ + "Dataset/726/726.cir", + "Dataset/726/Port726.txt", + "Dataset/726/Pagenumber726.txt", + "Dataset/726/Book726.png", + "Dataset/726/Cadence726.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "305", + "device_name_map": { + "M1": "M3", + "M2": "M5" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/726/Book726.png", + "observation": "Johns p.305 scan: Q1 diode-connected NMOS, Q2 output NMOS gate tied through a long wire (bias-distribution figure); basic 1:1 mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 1.0, + "l": 0.6, + "nf": 2 + }, + "M2": { + "w": 1.0, + "l": 0.6, + "nf": 2 + } + }, + "top_cell": "corpus_c01" + }, + "reference_id": "c01_dev_nf2_l060_independent_perfinger", + "contract": { + "task_id": "train_collection_c01", + "configuration_id": "dev_nf2_l060", + "reference_id": "c01_dev_nf2_l060_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ] + }, + "role": "development" + }, + { + "configuration_id": "dev_nf3_l045", + "parameters": { + "configuration_id": "dev_nf3_l045", + "circuit": { + "circuit_id": "C01", + "name": "basic_current_mirror", + "ports": [ + "VSS", + "IB1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IB1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "IOUT1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 726, + "files": [ + "Dataset/726/726.cir", + "Dataset/726/Port726.txt", + "Dataset/726/Pagenumber726.txt", + "Dataset/726/Book726.png", + "Dataset/726/Cadence726.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "305", + "device_name_map": { + "M1": "M3", + "M2": "M5" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/726/Book726.png", + "observation": "Johns p.305 scan: Q1 diode-connected NMOS, Q2 output NMOS gate tied through a long wire (bias-distribution figure); basic 1:1 mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 1.5, + "l": 0.45, + "nf": 3 + }, + "M2": { + "w": 1.5, + "l": 0.45, + "nf": 3 + } + }, + "top_cell": "corpus_c01" + }, + "reference_id": "c01_dev_nf3_l045_independent_perfinger", + "contract": { + "task_id": "train_collection_c01", + "configuration_id": "dev_nf3_l045", + "reference_id": "c01_dev_nf3_l045_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ] + }, + "role": "development" + }, + { + "configuration_id": "dev_nf6_l060", + "parameters": { + "configuration_id": "dev_nf6_l060", + "circuit": { + "circuit_id": "C01", + "name": "basic_current_mirror", + "ports": [ + "VSS", + "IB1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IB1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "IOUT1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 726, + "files": [ + "Dataset/726/726.cir", + "Dataset/726/Port726.txt", + "Dataset/726/Pagenumber726.txt", + "Dataset/726/Book726.png", + "Dataset/726/Cadence726.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "305", + "device_name_map": { + "M1": "M3", + "M2": "M5" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/726/Book726.png", + "observation": "Johns p.305 scan: Q1 diode-connected NMOS, Q2 output NMOS gate tied through a long wire (bias-distribution figure); basic 1:1 mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 3.0, + "l": 0.6, + "nf": 6 + }, + "M2": { + "w": 3.0, + "l": 0.6, + "nf": 6 + } + }, + "top_cell": "corpus_c01" + }, + "reference_id": "c01_dev_nf6_l060_independent_perfinger", + "contract": { + "task_id": "train_collection_c01", + "configuration_id": "dev_nf6_l060", + "reference_id": "c01_dev_nf6_l060_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ] + }, + "role": "development" + }, + { + "configuration_id": "dev_nf8_l090", + "parameters": { + "configuration_id": "dev_nf8_l090", + "circuit": { + "circuit_id": "C01", + "name": "basic_current_mirror", + "ports": [ + "VSS", + "IB1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IB1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "IOUT1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 726, + "files": [ + "Dataset/726/726.cir", + "Dataset/726/Port726.txt", + "Dataset/726/Pagenumber726.txt", + "Dataset/726/Book726.png", + "Dataset/726/Cadence726.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "305", + "device_name_map": { + "M1": "M3", + "M2": "M5" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/726/Book726.png", + "observation": "Johns p.305 scan: Q1 diode-connected NMOS, Q2 output NMOS gate tied through a long wire (bias-distribution figure); basic 1:1 mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 4.0, + "l": 0.9, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.9, + "nf": 8 + } + }, + "top_cell": "corpus_c01" + }, + "reference_id": "c01_dev_nf8_l090_independent_perfinger", + "contract": { + "task_id": "train_collection_c01", + "configuration_id": "dev_nf8_l090", + "reference_id": "c01_dev_nf8_l090_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ] + }, + "role": "development" + }, + { + "configuration_id": "dev_w075_l045", + "parameters": { + "configuration_id": "dev_w075_l045", + "circuit": { + "circuit_id": "C01", + "name": "basic_current_mirror", + "ports": [ + "VSS", + "IB1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IB1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "IOUT1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 726, + "files": [ + "Dataset/726/726.cir", + "Dataset/726/Port726.txt", + "Dataset/726/Pagenumber726.txt", + "Dataset/726/Book726.png", + "Dataset/726/Cadence726.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "305", + "device_name_map": { + "M1": "M3", + "M2": "M5" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/726/Book726.png", + "observation": "Johns p.305 scan: Q1 diode-connected NMOS, Q2 output NMOS gate tied through a long wire (bias-distribution figure); basic 1:1 mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 3.0, + "l": 0.45, + "nf": 4 + }, + "M2": { + "w": 3.0, + "l": 0.45, + "nf": 4 + } + }, + "top_cell": "corpus_c01" + }, + "reference_id": "c01_dev_w075_l045_independent_perfinger", + "contract": { + "task_id": "train_collection_c01", + "configuration_id": "dev_w075_l045", + "reference_id": "c01_dev_w075_l045_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ] + }, + "role": "development" + }, + { + "configuration_id": "dev_w100_l060", + "parameters": { + "configuration_id": "dev_w100_l060", + "circuit": { + "circuit_id": "C01", + "name": "basic_current_mirror", + "ports": [ + "VSS", + "IB1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IB1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "IOUT1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 726, + "files": [ + "Dataset/726/726.cir", + "Dataset/726/Port726.txt", + "Dataset/726/Pagenumber726.txt", + "Dataset/726/Book726.png", + "Dataset/726/Cadence726.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "305", + "device_name_map": { + "M1": "M3", + "M2": "M5" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/726/Book726.png", + "observation": "Johns p.305 scan: Q1 diode-connected NMOS, Q2 output NMOS gate tied through a long wire (bias-distribution figure); basic 1:1 mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 4.0, + "l": 0.6, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 0.6, + "nf": 4 + } + }, + "top_cell": "corpus_c01" + }, + "reference_id": "c01_dev_w100_l060_independent_perfinger", + "contract": { + "task_id": "train_collection_c01", + "configuration_id": "dev_w100_l060", + "reference_id": "c01_dev_w100_l060_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ] + }, + "role": "development" + }, + { + "configuration_id": "dev_l120", + "parameters": { + "configuration_id": "dev_l120", + "circuit": { + "circuit_id": "C01", + "name": "basic_current_mirror", + "ports": [ + "VSS", + "IB1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IB1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "IOUT1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 726, + "files": [ + "Dataset/726/726.cir", + "Dataset/726/Port726.txt", + "Dataset/726/Pagenumber726.txt", + "Dataset/726/Book726.png", + "Dataset/726/Cadence726.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "305", + "device_name_map": { + "M1": "M3", + "M2": "M5" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/726/Book726.png", + "observation": "Johns p.305 scan: Q1 diode-connected NMOS, Q2 output NMOS gate tied through a long wire (bias-distribution figure); basic 1:1 mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 2.0, + "l": 1.2, + "nf": 4 + }, + "M2": { + "w": 2.0, + "l": 1.2, + "nf": 4 + } + }, + "top_cell": "corpus_c01" + }, + "reference_id": "c01_dev_l120_independent_perfinger", + "contract": { + "task_id": "train_collection_c01", + "configuration_id": "dev_l120", + "reference_id": "c01_dev_l120_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ] + }, + "role": "development" + } + ], + "formal_training_rows": 0, + "formal_collection_started": false, + "per_task_context_scope": "complete modules only; actual length gate, no truncation; C08 uses a separate narrower scope if necessary", + "candidate_boundary": "explicit source/library only, sole GDS handoff to trusted process", + "label_rule_draft": { + "objectives": { + "c01_area_min": { + "metric": "area", + "unit": "um2", + "direction": "min", + "quality_absolute_tolerance": 1e-08, + "quality_relative_tolerance": 1e-06, + "quality_minimum_relative_effect": 0.01 + } + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_collection_preparation.json b/benchmarks/code_behind_layout/configs/development/c01_collection_preparation.json new file mode 100644 index 00000000..c68a8393 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_collection_preparation.json @@ -0,0 +1,1715 @@ +{ + "status": "DRAFT_READONLY_COLLECTION_CAPSULE_NOT_FROZEN", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "source_pack": "/srv/code-behind-layout/runtime/collection_preparation/c01_20261019T011319931899Z/source_pack", + "source_files": [ + "LICENSE", + "circuit_input.json", + "generator.py", + "glayout/__init__.py", + "glayout/backend/__init__.py", + "glayout/backend/_gdsfactory.py", + "glayout/backend/_gdstk.py", + "glayout/pdk/__init__.py", + "glayout/pdk/gf180_mapped/__init__.py", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x02p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x04p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x08p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x16p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_05p00x05p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_10p00x10p00.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_05p00x00p42.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_05p00x05p00.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_10p00x00p42.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_10p00x10p00.gds", + "glayout/pdk/gf180_mapped/gf180_grules.py", + "glayout/pdk/gf180_mapped/gf180_mapped.py", + "glayout/pdk/gf180_mapped/gf180mcu.drc", + "glayout/pdk/gf180_mapped/gf180mcu_drc.lydrc", + "glayout/pdk/gf180_mapped/gf180mcu_drc_wrapper.drc", + "glayout/pdk/gf180_mapped/gf180mcu_osu_sc_9T.spice", + "glayout/pdk/ihp130_mapped/__init__.py", + "glayout/pdk/ihp130_mapped/ihp130_drc.lydrc", + "glayout/pdk/ihp130_mapped/ihp130_grules.py", + "glayout/pdk/ihp130_mapped/ihp130_mapped.py", + "glayout/pdk/mappedpdk.py", + "glayout/pdk/sky130_mapped/__init__.py", + "glayout/pdk/sky130_mapped/sky130.lydrc", + "glayout/pdk/sky130_mapped/sky130_add_npc.py", + "glayout/pdk/sky130_mapped/sky130_fd_sc_hd.spice", + "glayout/pdk/sky130_mapped/sky130_grules.py", + "glayout/pdk/sky130_mapped/sky130_mapped.py", + "glayout/placement/__init__.py", + "glayout/placement/common_centroid_ab_ba.py", + "glayout/placement/four_transistor_interdigitized.py", + "glayout/placement/two_transistor_interdigitized.py", + "glayout/placement/two_transistor_place.py", + "glayout/primitives/__init__.py", + "glayout/primitives/bjt.py", + "glayout/primitives/fet.py", + "glayout/primitives/guardring.py", + "glayout/primitives/mimcap.py", + "glayout/primitives/resistor.py", + "glayout/primitives/via_gen.py", + "glayout/routing/L_route.py", + "glayout/routing/__init__.py", + "glayout/routing/c_route.py", + "glayout/routing/smart_route.py", + "glayout/routing/straight_route.py", + "glayout/sharing/README.md", + "glayout/sharing/__init__.py", + "glayout/sharing/enumeration.py", + "glayout/sharing/evidence.py", + "glayout/sharing/group.py", + "glayout/sharing/rules.py", + "glayout/sharing/spec.py", + "glayout/spice/__init__.py", + "glayout/spice/netlist.py", + "glayout/util/__init__.py", + "glayout/util/comp_utils.py", + "glayout/util/component_array_create.py", + "glayout/util/geometry.py", + "glayout/util/pattern.py", + "glayout/util/port_utils.py", + "glayout/util/print_rules.py", + "glayout/util/routing.py", + "glayout/util/snap_to_grid.py", + "sizing_input.json", + "textbook_sharing/__init__.py", + "textbook_sharing/assembly/__init__.py", + "textbook_sharing/assembly/adapters.py", + "textbook_sharing/assembly/engine.py", + "textbook_sharing/assembly/passives.py", + "textbook_sharing/assembly/pincell.py", + "textbook_sharing/layout.py", + "textbook_sharing/netlist.py" + ], + "editable_paths": [ + "textbook_sharing/layout.py", + "glayout/sharing/enumeration.py" + ], + "trusted_bundle": "/srv/code-behind-layout/runtime/collection_preparation/c01_20261019T011319931899Z/trusted", + "trusted_files": [ + "contracts/anchor.json", + "contracts/dev_l120.json", + "contracts/dev_nf1_l030.json", + "contracts/dev_nf2_l060.json", + "contracts/dev_nf3_l045.json", + "contracts/dev_nf6_l060.json", + "contracts/dev_nf8_l090.json", + "contracts/dev_w075_l045.json", + "contracts/dev_w100_l060.json", + "evaluate.py", + "physical.py", + "references/anchor.spice", + "references/dev_l120.spice", + "references/dev_nf1_l030.spice", + "references/dev_nf2_l060.spice", + "references/dev_nf3_l045.spice", + "references/dev_nf6_l060.spice", + "references/dev_nf8_l090.spice", + "references/dev_w075_l045.spice", + "references/dev_w100_l060.spice", + "run_pex.sh", + "src/__init__.py", + "src/corpus_metrics.py", + "src/measurement.py", + "src/physical_drc.py", + "src/report_parsers.py", + "src/spice_validation.py" + ], + "configurations": [ + { + "configuration_id": "anchor", + "parameters": { + "configuration_id": "anchor", + "circuit": { + "circuit_id": "C01", + "name": "basic_current_mirror", + "ports": [ + "VSS", + "IB1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IB1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "IOUT1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 726, + "files": [ + "Dataset/726/726.cir", + "Dataset/726/Port726.txt", + "Dataset/726/Pagenumber726.txt", + "Dataset/726/Book726.png", + "Dataset/726/Cadence726.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "305", + "device_name_map": { + "M1": "M3", + "M2": "M5" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/726/Book726.png", + "observation": "Johns p.305 scan: Q1 diode-connected NMOS, Q2 output NMOS gate tied through a long wire (bias-distribution figure); basic 1:1 mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M2": { + "w": 2.0, + "l": 0.6, + "nf": 4 + } + }, + "top_cell": "corpus_c01" + }, + "reference_id": "c01_anchor_independent_perfinger", + "contract": { + "task_id": "train_collection_c01", + "configuration_id": "anchor", + "reference_id": "c01_anchor_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ] + }, + "role": "anchor" + }, + { + "configuration_id": "dev_nf1_l030", + "parameters": { + "configuration_id": "dev_nf1_l030", + "circuit": { + "circuit_id": "C01", + "name": "basic_current_mirror", + "ports": [ + "VSS", + "IB1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IB1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "IOUT1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 726, + "files": [ + "Dataset/726/726.cir", + "Dataset/726/Port726.txt", + "Dataset/726/Pagenumber726.txt", + "Dataset/726/Book726.png", + "Dataset/726/Cadence726.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "305", + "device_name_map": { + "M1": "M3", + "M2": "M5" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/726/Book726.png", + "observation": "Johns p.305 scan: Q1 diode-connected NMOS, Q2 output NMOS gate tied through a long wire (bias-distribution figure); basic 1:1 mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 0.5, + "l": 0.3, + "nf": 1 + }, + "M2": { + "w": 0.5, + "l": 0.3, + "nf": 1 + } + }, + "top_cell": "corpus_c01" + }, + "reference_id": "c01_dev_nf1_l030_independent_perfinger", + "contract": { + "task_id": "train_collection_c01", + "configuration_id": "dev_nf1_l030", + "reference_id": "c01_dev_nf1_l030_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ] + }, + "role": "development" + }, + { + "configuration_id": "dev_nf2_l060", + "parameters": { + "configuration_id": "dev_nf2_l060", + "circuit": { + "circuit_id": "C01", + "name": "basic_current_mirror", + "ports": [ + "VSS", + "IB1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IB1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "IOUT1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 726, + "files": [ + "Dataset/726/726.cir", + "Dataset/726/Port726.txt", + "Dataset/726/Pagenumber726.txt", + "Dataset/726/Book726.png", + "Dataset/726/Cadence726.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "305", + "device_name_map": { + "M1": "M3", + "M2": "M5" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/726/Book726.png", + "observation": "Johns p.305 scan: Q1 diode-connected NMOS, Q2 output NMOS gate tied through a long wire (bias-distribution figure); basic 1:1 mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 1.0, + "l": 0.6, + "nf": 2 + }, + "M2": { + "w": 1.0, + "l": 0.6, + "nf": 2 + } + }, + "top_cell": "corpus_c01" + }, + "reference_id": "c01_dev_nf2_l060_independent_perfinger", + "contract": { + "task_id": "train_collection_c01", + "configuration_id": "dev_nf2_l060", + "reference_id": "c01_dev_nf2_l060_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ] + }, + "role": "development" + }, + { + "configuration_id": "dev_nf3_l045", + "parameters": { + "configuration_id": "dev_nf3_l045", + "circuit": { + "circuit_id": "C01", + "name": "basic_current_mirror", + "ports": [ + "VSS", + "IB1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IB1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "IOUT1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 726, + "files": [ + "Dataset/726/726.cir", + "Dataset/726/Port726.txt", + "Dataset/726/Pagenumber726.txt", + "Dataset/726/Book726.png", + "Dataset/726/Cadence726.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "305", + "device_name_map": { + "M1": "M3", + "M2": "M5" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/726/Book726.png", + "observation": "Johns p.305 scan: Q1 diode-connected NMOS, Q2 output NMOS gate tied through a long wire (bias-distribution figure); basic 1:1 mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 1.5, + "l": 0.45, + "nf": 3 + }, + "M2": { + "w": 1.5, + "l": 0.45, + "nf": 3 + } + }, + "top_cell": "corpus_c01" + }, + "reference_id": "c01_dev_nf3_l045_independent_perfinger", + "contract": { + "task_id": "train_collection_c01", + "configuration_id": "dev_nf3_l045", + "reference_id": "c01_dev_nf3_l045_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ] + }, + "role": "development" + }, + { + "configuration_id": "dev_nf6_l060", + "parameters": { + "configuration_id": "dev_nf6_l060", + "circuit": { + "circuit_id": "C01", + "name": "basic_current_mirror", + "ports": [ + "VSS", + "IB1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IB1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "IOUT1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 726, + "files": [ + "Dataset/726/726.cir", + "Dataset/726/Port726.txt", + "Dataset/726/Pagenumber726.txt", + "Dataset/726/Book726.png", + "Dataset/726/Cadence726.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "305", + "device_name_map": { + "M1": "M3", + "M2": "M5" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/726/Book726.png", + "observation": "Johns p.305 scan: Q1 diode-connected NMOS, Q2 output NMOS gate tied through a long wire (bias-distribution figure); basic 1:1 mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 3.0, + "l": 0.6, + "nf": 6 + }, + "M2": { + "w": 3.0, + "l": 0.6, + "nf": 6 + } + }, + "top_cell": "corpus_c01" + }, + "reference_id": "c01_dev_nf6_l060_independent_perfinger", + "contract": { + "task_id": "train_collection_c01", + "configuration_id": "dev_nf6_l060", + "reference_id": "c01_dev_nf6_l060_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ] + }, + "role": "development" + }, + { + "configuration_id": "dev_nf8_l090", + "parameters": { + "configuration_id": "dev_nf8_l090", + "circuit": { + "circuit_id": "C01", + "name": "basic_current_mirror", + "ports": [ + "VSS", + "IB1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IB1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "IOUT1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 726, + "files": [ + "Dataset/726/726.cir", + "Dataset/726/Port726.txt", + "Dataset/726/Pagenumber726.txt", + "Dataset/726/Book726.png", + "Dataset/726/Cadence726.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "305", + "device_name_map": { + "M1": "M3", + "M2": "M5" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/726/Book726.png", + "observation": "Johns p.305 scan: Q1 diode-connected NMOS, Q2 output NMOS gate tied through a long wire (bias-distribution figure); basic 1:1 mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 4.0, + "l": 0.9, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.9, + "nf": 8 + } + }, + "top_cell": "corpus_c01" + }, + "reference_id": "c01_dev_nf8_l090_independent_perfinger", + "contract": { + "task_id": "train_collection_c01", + "configuration_id": "dev_nf8_l090", + "reference_id": "c01_dev_nf8_l090_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ] + }, + "role": "development" + }, + { + "configuration_id": "dev_w075_l045", + "parameters": { + "configuration_id": "dev_w075_l045", + "circuit": { + "circuit_id": "C01", + "name": "basic_current_mirror", + "ports": [ + "VSS", + "IB1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IB1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "IOUT1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 726, + "files": [ + "Dataset/726/726.cir", + "Dataset/726/Port726.txt", + "Dataset/726/Pagenumber726.txt", + "Dataset/726/Book726.png", + "Dataset/726/Cadence726.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "305", + "device_name_map": { + "M1": "M3", + "M2": "M5" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/726/Book726.png", + "observation": "Johns p.305 scan: Q1 diode-connected NMOS, Q2 output NMOS gate tied through a long wire (bias-distribution figure); basic 1:1 mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 3.0, + "l": 0.45, + "nf": 4 + }, + "M2": { + "w": 3.0, + "l": 0.45, + "nf": 4 + } + }, + "top_cell": "corpus_c01" + }, + "reference_id": "c01_dev_w075_l045_independent_perfinger", + "contract": { + "task_id": "train_collection_c01", + "configuration_id": "dev_w075_l045", + "reference_id": "c01_dev_w075_l045_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ] + }, + "role": "development" + }, + { + "configuration_id": "dev_w100_l060", + "parameters": { + "configuration_id": "dev_w100_l060", + "circuit": { + "circuit_id": "C01", + "name": "basic_current_mirror", + "ports": [ + "VSS", + "IB1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IB1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "IOUT1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 726, + "files": [ + "Dataset/726/726.cir", + "Dataset/726/Port726.txt", + "Dataset/726/Pagenumber726.txt", + "Dataset/726/Book726.png", + "Dataset/726/Cadence726.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "305", + "device_name_map": { + "M1": "M3", + "M2": "M5" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/726/Book726.png", + "observation": "Johns p.305 scan: Q1 diode-connected NMOS, Q2 output NMOS gate tied through a long wire (bias-distribution figure); basic 1:1 mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 4.0, + "l": 0.6, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 0.6, + "nf": 4 + } + }, + "top_cell": "corpus_c01" + }, + "reference_id": "c01_dev_w100_l060_independent_perfinger", + "contract": { + "task_id": "train_collection_c01", + "configuration_id": "dev_w100_l060", + "reference_id": "c01_dev_w100_l060_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ] + }, + "role": "development" + }, + { + "configuration_id": "dev_l120", + "parameters": { + "configuration_id": "dev_l120", + "circuit": { + "circuit_id": "C01", + "name": "basic_current_mirror", + "ports": [ + "VSS", + "IB1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IB1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "IOUT1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 726, + "files": [ + "Dataset/726/726.cir", + "Dataset/726/Port726.txt", + "Dataset/726/Pagenumber726.txt", + "Dataset/726/Book726.png", + "Dataset/726/Cadence726.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "305", + "device_name_map": { + "M1": "M3", + "M2": "M5" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/726/Book726.png", + "observation": "Johns p.305 scan: Q1 diode-connected NMOS, Q2 output NMOS gate tied through a long wire (bias-distribution figure); basic 1:1 mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 2.0, + "l": 1.2, + "nf": 4 + }, + "M2": { + "w": 2.0, + "l": 1.2, + "nf": 4 + } + }, + "top_cell": "corpus_c01" + }, + "reference_id": "c01_dev_l120_independent_perfinger", + "contract": { + "task_id": "train_collection_c01", + "configuration_id": "dev_l120", + "reference_id": "c01_dev_l120_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ] + }, + "role": "development" + } + ], + "formal_training_rows": 0, + "formal_collection_started": false, + "per_task_context_scope": "complete modules only; actual length gate, no truncation; C08 uses a separate narrower scope if necessary", + "candidate_boundary": "explicit source/library only, sole GDS handoff to trusted process", + "label_rule_draft": { + "objectives": { + "c01_area_min": { + "metric": "area", + "unit": "um2", + "direction": "min", + "quality_absolute_tolerance": 1e-08, + "quality_relative_tolerance": 1e-06, + "quality_minimum_relative_effect": 0.01 + } + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_collection_v2_preparation.json b/benchmarks/code_behind_layout/configs/development/c01_collection_v2_preparation.json new file mode 100644 index 00000000..f543986c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_collection_v2_preparation.json @@ -0,0 +1,117 @@ +{ + "status": "DRAFT_NOT_FROZEN", + "role": "train_collection", + "collection_id": "c01_collection_v2", + "base_collection_manifest": "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1/collection.json", + "source_pack": "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1/source_pack", + "trusted_bundle": "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1/trusted", + "registry_path": "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1/registry.json", + "label_rule_path": "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1/label_rule.json", + "initial_states_path": "/srv/code-behind-layout/runtime/collection_preparation/c01_collection_v2_20261019T013548228888Z/initial_states.jsonl", + "initial_state_count": 3, + "editable_paths": [ + "textbook_sharing/layout.py" + ], + "frozen_additional_module": "glayout/sharing/enumeration.py", + "gold_controls": { + "train_c01_anchor": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012544091046Z_6c219e3a" + }, + "train_c01_dev_nf1_l030": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012544092418Z_161ea9e6" + }, + "train_c01_dev_nf2_l060": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012544093787Z_6705eaed" + }, + "train_c01_dev_nf3_l045": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012544093569Z_aaa07f75" + }, + "train_c01_dev_nf6_l060": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012653089230Z_2548a079" + }, + "train_c01_dev_nf8_l090": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012653288313Z_be3e9898" + }, + "train_c01_dev_w075_l045": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012653860895Z_024176ee" + }, + "train_c01_dev_w100_l060": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012653893490Z_b05add66" + }, + "train_c01_dev_l120": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012757942044Z_ed71443f" + } + }, + "gold_control_origin": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/gold_controls.json", + "sampling": { + "variant": "T0", + "mode": "train_collection_source", + "seeds": [ + 101, + 241, + 379, + 503, + 617, + 743, + 857, + 971 + ], + "temperature": 0.7, + "top_p": 0.95, + "max_new_tokens": 3072, + "max_context_tokens": 8192, + "timeout_seconds": 240, + "proposal_format": "full_source_teacher" + }, + "physical": { + "workers": 4, + "cpus_per_job": 2, + "generation_timeout_seconds": 240, + "evaluator_timeout_seconds": 720 + }, + "budget": { + "proposals_per_initial_state": 8, + "configurations_per_candidate": 9, + "effective_example_pipeline_pilot_target": 1000, + "initial_batch_initial_states": 3 + }, + "deduplication": { + "method": "exact_ast_dump", + "include_attributes": false, + "numeric_normalization": false, + "preserve_literals_identifiers_docstrings": true, + "unparseable_source": "Exact text identity only; real executor and gold required for any negative", + "duplicate_attempt_status": "semantic_duplicate_before_physics", + "all_generation_costs_retained": true + }, + "prospective_change": "Separate full-source proposal generation, mechanical exact diff, complete layout-only scope; existing tested-policy ACTION_SCHEMA and v1 results/budgets unchanged.", + "deadline_calibration": { + "full_original_layout_JSON_output_tokens": 1790, + "observed_v1_output_tokens": [ + 273, + 298, + 297, + 312, + 325, + 103, + 237, + 302 + ], + "observed_v1_generation_seconds": [ + 27.1361, + 28.4949, + 28.4213, + 28.445, + 28.8337, + 12.3011, + 23.1488, + 26.9524 + ], + "raw_evidence": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/attempts.json", + "reason_for_240_seconds": "Actual approximately 10-11 tokens/s requires roughly 160-180 seconds for the complete module." + }, + "old_development_outcomes_admitted": false, + "new_baseline9_per_state_and_new_teacher_proposals_required": true, + "excluded_observed_state_379": "Custom-plan assignment is overwritten immediately; distinct text did not establish distinct behavior.", + "formal_collection_launched": false +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_failure_minimal_gpt_teacher_preparation.json b/benchmarks/code_behind_layout/configs/development/c01_failure_minimal_gpt_teacher_preparation.json new file mode 100644 index 00000000..838543a2 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_failure_minimal_gpt_teacher_preparation.json @@ -0,0 +1,107 @@ +{ + "status": "DRAFT_NOT_FROZEN", + "role": "train_collection", + "collection_id": "c01_failure_minimal_gpt_teacher_v1", + "base_collection_manifest": "/srv/code-behind-layout/runtime/train_collections/c01_gpt_teacher_v1/collection.json", + "source_pack": "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1/source_pack", + "trusted_bundle": "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1/trusted", + "registry_path": "/srv/code-behind-layout/runtime/train_collections/c01_gpt_teacher_v1/registry.json", + "label_rule_path": "/srv/code-behind-layout/runtime/train_collections/c01_gpt_teacher_v1/label_rule.json", + "initial_states_path": "/srv/code-behind-layout/runtime/collection_preparation/c01_failure_minimal_gpt_teacher_v1_20261019T021023837897Z/initial_states.jsonl", + "initial_state_count": 1, + "editable_paths": [ + "textbook_sharing/layout.py" + ], + "gold_controls": { + "train_c01_anchor": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012544091046Z_6c219e3a" + }, + "train_c01_dev_nf1_l030": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012544092418Z_161ea9e6" + }, + "train_c01_dev_nf2_l060": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012544093787Z_6705eaed" + }, + "train_c01_dev_nf3_l045": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012544093569Z_aaa07f75" + }, + "train_c01_dev_nf6_l060": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012653089230Z_2548a079" + }, + "train_c01_dev_nf8_l090": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012653288313Z_be3e9898" + }, + "train_c01_dev_w075_l045": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012653860895Z_024176ee" + }, + "train_c01_dev_w100_l060": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012653893490Z_b05add66" + }, + "train_c01_dev_l120": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012757942044Z_ed71443f" + } + }, + "teacher_instruction_version": "minimal_source_edit_v1", + "student_preselection": { + "student_interface_version": "ordinary_policy_action_v1", + "max_new_tokens": 1024, + "max_context_tokens": 8192, + "stage": "before_physics" + }, + "sampling": { + "mode": "train_collection_source_gpt", + "backend": "isolated_gpt_cli", + "model": "gpt-6.1-sol", + "reasoning_effort": "high", + "trials": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8 + ], + "proposal_workers": 2, + "seed": null, + "seed_control_available": false, + "proposal_format": "full_source_teacher", + "max_new_tokens": 3072, + "max_context_tokens": 8192, + "timeout_seconds": 240 + }, + "physical": { + "workers": 2, + "cpus_per_job": 2, + "generation_timeout_seconds": 240, + "evaluator_timeout_seconds": 720 + }, + "budget": { + "proposals_per_initial_state": 8, + "configurations_per_candidate": 9, + "effective_example_pipeline_pilot_target": 1000, + "initial_batch_initial_states": 1 + }, + "deduplication": { + "method": "exact_ast_dump", + "include_attributes": false, + "numeric_normalization": false, + "preserve_literals_identifiers_docstrings": true, + "unparseable_source": "Exact text identity only; real executor and gold required for any negative", + "duplicate_attempt_status": "semantic_duplicate_before_physics", + "all_generation_costs_retained": true + }, + "prospective_change": "Preserve every unaffected line/comment/docstring/import/name/order. Reject oversized canonical ordinary actions before physics, retaining complete raw source and all generation costs. Never repair/shorten a proposal.", + "output_budget_scope": "3072 pinned student-tokenizer tokens for complete source JSON + EOS. Distinct student preselection is ordinary ACTION_JSON <=1024 and complete source/contract/action <=8192.", + "isolation": { + "fresh_ephemeral_session_per_trial": true, + "native_tools": false, + "no_sampling_seed_exposed": true, + "concurrent_slots_global": 2 + }, + "source_program_counting": "New teacher contexts do not create independent source programs or lineages. Count useful initial programs and unique terminal ASTs separately from pair counts.", + "new_baseline9_per_state_and_new_teacher_proposals_required": true, + "old_development_outcomes_admitted": false, + "formal_collection_launched": false +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c01_family/configurations.json new file mode 100644 index 00000000..c33d06a2 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_family/configurations.json @@ -0,0 +1,233 @@ +{ + "status": "DEVELOPMENT_FAMILY_YIELD_NOT_FROZEN", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "editable_paths": [ + "textbook_sharing/layout.py" + ], + "configuration_schema": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": "total width um", + "l": "length um", + "nf": "positive integer fingers" + }, + "M2": "identical sizing to M1, ratio remains 1:1" + } + }, + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M2": { + "w": 2.0, + "l": 0.6, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c01_family/references/anchor.spice", + "contract_file": "configs/development/c01_family/contracts/anchor.json", + "independently_generated_reference_before_any_candidate": true + }, + { + "configuration_id": "dev_nf1_l030", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 0.5, + "l": 0.3, + "nf": 1 + }, + "M2": { + "w": 0.5, + "l": 0.3, + "nf": 1 + } + } + }, + "reference_file": "configs/development/c01_family/references/dev_nf1_l030.spice", + "contract_file": "configs/development/c01_family/contracts/dev_nf1_l030.json", + "independently_generated_reference_before_any_candidate": true + }, + { + "configuration_id": "dev_nf2_l060", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 1.0, + "l": 0.6, + "nf": 2 + }, + "M2": { + "w": 1.0, + "l": 0.6, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c01_family/references/dev_nf2_l060.spice", + "contract_file": "configs/development/c01_family/contracts/dev_nf2_l060.json", + "independently_generated_reference_before_any_candidate": true + }, + { + "configuration_id": "dev_nf3_l045", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 1.5, + "l": 0.45, + "nf": 3 + }, + "M2": { + "w": 1.5, + "l": 0.45, + "nf": 3 + } + } + }, + "reference_file": "configs/development/c01_family/references/dev_nf3_l045.spice", + "contract_file": "configs/development/c01_family/contracts/dev_nf3_l045.json", + "independently_generated_reference_before_any_candidate": true + }, + { + "configuration_id": "dev_nf6_l060", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 3.0, + "l": 0.6, + "nf": 6 + }, + "M2": { + "w": 3.0, + "l": 0.6, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c01_family/references/dev_nf6_l060.spice", + "contract_file": "configs/development/c01_family/contracts/dev_nf6_l060.json", + "independently_generated_reference_before_any_candidate": true + }, + { + "configuration_id": "dev_nf8_l090", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 4.0, + "l": 0.9, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.9, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c01_family/references/dev_nf8_l090.spice", + "contract_file": "configs/development/c01_family/contracts/dev_nf8_l090.json", + "independently_generated_reference_before_any_candidate": true + }, + { + "configuration_id": "dev_w075_l045", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 3.0, + "l": 0.45, + "nf": 4 + }, + "M2": { + "w": 3.0, + "l": 0.45, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c01_family/references/dev_w075_l045.spice", + "contract_file": "configs/development/c01_family/contracts/dev_w075_l045.json", + "independently_generated_reference_before_any_candidate": true + }, + { + "configuration_id": "dev_w100_l060", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 4.0, + "l": 0.6, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 0.6, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c01_family/references/dev_w100_l060.spice", + "contract_file": "configs/development/c01_family/contracts/dev_w100_l060.json", + "independently_generated_reference_before_any_candidate": true + }, + { + "configuration_id": "dev_l120", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 2.0, + "l": 1.2, + "nf": 4 + }, + "M2": { + "w": 2.0, + "l": 1.2, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c01_family/references/dev_l120.spice", + "contract_file": "configs/development/c01_family/contracts/dev_l120.json", + "independently_generated_reference_before_any_candidate": true + } + ], + "formal_training_rows": 0, + "coverage_scope": "nine discrete geometries, three corners each; no continuous guarantee", + "label_rule_proposal": { + "direction": "min", + "quality_absolute_tolerance": 0.0001, + "coverage_absolute_tolerance": 0, + "family_priority": "S1_hard_correctness_then_S2_coverage_then_regression_count_then_mean_worst_corner_error_when_all_pass", + "initial_state": "original_unmodified_compiler_same_full_source_for_all_candidates", + "proposal_source": "eight_transparent_heuristic_source_edits_from_corpus_yield_pilot.variants", + "phase": "development_only" + }, + "planned_new_physical_cases": 72, + "previous_anchor_pilot": "phase0_20261018T234700264280Z_corpus_yield_pilot", + "baseline_feasibility_status": "new_eight_geometries_pending_actual_schematic_and_physical_checks_no_feasibility_claim" +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c01_family/contracts/anchor.json new file mode 100644 index 00000000..09d6b10d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_family/contracts/anchor.json @@ -0,0 +1,74 @@ +{ + "task_id": "development_corpus_C01_original_compiler", + "configuration_id": "anchor", + "reference_id": "c01_anchor_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.1 + } + ], + "objective": { + "metric": "nominal_current_relative_error", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "development_only_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_family/contracts/dev_l120.json b/benchmarks/code_behind_layout/configs/development/c01_family/contracts/dev_l120.json new file mode 100644 index 00000000..9c110a91 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_family/contracts/dev_l120.json @@ -0,0 +1,74 @@ +{ + "task_id": "development_corpus_C01_original_compiler", + "configuration_id": "dev_l120", + "reference_id": "c01_dev_l120_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.1 + } + ], + "objective": { + "metric": "nominal_current_relative_error", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "development_only_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_family/contracts/dev_nf1_l030.json b/benchmarks/code_behind_layout/configs/development/c01_family/contracts/dev_nf1_l030.json new file mode 100644 index 00000000..e1e7e4fa --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_family/contracts/dev_nf1_l030.json @@ -0,0 +1,74 @@ +{ + "task_id": "development_corpus_C01_original_compiler", + "configuration_id": "dev_nf1_l030", + "reference_id": "c01_dev_nf1_l030_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.1 + } + ], + "objective": { + "metric": "nominal_current_relative_error", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "development_only_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_family/contracts/dev_nf2_l060.json b/benchmarks/code_behind_layout/configs/development/c01_family/contracts/dev_nf2_l060.json new file mode 100644 index 00000000..83bcc355 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_family/contracts/dev_nf2_l060.json @@ -0,0 +1,74 @@ +{ + "task_id": "development_corpus_C01_original_compiler", + "configuration_id": "dev_nf2_l060", + "reference_id": "c01_dev_nf2_l060_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.1 + } + ], + "objective": { + "metric": "nominal_current_relative_error", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "development_only_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_family/contracts/dev_nf3_l045.json b/benchmarks/code_behind_layout/configs/development/c01_family/contracts/dev_nf3_l045.json new file mode 100644 index 00000000..cdb8d65f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_family/contracts/dev_nf3_l045.json @@ -0,0 +1,74 @@ +{ + "task_id": "development_corpus_C01_original_compiler", + "configuration_id": "dev_nf3_l045", + "reference_id": "c01_dev_nf3_l045_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.1 + } + ], + "objective": { + "metric": "nominal_current_relative_error", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "development_only_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_family/contracts/dev_nf6_l060.json b/benchmarks/code_behind_layout/configs/development/c01_family/contracts/dev_nf6_l060.json new file mode 100644 index 00000000..48be6d28 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_family/contracts/dev_nf6_l060.json @@ -0,0 +1,74 @@ +{ + "task_id": "development_corpus_C01_original_compiler", + "configuration_id": "dev_nf6_l060", + "reference_id": "c01_dev_nf6_l060_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.1 + } + ], + "objective": { + "metric": "nominal_current_relative_error", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "development_only_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_family/contracts/dev_nf8_l090.json b/benchmarks/code_behind_layout/configs/development/c01_family/contracts/dev_nf8_l090.json new file mode 100644 index 00000000..b2f21b16 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_family/contracts/dev_nf8_l090.json @@ -0,0 +1,74 @@ +{ + "task_id": "development_corpus_C01_original_compiler", + "configuration_id": "dev_nf8_l090", + "reference_id": "c01_dev_nf8_l090_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.1 + } + ], + "objective": { + "metric": "nominal_current_relative_error", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "development_only_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_family/contracts/dev_w075_l045.json b/benchmarks/code_behind_layout/configs/development/c01_family/contracts/dev_w075_l045.json new file mode 100644 index 00000000..45817cb2 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_family/contracts/dev_w075_l045.json @@ -0,0 +1,74 @@ +{ + "task_id": "development_corpus_C01_original_compiler", + "configuration_id": "dev_w075_l045", + "reference_id": "c01_dev_w075_l045_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.1 + } + ], + "objective": { + "metric": "nominal_current_relative_error", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "development_only_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_family/contracts/dev_w100_l060.json b/benchmarks/code_behind_layout/configs/development/c01_family/contracts/dev_w100_l060.json new file mode 100644 index 00000000..a851a74c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_family/contracts/dev_w100_l060.json @@ -0,0 +1,74 @@ +{ + "task_id": "development_corpus_C01_original_compiler", + "configuration_id": "dev_w100_l060", + "reference_id": "c01_dev_w100_l060_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.1 + } + ], + "objective": { + "metric": "nominal_current_relative_error", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "development_only_NOT_FROZEN", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c01_family/references/anchor.spice new file mode 100644 index 00000000..75809afd --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_family/references/anchor.spice @@ -0,0 +1,10 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_family/references/dev_l120.spice b/benchmarks/code_behind_layout/configs/development/c01_family/references/dev_l120.spice new file mode 100644 index 00000000..e9f74648 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_family/references/dev_l120.spice @@ -0,0 +1,10 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_family/references/dev_nf1_l030.spice b/benchmarks/code_behind_layout/configs/development/c01_family/references/dev_nf1_l030.spice new file mode 100644 index 00000000..b0736183 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_family/references/dev_nf1_l030.spice @@ -0,0 +1,4 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_family/references/dev_nf2_l060.spice b/benchmarks/code_behind_layout/configs/development/c01_family/references/dev_nf2_l060.spice new file mode 100644 index 00000000..54d1adaf --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_family/references/dev_nf2_l060.spice @@ -0,0 +1,6 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_family/references/dev_nf3_l045.spice b/benchmarks/code_behind_layout/configs/development/c01_family/references/dev_nf3_l045.spice new file mode 100644 index 00000000..7e70a18d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_family/references/dev_nf3_l045.spice @@ -0,0 +1,8 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_family/references/dev_nf6_l060.spice b/benchmarks/code_behind_layout/configs/development/c01_family/references/dev_nf6_l060.spice new file mode 100644 index 00000000..29a33b5a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_family/references/dev_nf6_l060.spice @@ -0,0 +1,14 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f4 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f5 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f4 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f5 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_family/references/dev_nf8_l090.spice b/benchmarks/code_behind_layout/configs/development/c01_family/references/dev_nf8_l090.spice new file mode 100644 index 00000000..89a569ed --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_family/references/dev_nf8_l090.spice @@ -0,0 +1,18 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f4 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f5 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f6 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f7 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f4 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f5 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f6 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f7 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_family/references/dev_w075_l045.spice b/benchmarks/code_behind_layout/configs/development/c01_family/references/dev_w075_l045.spice new file mode 100644 index 00000000..81f9872c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_family/references/dev_w075_l045.spice @@ -0,0 +1,10 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_family/references/dev_w100_l060.spice b/benchmarks/code_behind_layout/configs/development/c01_family/references/dev_w100_l060.spice new file mode 100644 index 00000000..02e2eef6 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_family/references/dev_w100_l060.spice @@ -0,0 +1,10 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_gpt_teacher_frozen_manifest.json b/benchmarks/code_behind_layout/configs/development/c01_gpt_teacher_frozen_manifest.json new file mode 100644 index 00000000..0e754336 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_gpt_teacher_frozen_manifest.json @@ -0,0 +1,152 @@ +{ + "status": "frozen", + "role": "train_collection", + "collection_id": "c01_gpt_teacher_v1", + "frozen_at_utc": "2026-10-19T01:46:24.844067+00:00", + "registry_path": "/srv/code-behind-layout/runtime/train_collections/c01_gpt_teacher_v1/registry.json", + "label_rule_path": "/srv/code-behind-layout/runtime/train_collections/c01_gpt_teacher_v1/label_rule.json", + "trusted_bundle": "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1/trusted", + "source_pack": "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1/source_pack", + "initial_states_path": "/srv/code-behind-layout/runtime/train_collections/c01_gpt_teacher_v1/initial_states.jsonl", + "output_root": "/srv/code-behind-layout/runs/train_collection/c01_gpt_teacher_v1", + "evidence_root": "/srv/code-behind-layout/runs/train_collection/c01_gpt_teacher_v1", + "source_smoke_evidence": "/srv/code-behind-layout/runs/development/c01_draft_bundle/executor_20261019T011845829122Z_c84f4a51", + "main_benchmark_protocol_status": "draft", + "pdk_revision": "0fe599b2afb6708d281543108caf8310912f54af", + "container_image": "hpretl/iic-osic-tools@sha256:7ef29be71a33b5b8994cde7f7476dfefd1af94f2922354242d1579346feec462", + "magic_runtime": "/srv/code-behind-layout/runtime/magic-8.3.685", + "sampling": { + "backend": "isolated_gpt_cli", + "mode": "train_collection_source_gpt", + "model": "gpt-6.1-sol", + "reasoning_effort": "high", + "trials": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8 + ], + "proposal_workers": 2, + "seed": null, + "seed_control_available": false, + "proposal_format": "full_source_teacher", + "max_new_tokens": 3072, + "max_context_tokens": 8192, + "timeout_seconds": 240 + }, + "physical": { + "workers": 2, + "cpus_per_job": 2, + "generation_timeout_seconds": 240, + "evaluator_timeout_seconds": 720 + }, + "budget": { + "proposals_per_initial_state": 8, + "configurations_per_candidate": 9, + "effective_example_pipeline_pilot_target": 1000, + "initial_batch_initial_states": 3 + }, + "failure_policy": "Keep all attempts, duplicate/noop/invalid patches, candidate failures, infrastructure failures and measured costs; unknowns never become physical negatives.", + "admission": "Fresh independent GPT proposals and fresh nine-point baselines; same frozen physical contracts, source capsule and label rule as T0 v2. Native tools disabled, no manual source repair, all failed requests retained.", + "context": "Complete layout module, frozen circuit/domain contract and actual fresh baseline feedback; no truncation.", + "base_collection_manifest": "/srv/code-behind-layout/runtime/train_collections/c01_collection_v2/collection.json", + "initial_state_count": 3, + "editable_paths": [ + "textbook_sharing/layout.py" + ], + "frozen_additional_module": "glayout/sharing/enumeration.py", + "gold_controls": { + "train_c01_anchor": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012544091046Z_6c219e3a" + }, + "train_c01_dev_nf1_l030": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012544092418Z_161ea9e6" + }, + "train_c01_dev_nf2_l060": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012544093787Z_6705eaed" + }, + "train_c01_dev_nf3_l045": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012544093569Z_aaa07f75" + }, + "train_c01_dev_nf6_l060": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012653089230Z_2548a079" + }, + "train_c01_dev_nf8_l090": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012653288313Z_be3e9898" + }, + "train_c01_dev_w075_l045": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012653860895Z_024176ee" + }, + "train_c01_dev_w100_l060": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012653893490Z_b05add66" + }, + "train_c01_dev_l120": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012757942044Z_ed71443f" + } + }, + "gold_control_origin": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/gold_controls.json", + "deduplication": { + "method": "exact_ast_dump", + "include_attributes": false, + "numeric_normalization": false, + "preserve_literals_identifiers_docstrings": true, + "unparseable_source": "Exact text identity only; real executor and gold required for any negative", + "duplicate_attempt_status": "semantic_duplicate_before_physics", + "all_generation_costs_retained": true + }, + "prospective_change": "Separate full-source proposal generation, mechanical exact diff, complete layout-only scope; existing tested-policy ACTION_SCHEMA and v1 results/budgets unchanged.", + "deadline_calibration": { + "full_original_layout_JSON_output_tokens": 1790, + "observed_v1_output_tokens": [ + 273, + 298, + 297, + 312, + 325, + 103, + 237, + 302 + ], + "observed_v1_generation_seconds": [ + 27.1361, + 28.4949, + 28.4213, + 28.445, + 28.8337, + 12.3011, + 23.1488, + 26.9524 + ], + "raw_evidence": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/attempts.json", + "reason_for_240_seconds": "Actual approximately 10-11 tokens/s requires roughly 160-180 seconds for the complete module." + }, + "old_development_outcomes_admitted": false, + "new_baseline9_per_state_and_new_teacher_proposals_required": true, + "excluded_observed_state_379": "Custom-plan assignment is overwritten immediately; distinct text did not establish distinct behavior.", + "formal_collection_launched": false, + "deduplication_scope": "Within initial state; separately report unique final programs across all states.", + "transport": { + "remote_endpoint": "http://127.0.0.1:8115", + "local_listen": "127.0.0.1:8115", + "mechanism": "SSH reverse forwarding to local authenticated GPT CLI broker; credentials remain on original host", + "service_script": "scripts/corpus_gpt_teacher_service.py", + "command_source": "command() uses the same native-capability disable flags as the existing isolated policy adapter" + }, + "isolation": { + "fresh_ephemeral_session_per_trial": true, + "sandbox": "read-only", + "native_tools": false, + "web_search": false, + "apps_plugins_mcp_memory": false, + "project_instructions": false, + "working_directory": "opaque random UUID, never trial-index text", + "shared_prompt_within_state": "byte-identical source_proposal_prompt(request)" + }, + "costs": "Keep every exact CLI argv/request/events/stderr/proposal/exit/wall and available public usage; no provider checkpoint, seed, hidden reasoning or billable price is inferred", + "output_budget_scope": "Pinned Qwen tokenizer counts complete returned JSON + EOS; excess outputs are retained but not applied, with no truncation", + "source_program_counting": "Same three initial AST programs as Qwen v2, not three new lineages or independent source programs; report unique terminal ASTs and useful initial states separately from DPO pairs" +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/circuit_input.json new file mode 100644 index 00000000..02963814 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/circuit_input.json @@ -0,0 +1,62 @@ +{ + "circuit_id": "C01", + "name": "basic_current_mirror", + "ports": [ + "VSS", + "IB1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IB1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "IOUT1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 726, + "files": [ + "Dataset/726/726.cir", + "Dataset/726/Port726.txt", + "Dataset/726/Pagenumber726.txt", + "Dataset/726/Book726.png", + "Dataset/726/Cadence726.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "305", + "device_name_map": { + "M1": "M3", + "M2": "M5" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/726/Book726.png", + "observation": "Johns p.305 scan: Q1 diode-connected NMOS, Q2 output NMOS gate tied through a long wire (bias-distribution figure); basic 1:1 mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/configurations.json new file mode 100644 index 00000000..b2c5ede4 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/configurations.json @@ -0,0 +1,215 @@ +{ + "status": "DRAFT_DECLARED_NO_PHYSICS_OR_MODEL_REQUESTS", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C01", + "development_domain_id": "C01_independent_nf", + "circuit_input_file": "configs/development/c01_independent_nf_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 3.0, + "l": 0.6, + "nf": 4 + }, + "M2": { + "w": 3.0, + "l": 0.6, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c01_independent_nf_family/references/anchor.spice", + "contract_file": "configs/development/c01_independent_nf_family/contracts/anchor.json", + "independently_generated_reference_before_any_candidate": true + }, + { + "configuration_id": "dev_nf2_l030", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 3.0, + "l": 0.3, + "nf": 2 + }, + "M2": { + "w": 3.0, + "l": 0.3, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c01_independent_nf_family/references/dev_nf2_l030.spice", + "contract_file": "configs/development/c01_independent_nf_family/contracts/dev_nf2_l030.json", + "independently_generated_reference_before_any_candidate": true + }, + { + "configuration_id": "dev_nf2_l060", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 3.0, + "l": 0.6, + "nf": 2 + }, + "M2": { + "w": 3.0, + "l": 0.6, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c01_independent_nf_family/references/dev_nf2_l060.spice", + "contract_file": "configs/development/c01_independent_nf_family/contracts/dev_nf2_l060.json", + "independently_generated_reference_before_any_candidate": true + }, + { + "configuration_id": "dev_nf2_l090", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 3.0, + "l": 0.9, + "nf": 2 + }, + "M2": { + "w": 3.0, + "l": 0.9, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c01_independent_nf_family/references/dev_nf2_l090.spice", + "contract_file": "configs/development/c01_independent_nf_family/contracts/dev_nf2_l090.json", + "independently_generated_reference_before_any_candidate": true + }, + { + "configuration_id": "dev_nf4_l030", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 3.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 3.0, + "l": 0.3, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c01_independent_nf_family/references/dev_nf4_l030.spice", + "contract_file": "configs/development/c01_independent_nf_family/contracts/dev_nf4_l030.json", + "independently_generated_reference_before_any_candidate": true + }, + { + "configuration_id": "dev_nf4_l090", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 3.0, + "l": 0.9, + "nf": 4 + }, + "M2": { + "w": 3.0, + "l": 0.9, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c01_independent_nf_family/references/dev_nf4_l090.spice", + "contract_file": "configs/development/c01_independent_nf_family/contracts/dev_nf4_l090.json", + "independently_generated_reference_before_any_candidate": true + }, + { + "configuration_id": "dev_nf6_l030", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M2": { + "w": 3.0, + "l": 0.3, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c01_independent_nf_family/references/dev_nf6_l030.spice", + "contract_file": "configs/development/c01_independent_nf_family/contracts/dev_nf6_l030.json", + "independently_generated_reference_before_any_candidate": true + }, + { + "configuration_id": "dev_nf6_l060", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 3.0, + "l": 0.6, + "nf": 6 + }, + "M2": { + "w": 3.0, + "l": 0.6, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c01_independent_nf_family/references/dev_nf6_l060.spice", + "contract_file": "configs/development/c01_independent_nf_family/contracts/dev_nf6_l060.json", + "independently_generated_reference_before_any_candidate": true + }, + { + "configuration_id": "dev_nf6_l090", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 3.0, + "l": 0.9, + "nf": 6 + }, + "M2": { + "w": 3.0, + "l": 0.9, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c01_independent_nf_family/references/dev_nf6_l090.spice", + "contract_file": "configs/development/c01_independent_nf_family/contracts/dev_nf6_l090.json", + "independently_generated_reference_before_any_candidate": true + } + ], + "hypothesis": "At fixed totalW, changing nf changes legal per-finger width, grouping and placement. Test whether these independent axes produce actual configuration-dependent area/feasibility rankings. The current domain already varies nf1..8 with mostly coupled totalW; no causal claim is made about its zero observed preference conflicts.", + "grid_selected_from_candidate_outcomes": false, + "source_lineages": 1, + "physical_runs": 0, + "model_requests": 0, + "old_frozen_domains_and_labels_changed": false, + "requires_actual_original_program9point_qualification_before_collection_freeze": true +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/anchor.json new file mode 100644 index 00000000..13d06df2 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/anchor.json @@ -0,0 +1,99 @@ +{ + "task_id": "development_train_domain_c01_independent_nf", + "configuration_id": "anchor", + "reference_id": "c01_independent_nf_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_UNLAUNCHED_INDEPENDENT_FINGER_AXIS", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 3.0, + "matched_ratio": "1:1", + "nf": 4, + "per_finger_width_um": 0.75, + "axes": "Full3x3 Cartesian nf={2,4,6},L={.3,.6,.9}um at fixed totalW3um. No point was selected from candidate outcomes." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/dev_nf2_l030.json b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/dev_nf2_l030.json new file mode 100644 index 00000000..10742df6 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/dev_nf2_l030.json @@ -0,0 +1,99 @@ +{ + "task_id": "development_train_domain_c01_independent_nf", + "configuration_id": "dev_nf2_l030", + "reference_id": "c01_independent_nf_dev_nf2_l030_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_UNLAUNCHED_INDEPENDENT_FINGER_AXIS", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 3.0, + "matched_ratio": "1:1", + "nf": 2, + "per_finger_width_um": 1.5, + "axes": "Full3x3 Cartesian nf={2,4,6},L={.3,.6,.9}um at fixed totalW3um. No point was selected from candidate outcomes." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/dev_nf2_l060.json b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/dev_nf2_l060.json new file mode 100644 index 00000000..3b7df35a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/dev_nf2_l060.json @@ -0,0 +1,99 @@ +{ + "task_id": "development_train_domain_c01_independent_nf", + "configuration_id": "dev_nf2_l060", + "reference_id": "c01_independent_nf_dev_nf2_l060_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_UNLAUNCHED_INDEPENDENT_FINGER_AXIS", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 3.0, + "matched_ratio": "1:1", + "nf": 2, + "per_finger_width_um": 1.5, + "axes": "Full3x3 Cartesian nf={2,4,6},L={.3,.6,.9}um at fixed totalW3um. No point was selected from candidate outcomes." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/dev_nf2_l090.json b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/dev_nf2_l090.json new file mode 100644 index 00000000..1aae6e4a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/dev_nf2_l090.json @@ -0,0 +1,99 @@ +{ + "task_id": "development_train_domain_c01_independent_nf", + "configuration_id": "dev_nf2_l090", + "reference_id": "c01_independent_nf_dev_nf2_l090_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_UNLAUNCHED_INDEPENDENT_FINGER_AXIS", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 3.0, + "matched_ratio": "1:1", + "nf": 2, + "per_finger_width_um": 1.5, + "axes": "Full3x3 Cartesian nf={2,4,6},L={.3,.6,.9}um at fixed totalW3um. No point was selected from candidate outcomes." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/dev_nf4_l030.json b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/dev_nf4_l030.json new file mode 100644 index 00000000..27498a0b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/dev_nf4_l030.json @@ -0,0 +1,99 @@ +{ + "task_id": "development_train_domain_c01_independent_nf", + "configuration_id": "dev_nf4_l030", + "reference_id": "c01_independent_nf_dev_nf4_l030_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_UNLAUNCHED_INDEPENDENT_FINGER_AXIS", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 3.0, + "matched_ratio": "1:1", + "nf": 4, + "per_finger_width_um": 0.75, + "axes": "Full3x3 Cartesian nf={2,4,6},L={.3,.6,.9}um at fixed totalW3um. No point was selected from candidate outcomes." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/dev_nf4_l090.json b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/dev_nf4_l090.json new file mode 100644 index 00000000..b445498f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/dev_nf4_l090.json @@ -0,0 +1,99 @@ +{ + "task_id": "development_train_domain_c01_independent_nf", + "configuration_id": "dev_nf4_l090", + "reference_id": "c01_independent_nf_dev_nf4_l090_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_UNLAUNCHED_INDEPENDENT_FINGER_AXIS", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 3.0, + "matched_ratio": "1:1", + "nf": 4, + "per_finger_width_um": 0.75, + "axes": "Full3x3 Cartesian nf={2,4,6},L={.3,.6,.9}um at fixed totalW3um. No point was selected from candidate outcomes." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/dev_nf6_l030.json b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/dev_nf6_l030.json new file mode 100644 index 00000000..7fd31489 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/dev_nf6_l030.json @@ -0,0 +1,99 @@ +{ + "task_id": "development_train_domain_c01_independent_nf", + "configuration_id": "dev_nf6_l030", + "reference_id": "c01_independent_nf_dev_nf6_l030_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_UNLAUNCHED_INDEPENDENT_FINGER_AXIS", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 3.0, + "matched_ratio": "1:1", + "nf": 6, + "per_finger_width_um": 0.5, + "axes": "Full3x3 Cartesian nf={2,4,6},L={.3,.6,.9}um at fixed totalW3um. No point was selected from candidate outcomes." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/dev_nf6_l060.json b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/dev_nf6_l060.json new file mode 100644 index 00000000..564e0a4d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/dev_nf6_l060.json @@ -0,0 +1,99 @@ +{ + "task_id": "development_train_domain_c01_independent_nf", + "configuration_id": "dev_nf6_l060", + "reference_id": "c01_independent_nf_dev_nf6_l060_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_UNLAUNCHED_INDEPENDENT_FINGER_AXIS", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 3.0, + "matched_ratio": "1:1", + "nf": 6, + "per_finger_width_um": 0.5, + "axes": "Full3x3 Cartesian nf={2,4,6},L={.3,.6,.9}um at fixed totalW3um. No point was selected from candidate outcomes." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/dev_nf6_l090.json b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/dev_nf6_l090.json new file mode 100644 index 00000000..45c7d972 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/contracts/dev_nf6_l090.json @@ -0,0 +1,99 @@ +{ + "task_id": "development_train_domain_c01_independent_nf", + "configuration_id": "dev_nf6_l090", + "reference_id": "c01_independent_nf_dev_nf6_l090_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_UNLAUNCHED_INDEPENDENT_FINGER_AXIS", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 3.0, + "matched_ratio": "1:1", + "nf": 6, + "per_finger_width_um": 0.5, + "axes": "Full3x3 Cartesian nf={2,4,6},L={.3,.6,.9}um at fixed totalW3um. No point was selected from candidate outcomes." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/qualification_commands.json b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/qualification_commands.json new file mode 100644 index 00000000..108dd01f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/qualification_commands.json @@ -0,0 +1,204 @@ +{ + "status": "PREPARED_NOT_LAUNCHED", + "resource_rule": "Do not compete with current C07/TG two-worker qualification; later at most one2CPU job and actualbusy+2<=24/RAM<=190GiB", + "commands": [ + { + "configuration_id": "anchor", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_independent_nf_family/configurations.json", + "--configuration-id", + "anchor" + ] + }, + { + "configuration_id": "dev_nf2_l030", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_independent_nf_family/configurations.json", + "--configuration-id", + "dev_nf2_l030" + ] + }, + { + "configuration_id": "dev_nf2_l060", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_independent_nf_family/configurations.json", + "--configuration-id", + "dev_nf2_l060" + ] + }, + { + "configuration_id": "dev_nf2_l090", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_independent_nf_family/configurations.json", + "--configuration-id", + "dev_nf2_l090" + ] + }, + { + "configuration_id": "dev_nf4_l030", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_independent_nf_family/configurations.json", + "--configuration-id", + "dev_nf4_l030" + ] + }, + { + "configuration_id": "dev_nf4_l090", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_independent_nf_family/configurations.json", + "--configuration-id", + "dev_nf4_l090" + ] + }, + { + "configuration_id": "dev_nf6_l030", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_independent_nf_family/configurations.json", + "--configuration-id", + "dev_nf6_l030" + ] + }, + { + "configuration_id": "dev_nf6_l060", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_independent_nf_family/configurations.json", + "--configuration-id", + "dev_nf6_l060" + ] + }, + { + "configuration_id": "dev_nf6_l090", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_independent_nf_family/configurations.json", + "--configuration-id", + "dev_nf6_l090" + ] + } + ] +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/anchor.spice new file mode 100644 index 00000000..281a6ada --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/anchor.spice @@ -0,0 +1,10 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/dev_nf2_l030.spice b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/dev_nf2_l030.spice new file mode 100644 index 00000000..2fa4907f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/dev_nf2_l030.spice @@ -0,0 +1,6 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.5 l=0.3 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.5 l=0.3 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.5 l=0.3 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.5 l=0.3 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/dev_nf2_l060.spice b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/dev_nf2_l060.spice new file mode 100644 index 00000000..54807ff0 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/dev_nf2_l060.spice @@ -0,0 +1,6 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.5 l=0.6 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.5 l=0.6 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.5 l=0.6 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.5 l=0.6 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/dev_nf2_l090.spice b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/dev_nf2_l090.spice new file mode 100644 index 00000000..2d6e91d9 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/dev_nf2_l090.spice @@ -0,0 +1,6 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.5 l=0.9 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.5 l=0.9 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.5 l=0.9 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.5 l=0.9 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/dev_nf4_l030.spice b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/dev_nf4_l030.spice new file mode 100644 index 00000000..219760ca --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/dev_nf4_l030.spice @@ -0,0 +1,10 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/dev_nf4_l090.spice b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/dev_nf4_l090.spice new file mode 100644 index 00000000..53fd9791 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/dev_nf4_l090.spice @@ -0,0 +1,10 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.9 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.9 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.9 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.9 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.9 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.9 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.9 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.9 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/dev_nf6_l030.spice b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/dev_nf6_l030.spice new file mode 100644 index 00000000..335b1116 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/dev_nf6_l030.spice @@ -0,0 +1,14 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/dev_nf6_l060.spice b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/dev_nf6_l060.spice new file mode 100644 index 00000000..29a33b5a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/dev_nf6_l060.spice @@ -0,0 +1,14 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f4 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f5 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f4 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f5 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/dev_nf6_l090.spice b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/dev_nf6_l090.spice new file mode 100644 index 00000000..b6a6812d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_independent_nf_family/references/dev_nf6_l090.spice @@ -0,0 +1,14 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f4 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f5 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f4 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f5 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/circuit_input.json new file mode 100644 index 00000000..02963814 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/circuit_input.json @@ -0,0 +1,62 @@ +{ + "circuit_id": "C01", + "name": "basic_current_mirror", + "ports": [ + "VSS", + "IB1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IB1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "IOUT1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 726, + "files": [ + "Dataset/726/726.cir", + "Dataset/726/Port726.txt", + "Dataset/726/Pagenumber726.txt", + "Dataset/726/Book726.png", + "Dataset/726/Cadence726.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "305", + "device_name_map": { + "M1": "M3", + "M2": "M5" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/726/Book726.png", + "observation": "Johns p.305 scan: Q1 diode-connected NMOS, Q2 output NMOS gate tied through a long wire (bias-distribution figure); basic 1:1 mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/configurations.json new file mode 100644 index 00000000..82f38206 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/configurations.json @@ -0,0 +1,275 @@ +{ + "status": "DRAFT_DECLARED_NO_PHYSICS_OR_MODEL_REQUESTS", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C01", + "development_domain_id": "C01_per_device_nf", + "circuit_input_file": "configs/development/c01_per_device_nf_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 3.0, + "l": 0.6, + "nf": 4 + }, + "M2": { + "w": 3.0, + "l": 0.6, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_family/references/anchor.spice", + "contract_file": "configs/development/c01_per_device_nf_family/contracts/anchor.json", + "independently_generated_reference_before_any_candidate": true, + "predicted_grouping": { + "sharing_group_sizes": [ + 2 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + }, + { + "configuration_id": "dev_n2_2", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 3.0, + "l": 0.6, + "nf": 2 + }, + "M2": { + "w": 3.0, + "l": 0.6, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_family/references/dev_n2_2.spice", + "contract_file": "configs/development/c01_per_device_nf_family/contracts/dev_n2_2.json", + "independently_generated_reference_before_any_candidate": true, + "predicted_grouping": { + "sharing_group_sizes": [ + 2 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + }, + { + "configuration_id": "dev_n2_4", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 3.0, + "l": 0.6, + "nf": 2 + }, + "M2": { + "w": 3.0, + "l": 0.6, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_family/references/dev_n2_4.spice", + "contract_file": "configs/development/c01_per_device_nf_family/contracts/dev_n2_4.json", + "independently_generated_reference_before_any_candidate": true, + "predicted_grouping": { + "sharing_group_sizes": [ + 1, + 1 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + }, + { + "configuration_id": "dev_n2_6", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 3.0, + "l": 0.6, + "nf": 2 + }, + "M2": { + "w": 3.0, + "l": 0.6, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_family/references/dev_n2_6.spice", + "contract_file": "configs/development/c01_per_device_nf_family/contracts/dev_n2_6.json", + "independently_generated_reference_before_any_candidate": true, + "predicted_grouping": { + "sharing_group_sizes": [ + 1, + 1 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + }, + { + "configuration_id": "dev_n4_2", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 3.0, + "l": 0.6, + "nf": 4 + }, + "M2": { + "w": 3.0, + "l": 0.6, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_family/references/dev_n4_2.spice", + "contract_file": "configs/development/c01_per_device_nf_family/contracts/dev_n4_2.json", + "independently_generated_reference_before_any_candidate": true, + "predicted_grouping": { + "sharing_group_sizes": [ + 1, + 1 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + }, + { + "configuration_id": "dev_n4_6", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 3.0, + "l": 0.6, + "nf": 4 + }, + "M2": { + "w": 3.0, + "l": 0.6, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_family/references/dev_n4_6.spice", + "contract_file": "configs/development/c01_per_device_nf_family/contracts/dev_n4_6.json", + "independently_generated_reference_before_any_candidate": true, + "predicted_grouping": { + "sharing_group_sizes": [ + 1, + 1 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + }, + { + "configuration_id": "dev_n6_2", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 3.0, + "l": 0.6, + "nf": 6 + }, + "M2": { + "w": 3.0, + "l": 0.6, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_family/references/dev_n6_2.spice", + "contract_file": "configs/development/c01_per_device_nf_family/contracts/dev_n6_2.json", + "independently_generated_reference_before_any_candidate": true, + "predicted_grouping": { + "sharing_group_sizes": [ + 1, + 1 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + }, + { + "configuration_id": "dev_n6_4", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 3.0, + "l": 0.6, + "nf": 6 + }, + "M2": { + "w": 3.0, + "l": 0.6, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_family/references/dev_n6_4.spice", + "contract_file": "configs/development/c01_per_device_nf_family/contracts/dev_n6_4.json", + "independently_generated_reference_before_any_candidate": true, + "predicted_grouping": { + "sharing_group_sizes": [ + 1, + 1 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + }, + { + "configuration_id": "dev_n6_6", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 3.0, + "l": 0.6, + "nf": 6 + }, + "M2": { + "w": 3.0, + "l": 0.6, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_family/references/dev_n6_6.spice", + "contract_file": "configs/development/c01_per_device_nf_family/contracts/dev_n6_6.json", + "independently_generated_reference_before_any_candidate": true, + "predicted_grouping": { + "sharing_group_sizes": [ + 2 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + } + ], + "hypothesis": "At fixed electrical totalW/L and1:1 ratio, independent per-device fingerization changes equal-unitwidth grouping: three diagonal two-device groups and six offdiagonal two-single-device cases. Actual current matching, ro, compliance, physical feasibility and candidate preferences remain unknown until measurement. No opposite preference or successful label is assumed.", + "grid_selected_from_candidate_outcomes": false, + "source_lineages": 1, + "physical_runs": 0, + "model_requests": 0, + "old_frozen_domains_and_labels_changed": false, + "requires_actual_original_program9point_qualification_before_collection_freeze": true +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/anchor.json new file mode 100644 index 00000000..2054ecea --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/anchor.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c01_per_device_nf", + "configuration_id": "anchor", + "reference_id": "c01_per_device_nf_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_UNLAUNCHED_INDEPENDENT_PER_DEVICE_FINGER_AXES", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 3.0, + "matched_ratio": "1:1", + "nf": { + "M1": 4, + "M2": 4 + }, + "per_finger_width_um": { + "M1": 0.75, + "M2": 0.75 + }, + "axes": "Full3x3 Cartesian nf(M1),nf(M2)={2,4,6}, fixed totalW3um and L.6um per device. No point selected from candidate outcomes." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/dev_n2_2.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/dev_n2_2.json new file mode 100644 index 00000000..58a4678e --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/dev_n2_2.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c01_per_device_nf", + "configuration_id": "dev_n2_2", + "reference_id": "c01_per_device_nf_dev_n2_2_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_UNLAUNCHED_INDEPENDENT_PER_DEVICE_FINGER_AXES", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 3.0, + "matched_ratio": "1:1", + "nf": { + "M1": 2, + "M2": 2 + }, + "per_finger_width_um": { + "M1": 1.5, + "M2": 1.5 + }, + "axes": "Full3x3 Cartesian nf(M1),nf(M2)={2,4,6}, fixed totalW3um and L.6um per device. No point selected from candidate outcomes." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/dev_n2_4.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/dev_n2_4.json new file mode 100644 index 00000000..48353953 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/dev_n2_4.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c01_per_device_nf", + "configuration_id": "dev_n2_4", + "reference_id": "c01_per_device_nf_dev_n2_4_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_UNLAUNCHED_INDEPENDENT_PER_DEVICE_FINGER_AXES", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 3.0, + "matched_ratio": "1:1", + "nf": { + "M1": 2, + "M2": 4 + }, + "per_finger_width_um": { + "M1": 1.5, + "M2": 0.75 + }, + "axes": "Full3x3 Cartesian nf(M1),nf(M2)={2,4,6}, fixed totalW3um and L.6um per device. No point selected from candidate outcomes." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/dev_n2_6.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/dev_n2_6.json new file mode 100644 index 00000000..fc1a3a65 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/dev_n2_6.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c01_per_device_nf", + "configuration_id": "dev_n2_6", + "reference_id": "c01_per_device_nf_dev_n2_6_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_UNLAUNCHED_INDEPENDENT_PER_DEVICE_FINGER_AXES", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 3.0, + "matched_ratio": "1:1", + "nf": { + "M1": 2, + "M2": 6 + }, + "per_finger_width_um": { + "M1": 1.5, + "M2": 0.5 + }, + "axes": "Full3x3 Cartesian nf(M1),nf(M2)={2,4,6}, fixed totalW3um and L.6um per device. No point selected from candidate outcomes." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/dev_n4_2.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/dev_n4_2.json new file mode 100644 index 00000000..0887cfa9 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/dev_n4_2.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c01_per_device_nf", + "configuration_id": "dev_n4_2", + "reference_id": "c01_per_device_nf_dev_n4_2_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_UNLAUNCHED_INDEPENDENT_PER_DEVICE_FINGER_AXES", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 3.0, + "matched_ratio": "1:1", + "nf": { + "M1": 4, + "M2": 2 + }, + "per_finger_width_um": { + "M1": 0.75, + "M2": 1.5 + }, + "axes": "Full3x3 Cartesian nf(M1),nf(M2)={2,4,6}, fixed totalW3um and L.6um per device. No point selected from candidate outcomes." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/dev_n4_6.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/dev_n4_6.json new file mode 100644 index 00000000..737d54ae --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/dev_n4_6.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c01_per_device_nf", + "configuration_id": "dev_n4_6", + "reference_id": "c01_per_device_nf_dev_n4_6_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_UNLAUNCHED_INDEPENDENT_PER_DEVICE_FINGER_AXES", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 3.0, + "matched_ratio": "1:1", + "nf": { + "M1": 4, + "M2": 6 + }, + "per_finger_width_um": { + "M1": 0.75, + "M2": 0.5 + }, + "axes": "Full3x3 Cartesian nf(M1),nf(M2)={2,4,6}, fixed totalW3um and L.6um per device. No point selected from candidate outcomes." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/dev_n6_2.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/dev_n6_2.json new file mode 100644 index 00000000..27164a00 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/dev_n6_2.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c01_per_device_nf", + "configuration_id": "dev_n6_2", + "reference_id": "c01_per_device_nf_dev_n6_2_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_UNLAUNCHED_INDEPENDENT_PER_DEVICE_FINGER_AXES", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 3.0, + "matched_ratio": "1:1", + "nf": { + "M1": 6, + "M2": 2 + }, + "per_finger_width_um": { + "M1": 0.5, + "M2": 1.5 + }, + "axes": "Full3x3 Cartesian nf(M1),nf(M2)={2,4,6}, fixed totalW3um and L.6um per device. No point selected from candidate outcomes." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/dev_n6_4.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/dev_n6_4.json new file mode 100644 index 00000000..bb02237b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/dev_n6_4.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c01_per_device_nf", + "configuration_id": "dev_n6_4", + "reference_id": "c01_per_device_nf_dev_n6_4_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_UNLAUNCHED_INDEPENDENT_PER_DEVICE_FINGER_AXES", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 3.0, + "matched_ratio": "1:1", + "nf": { + "M1": 6, + "M2": 4 + }, + "per_finger_width_um": { + "M1": 0.5, + "M2": 0.75 + }, + "axes": "Full3x3 Cartesian nf(M1),nf(M2)={2,4,6}, fixed totalW3um and L.6um per device. No point selected from candidate outcomes." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/dev_n6_6.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/dev_n6_6.json new file mode 100644 index 00000000..1dce759c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/contracts/dev_n6_6.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c01_per_device_nf", + "configuration_id": "dev_n6_6", + "reference_id": "c01_per_device_nf_dev_n6_6_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_UNLAUNCHED_INDEPENDENT_PER_DEVICE_FINGER_AXES", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 3.0, + "matched_ratio": "1:1", + "nf": { + "M1": 6, + "M2": 6 + }, + "per_finger_width_um": { + "M1": 0.5, + "M2": 0.5 + }, + "axes": "Full3x3 Cartesian nf(M1),nf(M2)={2,4,6}, fixed totalW3um and L.6um per device. No point selected from candidate outcomes." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/qualification_commands.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/qualification_commands.json new file mode 100644 index 00000000..760a1b00 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/qualification_commands.json @@ -0,0 +1,204 @@ +{ + "status": "PREPARED_NOT_LAUNCHED", + "resource_rule": "Only after the current C02 qualification lane has completed; one2CPU worker, actualbusy+2<=24/RAM<=190GiB before every dispatch", + "commands": [ + { + "configuration_id": "anchor", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_per_device_nf_family/configurations.json", + "--configuration-id", + "anchor" + ] + }, + { + "configuration_id": "dev_n2_2", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_per_device_nf_family/configurations.json", + "--configuration-id", + "dev_n2_2" + ] + }, + { + "configuration_id": "dev_n2_4", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_per_device_nf_family/configurations.json", + "--configuration-id", + "dev_n2_4" + ] + }, + { + "configuration_id": "dev_n2_6", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_per_device_nf_family/configurations.json", + "--configuration-id", + "dev_n2_6" + ] + }, + { + "configuration_id": "dev_n4_2", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_per_device_nf_family/configurations.json", + "--configuration-id", + "dev_n4_2" + ] + }, + { + "configuration_id": "dev_n4_6", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_per_device_nf_family/configurations.json", + "--configuration-id", + "dev_n4_6" + ] + }, + { + "configuration_id": "dev_n6_2", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_per_device_nf_family/configurations.json", + "--configuration-id", + "dev_n6_2" + ] + }, + { + "configuration_id": "dev_n6_4", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_per_device_nf_family/configurations.json", + "--configuration-id", + "dev_n6_4" + ] + }, + { + "configuration_id": "dev_n6_6", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_per_device_nf_family/configurations.json", + "--configuration-id", + "dev_n6_6" + ] + } + ] +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/anchor.spice new file mode 100644 index 00000000..281a6ada --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/anchor.spice @@ -0,0 +1,10 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/dev_n2_2.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/dev_n2_2.spice new file mode 100644 index 00000000..54807ff0 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/dev_n2_2.spice @@ -0,0 +1,6 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.5 l=0.6 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.5 l=0.6 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.5 l=0.6 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.5 l=0.6 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/dev_n2_4.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/dev_n2_4.spice new file mode 100644 index 00000000..00aa058d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/dev_n2_4.spice @@ -0,0 +1,8 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.5 l=0.6 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.5 l=0.6 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/dev_n2_6.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/dev_n2_6.spice new file mode 100644 index 00000000..69afb7d5 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/dev_n2_6.spice @@ -0,0 +1,10 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.5 l=0.6 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.5 l=0.6 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f4 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f5 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/dev_n4_2.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/dev_n4_2.spice new file mode 100644 index 00000000..52894679 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/dev_n4_2.spice @@ -0,0 +1,8 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.5 l=0.6 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.5 l=0.6 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/dev_n4_6.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/dev_n4_6.spice new file mode 100644 index 00000000..f11904fc --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/dev_n4_6.spice @@ -0,0 +1,12 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f4 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f5 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/dev_n6_2.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/dev_n6_2.spice new file mode 100644 index 00000000..28b301ce --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/dev_n6_2.spice @@ -0,0 +1,10 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f4 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f5 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.5 l=0.6 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.5 l=0.6 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/dev_n6_4.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/dev_n6_4.spice new file mode 100644 index 00000000..1ca5baef --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/dev_n6_4.spice @@ -0,0 +1,12 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f4 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f5 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/dev_n6_6.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/dev_n6_6.spice new file mode 100644 index 00000000..29a33b5a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_family/references/dev_n6_6.spice @@ -0,0 +1,14 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f4 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f5 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f4 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f5 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/circuit_input.json new file mode 100644 index 00000000..02963814 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/circuit_input.json @@ -0,0 +1,62 @@ +{ + "circuit_id": "C01", + "name": "basic_current_mirror", + "ports": [ + "VSS", + "IB1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IB1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "IOUT1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 726, + "files": [ + "Dataset/726/726.cir", + "Dataset/726/Port726.txt", + "Dataset/726/Pagenumber726.txt", + "Dataset/726/Book726.png", + "Dataset/726/Cadence726.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "305", + "device_name_map": { + "M1": "M3", + "M2": "M5" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/726/Book726.png", + "observation": "Johns p.305 scan: Q1 diode-connected NMOS, Q2 output NMOS gate tied through a long wire (bias-distribution figure); basic 1:1 mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/configurations.json new file mode 100644 index 00000000..171cab59 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/configurations.json @@ -0,0 +1,302 @@ +{ + "status": "DRAFT_NOT_APPROVED_NOT_SIMULATED", + "created_at_utc": "2026-10-19T04:36:46.019966+00:00", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "source_lineages": 1, + "circuit_id": "C01", + "development_domain_id": "C01_long_channel_per_device_nf", + "circuit_input_file": "configs/development/c01_per_device_nf_long_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "long_anchor", + "role": "anchor", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 15.0, + "l": 3.0, + "nf": 4 + }, + "M2": { + "w": 15.0, + "l": 3.0, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_long_family/references/long_anchor.spice", + "contract_file": "configs/development/c01_per_device_nf_long_family/contracts/long_anchor.json", + "same_nf_pair_as": "anchor", + "grouping_expectation": { + "sharing_group_sizes": [ + 2 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + }, + { + "configuration_id": "long_dev_n2_2", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 15.0, + "l": 3.0, + "nf": 2 + }, + "M2": { + "w": 15.0, + "l": 3.0, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_long_family/references/long_dev_n2_2.spice", + "contract_file": "configs/development/c01_per_device_nf_long_family/contracts/long_dev_n2_2.json", + "same_nf_pair_as": "dev_n2_2", + "grouping_expectation": { + "sharing_group_sizes": [ + 2 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + }, + { + "configuration_id": "long_dev_n2_4", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 15.0, + "l": 3.0, + "nf": 2 + }, + "M2": { + "w": 15.0, + "l": 3.0, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_long_family/references/long_dev_n2_4.spice", + "contract_file": "configs/development/c01_per_device_nf_long_family/contracts/long_dev_n2_4.json", + "same_nf_pair_as": "dev_n2_4", + "grouping_expectation": { + "sharing_group_sizes": [ + 1, + 1 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + }, + { + "configuration_id": "long_dev_n2_6", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 15.0, + "l": 3.0, + "nf": 2 + }, + "M2": { + "w": 15.0, + "l": 3.0, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_long_family/references/long_dev_n2_6.spice", + "contract_file": "configs/development/c01_per_device_nf_long_family/contracts/long_dev_n2_6.json", + "same_nf_pair_as": "dev_n2_6", + "grouping_expectation": { + "sharing_group_sizes": [ + 1, + 1 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + }, + { + "configuration_id": "long_dev_n4_2", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 15.0, + "l": 3.0, + "nf": 4 + }, + "M2": { + "w": 15.0, + "l": 3.0, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_long_family/references/long_dev_n4_2.spice", + "contract_file": "configs/development/c01_per_device_nf_long_family/contracts/long_dev_n4_2.json", + "same_nf_pair_as": "dev_n4_2", + "grouping_expectation": { + "sharing_group_sizes": [ + 1, + 1 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + }, + { + "configuration_id": "long_dev_n4_6", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 15.0, + "l": 3.0, + "nf": 4 + }, + "M2": { + "w": 15.0, + "l": 3.0, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_long_family/references/long_dev_n4_6.spice", + "contract_file": "configs/development/c01_per_device_nf_long_family/contracts/long_dev_n4_6.json", + "same_nf_pair_as": "dev_n4_6", + "grouping_expectation": { + "sharing_group_sizes": [ + 1, + 1 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + }, + { + "configuration_id": "long_dev_n6_2", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 15.0, + "l": 3.0, + "nf": 6 + }, + "M2": { + "w": 15.0, + "l": 3.0, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_long_family/references/long_dev_n6_2.spice", + "contract_file": "configs/development/c01_per_device_nf_long_family/contracts/long_dev_n6_2.json", + "same_nf_pair_as": "dev_n6_2", + "grouping_expectation": { + "sharing_group_sizes": [ + 1, + 1 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + }, + { + "configuration_id": "long_dev_n6_4", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 15.0, + "l": 3.0, + "nf": 6 + }, + "M2": { + "w": 15.0, + "l": 3.0, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_long_family/references/long_dev_n6_4.spice", + "contract_file": "configs/development/c01_per_device_nf_long_family/contracts/long_dev_n6_4.json", + "same_nf_pair_as": "dev_n6_4", + "grouping_expectation": { + "sharing_group_sizes": [ + 1, + 1 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + }, + { + "configuration_id": "long_dev_n6_6", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 15.0, + "l": 3.0, + "nf": 6 + }, + "M2": { + "w": 15.0, + "l": 3.0, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_long_family/references/long_dev_n6_6.spice", + "contract_file": "configs/development/c01_per_device_nf_long_family/contracts/long_dev_n6_6.json", + "same_nf_pair_as": "dev_n6_6", + "grouping_expectation": { + "sharing_group_sizes": [ + 2 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + } + ], + "nf_grid": { + "M1": [ + 2, + 4, + 6 + ], + "M2": [ + 2, + 4, + 6 + ] + }, + "hypothesis": "Scale original totalW3/L.6 together by five to totalW15/L3, preserving total W/L5 while changing physical channel length and per-finger widths to2.5/3.75/7.5um. No electrical equivalence or qualification is assumed.", + "application_and_bench_unchanged": [ + "20uA reference", + "1.8V supply", + "27C", + "tt/ss/ff", + "0.9V nominal output", + "complete0..1.8V/.1V DC", + "5percent nominal and .7..1.0V sampled compliance error", + "ro>=300kohm", + "original AC/transient analyses and tight tolerances" + ], + "domain_selection_rule": "All nine nf pairs fixed before any new simulation; no post-result screening or adaptive resizing.", + "causal_limitations": "Original ideal narrow-width-partition failures precede RC; internal BSIM gm/gds/vth/vdsat absent. Existing wide-domain failure causes require its raw fields, not inference from its1/9 summary.", + "requires_root_approval_before_one_complete_ideal_nine_point_run": true, + "layout_prohibited_before_whole_ideal_domain_qualified": true, + "old_results_contracts_or_training_labels_changed": false, + "new_model_calls": 0, + "new_physical_calls": 0, + "new_training_examples": 0 +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_anchor.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_anchor.json new file mode 100644 index 00000000..6e0a971a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_anchor.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c01_long_nf", + "configuration_id": "long_anchor", + "reference_id": "c01_long_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_PREDECLARED_LONG_CHANNEL_IDEAL_QUALIFICATION_PENDING", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 15.0, + "length_um": 3.0, + "nf": { + "M1": 4, + "M2": 4 + }, + "per_finger_width_um": { + "M1": 3.75, + "M2": 3.75 + }, + "matched_ratio": "1:1", + "total_W_over_L": 5.0 + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_dev_n2_2.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_dev_n2_2.json new file mode 100644 index 00000000..49eb0cb6 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_dev_n2_2.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c01_long_nf", + "configuration_id": "long_dev_n2_2", + "reference_id": "c01_long_dev_n2_2_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_PREDECLARED_LONG_CHANNEL_IDEAL_QUALIFICATION_PENDING", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 15.0, + "length_um": 3.0, + "nf": { + "M1": 2, + "M2": 2 + }, + "per_finger_width_um": { + "M1": 7.5, + "M2": 7.5 + }, + "matched_ratio": "1:1", + "total_W_over_L": 5.0 + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_dev_n2_4.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_dev_n2_4.json new file mode 100644 index 00000000..534ad664 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_dev_n2_4.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c01_long_nf", + "configuration_id": "long_dev_n2_4", + "reference_id": "c01_long_dev_n2_4_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_PREDECLARED_LONG_CHANNEL_IDEAL_QUALIFICATION_PENDING", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 15.0, + "length_um": 3.0, + "nf": { + "M1": 2, + "M2": 4 + }, + "per_finger_width_um": { + "M1": 7.5, + "M2": 3.75 + }, + "matched_ratio": "1:1", + "total_W_over_L": 5.0 + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_dev_n2_6.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_dev_n2_6.json new file mode 100644 index 00000000..495e030c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_dev_n2_6.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c01_long_nf", + "configuration_id": "long_dev_n2_6", + "reference_id": "c01_long_dev_n2_6_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_PREDECLARED_LONG_CHANNEL_IDEAL_QUALIFICATION_PENDING", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 15.0, + "length_um": 3.0, + "nf": { + "M1": 2, + "M2": 6 + }, + "per_finger_width_um": { + "M1": 7.5, + "M2": 2.5 + }, + "matched_ratio": "1:1", + "total_W_over_L": 5.0 + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_dev_n4_2.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_dev_n4_2.json new file mode 100644 index 00000000..9e5354bf --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_dev_n4_2.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c01_long_nf", + "configuration_id": "long_dev_n4_2", + "reference_id": "c01_long_dev_n4_2_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_PREDECLARED_LONG_CHANNEL_IDEAL_QUALIFICATION_PENDING", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 15.0, + "length_um": 3.0, + "nf": { + "M1": 4, + "M2": 2 + }, + "per_finger_width_um": { + "M1": 3.75, + "M2": 7.5 + }, + "matched_ratio": "1:1", + "total_W_over_L": 5.0 + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_dev_n4_6.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_dev_n4_6.json new file mode 100644 index 00000000..13a033e2 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_dev_n4_6.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c01_long_nf", + "configuration_id": "long_dev_n4_6", + "reference_id": "c01_long_dev_n4_6_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_PREDECLARED_LONG_CHANNEL_IDEAL_QUALIFICATION_PENDING", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 15.0, + "length_um": 3.0, + "nf": { + "M1": 4, + "M2": 6 + }, + "per_finger_width_um": { + "M1": 3.75, + "M2": 2.5 + }, + "matched_ratio": "1:1", + "total_W_over_L": 5.0 + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_dev_n6_2.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_dev_n6_2.json new file mode 100644 index 00000000..899e0527 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_dev_n6_2.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c01_long_nf", + "configuration_id": "long_dev_n6_2", + "reference_id": "c01_long_dev_n6_2_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_PREDECLARED_LONG_CHANNEL_IDEAL_QUALIFICATION_PENDING", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 15.0, + "length_um": 3.0, + "nf": { + "M1": 6, + "M2": 2 + }, + "per_finger_width_um": { + "M1": 2.5, + "M2": 7.5 + }, + "matched_ratio": "1:1", + "total_W_over_L": 5.0 + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_dev_n6_4.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_dev_n6_4.json new file mode 100644 index 00000000..4305e2da --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_dev_n6_4.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c01_long_nf", + "configuration_id": "long_dev_n6_4", + "reference_id": "c01_long_dev_n6_4_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_PREDECLARED_LONG_CHANNEL_IDEAL_QUALIFICATION_PENDING", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 15.0, + "length_um": 3.0, + "nf": { + "M1": 6, + "M2": 4 + }, + "per_finger_width_um": { + "M1": 2.5, + "M2": 3.75 + }, + "matched_ratio": "1:1", + "total_W_over_L": 5.0 + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_dev_n6_6.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_dev_n6_6.json new file mode 100644 index 00000000..7c598e6e --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/contracts/long_dev_n6_6.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c01_long_nf", + "configuration_id": "long_dev_n6_6", + "reference_id": "c01_long_dev_n6_6_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_PREDECLARED_LONG_CHANNEL_IDEAL_QUALIFICATION_PENDING", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 15.0, + "length_um": 3.0, + "nf": { + "M1": 6, + "M2": 6 + }, + "per_finger_width_um": { + "M1": 2.5, + "M2": 2.5 + }, + "matched_ratio": "1:1", + "total_W_over_L": 5.0 + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_anchor.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_anchor.spice new file mode 100644 index 00000000..ba079124 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_anchor.spice @@ -0,0 +1,10 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=3.75 l=3.0 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=3.75 l=3.0 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=3.75 l=3.0 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=3.75 l=3.0 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=3.75 l=3.0 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=3.75 l=3.0 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=3.75 l=3.0 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=3.75 l=3.0 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_dev_n2_2.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_dev_n2_2.spice new file mode 100644 index 00000000..fa547f9f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_dev_n2_2.spice @@ -0,0 +1,6 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=3.0 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=3.0 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=3.0 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=3.0 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_dev_n2_4.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_dev_n2_4.spice new file mode 100644 index 00000000..2e96271c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_dev_n2_4.spice @@ -0,0 +1,8 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=3.0 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=3.0 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=3.75 l=3.0 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=3.75 l=3.0 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=3.75 l=3.0 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=3.75 l=3.0 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_dev_n2_6.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_dev_n2_6.spice new file mode 100644 index 00000000..d6df8c8b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_dev_n2_6.spice @@ -0,0 +1,10 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=3.0 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=3.0 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM2_f4 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM2_f5 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_dev_n4_2.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_dev_n4_2.spice new file mode 100644 index 00000000..dded9bf0 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_dev_n4_2.spice @@ -0,0 +1,8 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=3.75 l=3.0 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=3.75 l=3.0 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=3.75 l=3.0 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=3.75 l=3.0 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=3.0 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=3.0 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_dev_n4_6.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_dev_n4_6.spice new file mode 100644 index 00000000..31c4efc2 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_dev_n4_6.spice @@ -0,0 +1,12 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=3.75 l=3.0 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=3.75 l=3.0 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=3.75 l=3.0 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=3.75 l=3.0 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM2_f4 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM2_f5 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_dev_n6_2.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_dev_n6_2.spice new file mode 100644 index 00000000..994b350e --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_dev_n6_2.spice @@ -0,0 +1,10 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM1_f4 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM1_f5 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=3.0 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=3.0 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_dev_n6_4.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_dev_n6_4.spice new file mode 100644 index 00000000..66507d16 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_dev_n6_4.spice @@ -0,0 +1,12 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM1_f4 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM1_f5 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=3.75 l=3.0 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=3.75 l=3.0 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=3.75 l=3.0 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=3.75 l=3.0 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_dev_n6_6.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_dev_n6_6.spice new file mode 100644 index 00000000..86280425 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_long_family/references/long_dev_n6_6.spice @@ -0,0 +1,14 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM1_f4 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM1_f5 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM2_f4 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +XM2_f5 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=2.5 l=3.0 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/circuit_input.json new file mode 100644 index 00000000..02963814 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/circuit_input.json @@ -0,0 +1,62 @@ +{ + "circuit_id": "C01", + "name": "basic_current_mirror", + "ports": [ + "VSS", + "IB1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IB1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "IOUT1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 726, + "files": [ + "Dataset/726/726.cir", + "Dataset/726/Port726.txt", + "Dataset/726/Pagenumber726.txt", + "Dataset/726/Book726.png", + "Dataset/726/Cadence726.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "305", + "device_name_map": { + "M1": "M3", + "M2": "M5" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/726/Book726.png", + "observation": "Johns p.305 scan: Q1 diode-connected NMOS, Q2 output NMOS gate tied through a long wire (bias-distribution figure); basic 1:1 mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/configurations.json new file mode 100644 index 00000000..e3bf7d8b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/configurations.json @@ -0,0 +1,276 @@ +{ + "status": "DRAFT_NO_IDEAL_OR_LAYOUT_MEASUREMENTS", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "source_lineages": 1, + "circuit_id": "C01", + "development_domain_id": "C01_wide_per_device_nf", + "circuit_input_file": "configs/development/c01_per_device_nf_wide_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "wide_anchor", + "role": "anchor", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 30.0, + "l": 0.6, + "nf": 4 + }, + "M2": { + "w": 30.0, + "l": 0.6, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_wide_family/references/wide_anchor.spice", + "contract_file": "configs/development/c01_per_device_nf_wide_family/contracts/wide_anchor.json", + "same_nf_pair_as": "anchor", + "grouping_expectation": { + "sharing_group_sizes": [ + 2 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + }, + { + "configuration_id": "wide_dev_n2_2", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 30.0, + "l": 0.6, + "nf": 2 + }, + "M2": { + "w": 30.0, + "l": 0.6, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_wide_family/references/wide_dev_n2_2.spice", + "contract_file": "configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n2_2.json", + "same_nf_pair_as": "dev_n2_2", + "grouping_expectation": { + "sharing_group_sizes": [ + 2 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + }, + { + "configuration_id": "wide_dev_n2_4", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 30.0, + "l": 0.6, + "nf": 2 + }, + "M2": { + "w": 30.0, + "l": 0.6, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_wide_family/references/wide_dev_n2_4.spice", + "contract_file": "configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n2_4.json", + "same_nf_pair_as": "dev_n2_4", + "grouping_expectation": { + "sharing_group_sizes": [ + 1, + 1 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + }, + { + "configuration_id": "wide_dev_n2_6", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 30.0, + "l": 0.6, + "nf": 2 + }, + "M2": { + "w": 30.0, + "l": 0.6, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_wide_family/references/wide_dev_n2_6.spice", + "contract_file": "configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n2_6.json", + "same_nf_pair_as": "dev_n2_6", + "grouping_expectation": { + "sharing_group_sizes": [ + 1, + 1 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + }, + { + "configuration_id": "wide_dev_n4_2", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 30.0, + "l": 0.6, + "nf": 4 + }, + "M2": { + "w": 30.0, + "l": 0.6, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_wide_family/references/wide_dev_n4_2.spice", + "contract_file": "configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n4_2.json", + "same_nf_pair_as": "dev_n4_2", + "grouping_expectation": { + "sharing_group_sizes": [ + 1, + 1 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + }, + { + "configuration_id": "wide_dev_n4_6", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 30.0, + "l": 0.6, + "nf": 4 + }, + "M2": { + "w": 30.0, + "l": 0.6, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_wide_family/references/wide_dev_n4_6.spice", + "contract_file": "configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n4_6.json", + "same_nf_pair_as": "dev_n4_6", + "grouping_expectation": { + "sharing_group_sizes": [ + 1, + 1 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + }, + { + "configuration_id": "wide_dev_n6_2", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 30.0, + "l": 0.6, + "nf": 6 + }, + "M2": { + "w": 30.0, + "l": 0.6, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_wide_family/references/wide_dev_n6_2.spice", + "contract_file": "configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n6_2.json", + "same_nf_pair_as": "dev_n6_2", + "grouping_expectation": { + "sharing_group_sizes": [ + 1, + 1 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + }, + { + "configuration_id": "wide_dev_n6_4", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 30.0, + "l": 0.6, + "nf": 6 + }, + "M2": { + "w": 30.0, + "l": 0.6, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_wide_family/references/wide_dev_n6_4.spice", + "contract_file": "configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n6_4.json", + "same_nf_pair_as": "dev_n6_4", + "grouping_expectation": { + "sharing_group_sizes": [ + 1, + 1 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + }, + { + "configuration_id": "wide_dev_n6_6", + "role": "development", + "parameters": { + "circuit_id": "C01", + "sizing": { + "M1": { + "w": 30.0, + "l": 0.6, + "nf": 6 + }, + "M2": { + "w": 30.0, + "l": 0.6, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c01_per_device_nf_wide_family/references/wide_dev_n6_6.spice", + "contract_file": "configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n6_6.json", + "same_nf_pair_as": "dev_n6_6", + "grouping_expectation": { + "sharing_group_sizes": [ + 2 + ], + "basis": "Actual source sharing_groups requires equal L and per-finger unit_width; graph and body remain identical. This is an algorithmic grouping expectation, not a physical pass or preference label." + } + } + ], + "hypothesis": "The complete same-nf and off-diagonal grid remains {2,4,6}x{2,4,6}; both device total widths are prospectively 30um, so finger widths are5/7.5/15um rather than.5/.75/1.5um. This tests whether model narrow-width dependence caused the original ideal mismatch. No physical pass or current matching is assumed; unchanged5% current/300kohm/compliance constraints apply. All nine ideal points must qualify before any layout.", + "configuration_or_spec_selected_by_postlayout_outcomes": false, + "retained_original_domain_unchanged": "/srv/code-behind-layout/configs/development/c01_per_device_nf_family/configurations.json", + "reference_sizing_fixed_before_any_new_ideal_simulation": true, + "formal_training_rows": 0, + "model_requests": 0, + "ideal_or_layout_runs": 0 +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_anchor.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_anchor.json new file mode 100644 index 00000000..0ef067c5 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_anchor.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c01_wide_nf", + "configuration_id": "wide_anchor", + "reference_id": "c01_wide_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_PREDECLARED_WIDE_WIDTH_IDEAL_QUALIFICATION_PENDING", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 30.0, + "length_um": 0.6, + "nf": { + "M1": 4, + "M2": 4 + }, + "per_finger_width_um": { + "M1": 7.5, + "M2": 7.5 + }, + "matched_ratio": "1:1" + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n2_2.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n2_2.json new file mode 100644 index 00000000..4e90a30d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n2_2.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c01_wide_nf", + "configuration_id": "wide_dev_n2_2", + "reference_id": "c01_wide_dev_n2_2_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_PREDECLARED_WIDE_WIDTH_IDEAL_QUALIFICATION_PENDING", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 30.0, + "length_um": 0.6, + "nf": { + "M1": 2, + "M2": 2 + }, + "per_finger_width_um": { + "M1": 15.0, + "M2": 15.0 + }, + "matched_ratio": "1:1" + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n2_4.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n2_4.json new file mode 100644 index 00000000..e00f7f4d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n2_4.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c01_wide_nf", + "configuration_id": "wide_dev_n2_4", + "reference_id": "c01_wide_dev_n2_4_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_PREDECLARED_WIDE_WIDTH_IDEAL_QUALIFICATION_PENDING", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 30.0, + "length_um": 0.6, + "nf": { + "M1": 2, + "M2": 4 + }, + "per_finger_width_um": { + "M1": 15.0, + "M2": 7.5 + }, + "matched_ratio": "1:1" + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n2_6.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n2_6.json new file mode 100644 index 00000000..ec93489b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n2_6.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c01_wide_nf", + "configuration_id": "wide_dev_n2_6", + "reference_id": "c01_wide_dev_n2_6_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_PREDECLARED_WIDE_WIDTH_IDEAL_QUALIFICATION_PENDING", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 30.0, + "length_um": 0.6, + "nf": { + "M1": 2, + "M2": 6 + }, + "per_finger_width_um": { + "M1": 15.0, + "M2": 5.0 + }, + "matched_ratio": "1:1" + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n4_2.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n4_2.json new file mode 100644 index 00000000..b9c2431f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n4_2.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c01_wide_nf", + "configuration_id": "wide_dev_n4_2", + "reference_id": "c01_wide_dev_n4_2_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_PREDECLARED_WIDE_WIDTH_IDEAL_QUALIFICATION_PENDING", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 30.0, + "length_um": 0.6, + "nf": { + "M1": 4, + "M2": 2 + }, + "per_finger_width_um": { + "M1": 7.5, + "M2": 15.0 + }, + "matched_ratio": "1:1" + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n4_6.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n4_6.json new file mode 100644 index 00000000..1afe99ff --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n4_6.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c01_wide_nf", + "configuration_id": "wide_dev_n4_6", + "reference_id": "c01_wide_dev_n4_6_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_PREDECLARED_WIDE_WIDTH_IDEAL_QUALIFICATION_PENDING", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 30.0, + "length_um": 0.6, + "nf": { + "M1": 4, + "M2": 6 + }, + "per_finger_width_um": { + "M1": 7.5, + "M2": 5.0 + }, + "matched_ratio": "1:1" + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n6_2.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n6_2.json new file mode 100644 index 00000000..f83798c3 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n6_2.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c01_wide_nf", + "configuration_id": "wide_dev_n6_2", + "reference_id": "c01_wide_dev_n6_2_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_PREDECLARED_WIDE_WIDTH_IDEAL_QUALIFICATION_PENDING", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 30.0, + "length_um": 0.6, + "nf": { + "M1": 6, + "M2": 2 + }, + "per_finger_width_um": { + "M1": 5.0, + "M2": 15.0 + }, + "matched_ratio": "1:1" + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n6_4.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n6_4.json new file mode 100644 index 00000000..03034930 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n6_4.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c01_wide_nf", + "configuration_id": "wide_dev_n6_4", + "reference_id": "c01_wide_dev_n6_4_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_PREDECLARED_WIDE_WIDTH_IDEAL_QUALIFICATION_PENDING", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 30.0, + "length_um": 0.6, + "nf": { + "M1": 6, + "M2": 4 + }, + "per_finger_width_um": { + "M1": 5.0, + "M2": 7.5 + }, + "matched_ratio": "1:1" + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n6_6.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n6_6.json new file mode 100644 index 00000000..cc37dffc --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n6_6.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c01_wide_nf", + "configuration_id": "wide_dev_n6_6", + "reference_id": "c01_wide_dev_n6_6_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 300000 + }, + { + "name": "compliance_band_max_relative_error", + "unit": "1", + "max": 0.05 + } + ], + "objective": { + "id": "c01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + } + }, + "scope": "DRAFT_PREDECLARED_WIDE_WIDTH_IDEAL_QUALIFICATION_PENDING", + "nominal_operating_point": { + "supply_V": 1.8, + "reference_current_A": 2e-05, + "output_voltage_V": 0.9, + "temperature_C": 27 + }, + "intent": { + "mirror_ratio": 1, + "all_nmos_bulk_source": "VSS", + "graph_and_sizes_immutable": true + }, + "diagnostic_dc_sweep_not_intrinsic_compliance_spec": { + "start_V": 0, + "end_V": 1.8, + "step_V": 0.1 + }, + "declared_compliance_sample_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "sizing_semantics": { + "total_width_um": 30.0, + "length_um": 0.6, + "nf": { + "M1": 6, + "M2": 6 + }, + "per_finger_width_um": { + "M1": 5.0, + "M2": 5.0 + }, + "matched_ratio": "1:1" + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/qualification_commands.json b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/qualification_commands.json new file mode 100644 index 00000000..e0e42815 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/qualification_commands.json @@ -0,0 +1,248 @@ +{ + "status": "DRAFT_NOT_DISPATCHED_IDEAL_OUTCOME_UNOBSERVED", + "scope": "development_only_not_training_labels", + "commands": [ + { + "configuration_id": "wide_anchor", + "independent_reference_file": "configs/development/c01_per_device_nf_wide_family/references/wide_anchor.spice", + "contract_file": "configs/development/c01_per_device_nf_wide_family/contracts/wide_anchor.json", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--input-dir", + "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_per_device_nf_wide_family/configurations.json", + "--configuration-id", + "wide_anchor" + ] + }, + { + "configuration_id": "wide_dev_n2_2", + "independent_reference_file": "configs/development/c01_per_device_nf_wide_family/references/wide_dev_n2_2.spice", + "contract_file": "configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n2_2.json", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--input-dir", + "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_per_device_nf_wide_family/configurations.json", + "--configuration-id", + "wide_dev_n2_2" + ] + }, + { + "configuration_id": "wide_dev_n2_4", + "independent_reference_file": "configs/development/c01_per_device_nf_wide_family/references/wide_dev_n2_4.spice", + "contract_file": "configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n2_4.json", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--input-dir", + "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_per_device_nf_wide_family/configurations.json", + "--configuration-id", + "wide_dev_n2_4" + ] + }, + { + "configuration_id": "wide_dev_n2_6", + "independent_reference_file": "configs/development/c01_per_device_nf_wide_family/references/wide_dev_n2_6.spice", + "contract_file": "configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n2_6.json", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--input-dir", + "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_per_device_nf_wide_family/configurations.json", + "--configuration-id", + "wide_dev_n2_6" + ] + }, + { + "configuration_id": "wide_dev_n4_2", + "independent_reference_file": "configs/development/c01_per_device_nf_wide_family/references/wide_dev_n4_2.spice", + "contract_file": "configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n4_2.json", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--input-dir", + "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_per_device_nf_wide_family/configurations.json", + "--configuration-id", + "wide_dev_n4_2" + ] + }, + { + "configuration_id": "wide_dev_n4_6", + "independent_reference_file": "configs/development/c01_per_device_nf_wide_family/references/wide_dev_n4_6.spice", + "contract_file": "configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n4_6.json", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--input-dir", + "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_per_device_nf_wide_family/configurations.json", + "--configuration-id", + "wide_dev_n4_6" + ] + }, + { + "configuration_id": "wide_dev_n6_2", + "independent_reference_file": "configs/development/c01_per_device_nf_wide_family/references/wide_dev_n6_2.spice", + "contract_file": "configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n6_2.json", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--input-dir", + "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_per_device_nf_wide_family/configurations.json", + "--configuration-id", + "wide_dev_n6_2" + ] + }, + { + "configuration_id": "wide_dev_n6_4", + "independent_reference_file": "configs/development/c01_per_device_nf_wide_family/references/wide_dev_n6_4.spice", + "contract_file": "configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n6_4.json", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--input-dir", + "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_per_device_nf_wide_family/configurations.json", + "--configuration-id", + "wide_dev_n6_4" + ] + }, + { + "configuration_id": "wide_dev_n6_6", + "independent_reference_file": "configs/development/c01_per_device_nf_wide_family/references/wide_dev_n6_6.spice", + "contract_file": "configs/development/c01_per_device_nf_wide_family/contracts/wide_dev_n6_6.json", + "argv": [ + "python3", + "scripts/run_eda_probe.py", + "--script", + "corpus_yield_pilot.py", + "--magic-runtime", + "magic-8.3.685", + "--timeout", + "1200", + "--input-dir", + "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1", + "--", + "--circuit", + "C01", + "--limit", + "0", + "--family-table", + "/work/configs/development/c01_per_device_nf_wide_family/configurations.json", + "--configuration-id", + "wide_dev_n6_6" + ] + } + ], + "all_nine_points_preserved": true, + "qualification_precondition": "Read existing wide_nf_ideal_qualification terminal raw result; all9 complete ideal tests and unchanged constraints must pass before any layout dispatch. Do not substitute narrow_nf ideal results.", + "resource_rule": "One2CPU worker; actualbusy+2<=24/RAMused<=190GiB/diskfree>=4GiB before every dispatch; retain everypoint; pause on infrastructure fault.", + "source_pack": "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1/source_pack", + "full_flow_gate": "New Magic full-rule DRC, independent gold LVS, exact per-finger/terminal graph, positive full unsimplified RC, complete three-corner OP/AC/transient/DC, original5percent current/300kohm/.7to1Vcompliance.", + "new_model_calls": 0, + "new_physical_calls": 0, + "new_usable_examples": 0 +} diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_anchor.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_anchor.spice new file mode 100644 index 00000000..30af1835 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_anchor.spice @@ -0,0 +1,10 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=0.6 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=0.6 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=0.6 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=0.6 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=0.6 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=0.6 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=0.6 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=0.6 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_dev_n2_2.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_dev_n2_2.spice new file mode 100644 index 00000000..af26e127 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_dev_n2_2.spice @@ -0,0 +1,6 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=15 l=0.6 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=15 l=0.6 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=15 l=0.6 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=15 l=0.6 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_dev_n2_4.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_dev_n2_4.spice new file mode 100644 index 00000000..6ce5d467 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_dev_n2_4.spice @@ -0,0 +1,8 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=15 l=0.6 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=15 l=0.6 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=0.6 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=0.6 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=0.6 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=0.6 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_dev_n2_6.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_dev_n2_6.spice new file mode 100644 index 00000000..a9eddb44 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_dev_n2_6.spice @@ -0,0 +1,10 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=15 l=0.6 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=15 l=0.6 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM2_f4 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM2_f5 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_dev_n4_2.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_dev_n4_2.spice new file mode 100644 index 00000000..3e30aee6 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_dev_n4_2.spice @@ -0,0 +1,8 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=0.6 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=0.6 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=0.6 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=0.6 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=15 l=0.6 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=15 l=0.6 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_dev_n4_6.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_dev_n4_6.spice new file mode 100644 index 00000000..33790d14 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_dev_n4_6.spice @@ -0,0 +1,12 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=0.6 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=0.6 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=0.6 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=0.6 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM2_f4 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM2_f5 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_dev_n6_2.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_dev_n6_2.spice new file mode 100644 index 00000000..ccbeccee --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_dev_n6_2.spice @@ -0,0 +1,10 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM1_f4 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM1_f5 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=15 l=0.6 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=15 l=0.6 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_dev_n6_4.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_dev_n6_4.spice new file mode 100644 index 00000000..38e0dfcb --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_dev_n6_4.spice @@ -0,0 +1,12 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM1_f4 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM1_f5 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=0.6 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=0.6 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=0.6 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=7.5 l=0.6 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_dev_n6_6.spice b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_dev_n6_6.spice new file mode 100644 index 00000000..395a5b30 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_per_device_nf_wide_family/references/wide_dev_n6_6.spice @@ -0,0 +1,14 @@ +.subckt corpus_c01 VSS IB1 IOUT1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM1_f4 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM1_f5 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM2_f0 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM2_f1 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM2_f2 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM2_f3 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM2_f4 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +XM2_f5 IOUT1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=5 l=0.6 +.ends corpus_c01 diff --git a/benchmarks/code_behind_layout/configs/development/c01_rule_collection_preparation.json b/benchmarks/code_behind_layout/configs/development/c01_rule_collection_preparation.json new file mode 100644 index 00000000..271b00c9 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c01_rule_collection_preparation.json @@ -0,0 +1,118 @@ +{ + "status": "DRAFT_PROSPECTIVE_RULE_COLLECTION_NOT_FROZEN", + "role": "train_collection", + "circuit_id": "C01", + "collection_id": "c01_rules_v1", + "capsule_preparation": "/srv/code-behind-layout/runtime/collection_preparation/c01_20261019T011833920147Z/preparation.json", + "source_pack": "/srv/code-behind-layout/runtime/collection_preparation/c01_20261019T011833920147Z/source_pack", + "trusted_bundle": "/srv/code-behind-layout/runtime/collection_preparation/c01_20261019T011833920147Z/trusted", + "initial_states_path": "/srv/code-behind-layout/runtime/collection_preparation/c01_rule_collection_20261019T020138863578Z/initial_states.jsonl", + "initial_state_count": 1, + "editable_paths": [ + "textbook_sharing/layout.py" + ], + "parent_lineage": "textbook_universal_compiler_cropped", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "rule_proposer_path": "/srv/code-behind-layout/runtime/collection_preparation/c01_rule_collection_20261019T020138863578Z/rule_proposer.py", + "rule_ids": [ + "diffusion_plan", + "gate_plan", + "combined_plan", + "reverse_device_order", + "gate_order", + "reverse_port_track_order", + "reverse_devices_combined", + "reverse_ports_combined" + ], + "borrowed_from": "scripts/corpus_yield_pilot.py:variants; same eight development planning rules", + "candidates": [ + { + "rule_id": "diffusion_plan", + "complete_source_file": "/srv/code-behind-layout/runtime/collection_preparation/c01_rule_collection_20261019T020138863578Z/diffusion_plan.py", + "candidate_patch": "--- a/textbook_sharing/layout.py\n+++ b/textbook_sharing/layout.py\n@@ -84,7 +84,7 @@\n plan = SharingPlan.from_json(plans[str(gi)]); src = \"explicit\"\n else:\n nm = named_plans(pdk, g)\n- plan = nm.get(mode) or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n+ plan = nm.get(\"diffusion_only\") or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n res = build_mos_group(pdk, g, plan=plan, name=f\"grp{gi}\")\n rows[pol].append(from_group_result(res, f\"grp{gi}\", pol, g[0].b))\n applied.append({\"group\": gi, \"devices\": [d.logical_id for d in g], \"plan\": res.applied_plan, \"mode_requested\": mode, \"plan_source\": src,\n", + "draft_generation_wall_seconds": 0.006844384130090475, + "draft_generation_process_cpu_seconds": 0.006843826999999997 + }, + { + "rule_id": "gate_plan", + "complete_source_file": "/srv/code-behind-layout/runtime/collection_preparation/c01_rule_collection_20261019T020138863578Z/gate_plan.py", + "candidate_patch": "--- a/textbook_sharing/layout.py\n+++ b/textbook_sharing/layout.py\n@@ -84,7 +84,7 @@\n plan = SharingPlan.from_json(plans[str(gi)]); src = \"explicit\"\n else:\n nm = named_plans(pdk, g)\n- plan = nm.get(mode) or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n+ plan = nm.get(\"gate_only\") or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n res = build_mos_group(pdk, g, plan=plan, name=f\"grp{gi}\")\n rows[pol].append(from_group_result(res, f\"grp{gi}\", pol, g[0].b))\n applied.append({\"group\": gi, \"devices\": [d.logical_id for d in g], \"plan\": res.applied_plan, \"mode_requested\": mode, \"plan_source\": src,\n", + "draft_generation_wall_seconds": 0.005961085669696331, + "draft_generation_process_cpu_seconds": 0.005962040999999987 + }, + { + "rule_id": "combined_plan", + "complete_source_file": "/srv/code-behind-layout/runtime/collection_preparation/c01_rule_collection_20261019T020138863578Z/combined_plan.py", + "candidate_patch": "--- a/textbook_sharing/layout.py\n+++ b/textbook_sharing/layout.py\n@@ -84,7 +84,7 @@\n plan = SharingPlan.from_json(plans[str(gi)]); src = \"explicit\"\n else:\n nm = named_plans(pdk, g)\n- plan = nm.get(mode) or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n+ plan = nm.get(\"combined\") or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n res = build_mos_group(pdk, g, plan=plan, name=f\"grp{gi}\")\n rows[pol].append(from_group_result(res, f\"grp{gi}\", pol, g[0].b))\n applied.append({\"group\": gi, \"devices\": [d.logical_id for d in g], \"plan\": res.applied_plan, \"mode_requested\": mode, \"plan_source\": src,\n", + "draft_generation_wall_seconds": 0.0052754878997802734, + "draft_generation_process_cpu_seconds": 0.005250857999999997 + }, + { + "rule_id": "reverse_device_order", + "complete_source_file": "/srv/code-behind-layout/runtime/collection_preparation/c01_rule_collection_20261019T020138863578Z/reverse_device_order.py", + "candidate_patch": "--- a/textbook_sharing/layout.py\n+++ b/textbook_sharing/layout.py\n@@ -26,7 +26,7 @@\n if d.kind in (\"nfet\", \"pfet\"):\n sz = sizing[d.name]\n out.append(DeviceSpec(d.name, d.kind, d.nets[0], d.nets[1], d.nets[2], d.nets[3], float(sz[\"w\"]), float(sz[\"l\"]), int(sz.get(\"nf\", 1))))\n- return out\n+ return list(reversed(out))\n \n \n def sharing_groups(devs: list[DeviceSpec]) -> list[list[DeviceSpec]]:\n", + "draft_generation_wall_seconds": 0.0050638578832149506, + "draft_generation_process_cpu_seconds": 0.005064883999999992 + }, + { + "rule_id": "gate_order", + "complete_source_file": "/srv/code-behind-layout/runtime/collection_preparation/c01_rule_collection_20261019T020138863578Z/gate_order.py", + "candidate_patch": "--- a/textbook_sharing/layout.py\n+++ b/textbook_sharing/layout.py\n@@ -26,7 +26,7 @@\n if d.kind in (\"nfet\", \"pfet\"):\n sz = sizing[d.name]\n out.append(DeviceSpec(d.name, d.kind, d.nets[0], d.nets[1], d.nets[2], d.nets[3], float(sz[\"w\"]), float(sz[\"l\"]), int(sz.get(\"nf\", 1))))\n- return out\n+ return sorted(out, key=lambda d: (d.g, d.d, d.logical_id))\n \n \n def sharing_groups(devs: list[DeviceSpec]) -> list[list[DeviceSpec]]:\n", + "draft_generation_wall_seconds": 0.005083936732262373, + "draft_generation_process_cpu_seconds": 0.005084904000000001 + }, + { + "rule_id": "reverse_port_track_order", + "complete_source_file": "/srv/code-behind-layout/runtime/collection_preparation/c01_rule_collection_20261019T020138863578Z/reverse_port_track_order.py", + "candidate_patch": "--- a/textbook_sharing/layout.py\n+++ b/textbook_sharing/layout.py\n@@ -95,6 +95,6 @@\n if rows[\"p\"]: row_specs.append(RowSpec(rows[\"p\"], \"p\", True, rows[\"p\"][0].body_net))\n if rows[\"passive\"]: row_specs.append(RowSpec(rows[\"passive\"], \"passive\", True, None, taps=False))\n top = name or f\"{circuit.circuit_id}_{pdk.name}_{mode}\"\n- asm = assemble(pdk, row_specs, circuit.ports, name=top)\n+ asm = assemble(pdk, row_specs, list(reversed(circuit.ports)), name=top)\n return {\"component\": asm[\"component\"], \"name\": top, \"groups\": [[d.logical_id for d in g] for g in groups], \"applied_plans\": applied, \"evidence\": evidence,\n \"assembly_stats\": asm[\"stats\"], \"expected_fingers\": nf_total, \"trunks\": asm[\"trunks\"]}\n", + "draft_generation_wall_seconds": 0.005158327054232359, + "draft_generation_process_cpu_seconds": 0.005159458000000006 + }, + { + "rule_id": "reverse_devices_combined", + "complete_source_file": "/srv/code-behind-layout/runtime/collection_preparation/c01_rule_collection_20261019T020138863578Z/reverse_devices_combined.py", + "candidate_patch": "--- a/textbook_sharing/layout.py\n+++ b/textbook_sharing/layout.py\n@@ -26,7 +26,7 @@\n if d.kind in (\"nfet\", \"pfet\"):\n sz = sizing[d.name]\n out.append(DeviceSpec(d.name, d.kind, d.nets[0], d.nets[1], d.nets[2], d.nets[3], float(sz[\"w\"]), float(sz[\"l\"]), int(sz.get(\"nf\", 1))))\n- return out\n+ return list(reversed(out))\n \n \n def sharing_groups(devs: list[DeviceSpec]) -> list[list[DeviceSpec]]:\n@@ -84,7 +84,7 @@\n plan = SharingPlan.from_json(plans[str(gi)]); src = \"explicit\"\n else:\n nm = named_plans(pdk, g)\n- plan = nm.get(mode) or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n+ plan = nm.get(\"combined\") or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n res = build_mos_group(pdk, g, plan=plan, name=f\"grp{gi}\")\n rows[pol].append(from_group_result(res, f\"grp{gi}\", pol, g[0].b))\n applied.append({\"group\": gi, \"devices\": [d.logical_id for d in g], \"plan\": res.applied_plan, \"mode_requested\": mode, \"plan_source\": src,\n", + "draft_generation_wall_seconds": 0.005176834762096405, + "draft_generation_process_cpu_seconds": 0.005177741999999999 + }, + { + "rule_id": "reverse_ports_combined", + "complete_source_file": "/srv/code-behind-layout/runtime/collection_preparation/c01_rule_collection_20261019T020138863578Z/reverse_ports_combined.py", + "candidate_patch": "--- a/textbook_sharing/layout.py\n+++ b/textbook_sharing/layout.py\n@@ -84,7 +84,7 @@\n plan = SharingPlan.from_json(plans[str(gi)]); src = \"explicit\"\n else:\n nm = named_plans(pdk, g)\n- plan = nm.get(mode) or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n+ plan = nm.get(\"combined\") or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n res = build_mos_group(pdk, g, plan=plan, name=f\"grp{gi}\")\n rows[pol].append(from_group_result(res, f\"grp{gi}\", pol, g[0].b))\n applied.append({\"group\": gi, \"devices\": [d.logical_id for d in g], \"plan\": res.applied_plan, \"mode_requested\": mode, \"plan_source\": src,\n@@ -95,6 +95,6 @@\n if rows[\"p\"]: row_specs.append(RowSpec(rows[\"p\"], \"p\", True, rows[\"p\"][0].body_net))\n if rows[\"passive\"]: row_specs.append(RowSpec(rows[\"passive\"], \"passive\", True, None, taps=False))\n top = name or f\"{circuit.circuit_id}_{pdk.name}_{mode}\"\n- asm = assemble(pdk, row_specs, circuit.ports, name=top)\n+ asm = assemble(pdk, row_specs, list(reversed(circuit.ports)), name=top)\n return {\"component\": asm[\"component\"], \"name\": top, \"groups\": [[d.logical_id for d in g] for g in groups], \"applied_plans\": applied, \"evidence\": evidence,\n \"assembly_stats\": asm[\"stats\"], \"expected_fingers\": nf_total, \"trunks\": asm[\"trunks\"]}\n", + "draft_generation_wall_seconds": 0.005232163239270449, + "draft_generation_process_cpu_seconds": 0.005233387000000006 + } + ], + "proposed_collection_mode": "train_collection_rules", + "sampling": { + "backend": "frozen_rule_proposer", + "rule_ids": [ + "diffusion_plan", + "gate_plan", + "combined_plan", + "reverse_device_order", + "gate_order", + "reverse_port_track_order", + "reverse_devices_combined", + "reverse_ports_combined" + ], + "model": null, + "seed": null, + "model_inferences": 0, + "generation_timeout_seconds": 5 + }, + "physical": { + "workers": 2, + "cpus_per_job": 2, + "generation_timeout_seconds": 240, + "evaluator_timeout_seconds": 720 + }, + "new_physical_point_budget": 81, + "source_diversity": "Eight programs, one original initial AST and the same one public compiler lineage; no extra lineage from rule count.", + "label_scope": "Use new frozen-contract physical runs only, with one fresh nine-point baseline and every candidate at all nine points. Old development outcomes stay excluded.", + "student_context": "Teacher source/format is provenance. Student supervision must retain full source/contract/feedback while requesting the frozen unified-diff action format.", + "counting": "Report unique useful initial states, unique terminal ASTs, per-method matched examples, anchor versus family winners, opposite non-tie pair preferences, and ties separately.", + "no_inverse_fault_injection": true, + "formal_collection_started": false, + "old_outcomes_relabelled": false +} diff --git a/benchmarks/code_behind_layout/configs/development/c02_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c02_family/circuit_input.json new file mode 100644 index 00000000..3f057597 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c02_family/circuit_input.json @@ -0,0 +1,86 @@ +{ + "circuit_id": "C02", + "name": "cascode_current_mirror", + "ports": [ + "VSS", + "IIN1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IIN1", + "IIN1", + "net6", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "net6", + "net6", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "IOUT1", + "IIN1", + "net12", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "nfet", + "nets": [ + "net12", + "net6", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 672, + "files": [ + "Dataset/672/672.cir", + "Dataset/672/Port672.txt", + "Dataset/672/Pagenumber672.txt", + "Dataset/672/Book672.png", + "Dataset/672/Cadence672.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "129", + "device_name_map": { + "M1": "M3", + "M2": "M2", + "M3": "M1", + "M4": "M0" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/672/Book672.png", + "observation": "Johns p.129 scan: Q1/Q2 bottom pair, Q3/Q4 cascode pair, Q3 and Q1 diode-connected, Iin source on top; cascode mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c02_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c02_family/configurations.json new file mode 100644 index 00000000..831c7447 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c02_family/configurations.json @@ -0,0 +1,280 @@ +{ + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_ONLY", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C02", + "circuit_input_file": "configs/development/c02_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "M3": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "M4": { + "w": 4.0, + "l": 0.6, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c02_family/references/anchor.spice", + "contract_file": "configs/development/c02_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M2": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M3": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M4": { + "w": 2.0, + "l": 0.6, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c02_family/references/dev_nf_half.spice", + "contract_file": "configs/development/c02_family/contracts/dev_nf_half.json" + }, + { + "configuration_id": "dev_nf_3quarters", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.6, + "nf": 6 + }, + "M2": { + "w": 3.0, + "l": 0.6, + "nf": 6 + }, + "M3": { + "w": 3.0, + "l": 0.6, + "nf": 6 + }, + "M4": { + "w": 3.0, + "l": 0.6, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c02_family/references/dev_nf_3quarters.spice", + "contract_file": "configs/development/c02_family/contracts/dev_nf_3quarters.json" + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.6, + "nf": 12 + }, + "M2": { + "w": 6.0, + "l": 0.6, + "nf": 12 + }, + "M3": { + "w": 6.0, + "l": 0.6, + "nf": 12 + }, + "M4": { + "w": 6.0, + "l": 0.6, + "nf": 12 + } + } + }, + "reference_file": "configs/development/c02_family/references/dev_nf_1half.spice", + "contract_file": "configs/development/c02_family/contracts/dev_nf_1half.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 8.0, + "l": 0.6, + "nf": 16 + }, + "M2": { + "w": 8.0, + "l": 0.6, + "nf": 16 + }, + "M3": { + "w": 8.0, + "l": 0.6, + "nf": 16 + }, + "M4": { + "w": 8.0, + "l": 0.6, + "nf": 16 + } + } + }, + "reference_file": "configs/development/c02_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c02_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len045", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.45, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.45, + "nf": 8 + }, + "M3": { + "w": 4.0, + "l": 0.45, + "nf": 8 + }, + "M4": { + "w": 4.0, + "l": 0.45, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c02_family/references/dev_len045.spice", + "contract_file": "configs/development/c02_family/contracts/dev_len045.json" + }, + { + "configuration_id": "dev_len090", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.9, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.9, + "nf": 8 + }, + "M3": { + "w": 4.0, + "l": 0.9, + "nf": 8 + }, + "M4": { + "w": 4.0, + "l": 0.9, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c02_family/references/dev_len090.spice", + "contract_file": "configs/development/c02_family/contracts/dev_len090.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.6, + "nf": 8 + }, + "M2": { + "w": 6.0, + "l": 0.6, + "nf": 8 + }, + "M3": { + "w": 6.0, + "l": 0.6, + "nf": 8 + }, + "M4": { + "w": 6.0, + "l": 0.6, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c02_family/references/dev_unit075.spice", + "contract_file": "configs/development/c02_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_unit100", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 8.0, + "l": 0.6, + "nf": 8 + }, + "M2": { + "w": 8.0, + "l": 0.6, + "nf": 8 + }, + "M3": { + "w": 8.0, + "l": 0.6, + "nf": 8 + }, + "M4": { + "w": 8.0, + "l": 0.6, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c02_family/references/dev_unit100.spice", + "contract_file": "configs/development/c02_family/contracts/dev_unit100.json" + } + ], + "ancestry": "Same cropped universal compiler source; no new source lineage. Geometry and per-finger references are fixed before any layout." +} diff --git a/benchmarks/code_behind_layout/configs/development/c02_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c02_family/contracts/anchor.json new file mode 100644 index 00000000..8b685178 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c02_family/contracts/anchor.json @@ -0,0 +1,87 @@ +{ + "task_id": "development_train_domain_c02", + "configuration_id": "anchor", + "reference_id": "c02_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c02_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.05, + "output_resistance_ohm_min": 300000, + "max_current_relative_error_1p3_to_1p7V": 0.05 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_V": 1.5, + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "output_transient_levels_V": [ + 1.475, + 1.525 + ], + "current_compliance_application_region_V": [ + 1.3, + 1.7 + ], + "load_definition": "Output voltage source sweeps the cascode compliance region; output-port current is measured. Bias is the two diode-connected reference devices in the immutable DUT, with a5uA external source from1.8V. No0.9V mirror clamp or voltage-gain claim.", + "power_definition": "Three-port DUT has no VDD pin. Report input-port and output-port dissipation, and external1.8V reference-source supply work separately." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c02_family/contracts/dev_len045.json b/benchmarks/code_behind_layout/configs/development/c02_family/contracts/dev_len045.json new file mode 100644 index 00000000..f413c94a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c02_family/contracts/dev_len045.json @@ -0,0 +1,87 @@ +{ + "task_id": "development_train_domain_c02", + "configuration_id": "dev_len045", + "reference_id": "c02_dev_len045_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c02_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.05, + "output_resistance_ohm_min": 300000, + "max_current_relative_error_1p3_to_1p7V": 0.05 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_V": 1.5, + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "output_transient_levels_V": [ + 1.475, + 1.525 + ], + "current_compliance_application_region_V": [ + 1.3, + 1.7 + ], + "load_definition": "Output voltage source sweeps the cascode compliance region; output-port current is measured. Bias is the two diode-connected reference devices in the immutable DUT, with a5uA external source from1.8V. No0.9V mirror clamp or voltage-gain claim.", + "power_definition": "Three-port DUT has no VDD pin. Report input-port and output-port dissipation, and external1.8V reference-source supply work separately." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c02_family/contracts/dev_len090.json b/benchmarks/code_behind_layout/configs/development/c02_family/contracts/dev_len090.json new file mode 100644 index 00000000..61c9101c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c02_family/contracts/dev_len090.json @@ -0,0 +1,87 @@ +{ + "task_id": "development_train_domain_c02", + "configuration_id": "dev_len090", + "reference_id": "c02_dev_len090_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c02_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.05, + "output_resistance_ohm_min": 300000, + "max_current_relative_error_1p3_to_1p7V": 0.05 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_V": 1.5, + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "output_transient_levels_V": [ + 1.475, + 1.525 + ], + "current_compliance_application_region_V": [ + 1.3, + 1.7 + ], + "load_definition": "Output voltage source sweeps the cascode compliance region; output-port current is measured. Bias is the two diode-connected reference devices in the immutable DUT, with a5uA external source from1.8V. No0.9V mirror clamp or voltage-gain claim.", + "power_definition": "Three-port DUT has no VDD pin. Report input-port and output-port dissipation, and external1.8V reference-source supply work separately." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c02_family/contracts/dev_nf_1half.json b/benchmarks/code_behind_layout/configs/development/c02_family/contracts/dev_nf_1half.json new file mode 100644 index 00000000..3c39e192 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c02_family/contracts/dev_nf_1half.json @@ -0,0 +1,87 @@ +{ + "task_id": "development_train_domain_c02", + "configuration_id": "dev_nf_1half", + "reference_id": "c02_dev_nf_1half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c02_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.05, + "output_resistance_ohm_min": 300000, + "max_current_relative_error_1p3_to_1p7V": 0.05 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_V": 1.5, + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "output_transient_levels_V": [ + 1.475, + 1.525 + ], + "current_compliance_application_region_V": [ + 1.3, + 1.7 + ], + "load_definition": "Output voltage source sweeps the cascode compliance region; output-port current is measured. Bias is the two diode-connected reference devices in the immutable DUT, with a5uA external source from1.8V. No0.9V mirror clamp or voltage-gain claim.", + "power_definition": "Three-port DUT has no VDD pin. Report input-port and output-port dissipation, and external1.8V reference-source supply work separately." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c02_family/contracts/dev_nf_3quarters.json b/benchmarks/code_behind_layout/configs/development/c02_family/contracts/dev_nf_3quarters.json new file mode 100644 index 00000000..7b524cb4 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c02_family/contracts/dev_nf_3quarters.json @@ -0,0 +1,87 @@ +{ + "task_id": "development_train_domain_c02", + "configuration_id": "dev_nf_3quarters", + "reference_id": "c02_dev_nf_3quarters_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c02_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.05, + "output_resistance_ohm_min": 300000, + "max_current_relative_error_1p3_to_1p7V": 0.05 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_V": 1.5, + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "output_transient_levels_V": [ + 1.475, + 1.525 + ], + "current_compliance_application_region_V": [ + 1.3, + 1.7 + ], + "load_definition": "Output voltage source sweeps the cascode compliance region; output-port current is measured. Bias is the two diode-connected reference devices in the immutable DUT, with a5uA external source from1.8V. No0.9V mirror clamp or voltage-gain claim.", + "power_definition": "Three-port DUT has no VDD pin. Report input-port and output-port dissipation, and external1.8V reference-source supply work separately." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c02_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c02_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..7443040c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c02_family/contracts/dev_nf_double.json @@ -0,0 +1,87 @@ +{ + "task_id": "development_train_domain_c02", + "configuration_id": "dev_nf_double", + "reference_id": "c02_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c02_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.05, + "output_resistance_ohm_min": 300000, + "max_current_relative_error_1p3_to_1p7V": 0.05 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_V": 1.5, + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "output_transient_levels_V": [ + 1.475, + 1.525 + ], + "current_compliance_application_region_V": [ + 1.3, + 1.7 + ], + "load_definition": "Output voltage source sweeps the cascode compliance region; output-port current is measured. Bias is the two diode-connected reference devices in the immutable DUT, with a5uA external source from1.8V. No0.9V mirror clamp or voltage-gain claim.", + "power_definition": "Three-port DUT has no VDD pin. Report input-port and output-port dissipation, and external1.8V reference-source supply work separately." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c02_family/contracts/dev_nf_half.json b/benchmarks/code_behind_layout/configs/development/c02_family/contracts/dev_nf_half.json new file mode 100644 index 00000000..e145581a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c02_family/contracts/dev_nf_half.json @@ -0,0 +1,87 @@ +{ + "task_id": "development_train_domain_c02", + "configuration_id": "dev_nf_half", + "reference_id": "c02_dev_nf_half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c02_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.05, + "output_resistance_ohm_min": 300000, + "max_current_relative_error_1p3_to_1p7V": 0.05 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_V": 1.5, + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "output_transient_levels_V": [ + 1.475, + 1.525 + ], + "current_compliance_application_region_V": [ + 1.3, + 1.7 + ], + "load_definition": "Output voltage source sweeps the cascode compliance region; output-port current is measured. Bias is the two diode-connected reference devices in the immutable DUT, with a5uA external source from1.8V. No0.9V mirror clamp or voltage-gain claim.", + "power_definition": "Three-port DUT has no VDD pin. Report input-port and output-port dissipation, and external1.8V reference-source supply work separately." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c02_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c02_family/contracts/dev_unit075.json new file mode 100644 index 00000000..6b1d012b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c02_family/contracts/dev_unit075.json @@ -0,0 +1,87 @@ +{ + "task_id": "development_train_domain_c02", + "configuration_id": "dev_unit075", + "reference_id": "c02_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c02_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.05, + "output_resistance_ohm_min": 300000, + "max_current_relative_error_1p3_to_1p7V": 0.05 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_V": 1.5, + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "output_transient_levels_V": [ + 1.475, + 1.525 + ], + "current_compliance_application_region_V": [ + 1.3, + 1.7 + ], + "load_definition": "Output voltage source sweeps the cascode compliance region; output-port current is measured. Bias is the two diode-connected reference devices in the immutable DUT, with a5uA external source from1.8V. No0.9V mirror clamp or voltage-gain claim.", + "power_definition": "Three-port DUT has no VDD pin. Report input-port and output-port dissipation, and external1.8V reference-source supply work separately." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c02_family/contracts/dev_unit100.json b/benchmarks/code_behind_layout/configs/development/c02_family/contracts/dev_unit100.json new file mode 100644 index 00000000..bab5a466 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c02_family/contracts/dev_unit100.json @@ -0,0 +1,87 @@ +{ + "task_id": "development_train_domain_c02", + "configuration_id": "dev_unit100", + "reference_id": "c02_dev_unit100_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c02_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.05, + "output_resistance_ohm_min": 300000, + "max_current_relative_error_1p3_to_1p7V": 0.05 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_V": 1.5, + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "output_transient_levels_V": [ + 1.475, + 1.525 + ], + "current_compliance_application_region_V": [ + 1.3, + 1.7 + ], + "load_definition": "Output voltage source sweeps the cascode compliance region; output-port current is measured. Bias is the two diode-connected reference devices in the immutable DUT, with a5uA external source from1.8V. No0.9V mirror clamp or voltage-gain claim.", + "power_definition": "Three-port DUT has no VDD pin. Report input-port and output-port dissipation, and external1.8V reference-source supply work separately." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c02_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c02_family/references/anchor.spice new file mode 100644 index 00000000..495a05fc --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c02_family/references/anchor.spice @@ -0,0 +1,34 @@ +.subckt corpus_c02 VSS IIN1 IOUT1 +XM1_f0 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f4 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f5 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f6 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f7 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f4 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f5 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f6 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f7 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f0 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f1 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f2 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f3 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f4 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f5 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f6 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f7 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f0 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f1 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f2 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f3 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f4 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f5 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f6 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f7 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends corpus_c02 diff --git a/benchmarks/code_behind_layout/configs/development/c02_family/references/dev_len045.spice b/benchmarks/code_behind_layout/configs/development/c02_family/references/dev_len045.spice new file mode 100644 index 00000000..8894dec6 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c02_family/references/dev_len045.spice @@ -0,0 +1,34 @@ +.subckt corpus_c02 VSS IIN1 IOUT1 +XM1_f0 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f1 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f2 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f3 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f4 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f5 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f6 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f7 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f0 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f1 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f2 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f3 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f4 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f5 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f6 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f7 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f0 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f1 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f2 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f3 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f4 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f5 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f6 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f7 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f0 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f1 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f2 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f3 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f4 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f5 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f6 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f7 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +.ends corpus_c02 diff --git a/benchmarks/code_behind_layout/configs/development/c02_family/references/dev_len090.spice b/benchmarks/code_behind_layout/configs/development/c02_family/references/dev_len090.spice new file mode 100644 index 00000000..e3b34155 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c02_family/references/dev_len090.spice @@ -0,0 +1,34 @@ +.subckt corpus_c02 VSS IIN1 IOUT1 +XM1_f0 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f1 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f2 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f3 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f4 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f5 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f6 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f7 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f0 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f1 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f2 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f3 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f4 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f5 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f6 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f7 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f0 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f1 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f2 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f3 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f4 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f5 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f6 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f7 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM4_f0 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM4_f1 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM4_f2 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM4_f3 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM4_f4 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM4_f5 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM4_f6 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM4_f7 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +.ends corpus_c02 diff --git a/benchmarks/code_behind_layout/configs/development/c02_family/references/dev_nf_1half.spice b/benchmarks/code_behind_layout/configs/development/c02_family/references/dev_nf_1half.spice new file mode 100644 index 00000000..af3dd2fd --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c02_family/references/dev_nf_1half.spice @@ -0,0 +1,50 @@ +.subckt corpus_c02 VSS IIN1 IOUT1 +XM1_f0 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f4 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f5 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f6 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f7 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f8 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f9 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f10 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f11 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f4 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f5 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f6 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f7 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f8 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f9 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f10 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f11 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f0 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f1 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f2 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f3 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f4 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f5 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f6 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f7 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f8 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f9 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f10 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f11 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f0 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f1 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f2 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f3 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f4 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f5 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f6 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f7 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f8 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f9 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f10 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f11 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends corpus_c02 diff --git a/benchmarks/code_behind_layout/configs/development/c02_family/references/dev_nf_3quarters.spice b/benchmarks/code_behind_layout/configs/development/c02_family/references/dev_nf_3quarters.spice new file mode 100644 index 00000000..63cc7674 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c02_family/references/dev_nf_3quarters.spice @@ -0,0 +1,26 @@ +.subckt corpus_c02 VSS IIN1 IOUT1 +XM1_f0 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f4 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f5 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f4 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f5 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f0 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f1 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f2 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f3 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f4 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f5 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f0 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f1 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f2 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f3 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f4 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f5 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends corpus_c02 diff --git a/benchmarks/code_behind_layout/configs/development/c02_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c02_family/references/dev_nf_double.spice new file mode 100644 index 00000000..116ac301 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c02_family/references/dev_nf_double.spice @@ -0,0 +1,66 @@ +.subckt corpus_c02 VSS IIN1 IOUT1 +XM1_f0 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f4 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f5 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f6 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f7 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f8 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f9 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f10 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f11 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f12 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f13 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f14 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f15 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f4 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f5 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f6 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f7 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f8 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f9 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f10 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f11 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f12 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f13 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f14 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f15 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f0 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f1 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f2 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f3 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f4 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f5 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f6 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f7 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f8 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f9 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f10 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f11 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f12 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f13 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f14 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f15 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f0 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f1 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f2 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f3 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f4 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f5 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f6 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f7 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f8 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f9 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f10 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f11 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f12 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f13 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f14 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f15 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends corpus_c02 diff --git a/benchmarks/code_behind_layout/configs/development/c02_family/references/dev_nf_half.spice b/benchmarks/code_behind_layout/configs/development/c02_family/references/dev_nf_half.spice new file mode 100644 index 00000000..7007c082 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c02_family/references/dev_nf_half.spice @@ -0,0 +1,18 @@ +.subckt corpus_c02 VSS IIN1 IOUT1 +XM1_f0 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f0 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f1 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f2 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f3 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f0 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f1 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f2 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f3 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends corpus_c02 diff --git a/benchmarks/code_behind_layout/configs/development/c02_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c02_family/references/dev_unit075.spice new file mode 100644 index 00000000..645c94a0 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c02_family/references/dev_unit075.spice @@ -0,0 +1,34 @@ +.subckt corpus_c02 VSS IIN1 IOUT1 +XM1_f0 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f1 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f2 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f3 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f4 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f5 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f6 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f7 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f0 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f1 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f2 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f3 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f4 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f5 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f6 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f7 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM3_f0 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM3_f1 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM3_f2 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM3_f3 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM3_f4 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM3_f5 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM3_f6 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM3_f7 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM4_f0 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM4_f1 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM4_f2 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM4_f3 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM4_f4 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM4_f5 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM4_f6 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM4_f7 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +.ends corpus_c02 diff --git a/benchmarks/code_behind_layout/configs/development/c02_family/references/dev_unit100.spice b/benchmarks/code_behind_layout/configs/development/c02_family/references/dev_unit100.spice new file mode 100644 index 00000000..bc152036 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c02_family/references/dev_unit100.spice @@ -0,0 +1,34 @@ +.subckt corpus_c02 VSS IIN1 IOUT1 +XM1_f0 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f1 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f2 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f3 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f4 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f5 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f6 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f7 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f0 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f1 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f2 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f3 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f4 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f5 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f6 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f7 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM3_f0 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM3_f1 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM3_f2 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM3_f3 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM3_f4 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM3_f5 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM3_f6 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM3_f7 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f0 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f1 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f2 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f3 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f4 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f5 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f6 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f7 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +.ends corpus_c02 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/circuit_input.json new file mode 100644 index 00000000..9d6b9882 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/circuit_input.json @@ -0,0 +1,76 @@ +{ + "circuit_id": "C03", + "name": "wilson_current_mirror", + "ports": [ + "VSS", + "IIN1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IIN1", + "Y", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "Y", + "Y", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "IOUT1", + "IIN1", + "Y", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 840, + "files": [ + "Dataset/840/840.cir", + "Dataset/840/Port840.txt", + "Dataset/840/Pagenumber840.txt", + "Dataset/840/Book840.png", + "Dataset/840/Cadence840.png" + ], + "book": "P. R. Gray, P. J. Hurst, S. H. Lewis, R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 5th ed., Wiley, 2009", + "book_key": "gray", + "page_ref": "272 (bipolar Wilson mirror; MOS form from Gray et al. Sec. 4.2.5 'Wilson current mirror', MOS subsection)", + "device_name_map": { + "M1": "Q0 (npn)", + "M2": "Q1 (npn)", + "M3": "Q2 (npn)" + }, + "source_verification_level": "topology_from_textbook_section;netlist_authored (AnalogGenie has no MOS Wilson entry: isomorphism search over 3350 netlists found only bipolar versions #606 and #840)", + "image_review": { + "file": "Dataset/840/Book840.png", + "observation": "Gray p.272 scan: bipolar Wilson mirror Q3 (input), Q1 (diode), Q2 (output, emitter on Q1 collector); MOS form authored with identical graph" + }, + "modifications": [ + "bipolar devices replaced by NMOS with the same connection graph (C->D, B->G, E->S, bulk to VSS)" + ], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/configurations.json new file mode 100644 index 00000000..0a115896 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/configurations.json @@ -0,0 +1,248 @@ +{ + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_ONLY", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C03", + "domain_id": "C03_cfg1", + "textbook_sizing_source": "presimulated size configuration cfg1 of the textbook benchmark", + "circuit_name": "wilson_current_mirror", + "bench_category": "mirror", + "circuit_input_file": "configs/development/c03_cfg1_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 1.2, + "nf": 12 + }, + "M2": { + "w": 6.0, + "l": 1.2, + "nf": 12 + }, + "M3": { + "w": 6.0, + "l": 1.2, + "nf": 12 + } + } + }, + "reference_file": "configs/development/c03_cfg1_family/references/anchor.spice", + "contract_file": "configs/development/c03_cfg1_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 1.2, + "nf": 6 + }, + "M2": { + "w": 3.0, + "l": 1.2, + "nf": 6 + }, + "M3": { + "w": 3.0, + "l": 1.2, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c03_cfg1_family/references/dev_nf_half.spice", + "contract_file": "configs/development/c03_cfg1_family/contracts/dev_nf_half.json" + }, + { + "configuration_id": "dev_nf_3quarters", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.5, + "l": 1.2, + "nf": 9 + }, + "M2": { + "w": 4.5, + "l": 1.2, + "nf": 9 + }, + "M3": { + "w": 4.5, + "l": 1.2, + "nf": 9 + } + } + }, + "reference_file": "configs/development/c03_cfg1_family/references/dev_nf_3quarters.spice", + "contract_file": "configs/development/c03_cfg1_family/contracts/dev_nf_3quarters.json" + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 9.0, + "l": 1.2, + "nf": 18 + }, + "M2": { + "w": 9.0, + "l": 1.2, + "nf": 18 + }, + "M3": { + "w": 9.0, + "l": 1.2, + "nf": 18 + } + } + }, + "reference_file": "configs/development/c03_cfg1_family/references/dev_nf_1half.spice", + "contract_file": "configs/development/c03_cfg1_family/contracts/dev_nf_1half.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 12.0, + "l": 1.2, + "nf": 24 + }, + "M2": { + "w": 12.0, + "l": 1.2, + "nf": 24 + }, + "M3": { + "w": 12.0, + "l": 1.2, + "nf": 24 + } + } + }, + "reference_file": "configs/development/c03_cfg1_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c03_cfg1_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.9, + "nf": 12 + }, + "M2": { + "w": 6.0, + "l": 0.9, + "nf": 12 + }, + "M3": { + "w": 6.0, + "l": 0.9, + "nf": 12 + } + } + }, + "reference_file": "configs/development/c03_cfg1_family/references/dev_len075.spice", + "contract_file": "configs/development/c03_cfg1_family/contracts/dev_len075.json" + }, + { + "configuration_id": "dev_len150", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 1.8, + "nf": 12 + }, + "M2": { + "w": 6.0, + "l": 1.8, + "nf": 12 + }, + "M3": { + "w": 6.0, + "l": 1.8, + "nf": 12 + } + } + }, + "reference_file": "configs/development/c03_cfg1_family/references/dev_len150.spice", + "contract_file": "configs/development/c03_cfg1_family/contracts/dev_len150.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 9.0, + "l": 1.2, + "nf": 12 + }, + "M2": { + "w": 9.0, + "l": 1.2, + "nf": 12 + }, + "M3": { + "w": 9.0, + "l": 1.2, + "nf": 12 + } + } + }, + "reference_file": "configs/development/c03_cfg1_family/references/dev_unit075.spice", + "contract_file": "configs/development/c03_cfg1_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_unit100", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 12.0, + "l": 1.2, + "nf": 12 + }, + "M2": { + "w": 12.0, + "l": 1.2, + "nf": 12 + }, + "M3": { + "w": 12.0, + "l": 1.2, + "nf": 12 + } + } + }, + "reference_file": "configs/development/c03_cfg1_family/references/dev_unit100.spice", + "contract_file": "configs/development/c03_cfg1_family/contracts/dev_unit100.json" + } + ], + "textbook_specification_floors": { + "err": { + "abs_max": 0.1 + }, + "vmin": { + "max": 1.1700000000000002 + } + }, + "declared_by": "scripts/prepare_textbook_train_domains.py", + "ancestry": "Same cropped universal compiler source; no new source lineage. Geometry and per-finger references are fixed before any layout." +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/anchor.json new file mode 100644 index 00000000..dfecef94 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/anchor.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg1", + "configuration_id": "anchor", + "reference_id": "c03_cfg1_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_len075.json b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_len075.json new file mode 100644 index 00000000..b2d74407 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_len075.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg1", + "configuration_id": "dev_len075", + "reference_id": "c03_cfg1_dev_len075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_len150.json b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_len150.json new file mode 100644 index 00000000..5012f6c7 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_len150.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg1", + "configuration_id": "dev_len150", + "reference_id": "c03_cfg1_dev_len150_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_nf_1half.json b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_nf_1half.json new file mode 100644 index 00000000..04235852 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_nf_1half.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg1", + "configuration_id": "dev_nf_1half", + "reference_id": "c03_cfg1_dev_nf_1half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_nf_3quarters.json b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_nf_3quarters.json new file mode 100644 index 00000000..5e8ea6f1 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_nf_3quarters.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg1", + "configuration_id": "dev_nf_3quarters", + "reference_id": "c03_cfg1_dev_nf_3quarters_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..17c7f676 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_nf_double.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg1", + "configuration_id": "dev_nf_double", + "reference_id": "c03_cfg1_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_nf_half.json b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_nf_half.json new file mode 100644 index 00000000..c24c4abd --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_nf_half.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg1", + "configuration_id": "dev_nf_half", + "reference_id": "c03_cfg1_dev_nf_half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_unit075.json new file mode 100644 index 00000000..d9883a48 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_unit075.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg1", + "configuration_id": "dev_unit075", + "reference_id": "c03_cfg1_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_unit100.json b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_unit100.json new file mode 100644 index 00000000..c3360f6b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/contracts/dev_unit100.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg1", + "configuration_id": "dev_unit100", + "reference_id": "c03_cfg1_dev_unit100_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/anchor.spice new file mode 100644 index 00000000..d10ae33d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/anchor.spice @@ -0,0 +1,38 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f6 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f7 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f8 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f9 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f10 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f11 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f6 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f7 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f8 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f9 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f10 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f11 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f6 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f7 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f8 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f9 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f10 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f11 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_len075.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_len075.spice new file mode 100644 index 00000000..f2cb3daf --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_len075.spice @@ -0,0 +1,38 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f6 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f7 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f8 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f9 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f10 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f11 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f6 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f7 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f8 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f9 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f10 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f11 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f6 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f7 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f8 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f9 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f10 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f11 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_len150.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_len150.spice new file mode 100644 index 00000000..0f243372 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_len150.spice @@ -0,0 +1,38 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f6 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f7 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f8 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f9 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f10 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f11 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f6 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f7 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f8 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f9 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f10 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f11 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f6 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f7 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f8 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f9 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f10 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f11 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_nf_1half.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_nf_1half.spice new file mode 100644 index 00000000..51db4475 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_nf_1half.spice @@ -0,0 +1,56 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f6 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f7 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f8 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f9 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f10 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f11 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f12 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f13 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f14 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f15 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f16 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f17 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f6 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f7 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f8 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f9 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f10 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f11 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f12 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f13 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f14 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f15 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f16 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f17 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f6 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f7 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f8 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f9 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f10 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f11 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f12 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f13 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f14 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f15 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f16 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f17 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_nf_3quarters.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_nf_3quarters.spice new file mode 100644 index 00000000..5c2ce9f5 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_nf_3quarters.spice @@ -0,0 +1,29 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f6 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f7 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f8 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f6 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f7 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f8 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f6 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f7 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f8 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_nf_double.spice new file mode 100644 index 00000000..748f9c0d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_nf_double.spice @@ -0,0 +1,74 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f6 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f7 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f8 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f9 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f10 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f11 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f12 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f13 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f14 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f15 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f16 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f17 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f18 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f19 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f20 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f21 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f22 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f23 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f6 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f7 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f8 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f9 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f10 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f11 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f12 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f13 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f14 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f15 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f16 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f17 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f18 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f19 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f20 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f21 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f22 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f23 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f6 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f7 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f8 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f9 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f10 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f11 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f12 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f13 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f14 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f15 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f16 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f17 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f18 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f19 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f20 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f21 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f22 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f23 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_nf_half.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_nf_half.spice new file mode 100644 index 00000000..6a6ab53b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_nf_half.spice @@ -0,0 +1,20 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_unit075.spice new file mode 100644 index 00000000..79cbb777 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_unit075.spice @@ -0,0 +1,38 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM1_f6 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM1_f7 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM1_f8 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM1_f9 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM1_f10 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM1_f11 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM2_f6 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM2_f7 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM2_f8 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM2_f9 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM2_f10 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM2_f11 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM3_f6 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM3_f7 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM3_f8 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM3_f9 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM3_f10 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM3_f11 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_unit100.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_unit100.spice new file mode 100644 index 00000000..e5687d4e --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg1_family/references/dev_unit100.spice @@ -0,0 +1,38 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f6 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f7 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f8 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f9 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f10 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f11 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f6 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f7 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f8 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f9 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f10 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f11 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f6 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f7 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f8 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f9 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f10 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f11 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/circuit_input.json new file mode 100644 index 00000000..9d6b9882 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/circuit_input.json @@ -0,0 +1,76 @@ +{ + "circuit_id": "C03", + "name": "wilson_current_mirror", + "ports": [ + "VSS", + "IIN1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IIN1", + "Y", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "Y", + "Y", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "IOUT1", + "IIN1", + "Y", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 840, + "files": [ + "Dataset/840/840.cir", + "Dataset/840/Port840.txt", + "Dataset/840/Pagenumber840.txt", + "Dataset/840/Book840.png", + "Dataset/840/Cadence840.png" + ], + "book": "P. R. Gray, P. J. Hurst, S. H. Lewis, R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 5th ed., Wiley, 2009", + "book_key": "gray", + "page_ref": "272 (bipolar Wilson mirror; MOS form from Gray et al. Sec. 4.2.5 'Wilson current mirror', MOS subsection)", + "device_name_map": { + "M1": "Q0 (npn)", + "M2": "Q1 (npn)", + "M3": "Q2 (npn)" + }, + "source_verification_level": "topology_from_textbook_section;netlist_authored (AnalogGenie has no MOS Wilson entry: isomorphism search over 3350 netlists found only bipolar versions #606 and #840)", + "image_review": { + "file": "Dataset/840/Book840.png", + "observation": "Gray p.272 scan: bipolar Wilson mirror Q3 (input), Q1 (diode), Q2 (output, emitter on Q1 collector); MOS form authored with identical graph" + }, + "modifications": [ + "bipolar devices replaced by NMOS with the same connection graph (C->D, B->G, E->S, bulk to VSS)" + ], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/configurations.json new file mode 100644 index 00000000..0168e803 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/configurations.json @@ -0,0 +1,248 @@ +{ + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_ONLY", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C03", + "domain_id": "C03_cfg2", + "textbook_sizing_source": "presimulated size configuration cfg2 of the textbook benchmark", + "circuit_name": "wilson_current_mirror", + "bench_category": "mirror", + "circuit_input_file": "configs/development/c03_cfg2_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 1.2, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 1.2, + "nf": 4 + }, + "M3": { + "w": 4.0, + "l": 1.2, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c03_cfg2_family/references/anchor.spice", + "contract_file": "configs/development/c03_cfg2_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 1.2, + "nf": 2 + }, + "M2": { + "w": 2.0, + "l": 1.2, + "nf": 2 + }, + "M3": { + "w": 2.0, + "l": 1.2, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c03_cfg2_family/references/dev_nf_half.spice", + "contract_file": "configs/development/c03_cfg2_family/contracts/dev_nf_half.json" + }, + { + "configuration_id": "dev_nf_3quarters", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 1.2, + "nf": 3 + }, + "M2": { + "w": 3.0, + "l": 1.2, + "nf": 3 + }, + "M3": { + "w": 3.0, + "l": 1.2, + "nf": 3 + } + } + }, + "reference_file": "configs/development/c03_cfg2_family/references/dev_nf_3quarters.spice", + "contract_file": "configs/development/c03_cfg2_family/contracts/dev_nf_3quarters.json" + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 1.2, + "nf": 6 + }, + "M2": { + "w": 6.0, + "l": 1.2, + "nf": 6 + }, + "M3": { + "w": 6.0, + "l": 1.2, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c03_cfg2_family/references/dev_nf_1half.spice", + "contract_file": "configs/development/c03_cfg2_family/contracts/dev_nf_1half.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 8.0, + "l": 1.2, + "nf": 8 + }, + "M2": { + "w": 8.0, + "l": 1.2, + "nf": 8 + }, + "M3": { + "w": 8.0, + "l": 1.2, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c03_cfg2_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c03_cfg2_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.9, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 0.9, + "nf": 4 + }, + "M3": { + "w": 4.0, + "l": 0.9, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c03_cfg2_family/references/dev_len075.spice", + "contract_file": "configs/development/c03_cfg2_family/contracts/dev_len075.json" + }, + { + "configuration_id": "dev_len150", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 1.8, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 1.8, + "nf": 4 + }, + "M3": { + "w": 4.0, + "l": 1.8, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c03_cfg2_family/references/dev_len150.spice", + "contract_file": "configs/development/c03_cfg2_family/contracts/dev_len150.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 1.2, + "nf": 4 + }, + "M2": { + "w": 3.0, + "l": 1.2, + "nf": 4 + }, + "M3": { + "w": 3.0, + "l": 1.2, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c03_cfg2_family/references/dev_unit075.spice", + "contract_file": "configs/development/c03_cfg2_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_len200", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 2.4, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 2.4, + "nf": 4 + }, + "M3": { + "w": 4.0, + "l": 2.4, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c03_cfg2_family/references/dev_len200.spice", + "contract_file": "configs/development/c03_cfg2_family/contracts/dev_len200.json" + } + ], + "textbook_specification_floors": { + "err": { + "abs_max": 0.1 + }, + "vmin": { + "max": 1.1700000000000002 + } + }, + "declared_by": "scripts/prepare_textbook_train_domains.py", + "ancestry": "Same cropped universal compiler source; no new source lineage. Geometry and per-finger references are fixed before any layout." +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/anchor.json new file mode 100644 index 00000000..2ec0aba9 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/anchor.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg2", + "configuration_id": "anchor", + "reference_id": "c03_cfg2_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_len075.json b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_len075.json new file mode 100644 index 00000000..4366c3b6 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_len075.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg2", + "configuration_id": "dev_len075", + "reference_id": "c03_cfg2_dev_len075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_len150.json b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_len150.json new file mode 100644 index 00000000..cf16787c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_len150.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg2", + "configuration_id": "dev_len150", + "reference_id": "c03_cfg2_dev_len150_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_len200.json b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_len200.json new file mode 100644 index 00000000..a47f222f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_len200.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg2", + "configuration_id": "dev_len200", + "reference_id": "c03_cfg2_dev_len200_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_nf_1half.json b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_nf_1half.json new file mode 100644 index 00000000..0c63c982 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_nf_1half.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg2", + "configuration_id": "dev_nf_1half", + "reference_id": "c03_cfg2_dev_nf_1half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_nf_3quarters.json b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_nf_3quarters.json new file mode 100644 index 00000000..d446a20d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_nf_3quarters.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg2", + "configuration_id": "dev_nf_3quarters", + "reference_id": "c03_cfg2_dev_nf_3quarters_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..13b12640 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_nf_double.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg2", + "configuration_id": "dev_nf_double", + "reference_id": "c03_cfg2_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_nf_half.json b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_nf_half.json new file mode 100644 index 00000000..b19f350e --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_nf_half.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg2", + "configuration_id": "dev_nf_half", + "reference_id": "c03_cfg2_dev_nf_half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_unit075.json new file mode 100644 index 00000000..464c7ec0 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/contracts/dev_unit075.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg2", + "configuration_id": "dev_unit075", + "reference_id": "c03_cfg2_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/anchor.spice new file mode 100644 index 00000000..3da81799 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/anchor.spice @@ -0,0 +1,14 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_len075.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_len075.spice new file mode 100644 index 00000000..8d98c9a9 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_len075.spice @@ -0,0 +1,14 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.9 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.9 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.9 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.9 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.9 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.9 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.9 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.9 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=0.9 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=0.9 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=0.9 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=0.9 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_len150.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_len150.spice new file mode 100644 index 00000000..def6bc54 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_len150.spice @@ -0,0 +1,14 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_len200.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_len200.spice new file mode 100644 index 00000000..9643c7bf --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_len200.spice @@ -0,0 +1,14 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=2.4 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=2.4 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=2.4 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=2.4 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=2.4 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=2.4 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=2.4 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=2.4 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=2.4 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=2.4 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=2.4 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=2.4 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_nf_1half.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_nf_1half.spice new file mode 100644 index 00000000..919f94e5 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_nf_1half.spice @@ -0,0 +1,20 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_nf_3quarters.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_nf_3quarters.spice new file mode 100644 index 00000000..b639f097 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_nf_3quarters.spice @@ -0,0 +1,11 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_nf_double.spice new file mode 100644 index 00000000..5cde664e --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_nf_double.spice @@ -0,0 +1,26 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f6 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f7 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f6 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f7 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f6 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f7 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_nf_half.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_nf_half.spice new file mode 100644 index 00000000..60b8b24b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_nf_half.spice @@ -0,0 +1,8 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_unit075.spice new file mode 100644 index 00000000..5316e9e0 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg2_family/references/dev_unit075.spice @@ -0,0 +1,14 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/circuit_input.json new file mode 100644 index 00000000..9d6b9882 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/circuit_input.json @@ -0,0 +1,76 @@ +{ + "circuit_id": "C03", + "name": "wilson_current_mirror", + "ports": [ + "VSS", + "IIN1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IIN1", + "Y", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "Y", + "Y", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "IOUT1", + "IIN1", + "Y", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 840, + "files": [ + "Dataset/840/840.cir", + "Dataset/840/Port840.txt", + "Dataset/840/Pagenumber840.txt", + "Dataset/840/Book840.png", + "Dataset/840/Cadence840.png" + ], + "book": "P. R. Gray, P. J. Hurst, S. H. Lewis, R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 5th ed., Wiley, 2009", + "book_key": "gray", + "page_ref": "272 (bipolar Wilson mirror; MOS form from Gray et al. Sec. 4.2.5 'Wilson current mirror', MOS subsection)", + "device_name_map": { + "M1": "Q0 (npn)", + "M2": "Q1 (npn)", + "M3": "Q2 (npn)" + }, + "source_verification_level": "topology_from_textbook_section;netlist_authored (AnalogGenie has no MOS Wilson entry: isomorphism search over 3350 netlists found only bipolar versions #606 and #840)", + "image_review": { + "file": "Dataset/840/Book840.png", + "observation": "Gray p.272 scan: bipolar Wilson mirror Q3 (input), Q1 (diode), Q2 (output, emitter on Q1 collector); MOS form authored with identical graph" + }, + "modifications": [ + "bipolar devices replaced by NMOS with the same connection graph (C->D, B->G, E->S, bulk to VSS)" + ], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/configurations.json new file mode 100644 index 00000000..fd59ec20 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/configurations.json @@ -0,0 +1,248 @@ +{ + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_ONLY", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C03", + "domain_id": "C03_cfg3", + "textbook_sizing_source": "presimulated size configuration cfg3 of the textbook benchmark", + "circuit_name": "wilson_current_mirror", + "bench_category": "mirror", + "circuit_input_file": "configs/development/c03_cfg3_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 1.8, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 1.8, + "nf": 8 + }, + "M3": { + "w": 4.0, + "l": 1.8, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c03_cfg3_family/references/anchor.spice", + "contract_file": "configs/development/c03_cfg3_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 1.8, + "nf": 4 + }, + "M2": { + "w": 2.0, + "l": 1.8, + "nf": 4 + }, + "M3": { + "w": 2.0, + "l": 1.8, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c03_cfg3_family/references/dev_nf_half.spice", + "contract_file": "configs/development/c03_cfg3_family/contracts/dev_nf_half.json" + }, + { + "configuration_id": "dev_nf_3quarters", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 1.8, + "nf": 6 + }, + "M2": { + "w": 3.0, + "l": 1.8, + "nf": 6 + }, + "M3": { + "w": 3.0, + "l": 1.8, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c03_cfg3_family/references/dev_nf_3quarters.spice", + "contract_file": "configs/development/c03_cfg3_family/contracts/dev_nf_3quarters.json" + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 1.8, + "nf": 12 + }, + "M2": { + "w": 6.0, + "l": 1.8, + "nf": 12 + }, + "M3": { + "w": 6.0, + "l": 1.8, + "nf": 12 + } + } + }, + "reference_file": "configs/development/c03_cfg3_family/references/dev_nf_1half.spice", + "contract_file": "configs/development/c03_cfg3_family/contracts/dev_nf_1half.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 8.0, + "l": 1.8, + "nf": 16 + }, + "M2": { + "w": 8.0, + "l": 1.8, + "nf": 16 + }, + "M3": { + "w": 8.0, + "l": 1.8, + "nf": 16 + } + } + }, + "reference_file": "configs/development/c03_cfg3_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c03_cfg3_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 1.35, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 1.35, + "nf": 8 + }, + "M3": { + "w": 4.0, + "l": 1.35, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c03_cfg3_family/references/dev_len075.spice", + "contract_file": "configs/development/c03_cfg3_family/contracts/dev_len075.json" + }, + { + "configuration_id": "dev_len150", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 2.7, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 2.7, + "nf": 8 + }, + "M3": { + "w": 4.0, + "l": 2.7, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c03_cfg3_family/references/dev_len150.spice", + "contract_file": "configs/development/c03_cfg3_family/contracts/dev_len150.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 1.8, + "nf": 8 + }, + "M2": { + "w": 6.0, + "l": 1.8, + "nf": 8 + }, + "M3": { + "w": 6.0, + "l": 1.8, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c03_cfg3_family/references/dev_unit075.spice", + "contract_file": "configs/development/c03_cfg3_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_unit100", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 8.0, + "l": 1.8, + "nf": 8 + }, + "M2": { + "w": 8.0, + "l": 1.8, + "nf": 8 + }, + "M3": { + "w": 8.0, + "l": 1.8, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c03_cfg3_family/references/dev_unit100.spice", + "contract_file": "configs/development/c03_cfg3_family/contracts/dev_unit100.json" + } + ], + "textbook_specification_floors": { + "err": { + "abs_max": 0.1 + }, + "vmin": { + "max": 1.1700000000000002 + } + }, + "declared_by": "scripts/prepare_textbook_train_domains.py", + "ancestry": "Same cropped universal compiler source; no new source lineage. Geometry and per-finger references are fixed before any layout." +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/anchor.json new file mode 100644 index 00000000..4f7dad4a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/anchor.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg3", + "configuration_id": "anchor", + "reference_id": "c03_cfg3_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_len075.json b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_len075.json new file mode 100644 index 00000000..1f33df90 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_len075.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg3", + "configuration_id": "dev_len075", + "reference_id": "c03_cfg3_dev_len075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_len150.json b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_len150.json new file mode 100644 index 00000000..be3e5c41 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_len150.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg3", + "configuration_id": "dev_len150", + "reference_id": "c03_cfg3_dev_len150_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_nf_1half.json b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_nf_1half.json new file mode 100644 index 00000000..16052c59 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_nf_1half.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg3", + "configuration_id": "dev_nf_1half", + "reference_id": "c03_cfg3_dev_nf_1half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_nf_3quarters.json b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_nf_3quarters.json new file mode 100644 index 00000000..177d96f6 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_nf_3quarters.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg3", + "configuration_id": "dev_nf_3quarters", + "reference_id": "c03_cfg3_dev_nf_3quarters_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..c3ee5871 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_nf_double.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg3", + "configuration_id": "dev_nf_double", + "reference_id": "c03_cfg3_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_nf_half.json b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_nf_half.json new file mode 100644 index 00000000..697e152a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_nf_half.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg3", + "configuration_id": "dev_nf_half", + "reference_id": "c03_cfg3_dev_nf_half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_unit075.json new file mode 100644 index 00000000..55091c30 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_unit075.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg3", + "configuration_id": "dev_unit075", + "reference_id": "c03_cfg3_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_unit100.json b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_unit100.json new file mode 100644 index 00000000..601eaedb --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/contracts/dev_unit100.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03_cfg3", + "configuration_id": "dev_unit100", + "reference_id": "c03_cfg3_dev_unit100_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/anchor.spice new file mode 100644 index 00000000..e7048e87 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/anchor.spice @@ -0,0 +1,26 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f6 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f7 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f6 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f7 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f6 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f7 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_len075.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_len075.spice new file mode 100644 index 00000000..4ff7ddc4 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_len075.spice @@ -0,0 +1,26 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.35 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.35 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.35 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.35 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.35 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.35 +XM1_f6 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.35 +XM1_f7 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.35 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.35 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.35 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.35 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.35 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.35 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.35 +XM2_f6 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.35 +XM2_f7 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.35 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.35 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.35 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.35 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.35 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.35 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.35 +XM3_f6 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.35 +XM3_f7 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.35 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_len150.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_len150.spice new file mode 100644 index 00000000..dc75730e --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_len150.spice @@ -0,0 +1,26 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=2.7 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=2.7 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=2.7 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=2.7 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=2.7 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=2.7 +XM1_f6 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=2.7 +XM1_f7 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=2.7 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=2.7 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=2.7 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=2.7 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=2.7 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=2.7 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=2.7 +XM2_f6 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=2.7 +XM2_f7 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=2.7 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=2.7 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=2.7 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=2.7 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=2.7 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=2.7 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=2.7 +XM3_f6 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=2.7 +XM3_f7 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=2.7 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_nf_1half.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_nf_1half.spice new file mode 100644 index 00000000..0f243372 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_nf_1half.spice @@ -0,0 +1,38 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f6 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f7 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f8 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f9 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f10 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f11 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f6 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f7 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f8 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f9 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f10 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f11 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f6 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f7 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f8 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f9 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f10 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f11 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_nf_3quarters.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_nf_3quarters.spice new file mode 100644 index 00000000..a073376c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_nf_3quarters.spice @@ -0,0 +1,20 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_nf_double.spice new file mode 100644 index 00000000..b199f59b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_nf_double.spice @@ -0,0 +1,50 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f6 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f7 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f8 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f9 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f10 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f11 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f12 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f13 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f14 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f15 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f6 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f7 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f8 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f9 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f10 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f11 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f12 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f13 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f14 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f15 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f6 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f7 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f8 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f9 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f10 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f11 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f12 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f13 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f14 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f15 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_nf_half.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_nf_half.spice new file mode 100644 index 00000000..63937b06 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_nf_half.spice @@ -0,0 +1,14 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_unit075.spice new file mode 100644 index 00000000..f775f840 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_unit075.spice @@ -0,0 +1,26 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.8 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.8 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.8 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.8 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.8 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.8 +XM1_f6 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.8 +XM1_f7 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.8 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.8 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.8 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.8 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.8 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.8 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.8 +XM2_f6 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.8 +XM2_f7 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.8 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.8 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.8 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.8 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.8 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.8 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.8 +XM3_f6 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.8 +XM3_f7 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.8 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_unit100.spice b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_unit100.spice new file mode 100644 index 00000000..0f887d21 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_cfg3_family/references/dev_unit100.spice @@ -0,0 +1,26 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM1_f6 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM1_f7 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM2_f6 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM2_f7 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM3_f6 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +XM3_f7 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.8 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c03_family/circuit_input.json new file mode 100644 index 00000000..9d6b9882 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_family/circuit_input.json @@ -0,0 +1,76 @@ +{ + "circuit_id": "C03", + "name": "wilson_current_mirror", + "ports": [ + "VSS", + "IIN1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IIN1", + "Y", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "Y", + "Y", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "IOUT1", + "IIN1", + "Y", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 840, + "files": [ + "Dataset/840/840.cir", + "Dataset/840/Port840.txt", + "Dataset/840/Pagenumber840.txt", + "Dataset/840/Book840.png", + "Dataset/840/Cadence840.png" + ], + "book": "P. R. Gray, P. J. Hurst, S. H. Lewis, R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 5th ed., Wiley, 2009", + "book_key": "gray", + "page_ref": "272 (bipolar Wilson mirror; MOS form from Gray et al. Sec. 4.2.5 'Wilson current mirror', MOS subsection)", + "device_name_map": { + "M1": "Q0 (npn)", + "M2": "Q1 (npn)", + "M3": "Q2 (npn)" + }, + "source_verification_level": "topology_from_textbook_section;netlist_authored (AnalogGenie has no MOS Wilson entry: isomorphism search over 3350 netlists found only bipolar versions #606 and #840)", + "image_review": { + "file": "Dataset/840/Book840.png", + "observation": "Gray p.272 scan: bipolar Wilson mirror Q3 (input), Q1 (diode), Q2 (output, emitter on Q1 collector); MOS form authored with identical graph" + }, + "modifications": [ + "bipolar devices replaced by NMOS with the same connection graph (C->D, B->G, E->S, bulk to VSS)" + ], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c03_family/configurations.json new file mode 100644 index 00000000..61f69823 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_family/configurations.json @@ -0,0 +1,246 @@ +{ + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_ONLY", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C03", + "circuit_name": "wilson_current_mirror", + "bench_category": "mirror", + "circuit_input_file": "configs/development/c03_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 1.2, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 1.2, + "nf": 8 + }, + "M3": { + "w": 4.0, + "l": 1.2, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c03_family/references/anchor.spice", + "contract_file": "configs/development/c03_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 1.2, + "nf": 4 + }, + "M2": { + "w": 2.0, + "l": 1.2, + "nf": 4 + }, + "M3": { + "w": 2.0, + "l": 1.2, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c03_family/references/dev_nf_half.spice", + "contract_file": "configs/development/c03_family/contracts/dev_nf_half.json" + }, + { + "configuration_id": "dev_nf_3quarters", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 1.2, + "nf": 6 + }, + "M2": { + "w": 3.0, + "l": 1.2, + "nf": 6 + }, + "M3": { + "w": 3.0, + "l": 1.2, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c03_family/references/dev_nf_3quarters.spice", + "contract_file": "configs/development/c03_family/contracts/dev_nf_3quarters.json" + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 1.2, + "nf": 12 + }, + "M2": { + "w": 6.0, + "l": 1.2, + "nf": 12 + }, + "M3": { + "w": 6.0, + "l": 1.2, + "nf": 12 + } + } + }, + "reference_file": "configs/development/c03_family/references/dev_nf_1half.spice", + "contract_file": "configs/development/c03_family/contracts/dev_nf_1half.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 8.0, + "l": 1.2, + "nf": 16 + }, + "M2": { + "w": 8.0, + "l": 1.2, + "nf": 16 + }, + "M3": { + "w": 8.0, + "l": 1.2, + "nf": 16 + } + } + }, + "reference_file": "configs/development/c03_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c03_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.9, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.9, + "nf": 8 + }, + "M3": { + "w": 4.0, + "l": 0.9, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c03_family/references/dev_len075.spice", + "contract_file": "configs/development/c03_family/contracts/dev_len075.json" + }, + { + "configuration_id": "dev_len150", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 1.8, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 1.8, + "nf": 8 + }, + "M3": { + "w": 4.0, + "l": 1.8, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c03_family/references/dev_len150.spice", + "contract_file": "configs/development/c03_family/contracts/dev_len150.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 1.2, + "nf": 8 + }, + "M2": { + "w": 6.0, + "l": 1.2, + "nf": 8 + }, + "M3": { + "w": 6.0, + "l": 1.2, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c03_family/references/dev_unit075.spice", + "contract_file": "configs/development/c03_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_unit100", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 8.0, + "l": 1.2, + "nf": 8 + }, + "M2": { + "w": 8.0, + "l": 1.2, + "nf": 8 + }, + "M3": { + "w": 8.0, + "l": 1.2, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c03_family/references/dev_unit100.spice", + "contract_file": "configs/development/c03_family/contracts/dev_unit100.json" + } + ], + "textbook_specification_floors": { + "err": { + "abs_max": 0.1 + }, + "vmin": { + "max": 1.1700000000000002 + } + }, + "declared_by": "scripts/prepare_textbook_train_domains.py", + "ancestry": "Same cropped universal compiler source; no new source lineage. Geometry and per-finger references are fixed before any layout." +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c03_family/contracts/anchor.json new file mode 100644 index 00000000..295e0225 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_family/contracts/anchor.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03", + "configuration_id": "anchor", + "reference_id": "c03_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_len075.json b/benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_len075.json new file mode 100644 index 00000000..08925f2a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_len075.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03", + "configuration_id": "dev_len075", + "reference_id": "c03_dev_len075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_len150.json b/benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_len150.json new file mode 100644 index 00000000..4b7c4471 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_len150.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03", + "configuration_id": "dev_len150", + "reference_id": "c03_dev_len150_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_nf_1half.json b/benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_nf_1half.json new file mode 100644 index 00000000..cc889960 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_nf_1half.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03", + "configuration_id": "dev_nf_1half", + "reference_id": "c03_dev_nf_1half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_nf_3quarters.json b/benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_nf_3quarters.json new file mode 100644 index 00000000..1bb6b608 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_nf_3quarters.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03", + "configuration_id": "dev_nf_3quarters", + "reference_id": "c03_dev_nf_3quarters_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..9633a64b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_nf_double.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03", + "configuration_id": "dev_nf_double", + "reference_id": "c03_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_nf_half.json b/benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_nf_half.json new file mode 100644 index 00000000..67b10994 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_nf_half.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03", + "configuration_id": "dev_nf_half", + "reference_id": "c03_dev_nf_half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_unit075.json new file mode 100644 index 00000000..55ba4f25 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_unit075.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03", + "configuration_id": "dev_unit075", + "reference_id": "c03_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_unit100.json b/benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_unit100.json new file mode 100644 index 00000000..509516e1 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_family/contracts/dev_unit100.json @@ -0,0 +1,100 @@ +{ + "task_id": "development_train_domain_c03", + "configuration_id": "dev_unit100", + "reference_id": "c03_dev_unit100_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c03_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.1, + "compliance_low_V_max": 1.17 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "extra_current_sources_A": {}, + "output_test_V": 1.17, + "tolerance": 0.1, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.1 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": "reference current 5e-06 A instead of the first-pass 2e-05 A: supply headroom of the input node at the slow corner (schematic control)" + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c03_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c03_family/references/anchor.spice new file mode 100644 index 00000000..1dc0539d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_family/references/anchor.spice @@ -0,0 +1,26 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f6 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f7 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f6 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f7 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f6 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f7 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_family/references/dev_len075.spice b/benchmarks/code_behind_layout/configs/development/c03_family/references/dev_len075.spice new file mode 100644 index 00000000..2600224a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_family/references/dev_len075.spice @@ -0,0 +1,26 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f6 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f7 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f6 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f7 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f6 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f7 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_family/references/dev_len150.spice b/benchmarks/code_behind_layout/configs/development/c03_family/references/dev_len150.spice new file mode 100644 index 00000000..e7048e87 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_family/references/dev_len150.spice @@ -0,0 +1,26 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f6 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM1_f7 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f6 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM2_f7 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f6 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +XM3_f7 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.8 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_family/references/dev_nf_1half.spice b/benchmarks/code_behind_layout/configs/development/c03_family/references/dev_nf_1half.spice new file mode 100644 index 00000000..d10ae33d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_family/references/dev_nf_1half.spice @@ -0,0 +1,38 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f6 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f7 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f8 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f9 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f10 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f11 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f6 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f7 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f8 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f9 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f10 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f11 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f6 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f7 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f8 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f9 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f10 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f11 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_family/references/dev_nf_3quarters.spice b/benchmarks/code_behind_layout/configs/development/c03_family/references/dev_nf_3quarters.spice new file mode 100644 index 00000000..6a6ab53b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_family/references/dev_nf_3quarters.spice @@ -0,0 +1,20 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c03_family/references/dev_nf_double.spice new file mode 100644 index 00000000..5000170b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_family/references/dev_nf_double.spice @@ -0,0 +1,50 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f6 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f7 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f8 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f9 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f10 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f11 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f12 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f13 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f14 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f15 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f6 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f7 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f8 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f9 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f10 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f11 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f12 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f13 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f14 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f15 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f6 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f7 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f8 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f9 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f10 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f11 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f12 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f13 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f14 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f15 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_family/references/dev_nf_half.spice b/benchmarks/code_behind_layout/configs/development/c03_family/references/dev_nf_half.spice new file mode 100644 index 00000000..be4357f9 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_family/references/dev_nf_half.spice @@ -0,0 +1,14 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c03_family/references/dev_unit075.spice new file mode 100644 index 00000000..538dc30f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_family/references/dev_unit075.spice @@ -0,0 +1,26 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM1_f6 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM1_f7 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM2_f6 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM2_f7 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM3_f6 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +XM3_f7 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=0.75 l=1.2 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c03_family/references/dev_unit100.spice b/benchmarks/code_behind_layout/configs/development/c03_family/references/dev_unit100.spice new file mode 100644 index 00000000..5cde664e --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c03_family/references/dev_unit100.spice @@ -0,0 +1,26 @@ +.subckt corpus_c03 VSS IIN1 IOUT1 +XM1_f0 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f1 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f2 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f3 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f4 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f5 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f6 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f7 IIN1 Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f0 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f1 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f2 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f3 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f4 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f5 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f6 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f7 Y Y VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f0 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f1 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f2 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f3 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f4 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f5 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f6 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f7 IOUT1 IIN1 Y VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +.ends corpus_c03 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/circuit_input.json new file mode 100644 index 00000000..7f72f2a0 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/circuit_input.json @@ -0,0 +1,64 @@ +{ + "circuit_id": "C04", + "name": "cs_amplifier_current_source_load", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VOUT1", + "VB1" + ], + "devices": [ + { + "name": "M1", + "kind": "pfet", + "nets": [ + "VOUT1", + "VB1", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 9, + "files": [ + "Dataset/9/9.cir", + "Dataset/9/Port9.txt", + "Dataset/9/Pagenumber9.txt", + "Dataset/9/Book9.png", + "Dataset/9/Cadence9.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "58", + "device_name_map": { + "M1": "M0", + "M2": "M1" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/9/Book9.png", + "observation": "Razavi p.58 scan: M1 NMOS input, M2 PMOS current-source load biased by Vb" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/configurations.json new file mode 100644 index 00000000..caf13a15 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/configurations.json @@ -0,0 +1,203 @@ +{ + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_ONLY", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C04", + "domain_id": "C04_cfg1", + "textbook_sizing_source": "presimulated size configuration cfg1 of the textbook benchmark", + "circuit_name": "cs_amplifier_current_source_load", + "bench_category": "single", + "circuit_input_file": "configs/development/c04_cfg1_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M2": { + "w": 3.0, + "l": 0.3, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c04_cfg1_family/references/anchor.spice", + "contract_file": "configs/development/c04_cfg1_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M2": { + "w": 1.5, + "l": 0.3, + "nf": 3 + } + } + }, + "reference_file": "configs/development/c04_cfg1_family/references/dev_nf_half.spice", + "contract_file": "configs/development/c04_cfg1_family/contracts/dev_nf_half.json" + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 9.0, + "l": 0.3, + "nf": 18 + }, + "M2": { + "w": 4.5, + "l": 0.3, + "nf": 9 + } + } + }, + "reference_file": "configs/development/c04_cfg1_family/references/dev_nf_1half.spice", + "contract_file": "configs/development/c04_cfg1_family/contracts/dev_nf_1half.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 12.0, + "l": 0.3, + "nf": 24 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 12 + } + } + }, + "reference_file": "configs/development/c04_cfg1_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c04_cfg1_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.225, + "nf": 12 + }, + "M2": { + "w": 3.0, + "l": 0.225, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c04_cfg1_family/references/dev_len075.spice", + "contract_file": "configs/development/c04_cfg1_family/contracts/dev_len075.json" + }, + { + "configuration_id": "dev_len150", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.45, + "nf": 12 + }, + "M2": { + "w": 3.0, + "l": 0.45, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c04_cfg1_family/references/dev_len150.spice", + "contract_file": "configs/development/c04_cfg1_family/contracts/dev_len150.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 9.0, + "l": 0.3, + "nf": 12 + }, + "M2": { + "w": 4.5, + "l": 0.3, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c04_cfg1_family/references/dev_unit075.spice", + "contract_file": "configs/development/c04_cfg1_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_unit100", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 12.0, + "l": 0.3, + "nf": 12 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c04_cfg1_family/references/dev_unit100.spice", + "contract_file": "configs/development/c04_cfg1_family/contracts/dev_unit100.json" + }, + { + "configuration_id": "dev_len200", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.6, + "nf": 12 + }, + "M2": { + "w": 3.0, + "l": 0.6, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c04_cfg1_family/references/dev_len200.spice", + "contract_file": "configs/development/c04_cfg1_family/contracts/dev_len200.json" + } + ], + "textbook_specification_floors": { + "gain_lf": { + "min": 20.0 + }, + "f3db": { + "min": 1000000.0 + } + }, + "declared_by": "scripts/prepare_textbook_train_domains.py", + "ancestry": "Same cropped universal compiler source; no new source lineage. Geometry and per-finger references are fixed before any layout." +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/anchor.json new file mode 100644 index 00000000..5056031b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/anchor.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg1", + "configuration_id": "anchor", + "reference_id": "c04_cfg1_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_len075.json b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_len075.json new file mode 100644 index 00000000..32a582d3 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_len075.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg1", + "configuration_id": "dev_len075", + "reference_id": "c04_cfg1_dev_len075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_len150.json b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_len150.json new file mode 100644 index 00000000..57e4b815 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_len150.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg1", + "configuration_id": "dev_len150", + "reference_id": "c04_cfg1_dev_len150_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_len200.json b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_len200.json new file mode 100644 index 00000000..40c92098 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_len200.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg1", + "configuration_id": "dev_len200", + "reference_id": "c04_cfg1_dev_len200_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_nf_1half.json b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_nf_1half.json new file mode 100644 index 00000000..1614e9a4 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_nf_1half.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg1", + "configuration_id": "dev_nf_1half", + "reference_id": "c04_cfg1_dev_nf_1half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..1b25a75b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_nf_double.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg1", + "configuration_id": "dev_nf_double", + "reference_id": "c04_cfg1_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_nf_half.json b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_nf_half.json new file mode 100644 index 00000000..5e0fc2ff --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_nf_half.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg1", + "configuration_id": "dev_nf_half", + "reference_id": "c04_cfg1_dev_nf_half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_unit075.json new file mode 100644 index 00000000..4b92fc54 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_unit075.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg1", + "configuration_id": "dev_unit075", + "reference_id": "c04_cfg1_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_unit100.json b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_unit100.json new file mode 100644 index 00000000..ba4dd0fc --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/contracts/dev_unit100.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg1", + "configuration_id": "dev_unit100", + "reference_id": "c04_cfg1_dev_unit100_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/anchor.spice new file mode 100644 index 00000000..70d5542c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/anchor.spice @@ -0,0 +1,20 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f8 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f9 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f10 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f11 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_len075.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_len075.spice new file mode 100644 index 00000000..551ae023 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_len075.spice @@ -0,0 +1,20 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f8 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f9 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f10 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f11 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM2_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM2_f4 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM2_f5 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_len150.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_len150.spice new file mode 100644 index 00000000..62bd1353 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_len150.spice @@ -0,0 +1,20 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f8 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f9 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f10 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f11 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f4 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f5 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_len200.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_len200.spice new file mode 100644 index 00000000..3a1d541f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_len200.spice @@ -0,0 +1,20 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM1_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM1_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM1_f8 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM1_f9 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM1_f10 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM1_f11 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f4 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f5 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_nf_1half.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_nf_1half.spice new file mode 100644 index 00000000..fc275f9a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_nf_1half.spice @@ -0,0 +1,29 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f8 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f9 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f10 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f11 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f12 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f13 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f14 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f15 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f16 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f17 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f8 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_nf_double.spice new file mode 100644 index 00000000..6ee97a86 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_nf_double.spice @@ -0,0 +1,38 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f8 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f9 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f10 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f11 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f12 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f13 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f14 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f15 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f16 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f17 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f18 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f19 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f20 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f21 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f22 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f23 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f8 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f9 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f10 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f11 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_nf_half.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_nf_half.spice new file mode 100644 index 00000000..52a205f8 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_nf_half.spice @@ -0,0 +1,11 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_unit075.spice new file mode 100644 index 00000000..0a330e50 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_unit075.spice @@ -0,0 +1,20 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f8 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f9 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f10 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f11 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f4 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f5 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_unit100.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_unit100.spice new file mode 100644 index 00000000..0e4417f9 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg1_family/references/dev_unit100.spice @@ -0,0 +1,20 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f8 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f9 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f10 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f11 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f4 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f5 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/circuit_input.json new file mode 100644 index 00000000..7f72f2a0 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/circuit_input.json @@ -0,0 +1,64 @@ +{ + "circuit_id": "C04", + "name": "cs_amplifier_current_source_load", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VOUT1", + "VB1" + ], + "devices": [ + { + "name": "M1", + "kind": "pfet", + "nets": [ + "VOUT1", + "VB1", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 9, + "files": [ + "Dataset/9/9.cir", + "Dataset/9/Port9.txt", + "Dataset/9/Pagenumber9.txt", + "Dataset/9/Book9.png", + "Dataset/9/Cadence9.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "58", + "device_name_map": { + "M1": "M0", + "M2": "M1" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/9/Book9.png", + "observation": "Razavi p.58 scan: M1 NMOS input, M2 PMOS current-source load biased by Vb" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/configurations.json new file mode 100644 index 00000000..87e18667 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/configurations.json @@ -0,0 +1,203 @@ +{ + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_ONLY", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C04", + "domain_id": "C04_cfg2", + "textbook_sizing_source": "presimulated size configuration cfg2 of the textbook benchmark", + "circuit_name": "cs_amplifier_current_source_load", + "bench_category": "single", + "circuit_input_file": "configs/development/c04_cfg2_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 2.0, + "l": 0.3, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c04_cfg2_family/references/anchor.spice", + "contract_file": "configs/development/c04_cfg2_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.3, + "nf": 2 + }, + "M2": { + "w": 1.0, + "l": 0.3, + "nf": 1 + } + } + }, + "reference_file": "configs/development/c04_cfg2_family/references/dev_nf_half.spice", + "contract_file": "configs/development/c04_cfg2_family/contracts/dev_nf_half.json" + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.3, + "nf": 6 + }, + "M2": { + "w": 3.0, + "l": 0.3, + "nf": 3 + } + } + }, + "reference_file": "configs/development/c04_cfg2_family/references/dev_nf_1half.spice", + "contract_file": "configs/development/c04_cfg2_family/contracts/dev_nf_1half.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 8.0, + "l": 0.3, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.3, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c04_cfg2_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c04_cfg2_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.225, + "nf": 4 + }, + "M2": { + "w": 2.0, + "l": 0.225, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c04_cfg2_family/references/dev_len075.spice", + "contract_file": "configs/development/c04_cfg2_family/contracts/dev_len075.json" + }, + { + "configuration_id": "dev_len150", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.45, + "nf": 4 + }, + "M2": { + "w": 2.0, + "l": 0.45, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c04_cfg2_family/references/dev_len150.spice", + "contract_file": "configs/development/c04_cfg2_family/contracts/dev_len150.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 1.5, + "l": 0.3, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c04_cfg2_family/references/dev_unit075.spice", + "contract_file": "configs/development/c04_cfg2_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_len200", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.6, + "nf": 4 + }, + "M2": { + "w": 2.0, + "l": 0.6, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c04_cfg2_family/references/dev_len200.spice", + "contract_file": "configs/development/c04_cfg2_family/contracts/dev_len200.json" + }, + { + "configuration_id": "dev_nf_triple", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 12.0, + "l": 0.3, + "nf": 12 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c04_cfg2_family/references/dev_nf_triple.spice", + "contract_file": "configs/development/c04_cfg2_family/contracts/dev_nf_triple.json" + } + ], + "textbook_specification_floors": { + "gain_lf": { + "min": 20.0 + }, + "f3db": { + "min": 1000000.0 + } + }, + "declared_by": "scripts/prepare_textbook_train_domains.py", + "ancestry": "Same cropped universal compiler source; no new source lineage. Geometry and per-finger references are fixed before any layout." +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/anchor.json new file mode 100644 index 00000000..1f61c5b1 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/anchor.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg2", + "configuration_id": "anchor", + "reference_id": "c04_cfg2_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_len075.json b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_len075.json new file mode 100644 index 00000000..b8466b88 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_len075.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg2", + "configuration_id": "dev_len075", + "reference_id": "c04_cfg2_dev_len075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_len150.json b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_len150.json new file mode 100644 index 00000000..c21df013 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_len150.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg2", + "configuration_id": "dev_len150", + "reference_id": "c04_cfg2_dev_len150_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_len200.json b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_len200.json new file mode 100644 index 00000000..11d0780f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_len200.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg2", + "configuration_id": "dev_len200", + "reference_id": "c04_cfg2_dev_len200_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_nf_1half.json b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_nf_1half.json new file mode 100644 index 00000000..7b634a56 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_nf_1half.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg2", + "configuration_id": "dev_nf_1half", + "reference_id": "c04_cfg2_dev_nf_1half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..c5c528a8 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_nf_double.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg2", + "configuration_id": "dev_nf_double", + "reference_id": "c04_cfg2_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_nf_half.json b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_nf_half.json new file mode 100644 index 00000000..3426f637 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_nf_half.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg2", + "configuration_id": "dev_nf_half", + "reference_id": "c04_cfg2_dev_nf_half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_nf_triple.json b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_nf_triple.json new file mode 100644 index 00000000..17e10bfe --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_nf_triple.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg2", + "configuration_id": "dev_nf_triple", + "reference_id": "c04_cfg2_dev_nf_triple_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_unit075.json new file mode 100644 index 00000000..46831f5a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/contracts/dev_unit075.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg2", + "configuration_id": "dev_unit075", + "reference_id": "c04_cfg2_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/anchor.spice new file mode 100644 index 00000000..58714c48 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/anchor.spice @@ -0,0 +1,8 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_len075.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_len075.spice new file mode 100644 index 00000000..048d0747 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_len075.spice @@ -0,0 +1,8 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.225 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.225 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.225 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.225 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.225 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.225 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_len150.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_len150.spice new file mode 100644 index 00000000..d5a89e9a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_len150.spice @@ -0,0 +1,8 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_len200.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_len200.spice new file mode 100644 index 00000000..2793717a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_len200.spice @@ -0,0 +1,8 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.6 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.6 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.6 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.6 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_nf_1half.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_nf_1half.spice new file mode 100644 index 00000000..f2ef62a0 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_nf_1half.spice @@ -0,0 +1,11 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_nf_double.spice new file mode 100644 index 00000000..be1ca73c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_nf_double.spice @@ -0,0 +1,14 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_nf_half.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_nf_half.spice new file mode 100644 index 00000000..b20aa938 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_nf_half.spice @@ -0,0 +1,5 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_nf_triple.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_nf_triple.spice new file mode 100644 index 00000000..0e4417f9 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_nf_triple.spice @@ -0,0 +1,20 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f8 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f9 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f10 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f11 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f4 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f5 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_unit075.spice new file mode 100644 index 00000000..4f2c9c6b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg2_family/references/dev_unit075.spice @@ -0,0 +1,8 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/circuit_input.json new file mode 100644 index 00000000..7f72f2a0 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/circuit_input.json @@ -0,0 +1,64 @@ +{ + "circuit_id": "C04", + "name": "cs_amplifier_current_source_load", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VOUT1", + "VB1" + ], + "devices": [ + { + "name": "M1", + "kind": "pfet", + "nets": [ + "VOUT1", + "VB1", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 9, + "files": [ + "Dataset/9/9.cir", + "Dataset/9/Port9.txt", + "Dataset/9/Pagenumber9.txt", + "Dataset/9/Book9.png", + "Dataset/9/Cadence9.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "58", + "device_name_map": { + "M1": "M0", + "M2": "M1" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/9/Book9.png", + "observation": "Razavi p.58 scan: M1 NMOS input, M2 PMOS current-source load biased by Vb" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/configurations.json new file mode 100644 index 00000000..b83b57aa --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/configurations.json @@ -0,0 +1,203 @@ +{ + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_ONLY", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C04", + "domain_id": "C04_cfg3", + "textbook_sizing_source": "presimulated size configuration cfg3 of the textbook benchmark", + "circuit_name": "cs_amplifier_current_source_load", + "bench_category": "single", + "circuit_input_file": "configs/development/c04_cfg3_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.45, + "nf": 8 + }, + "M2": { + "w": 2.0, + "l": 0.45, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c04_cfg3_family/references/anchor.spice", + "contract_file": "configs/development/c04_cfg3_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.45, + "nf": 4 + }, + "M2": { + "w": 1.0, + "l": 0.45, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c04_cfg3_family/references/dev_nf_half.spice", + "contract_file": "configs/development/c04_cfg3_family/contracts/dev_nf_half.json" + }, + { + "configuration_id": "dev_nf_3quarters", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.45, + "nf": 6 + }, + "M2": { + "w": 1.5, + "l": 0.45, + "nf": 3 + } + } + }, + "reference_file": "configs/development/c04_cfg3_family/references/dev_nf_3quarters.spice", + "contract_file": "configs/development/c04_cfg3_family/contracts/dev_nf_3quarters.json" + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.45, + "nf": 12 + }, + "M2": { + "w": 3.0, + "l": 0.45, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c04_cfg3_family/references/dev_nf_1half.spice", + "contract_file": "configs/development/c04_cfg3_family/contracts/dev_nf_1half.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 8.0, + "l": 0.45, + "nf": 16 + }, + "M2": { + "w": 4.0, + "l": 0.45, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c04_cfg3_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c04_cfg3_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.338, + "nf": 8 + }, + "M2": { + "w": 2.0, + "l": 0.338, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c04_cfg3_family/references/dev_len075.spice", + "contract_file": "configs/development/c04_cfg3_family/contracts/dev_len075.json" + }, + { + "configuration_id": "dev_len150", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.675, + "nf": 8 + }, + "M2": { + "w": 2.0, + "l": 0.675, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c04_cfg3_family/references/dev_len150.spice", + "contract_file": "configs/development/c04_cfg3_family/contracts/dev_len150.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.45, + "nf": 8 + }, + "M2": { + "w": 3.0, + "l": 0.45, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c04_cfg3_family/references/dev_unit075.spice", + "contract_file": "configs/development/c04_cfg3_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_unit100", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 8.0, + "l": 0.45, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.45, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c04_cfg3_family/references/dev_unit100.spice", + "contract_file": "configs/development/c04_cfg3_family/contracts/dev_unit100.json" + } + ], + "textbook_specification_floors": { + "gain_lf": { + "min": 20.0 + }, + "f3db": { + "min": 1000000.0 + } + }, + "declared_by": "scripts/prepare_textbook_train_domains.py", + "ancestry": "Same cropped universal compiler source; no new source lineage. Geometry and per-finger references are fixed before any layout." +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/anchor.json new file mode 100644 index 00000000..0b16f9f4 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/anchor.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg3", + "configuration_id": "anchor", + "reference_id": "c04_cfg3_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_len075.json b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_len075.json new file mode 100644 index 00000000..3db14688 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_len075.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg3", + "configuration_id": "dev_len075", + "reference_id": "c04_cfg3_dev_len075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_len150.json b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_len150.json new file mode 100644 index 00000000..9532b891 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_len150.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg3", + "configuration_id": "dev_len150", + "reference_id": "c04_cfg3_dev_len150_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_nf_1half.json b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_nf_1half.json new file mode 100644 index 00000000..5566d79c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_nf_1half.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg3", + "configuration_id": "dev_nf_1half", + "reference_id": "c04_cfg3_dev_nf_1half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_nf_3quarters.json b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_nf_3quarters.json new file mode 100644 index 00000000..b4a31284 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_nf_3quarters.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg3", + "configuration_id": "dev_nf_3quarters", + "reference_id": "c04_cfg3_dev_nf_3quarters_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..86114c42 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_nf_double.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg3", + "configuration_id": "dev_nf_double", + "reference_id": "c04_cfg3_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_nf_half.json b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_nf_half.json new file mode 100644 index 00000000..39b99d38 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_nf_half.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg3", + "configuration_id": "dev_nf_half", + "reference_id": "c04_cfg3_dev_nf_half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_unit075.json new file mode 100644 index 00000000..ce3dfd3c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_unit075.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg3", + "configuration_id": "dev_unit075", + "reference_id": "c04_cfg3_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_unit100.json b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_unit100.json new file mode 100644 index 00000000..8ec815b9 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/contracts/dev_unit100.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04_cfg3", + "configuration_id": "dev_unit100", + "reference_id": "c04_cfg3_dev_unit100_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/anchor.spice new file mode 100644 index 00000000..3dc2ca65 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/anchor.spice @@ -0,0 +1,14 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_len075.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_len075.spice new file mode 100644 index 00000000..eccd3546 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_len075.spice @@ -0,0 +1,14 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM1_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM1_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM2_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_len150.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_len150.spice new file mode 100644 index 00000000..95d3c5f4 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_len150.spice @@ -0,0 +1,14 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM1_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM1_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM2_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_nf_1half.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_nf_1half.spice new file mode 100644 index 00000000..62bd1353 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_nf_1half.spice @@ -0,0 +1,20 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f8 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f9 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f10 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f11 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f4 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f5 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_nf_3quarters.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_nf_3quarters.spice new file mode 100644 index 00000000..bcf909f8 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_nf_3quarters.spice @@ -0,0 +1,11 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_nf_double.spice new file mode 100644 index 00000000..506908e4 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_nf_double.spice @@ -0,0 +1,26 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f8 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f9 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f10 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f11 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f12 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f13 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f14 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f15 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f4 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f5 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f6 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f7 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_nf_half.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_nf_half.spice new file mode 100644 index 00000000..3127e964 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_nf_half.spice @@ -0,0 +1,8 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_unit075.spice new file mode 100644 index 00000000..407d6ce1 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_unit075.spice @@ -0,0 +1,14 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM1_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM1_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM2_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_unit100.spice b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_unit100.spice new file mode 100644 index 00000000..534e0f6b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_cfg3_family/references/dev_unit100.spice @@ -0,0 +1,14 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM1_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM1_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM2_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c04_family/circuit_input.json new file mode 100644 index 00000000..7f72f2a0 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_family/circuit_input.json @@ -0,0 +1,64 @@ +{ + "circuit_id": "C04", + "name": "cs_amplifier_current_source_load", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VOUT1", + "VB1" + ], + "devices": [ + { + "name": "M1", + "kind": "pfet", + "nets": [ + "VOUT1", + "VB1", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 9, + "files": [ + "Dataset/9/9.cir", + "Dataset/9/Port9.txt", + "Dataset/9/Pagenumber9.txt", + "Dataset/9/Book9.png", + "Dataset/9/Cadence9.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "58", + "device_name_map": { + "M1": "M0", + "M2": "M1" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/9/Book9.png", + "observation": "Razavi p.58 scan: M1 NMOS input, M2 PMOS current-source load biased by Vb" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c04_family/configurations.json new file mode 100644 index 00000000..e4fe0995 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_family/configurations.json @@ -0,0 +1,201 @@ +{ + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_ONLY", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C04", + "circuit_name": "cs_amplifier_current_source_load", + "bench_category": "single", + "circuit_input_file": "configs/development/c04_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M2": { + "w": 2.0, + "l": 0.3, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c04_family/references/anchor.spice", + "contract_file": "configs/development/c04_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 1.0, + "l": 0.3, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c04_family/references/dev_nf_half.spice", + "contract_file": "configs/development/c04_family/contracts/dev_nf_half.json" + }, + { + "configuration_id": "dev_nf_3quarters", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M2": { + "w": 1.5, + "l": 0.3, + "nf": 3 + } + } + }, + "reference_file": "configs/development/c04_family/references/dev_nf_3quarters.spice", + "contract_file": "configs/development/c04_family/contracts/dev_nf_3quarters.json" + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M2": { + "w": 3.0, + "l": 0.3, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c04_family/references/dev_nf_1half.spice", + "contract_file": "configs/development/c04_family/contracts/dev_nf_1half.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 8.0, + "l": 0.3, + "nf": 16 + }, + "M2": { + "w": 4.0, + "l": 0.3, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c04_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c04_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.225, + "nf": 8 + }, + "M2": { + "w": 2.0, + "l": 0.225, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c04_family/references/dev_len075.spice", + "contract_file": "configs/development/c04_family/contracts/dev_len075.json" + }, + { + "configuration_id": "dev_len150", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.45, + "nf": 8 + }, + "M2": { + "w": 2.0, + "l": 0.45, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c04_family/references/dev_len150.spice", + "contract_file": "configs/development/c04_family/contracts/dev_len150.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.3, + "nf": 8 + }, + "M2": { + "w": 3.0, + "l": 0.3, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c04_family/references/dev_unit075.spice", + "contract_file": "configs/development/c04_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_unit100", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 8.0, + "l": 0.3, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.3, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c04_family/references/dev_unit100.spice", + "contract_file": "configs/development/c04_family/contracts/dev_unit100.json" + } + ], + "textbook_specification_floors": { + "gain_lf": { + "min": 20.0 + }, + "f3db": { + "min": 1000000.0 + } + }, + "declared_by": "scripts/prepare_textbook_train_domains.py", + "ancestry": "Same cropped universal compiler source; no new source lineage. Geometry and per-finger references are fixed before any layout." +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c04_family/contracts/anchor.json new file mode 100644 index 00000000..addfc7f4 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_family/contracts/anchor.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04", + "configuration_id": "anchor", + "reference_id": "c04_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_len075.json b/benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_len075.json new file mode 100644 index 00000000..7b2a04a1 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_len075.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04", + "configuration_id": "dev_len075", + "reference_id": "c04_dev_len075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_len150.json b/benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_len150.json new file mode 100644 index 00000000..8bc33cf5 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_len150.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04", + "configuration_id": "dev_len150", + "reference_id": "c04_dev_len150_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_nf_1half.json b/benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_nf_1half.json new file mode 100644 index 00000000..b4c3ae46 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_nf_1half.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04", + "configuration_id": "dev_nf_1half", + "reference_id": "c04_dev_nf_1half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_nf_3quarters.json b/benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_nf_3quarters.json new file mode 100644 index 00000000..76b81bb3 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_nf_3quarters.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04", + "configuration_id": "dev_nf_3quarters", + "reference_id": "c04_dev_nf_3quarters_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..e9bc5c41 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_nf_double.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04", + "configuration_id": "dev_nf_double", + "reference_id": "c04_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_nf_half.json b/benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_nf_half.json new file mode 100644 index 00000000..8118b3d0 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_nf_half.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04", + "configuration_id": "dev_nf_half", + "reference_id": "c04_dev_nf_half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_unit075.json new file mode 100644 index 00000000..7c476168 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_unit075.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04", + "configuration_id": "dev_unit075", + "reference_id": "c04_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_unit100.json b/benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_unit100.json new file mode 100644 index 00000000..fd766ac6 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_family/contracts/dev_unit100.json @@ -0,0 +1,93 @@ +{ + "task_id": "development_train_domain_c04", + "configuration_id": "dev_unit100", + "reference_id": "c04_dev_unit100_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c04_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 20.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M1", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M1", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c04_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c04_family/references/anchor.spice new file mode 100644 index 00000000..0ae42b53 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_family/references/anchor.spice @@ -0,0 +1,14 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_family/references/dev_len075.spice b/benchmarks/code_behind_layout/configs/development/c04_family/references/dev_len075.spice new file mode 100644 index 00000000..6efbe11c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_family/references/dev_len075.spice @@ -0,0 +1,14 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM2_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_family/references/dev_len150.spice b/benchmarks/code_behind_layout/configs/development/c04_family/references/dev_len150.spice new file mode 100644 index 00000000..3dc2ca65 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_family/references/dev_len150.spice @@ -0,0 +1,14 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_family/references/dev_nf_1half.spice b/benchmarks/code_behind_layout/configs/development/c04_family/references/dev_nf_1half.spice new file mode 100644 index 00000000..70d5542c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_family/references/dev_nf_1half.spice @@ -0,0 +1,20 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f8 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f9 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f10 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f11 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_family/references/dev_nf_3quarters.spice b/benchmarks/code_behind_layout/configs/development/c04_family/references/dev_nf_3quarters.spice new file mode 100644 index 00000000..52a205f8 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_family/references/dev_nf_3quarters.spice @@ -0,0 +1,11 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c04_family/references/dev_nf_double.spice new file mode 100644 index 00000000..060b2b68 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_family/references/dev_nf_double.spice @@ -0,0 +1,26 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f8 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f9 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f10 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f11 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f12 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f13 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f14 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f15 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_family/references/dev_nf_half.spice b/benchmarks/code_behind_layout/configs/development/c04_family/references/dev_nf_half.spice new file mode 100644 index 00000000..638f9847 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_family/references/dev_nf_half.spice @@ -0,0 +1,8 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c04_family/references/dev_unit075.spice new file mode 100644 index 00000000..680d87b8 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_family/references/dev_unit075.spice @@ -0,0 +1,14 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c04_family/references/dev_unit100.spice b/benchmarks/code_behind_layout/configs/development/c04_family/references/dev_unit100.spice new file mode 100644 index 00000000..be1ca73c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c04_family/references/dev_unit100.spice @@ -0,0 +1,14 @@ +.subckt corpus_c04 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +.ends corpus_c04 diff --git a/benchmarks/code_behind_layout/configs/development/c05_collection_preparation.json b/benchmarks/code_behind_layout/configs/development/c05_collection_preparation.json new file mode 100644 index 00000000..2203df87 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c05_collection_preparation.json @@ -0,0 +1,1650 @@ +{ + "status": "DRAFT_READONLY_COLLECTION_CAPSULE_NOT_FROZEN", + "circuit_id": "C05", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "source_pack": "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1/source_pack", + "source_files": [ + "LICENSE", + "circuit_input.json", + "generator.py", + "glayout/__init__.py", + "glayout/backend/__init__.py", + "glayout/backend/_gdsfactory.py", + "glayout/backend/_gdstk.py", + "glayout/pdk/__init__.py", + "glayout/pdk/gf180_mapped/__init__.py", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x02p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x04p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x08p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x16p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_05p00x05p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_10p00x10p00.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_05p00x00p42.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_05p00x05p00.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_10p00x00p42.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_10p00x10p00.gds", + "glayout/pdk/gf180_mapped/gf180_grules.py", + "glayout/pdk/gf180_mapped/gf180_mapped.py", + "glayout/pdk/gf180_mapped/gf180mcu.drc", + "glayout/pdk/gf180_mapped/gf180mcu_drc.lydrc", + "glayout/pdk/gf180_mapped/gf180mcu_drc_wrapper.drc", + "glayout/pdk/gf180_mapped/gf180mcu_osu_sc_9T.spice", + "glayout/pdk/ihp130_mapped/__init__.py", + "glayout/pdk/ihp130_mapped/ihp130_drc.lydrc", + "glayout/pdk/ihp130_mapped/ihp130_grules.py", + "glayout/pdk/ihp130_mapped/ihp130_mapped.py", + "glayout/pdk/mappedpdk.py", + "glayout/pdk/sky130_mapped/__init__.py", + "glayout/pdk/sky130_mapped/sky130.lydrc", + "glayout/pdk/sky130_mapped/sky130_add_npc.py", + "glayout/pdk/sky130_mapped/sky130_fd_sc_hd.spice", + "glayout/pdk/sky130_mapped/sky130_grules.py", + "glayout/pdk/sky130_mapped/sky130_mapped.py", + "glayout/placement/__init__.py", + "glayout/placement/common_centroid_ab_ba.py", + "glayout/placement/four_transistor_interdigitized.py", + "glayout/placement/two_transistor_interdigitized.py", + "glayout/placement/two_transistor_place.py", + "glayout/primitives/__init__.py", + "glayout/primitives/bjt.py", + "glayout/primitives/fet.py", + "glayout/primitives/guardring.py", + "glayout/primitives/mimcap.py", + "glayout/primitives/resistor.py", + "glayout/primitives/via_gen.py", + "glayout/routing/L_route.py", + "glayout/routing/__init__.py", + "glayout/routing/c_route.py", + "glayout/routing/smart_route.py", + "glayout/routing/straight_route.py", + "glayout/sharing/README.md", + "glayout/sharing/__init__.py", + "glayout/sharing/enumeration.py", + "glayout/sharing/evidence.py", + "glayout/sharing/group.py", + "glayout/sharing/rules.py", + "glayout/sharing/spec.py", + "glayout/spice/__init__.py", + "glayout/spice/netlist.py", + "glayout/util/__init__.py", + "glayout/util/comp_utils.py", + "glayout/util/component_array_create.py", + "glayout/util/geometry.py", + "glayout/util/pattern.py", + "glayout/util/port_utils.py", + "glayout/util/print_rules.py", + "glayout/util/routing.py", + "glayout/util/snap_to_grid.py", + "sizing_input.json", + "textbook_sharing/__init__.py", + "textbook_sharing/assembly/__init__.py", + "textbook_sharing/assembly/adapters.py", + "textbook_sharing/assembly/engine.py", + "textbook_sharing/assembly/passives.py", + "textbook_sharing/assembly/pincell.py", + "textbook_sharing/layout.py", + "textbook_sharing/netlist.py" + ], + "editable_paths": [ + "textbook_sharing/layout.py" + ], + "trusted_bundle": "/srv/code-behind-layout/runtime/collection_preparation/c05_collection_20261019T015456849898Z/trusted", + "trusted_files": [ + "contracts/anchor.json", + "contracts/dev_len045.json", + "contracts/dev_len060.json", + "contracts/dev_nf_1half.json", + "contracts/dev_nf_3quarters.json", + "contracts/dev_nf_double.json", + "contracts/dev_nf_half.json", + "contracts/dev_unit075.json", + "contracts/dev_unit100.json", + "evaluate.py", + "physical.py", + "references/anchor.spice", + "references/dev_len045.spice", + "references/dev_len060.spice", + "references/dev_nf_1half.spice", + "references/dev_nf_3quarters.spice", + "references/dev_nf_double.spice", + "references/dev_nf_half.spice", + "references/dev_unit075.spice", + "references/dev_unit100.spice", + "run_pex.sh", + "src/__init__.py", + "src/corpus_metrics.py", + "src/measurement.py", + "src/physical_drc.py", + "src/report_parsers.py", + "src/spice_validation.py" + ], + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "reference_id": "c05_anchor_independent_perfinger", + "contract": { + "task_id": "train_collection_c05", + "configuration_id": "anchor", + "reference_id": "c05_anchor_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_COLLECTION_AFTER_ACTUAL_NINE_POINT_QUALIFICATION", + "objective": { + "id": "c05_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_real", + "unit": "1", + "min": 0.6 + }, + { + "name": "f3db_Hz", + "unit": "Hz", + "min": 40000000.0 + }, + { + "name": "DUT_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 1.17, + "load_C_F": 1e-12, + "replica_current_A": 2e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.8, + "end": 1.4, + "points": 13, + "scale": "linear" + } + } + }, + "parameters": { + "configuration_id": "anchor", + "circuit": { + "circuit_id": "C05", + "name": "source_follower_mos_current_source", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VOUT1", + "VB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "VOUT1", + "VB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VDD", + "VIN1", + "VOUT1", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 20, + "files": [ + "Dataset/20/20.cir", + "Dataset/20/Port20.txt", + "Dataset/20/Pagenumber20.txt", + "Dataset/20/Book20.png", + "Dataset/20/Cadence20.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "72", + "device_name_map": { + "M1": "M0", + "M2": "M1" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/20/Book20.png", + "observation": "Razavi p.72 scan: M1 follower, M2 NMOS current source (Vb), RL load resistor drawn as an external load to ground" + }, + "modifications": [ + "source resistor R0 (VOUT1-VSS) is interpreted as the external load R_L and lives in the testbench, not in the DUT" + ], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 0.3, + "nf": 8 + } + }, + "top_cell": "corpus_c05" + } + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "reference_id": "c05_dev_nf_half_independent_perfinger", + "contract": { + "task_id": "train_collection_c05", + "configuration_id": "dev_nf_half", + "reference_id": "c05_dev_nf_half_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_COLLECTION_AFTER_ACTUAL_NINE_POINT_QUALIFICATION", + "objective": { + "id": "c05_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_real", + "unit": "1", + "min": 0.6 + }, + { + "name": "f3db_Hz", + "unit": "Hz", + "min": 40000000.0 + }, + { + "name": "DUT_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 1.17, + "load_C_F": 1e-12, + "replica_current_A": 2e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.8, + "end": 1.4, + "points": 13, + "scale": "linear" + } + } + }, + "parameters": { + "configuration_id": "dev_nf_half", + "circuit": { + "circuit_id": "C05", + "name": "source_follower_mos_current_source", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VOUT1", + "VB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "VOUT1", + "VB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VDD", + "VIN1", + "VOUT1", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 20, + "files": [ + "Dataset/20/20.cir", + "Dataset/20/Port20.txt", + "Dataset/20/Pagenumber20.txt", + "Dataset/20/Book20.png", + "Dataset/20/Cadence20.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "72", + "device_name_map": { + "M1": "M0", + "M2": "M1" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/20/Book20.png", + "observation": "Razavi p.72 scan: M1 follower, M2 NMOS current source (Vb), RL load resistor drawn as an external load to ground" + }, + "modifications": [ + "source resistor R0 (VOUT1-VSS) is interpreted as the external load R_L and lives in the testbench, not in the DUT" + ], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 1.0, + "l": 0.3, + "nf": 2 + }, + "M2": { + "w": 2.0, + "l": 0.3, + "nf": 4 + } + }, + "top_cell": "corpus_c05" + } + }, + { + "configuration_id": "dev_nf_3quarters", + "role": "development", + "reference_id": "c05_dev_nf_3quarters_independent_perfinger", + "contract": { + "task_id": "train_collection_c05", + "configuration_id": "dev_nf_3quarters", + "reference_id": "c05_dev_nf_3quarters_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_COLLECTION_AFTER_ACTUAL_NINE_POINT_QUALIFICATION", + "objective": { + "id": "c05_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_real", + "unit": "1", + "min": 0.6 + }, + { + "name": "f3db_Hz", + "unit": "Hz", + "min": 40000000.0 + }, + { + "name": "DUT_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 1.17, + "load_C_F": 1e-12, + "replica_current_A": 2e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.8, + "end": 1.4, + "points": 13, + "scale": "linear" + } + } + }, + "parameters": { + "configuration_id": "dev_nf_3quarters", + "circuit": { + "circuit_id": "C05", + "name": "source_follower_mos_current_source", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VOUT1", + "VB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "VOUT1", + "VB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VDD", + "VIN1", + "VOUT1", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 20, + "files": [ + "Dataset/20/20.cir", + "Dataset/20/Port20.txt", + "Dataset/20/Pagenumber20.txt", + "Dataset/20/Book20.png", + "Dataset/20/Cadence20.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "72", + "device_name_map": { + "M1": "M0", + "M2": "M1" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/20/Book20.png", + "observation": "Razavi p.72 scan: M1 follower, M2 NMOS current source (Vb), RL load resistor drawn as an external load to ground" + }, + "modifications": [ + "source resistor R0 (VOUT1-VSS) is interpreted as the external load R_L and lives in the testbench, not in the DUT" + ], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 1.5, + "l": 0.3, + "nf": 3 + }, + "M2": { + "w": 3.0, + "l": 0.3, + "nf": 6 + } + }, + "top_cell": "corpus_c05" + } + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "reference_id": "c05_dev_nf_1half_independent_perfinger", + "contract": { + "task_id": "train_collection_c05", + "configuration_id": "dev_nf_1half", + "reference_id": "c05_dev_nf_1half_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_COLLECTION_AFTER_ACTUAL_NINE_POINT_QUALIFICATION", + "objective": { + "id": "c05_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_real", + "unit": "1", + "min": 0.6 + }, + { + "name": "f3db_Hz", + "unit": "Hz", + "min": 40000000.0 + }, + { + "name": "DUT_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 1.17, + "load_C_F": 1e-12, + "replica_current_A": 2e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.8, + "end": 1.4, + "points": 13, + "scale": "linear" + } + } + }, + "parameters": { + "configuration_id": "dev_nf_1half", + "circuit": { + "circuit_id": "C05", + "name": "source_follower_mos_current_source", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VOUT1", + "VB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "VOUT1", + "VB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VDD", + "VIN1", + "VOUT1", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 20, + "files": [ + "Dataset/20/20.cir", + "Dataset/20/Port20.txt", + "Dataset/20/Pagenumber20.txt", + "Dataset/20/Book20.png", + "Dataset/20/Cadence20.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "72", + "device_name_map": { + "M1": "M0", + "M2": "M1" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/20/Book20.png", + "observation": "Razavi p.72 scan: M1 follower, M2 NMOS current source (Vb), RL load resistor drawn as an external load to ground" + }, + "modifications": [ + "source resistor R0 (VOUT1-VSS) is interpreted as the external load R_L and lives in the testbench, not in the DUT" + ], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 12 + } + }, + "top_cell": "corpus_c05" + } + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "reference_id": "c05_dev_nf_double_independent_perfinger", + "contract": { + "task_id": "train_collection_c05", + "configuration_id": "dev_nf_double", + "reference_id": "c05_dev_nf_double_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_COLLECTION_AFTER_ACTUAL_NINE_POINT_QUALIFICATION", + "objective": { + "id": "c05_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_real", + "unit": "1", + "min": 0.6 + }, + { + "name": "f3db_Hz", + "unit": "Hz", + "min": 40000000.0 + }, + { + "name": "DUT_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 1.17, + "load_C_F": 1e-12, + "replica_current_A": 2e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.8, + "end": 1.4, + "points": 13, + "scale": "linear" + } + } + }, + "parameters": { + "configuration_id": "dev_nf_double", + "circuit": { + "circuit_id": "C05", + "name": "source_follower_mos_current_source", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VOUT1", + "VB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "VOUT1", + "VB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VDD", + "VIN1", + "VOUT1", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 20, + "files": [ + "Dataset/20/20.cir", + "Dataset/20/Port20.txt", + "Dataset/20/Pagenumber20.txt", + "Dataset/20/Book20.png", + "Dataset/20/Cadence20.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "72", + "device_name_map": { + "M1": "M0", + "M2": "M1" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/20/Book20.png", + "observation": "Razavi p.72 scan: M1 follower, M2 NMOS current source (Vb), RL load resistor drawn as an external load to ground" + }, + "modifications": [ + "source resistor R0 (VOUT1-VSS) is interpreted as the external load R_L and lives in the testbench, not in the DUT" + ], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M2": { + "w": 8.0, + "l": 0.3, + "nf": 16 + } + }, + "top_cell": "corpus_c05" + } + }, + { + "configuration_id": "dev_len045", + "role": "development", + "reference_id": "c05_dev_len045_independent_perfinger", + "contract": { + "task_id": "train_collection_c05", + "configuration_id": "dev_len045", + "reference_id": "c05_dev_len045_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_COLLECTION_AFTER_ACTUAL_NINE_POINT_QUALIFICATION", + "objective": { + "id": "c05_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_real", + "unit": "1", + "min": 0.6 + }, + { + "name": "f3db_Hz", + "unit": "Hz", + "min": 40000000.0 + }, + { + "name": "DUT_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 1.17, + "load_C_F": 1e-12, + "replica_current_A": 2e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.8, + "end": 1.4, + "points": 13, + "scale": "linear" + } + } + }, + "parameters": { + "configuration_id": "dev_len045", + "circuit": { + "circuit_id": "C05", + "name": "source_follower_mos_current_source", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VOUT1", + "VB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "VOUT1", + "VB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VDD", + "VIN1", + "VOUT1", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 20, + "files": [ + "Dataset/20/20.cir", + "Dataset/20/Port20.txt", + "Dataset/20/Pagenumber20.txt", + "Dataset/20/Book20.png", + "Dataset/20/Cadence20.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "72", + "device_name_map": { + "M1": "M0", + "M2": "M1" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/20/Book20.png", + "observation": "Razavi p.72 scan: M1 follower, M2 NMOS current source (Vb), RL load resistor drawn as an external load to ground" + }, + "modifications": [ + "source resistor R0 (VOUT1-VSS) is interpreted as the external load R_L and lives in the testbench, not in the DUT" + ], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 2.0, + "l": 0.45, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 0.45, + "nf": 8 + } + }, + "top_cell": "corpus_c05" + } + }, + { + "configuration_id": "dev_len060", + "role": "development", + "reference_id": "c05_dev_len060_independent_perfinger", + "contract": { + "task_id": "train_collection_c05", + "configuration_id": "dev_len060", + "reference_id": "c05_dev_len060_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_COLLECTION_AFTER_ACTUAL_NINE_POINT_QUALIFICATION", + "objective": { + "id": "c05_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_real", + "unit": "1", + "min": 0.6 + }, + { + "name": "f3db_Hz", + "unit": "Hz", + "min": 40000000.0 + }, + { + "name": "DUT_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 1.17, + "load_C_F": 1e-12, + "replica_current_A": 2e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.8, + "end": 1.4, + "points": 13, + "scale": "linear" + } + } + }, + "parameters": { + "configuration_id": "dev_len060", + "circuit": { + "circuit_id": "C05", + "name": "source_follower_mos_current_source", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VOUT1", + "VB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "VOUT1", + "VB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VDD", + "VIN1", + "VOUT1", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 20, + "files": [ + "Dataset/20/20.cir", + "Dataset/20/Port20.txt", + "Dataset/20/Pagenumber20.txt", + "Dataset/20/Book20.png", + "Dataset/20/Cadence20.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "72", + "device_name_map": { + "M1": "M0", + "M2": "M1" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/20/Book20.png", + "observation": "Razavi p.72 scan: M1 follower, M2 NMOS current source (Vb), RL load resistor drawn as an external load to ground" + }, + "modifications": [ + "source resistor R0 (VOUT1-VSS) is interpreted as the external load R_L and lives in the testbench, not in the DUT" + ], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 0.6, + "nf": 8 + } + }, + "top_cell": "corpus_c05" + } + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "reference_id": "c05_dev_unit075_independent_perfinger", + "contract": { + "task_id": "train_collection_c05", + "configuration_id": "dev_unit075", + "reference_id": "c05_dev_unit075_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_COLLECTION_AFTER_ACTUAL_NINE_POINT_QUALIFICATION", + "objective": { + "id": "c05_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_real", + "unit": "1", + "min": 0.6 + }, + { + "name": "f3db_Hz", + "unit": "Hz", + "min": 40000000.0 + }, + { + "name": "DUT_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 1.17, + "load_C_F": 1e-12, + "replica_current_A": 2e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.8, + "end": 1.4, + "points": 13, + "scale": "linear" + } + } + }, + "parameters": { + "configuration_id": "dev_unit075", + "circuit": { + "circuit_id": "C05", + "name": "source_follower_mos_current_source", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VOUT1", + "VB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "VOUT1", + "VB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VDD", + "VIN1", + "VOUT1", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 20, + "files": [ + "Dataset/20/20.cir", + "Dataset/20/Port20.txt", + "Dataset/20/Pagenumber20.txt", + "Dataset/20/Book20.png", + "Dataset/20/Cadence20.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "72", + "device_name_map": { + "M1": "M0", + "M2": "M1" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/20/Book20.png", + "observation": "Razavi p.72 scan: M1 follower, M2 NMOS current source (Vb), RL load resistor drawn as an external load to ground" + }, + "modifications": [ + "source resistor R0 (VOUT1-VSS) is interpreted as the external load R_L and lives in the testbench, not in the DUT" + ], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 3.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 8 + } + }, + "top_cell": "corpus_c05" + } + }, + { + "configuration_id": "dev_unit100", + "role": "development", + "reference_id": "c05_dev_unit100_independent_perfinger", + "contract": { + "task_id": "train_collection_c05", + "configuration_id": "dev_unit100", + "reference_id": "c05_dev_unit100_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_COLLECTION_AFTER_ACTUAL_NINE_POINT_QUALIFICATION", + "objective": { + "id": "c05_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_real", + "unit": "1", + "min": 0.6 + }, + { + "name": "f3db_Hz", + "unit": "Hz", + "min": 40000000.0 + }, + { + "name": "DUT_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 1.17, + "load_C_F": 1e-12, + "replica_current_A": 2e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.8, + "end": 1.4, + "points": 13, + "scale": "linear" + } + } + }, + "parameters": { + "configuration_id": "dev_unit100", + "circuit": { + "circuit_id": "C05", + "name": "source_follower_mos_current_source", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VOUT1", + "VB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "VOUT1", + "VB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VDD", + "VIN1", + "VOUT1", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 20, + "files": [ + "Dataset/20/20.cir", + "Dataset/20/Port20.txt", + "Dataset/20/Pagenumber20.txt", + "Dataset/20/Book20.png", + "Dataset/20/Cadence20.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "72", + "device_name_map": { + "M1": "M0", + "M2": "M1" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/20/Book20.png", + "observation": "Razavi p.72 scan: M1 follower, M2 NMOS current source (Vb), RL load resistor drawn as an external load to ground" + }, + "modifications": [ + "source resistor R0 (VOUT1-VSS) is interpreted as the external load R_L and lives in the testbench, not in the DUT" + ], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 4.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 8.0, + "l": 0.3, + "nf": 8 + } + }, + "top_cell": "corpus_c05" + } + } + ], + "qualification_path": "/srv/code-behind-layout/results/derived/C05_C08_domain_development_qualification.json", + "prospective_hard_specifications": [ + { + "name": "gain_10Hz_real", + "unit": "1", + "min": 0.6 + }, + { + "name": "f3db_Hz", + "unit": "Hz", + "min": 40000000.0 + }, + { + "name": "DUT_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "objective": { + "id": "c05_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "label_rule_draft": { + "objectives": { + "c05_area_min": { + "metric": "area", + "unit": "um2", + "direction": "min", + "quality_absolute_tolerance": 1e-08, + "quality_relative_tolerance": 1e-06, + "quality_minimum_relative_effect": 0.01 + } + } + }, + "source_scope_note": "Actual generic C01-v1 source capsule is reused byte-for-byte; generator.py consumes the host configuration, not the unused frozen circuit_input.json. The sole editable layout.py is the same compiler lineage.", + "power_scope": "DUT supply only; external20uA/40uA diode-bias power recorded separately. Three process corners at1.8V/27C.", + "formal_collection_started": false, + "old_development_evidence_relabelled": false +} diff --git a/benchmarks/code_behind_layout/configs/development/c05_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c05_family/configurations.json new file mode 100644 index 00000000..7a9c8a06 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c05_family/configurations.json @@ -0,0 +1,189 @@ +{ + "scope": "development_only_train_domain_qualification_not_frozen", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C05", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 0.3, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c05_family/references/anchor.spice", + "contract_file": "configs/development/c05_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.0, + "l": 0.3, + "nf": 2 + }, + "M2": { + "w": 2.0, + "l": 0.3, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c05_family/references/dev_nf_half.spice", + "contract_file": "configs/development/c05_family/contracts/dev_nf_half.json" + }, + { + "configuration_id": "dev_nf_3quarters", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.5, + "l": 0.3, + "nf": 3 + }, + "M2": { + "w": 3.0, + "l": 0.3, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c05_family/references/dev_nf_3quarters.spice", + "contract_file": "configs/development/c05_family/contracts/dev_nf_3quarters.json" + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 12 + } + } + }, + "reference_file": "configs/development/c05_family/references/dev_nf_1half.spice", + "contract_file": "configs/development/c05_family/contracts/dev_nf_1half.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M2": { + "w": 8.0, + "l": 0.3, + "nf": 16 + } + } + }, + "reference_file": "configs/development/c05_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c05_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len045", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.45, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 0.45, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c05_family/references/dev_len045.spice", + "contract_file": "configs/development/c05_family/contracts/dev_len045.json" + }, + { + "configuration_id": "dev_len060", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 0.6, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c05_family/references/dev_len060.spice", + "contract_file": "configs/development/c05_family/contracts/dev_len060.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c05_family/references/dev_unit075.spice", + "contract_file": "configs/development/c05_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_unit100", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 8.0, + "l": 0.3, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c05_family/references/dev_unit100.spice", + "contract_file": "configs/development/c05_family/contracts/dev_unit100.json" + } + ], + "identity_note": "One universal compiler lineage; geometry points are not independent source programs. No old data are relabeled." +} diff --git a/benchmarks/code_behind_layout/configs/development/c05_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c05_family/contracts/anchor.json new file mode 100644 index 00000000..f0bd20f5 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c05_family/contracts/anchor.json @@ -0,0 +1,72 @@ +{ + "task_id": "development_train_domain_C05", + "configuration_id": "anchor", + "reference_id": "c05_anchor_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c05_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_real", + "unit": "1", + "min": 0.6 + } + ], + "pending_before_freeze": [ + "bandwidth_floor_Hz_from_actual_baseline_qualification", + "DUT_supply_power_ceiling_W_from_actual_baseline_qualification" + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 1.17, + "load_C_F": 1e-12, + "replica_current_A": 2e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.8, + "end": 1.4, + "points": 13, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_len045.json b/benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_len045.json new file mode 100644 index 00000000..cba72aa3 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_len045.json @@ -0,0 +1,72 @@ +{ + "task_id": "development_train_domain_C05", + "configuration_id": "dev_len045", + "reference_id": "c05_dev_len045_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c05_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_real", + "unit": "1", + "min": 0.6 + } + ], + "pending_before_freeze": [ + "bandwidth_floor_Hz_from_actual_baseline_qualification", + "DUT_supply_power_ceiling_W_from_actual_baseline_qualification" + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 1.17, + "load_C_F": 1e-12, + "replica_current_A": 2e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.8, + "end": 1.4, + "points": 13, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_len060.json b/benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_len060.json new file mode 100644 index 00000000..8de2ffd4 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_len060.json @@ -0,0 +1,72 @@ +{ + "task_id": "development_train_domain_C05", + "configuration_id": "dev_len060", + "reference_id": "c05_dev_len060_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c05_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_real", + "unit": "1", + "min": 0.6 + } + ], + "pending_before_freeze": [ + "bandwidth_floor_Hz_from_actual_baseline_qualification", + "DUT_supply_power_ceiling_W_from_actual_baseline_qualification" + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 1.17, + "load_C_F": 1e-12, + "replica_current_A": 2e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.8, + "end": 1.4, + "points": 13, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_nf_1half.json b/benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_nf_1half.json new file mode 100644 index 00000000..fda08db9 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_nf_1half.json @@ -0,0 +1,72 @@ +{ + "task_id": "development_train_domain_C05", + "configuration_id": "dev_nf_1half", + "reference_id": "c05_dev_nf_1half_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c05_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_real", + "unit": "1", + "min": 0.6 + } + ], + "pending_before_freeze": [ + "bandwidth_floor_Hz_from_actual_baseline_qualification", + "DUT_supply_power_ceiling_W_from_actual_baseline_qualification" + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 1.17, + "load_C_F": 1e-12, + "replica_current_A": 2e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.8, + "end": 1.4, + "points": 13, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_nf_3quarters.json b/benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_nf_3quarters.json new file mode 100644 index 00000000..a051e012 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_nf_3quarters.json @@ -0,0 +1,72 @@ +{ + "task_id": "development_train_domain_C05", + "configuration_id": "dev_nf_3quarters", + "reference_id": "c05_dev_nf_3quarters_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c05_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_real", + "unit": "1", + "min": 0.6 + } + ], + "pending_before_freeze": [ + "bandwidth_floor_Hz_from_actual_baseline_qualification", + "DUT_supply_power_ceiling_W_from_actual_baseline_qualification" + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 1.17, + "load_C_F": 1e-12, + "replica_current_A": 2e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.8, + "end": 1.4, + "points": 13, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..8324c32c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_nf_double.json @@ -0,0 +1,72 @@ +{ + "task_id": "development_train_domain_C05", + "configuration_id": "dev_nf_double", + "reference_id": "c05_dev_nf_double_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c05_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_real", + "unit": "1", + "min": 0.6 + } + ], + "pending_before_freeze": [ + "bandwidth_floor_Hz_from_actual_baseline_qualification", + "DUT_supply_power_ceiling_W_from_actual_baseline_qualification" + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 1.17, + "load_C_F": 1e-12, + "replica_current_A": 2e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.8, + "end": 1.4, + "points": 13, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_nf_half.json b/benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_nf_half.json new file mode 100644 index 00000000..065bbbdd --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_nf_half.json @@ -0,0 +1,72 @@ +{ + "task_id": "development_train_domain_C05", + "configuration_id": "dev_nf_half", + "reference_id": "c05_dev_nf_half_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c05_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_real", + "unit": "1", + "min": 0.6 + } + ], + "pending_before_freeze": [ + "bandwidth_floor_Hz_from_actual_baseline_qualification", + "DUT_supply_power_ceiling_W_from_actual_baseline_qualification" + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 1.17, + "load_C_F": 1e-12, + "replica_current_A": 2e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.8, + "end": 1.4, + "points": 13, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_unit075.json new file mode 100644 index 00000000..44e2b689 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_unit075.json @@ -0,0 +1,72 @@ +{ + "task_id": "development_train_domain_C05", + "configuration_id": "dev_unit075", + "reference_id": "c05_dev_unit075_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c05_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_real", + "unit": "1", + "min": 0.6 + } + ], + "pending_before_freeze": [ + "bandwidth_floor_Hz_from_actual_baseline_qualification", + "DUT_supply_power_ceiling_W_from_actual_baseline_qualification" + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 1.17, + "load_C_F": 1e-12, + "replica_current_A": 2e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.8, + "end": 1.4, + "points": 13, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_unit100.json b/benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_unit100.json new file mode 100644 index 00000000..f6f36864 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c05_family/contracts/dev_unit100.json @@ -0,0 +1,72 @@ +{ + "task_id": "development_train_domain_C05", + "configuration_id": "dev_unit100", + "reference_id": "c05_dev_unit100_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c05_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_real", + "unit": "1", + "min": 0.6 + } + ], + "pending_before_freeze": [ + "bandwidth_floor_Hz_from_actual_baseline_qualification", + "DUT_supply_power_ceiling_W_from_actual_baseline_qualification" + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 1.17, + "load_C_F": 1e-12, + "replica_current_A": 2e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.8, + "end": 1.4, + "points": 13, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c05_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c05_family/references/anchor.spice new file mode 100644 index 00000000..b392a6ae --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c05_family/references/anchor.spice @@ -0,0 +1,14 @@ +.subckt corpus_c05 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f6 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f7 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c05 diff --git a/benchmarks/code_behind_layout/configs/development/c05_family/references/dev_len045.spice b/benchmarks/code_behind_layout/configs/development/c05_family/references/dev_len045.spice new file mode 100644 index 00000000..690ccade --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c05_family/references/dev_len045.spice @@ -0,0 +1,14 @@ +.subckt corpus_c05 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f1 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f2 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f3 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f0 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f1 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f2 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f3 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f4 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f5 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f6 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f7 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +.ends corpus_c05 diff --git a/benchmarks/code_behind_layout/configs/development/c05_family/references/dev_len060.spice b/benchmarks/code_behind_layout/configs/development/c05_family/references/dev_len060.spice new file mode 100644 index 00000000..bda3fd24 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c05_family/references/dev_len060.spice @@ -0,0 +1,14 @@ +.subckt corpus_c05 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f4 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f5 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f6 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f7 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends corpus_c05 diff --git a/benchmarks/code_behind_layout/configs/development/c05_family/references/dev_nf_1half.spice b/benchmarks/code_behind_layout/configs/development/c05_family/references/dev_nf_1half.spice new file mode 100644 index 00000000..e3941463 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c05_family/references/dev_nf_1half.spice @@ -0,0 +1,20 @@ +.subckt corpus_c05 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f6 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f7 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f8 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f9 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f10 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f11 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c05 diff --git a/benchmarks/code_behind_layout/configs/development/c05_family/references/dev_nf_3quarters.spice b/benchmarks/code_behind_layout/configs/development/c05_family/references/dev_nf_3quarters.spice new file mode 100644 index 00000000..a9fafcce --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c05_family/references/dev_nf_3quarters.spice @@ -0,0 +1,11 @@ +.subckt corpus_c05 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c05 diff --git a/benchmarks/code_behind_layout/configs/development/c05_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c05_family/references/dev_nf_double.spice new file mode 100644 index 00000000..d96993fe --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c05_family/references/dev_nf_double.spice @@ -0,0 +1,26 @@ +.subckt corpus_c05 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f6 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f7 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f8 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f9 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f10 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f11 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f12 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f13 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f14 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f15 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c05 diff --git a/benchmarks/code_behind_layout/configs/development/c05_family/references/dev_nf_half.spice b/benchmarks/code_behind_layout/configs/development/c05_family/references/dev_nf_half.spice new file mode 100644 index 00000000..b35e49dd --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c05_family/references/dev_nf_half.spice @@ -0,0 +1,8 @@ +.subckt corpus_c05 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c05 diff --git a/benchmarks/code_behind_layout/configs/development/c05_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c05_family/references/dev_unit075.spice new file mode 100644 index 00000000..11e74215 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c05_family/references/dev_unit075.spice @@ -0,0 +1,14 @@ +.subckt corpus_c05 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f1 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f2 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f3 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f0 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f1 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f2 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f3 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f4 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f5 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f6 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f7 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +.ends corpus_c05 diff --git a/benchmarks/code_behind_layout/configs/development/c05_family/references/dev_unit100.spice b/benchmarks/code_behind_layout/configs/development/c05_family/references/dev_unit100.spice new file mode 100644 index 00000000..ffd5fd20 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c05_family/references/dev_unit100.spice @@ -0,0 +1,14 @@ +.subckt corpus_c05 VDD VSS VIN1 VOUT1 VB1 +XM1_f0 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f1 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f2 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f3 VOUT1 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f0 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f1 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f2 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f3 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f4 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f5 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f6 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f7 VDD VIN1 VOUT1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +.ends corpus_c05 diff --git a/benchmarks/code_behind_layout/configs/development/c05_minimal_gpt_teacher_preparation.json b/benchmarks/code_behind_layout/configs/development/c05_minimal_gpt_teacher_preparation.json new file mode 100644 index 00000000..1071d959 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c05_minimal_gpt_teacher_preparation.json @@ -0,0 +1,75 @@ +{ + "status": "DRAFT_NOT_FROZEN", + "role": "train_collection", + "collection_id": "c05_minimal_gpt_teacher_v1", + "base_collection_manifest": "/srv/code-behind-layout/runtime/train_collections/c05_collection_v1/collection.json", + "source_pack": "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1/source_pack", + "trusted_bundle": "/srv/code-behind-layout/runtime/train_collections/c05_collection_v1/trusted", + "registry_path": "/srv/code-behind-layout/runtime/train_collections/c05_collection_v1/registry.json", + "label_rule_path": "/srv/code-behind-layout/runtime/train_collections/c05_collection_v1/label_rule.json", + "initial_states_path": "/srv/code-behind-layout/runtime/collection_preparation/c05_minimal_gpt_teacher_v1_20261019T021012843074Z/initial_states.jsonl", + "initial_state_count": 3, + "editable_paths": [ + "textbook_sharing/layout.py" + ], + "gold_controls": {}, + "teacher_instruction_version": "minimal_source_edit_v1", + "student_preselection": { + "student_interface_version": "ordinary_policy_action_v1", + "max_new_tokens": 1024, + "max_context_tokens": 8192, + "stage": "before_physics" + }, + "sampling": { + "mode": "train_collection_source_gpt", + "backend": "isolated_gpt_cli", + "model": "gpt-6.1-sol", + "reasoning_effort": "high", + "trials": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8 + ], + "proposal_workers": 2, + "seed": null, + "seed_control_available": false, + "proposal_format": "full_source_teacher", + "max_new_tokens": 3072, + "max_context_tokens": 8192, + "timeout_seconds": 240 + }, + "physical": { + "workers": 2, + "cpus_per_job": 2, + "generation_timeout_seconds": 240, + "evaluator_timeout_seconds": 720 + }, + "budget": { + "proposals_per_initial_state": 8, + "configurations_per_candidate": 9, + "effective_example_pipeline_pilot_target": 1000, + "initial_batch_initial_states": 3 + }, + "deduplication": { + "method": "exact_ast_dump", + "include_attributes": false, + "numeric_normalization": false + }, + "prospective_change": "Preserve every unaffected line/comment/docstring/import/name/order. Reject oversized canonical ordinary actions before physics, retaining complete raw source and all generation costs. Never repair/shorten a proposal.", + "output_budget_scope": "3072 pinned student-tokenizer tokens for complete source JSON + EOS. Distinct student preselection is ordinary ACTION_JSON <=1024 and complete source/contract/action <=8192.", + "isolation": { + "fresh_ephemeral_session_per_trial": true, + "native_tools": false, + "no_sampling_seed_exposed": true, + "concurrent_slots_global": 2 + }, + "source_program_counting": "New teacher contexts do not create independent source programs or lineages. Count useful initial programs and unique terminal ASTs separately from pair counts.", + "new_baseline9_per_state_and_new_teacher_proposals_required": true, + "old_development_outcomes_admitted": false, + "formal_collection_launched": false +} diff --git a/benchmarks/code_behind_layout/configs/development/c05_observed_states_preparation.json b/benchmarks/code_behind_layout/configs/development/c05_observed_states_preparation.json new file mode 100644 index 00000000..5b0db3bb --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c05_observed_states_preparation.json @@ -0,0 +1,14 @@ +{ + "status": "DRAFT_NEW_INITIAL_STATES_NOT_FROZEN", + "circuit_id": "C05", + "capsule_preparation": "/srv/code-behind-layout/runtime/collection_preparation/c05_collection_20261019T015456849898Z/preparation.json", + "initial_states_path": "/srv/code-behind-layout/runtime/collection_preparation/c05_observed_states_20261019T015857271749Z/initial_states.jsonl", + "initial_state_count": 3, + "complete_editable_paths": [ + "textbook_sharing/layout.py" + ], + "old_evidence_labels_admitted": false, + "fresh_baselines_and_new_proposals_required": true, + "source_counting": "One universal compiler lineage. Identical source ASTs across topologies/teachers are the same program, even when task contexts differ.", + "inverse_injection_note": "Each intermediate is byte-exact actual T0 output, bound by its raw diff and real executed source; no artificial fault or hand-written repair supplied." +} diff --git a/benchmarks/code_behind_layout/configs/development/c05_rule_collection_preparation.json b/benchmarks/code_behind_layout/configs/development/c05_rule_collection_preparation.json new file mode 100644 index 00000000..72abdb81 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c05_rule_collection_preparation.json @@ -0,0 +1,118 @@ +{ + "status": "DRAFT_PROSPECTIVE_RULE_COLLECTION_NOT_FROZEN", + "role": "train_collection", + "circuit_id": "C05", + "collection_id": "c05_rules_v1", + "capsule_preparation": "/srv/code-behind-layout/runtime/collection_preparation/c05_collection_20261019T015456849898Z/preparation.json", + "source_pack": "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1/source_pack", + "trusted_bundle": "/srv/code-behind-layout/runtime/collection_preparation/c05_collection_20261019T015456849898Z/trusted", + "initial_states_path": "/srv/code-behind-layout/runtime/collection_preparation/c05_rule_collection_20261019T020138561581Z/initial_states.jsonl", + "initial_state_count": 1, + "editable_paths": [ + "textbook_sharing/layout.py" + ], + "parent_lineage": "textbook_universal_compiler_cropped", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "rule_proposer_path": "/srv/code-behind-layout/runtime/collection_preparation/c05_rule_collection_20261019T020138561581Z/rule_proposer.py", + "rule_ids": [ + "diffusion_plan", + "gate_plan", + "combined_plan", + "reverse_device_order", + "gate_order", + "reverse_port_track_order", + "reverse_devices_combined", + "reverse_ports_combined" + ], + "borrowed_from": "scripts/corpus_yield_pilot.py:variants; same eight development planning rules", + "candidates": [ + { + "rule_id": "diffusion_plan", + "complete_source_file": "/srv/code-behind-layout/runtime/collection_preparation/c05_rule_collection_20261019T020138561581Z/diffusion_plan.py", + "candidate_patch": "--- a/textbook_sharing/layout.py\n+++ b/textbook_sharing/layout.py\n@@ -84,7 +84,7 @@\n plan = SharingPlan.from_json(plans[str(gi)]); src = \"explicit\"\n else:\n nm = named_plans(pdk, g)\n- plan = nm.get(mode) or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n+ plan = nm.get(\"diffusion_only\") or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n res = build_mos_group(pdk, g, plan=plan, name=f\"grp{gi}\")\n rows[pol].append(from_group_result(res, f\"grp{gi}\", pol, g[0].b))\n applied.append({\"group\": gi, \"devices\": [d.logical_id for d in g], \"plan\": res.applied_plan, \"mode_requested\": mode, \"plan_source\": src,\n", + "draft_generation_wall_seconds": 0.009358872659504414, + "draft_generation_process_cpu_seconds": 0.009349593999999989 + }, + { + "rule_id": "gate_plan", + "complete_source_file": "/srv/code-behind-layout/runtime/collection_preparation/c05_rule_collection_20261019T020138561581Z/gate_plan.py", + "candidate_patch": "--- a/textbook_sharing/layout.py\n+++ b/textbook_sharing/layout.py\n@@ -84,7 +84,7 @@\n plan = SharingPlan.from_json(plans[str(gi)]); src = \"explicit\"\n else:\n nm = named_plans(pdk, g)\n- plan = nm.get(mode) or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n+ plan = nm.get(\"gate_only\") or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n res = build_mos_group(pdk, g, plan=plan, name=f\"grp{gi}\")\n rows[pol].append(from_group_result(res, f\"grp{gi}\", pol, g[0].b))\n applied.append({\"group\": gi, \"devices\": [d.logical_id for d in g], \"plan\": res.applied_plan, \"mode_requested\": mode, \"plan_source\": src,\n", + "draft_generation_wall_seconds": 0.006915218196809292, + "draft_generation_process_cpu_seconds": 0.006916275999999999 + }, + { + "rule_id": "combined_plan", + "complete_source_file": "/srv/code-behind-layout/runtime/collection_preparation/c05_rule_collection_20261019T020138561581Z/combined_plan.py", + "candidate_patch": "--- a/textbook_sharing/layout.py\n+++ b/textbook_sharing/layout.py\n@@ -84,7 +84,7 @@\n plan = SharingPlan.from_json(plans[str(gi)]); src = \"explicit\"\n else:\n nm = named_plans(pdk, g)\n- plan = nm.get(mode) or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n+ plan = nm.get(\"combined\") or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n res = build_mos_group(pdk, g, plan=plan, name=f\"grp{gi}\")\n rows[pol].append(from_group_result(res, f\"grp{gi}\", pol, g[0].b))\n applied.append({\"group\": gi, \"devices\": [d.logical_id for d in g], \"plan\": res.applied_plan, \"mode_requested\": mode, \"plan_source\": src,\n", + "draft_generation_wall_seconds": 0.005978642031550407, + "draft_generation_process_cpu_seconds": 0.005979662999999996 + }, + { + "rule_id": "reverse_device_order", + "complete_source_file": "/srv/code-behind-layout/runtime/collection_preparation/c05_rule_collection_20261019T020138561581Z/reverse_device_order.py", + "candidate_patch": "--- a/textbook_sharing/layout.py\n+++ b/textbook_sharing/layout.py\n@@ -26,7 +26,7 @@\n if d.kind in (\"nfet\", \"pfet\"):\n sz = sizing[d.name]\n out.append(DeviceSpec(d.name, d.kind, d.nets[0], d.nets[1], d.nets[2], d.nets[3], float(sz[\"w\"]), float(sz[\"l\"]), int(sz.get(\"nf\", 1))))\n- return out\n+ return list(reversed(out))\n \n \n def sharing_groups(devs: list[DeviceSpec]) -> list[list[DeviceSpec]]:\n", + "draft_generation_wall_seconds": 0.0063867708668112755, + "draft_generation_process_cpu_seconds": 0.006387592999999997 + }, + { + "rule_id": "gate_order", + "complete_source_file": "/srv/code-behind-layout/runtime/collection_preparation/c05_rule_collection_20261019T020138561581Z/gate_order.py", + "candidate_patch": "--- a/textbook_sharing/layout.py\n+++ b/textbook_sharing/layout.py\n@@ -26,7 +26,7 @@\n if d.kind in (\"nfet\", \"pfet\"):\n sz = sizing[d.name]\n out.append(DeviceSpec(d.name, d.kind, d.nets[0], d.nets[1], d.nets[2], d.nets[3], float(sz[\"w\"]), float(sz[\"l\"]), int(sz.get(\"nf\", 1))))\n- return out\n+ return sorted(out, key=lambda d: (d.g, d.d, d.logical_id))\n \n \n def sharing_groups(devs: list[DeviceSpec]) -> list[list[DeviceSpec]]:\n", + "draft_generation_wall_seconds": 0.006433086935430765, + "draft_generation_process_cpu_seconds": 0.006434009000000004 + }, + { + "rule_id": "reverse_port_track_order", + "complete_source_file": "/srv/code-behind-layout/runtime/collection_preparation/c05_rule_collection_20261019T020138561581Z/reverse_port_track_order.py", + "candidate_patch": "--- a/textbook_sharing/layout.py\n+++ b/textbook_sharing/layout.py\n@@ -95,6 +95,6 @@\n if rows[\"p\"]: row_specs.append(RowSpec(rows[\"p\"], \"p\", True, rows[\"p\"][0].body_net))\n if rows[\"passive\"]: row_specs.append(RowSpec(rows[\"passive\"], \"passive\", True, None, taps=False))\n top = name or f\"{circuit.circuit_id}_{pdk.name}_{mode}\"\n- asm = assemble(pdk, row_specs, circuit.ports, name=top)\n+ asm = assemble(pdk, row_specs, list(reversed(circuit.ports)), name=top)\n return {\"component\": asm[\"component\"], \"name\": top, \"groups\": [[d.logical_id for d in g] for g in groups], \"applied_plans\": applied, \"evidence\": evidence,\n \"assembly_stats\": asm[\"stats\"], \"expected_fingers\": nf_total, \"trunks\": asm[\"trunks\"]}\n", + "draft_generation_wall_seconds": 0.005433342885226011, + "draft_generation_process_cpu_seconds": 0.005434557999999992 + }, + { + "rule_id": "reverse_devices_combined", + "complete_source_file": "/srv/code-behind-layout/runtime/collection_preparation/c05_rule_collection_20261019T020138561581Z/reverse_devices_combined.py", + "candidate_patch": "--- a/textbook_sharing/layout.py\n+++ b/textbook_sharing/layout.py\n@@ -26,7 +26,7 @@\n if d.kind in (\"nfet\", \"pfet\"):\n sz = sizing[d.name]\n out.append(DeviceSpec(d.name, d.kind, d.nets[0], d.nets[1], d.nets[2], d.nets[3], float(sz[\"w\"]), float(sz[\"l\"]), int(sz.get(\"nf\", 1))))\n- return out\n+ return list(reversed(out))\n \n \n def sharing_groups(devs: list[DeviceSpec]) -> list[list[DeviceSpec]]:\n@@ -84,7 +84,7 @@\n plan = SharingPlan.from_json(plans[str(gi)]); src = \"explicit\"\n else:\n nm = named_plans(pdk, g)\n- plan = nm.get(mode) or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n+ plan = nm.get(\"combined\") or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n res = build_mos_group(pdk, g, plan=plan, name=f\"grp{gi}\")\n rows[pol].append(from_group_result(res, f\"grp{gi}\", pol, g[0].b))\n applied.append({\"group\": gi, \"devices\": [d.logical_id for d in g], \"plan\": res.applied_plan, \"mode_requested\": mode, \"plan_source\": src,\n", + "draft_generation_wall_seconds": 0.005064679775387049, + "draft_generation_process_cpu_seconds": 0.005065766999999999 + }, + { + "rule_id": "reverse_ports_combined", + "complete_source_file": "/srv/code-behind-layout/runtime/collection_preparation/c05_rule_collection_20261019T020138561581Z/reverse_ports_combined.py", + "candidate_patch": "--- a/textbook_sharing/layout.py\n+++ b/textbook_sharing/layout.py\n@@ -84,7 +84,7 @@\n plan = SharingPlan.from_json(plans[str(gi)]); src = \"explicit\"\n else:\n nm = named_plans(pdk, g)\n- plan = nm.get(mode) or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n+ plan = nm.get(\"combined\") or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n res = build_mos_group(pdk, g, plan=plan, name=f\"grp{gi}\")\n rows[pol].append(from_group_result(res, f\"grp{gi}\", pol, g[0].b))\n applied.append({\"group\": gi, \"devices\": [d.logical_id for d in g], \"plan\": res.applied_plan, \"mode_requested\": mode, \"plan_source\": src,\n@@ -95,6 +95,6 @@\n if rows[\"p\"]: row_specs.append(RowSpec(rows[\"p\"], \"p\", True, rows[\"p\"][0].body_net))\n if rows[\"passive\"]: row_specs.append(RowSpec(rows[\"passive\"], \"passive\", True, None, taps=False))\n top = name or f\"{circuit.circuit_id}_{pdk.name}_{mode}\"\n- asm = assemble(pdk, row_specs, circuit.ports, name=top)\n+ asm = assemble(pdk, row_specs, list(reversed(circuit.ports)), name=top)\n return {\"component\": asm[\"component\"], \"name\": top, \"groups\": [[d.logical_id for d in g] for g in groups], \"applied_plans\": applied, \"evidence\": evidence,\n \"assembly_stats\": asm[\"stats\"], \"expected_fingers\": nf_total, \"trunks\": asm[\"trunks\"]}\n", + "draft_generation_wall_seconds": 0.005146315786987543, + "draft_generation_process_cpu_seconds": 0.005147376999999981 + } + ], + "proposed_collection_mode": "train_collection_rules", + "sampling": { + "backend": "frozen_rule_proposer", + "rule_ids": [ + "diffusion_plan", + "gate_plan", + "combined_plan", + "reverse_device_order", + "gate_order", + "reverse_port_track_order", + "reverse_devices_combined", + "reverse_ports_combined" + ], + "model": null, + "seed": null, + "model_inferences": 0, + "generation_timeout_seconds": 5 + }, + "physical": { + "workers": 2, + "cpus_per_job": 2, + "generation_timeout_seconds": 240, + "evaluator_timeout_seconds": 720 + }, + "new_physical_point_budget": 81, + "source_diversity": "Eight programs, one original initial AST and the same one public compiler lineage; no extra lineage from rule count.", + "label_scope": "Use new frozen-contract physical runs only, with one fresh nine-point baseline and every candidate at all nine points. Old development outcomes stay excluded.", + "student_context": "Teacher source/format is provenance. Student supervision must retain full source/contract/feedback while requesting the frozen unified-diff action format.", + "counting": "Report unique useful initial states, unique terminal ASTs, per-method matched examples, anchor versus family winners, opposite non-tie pair preferences, and ties separately.", + "no_inverse_fault_injection": true, + "formal_collection_started": false, + "old_outcomes_relabelled": false +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/circuit_input.json new file mode 100644 index 00000000..97acc72b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/circuit_input.json @@ -0,0 +1,90 @@ +{ + "circuit_id": "C06", + "name": "cascode_amplifier_cascode_load", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VOUT1", + "VB1", + "VB2", + "VB3" + ], + "devices": [ + { + "name": "M1", + "kind": "pfet", + "nets": [ + "VOUT1", + "VB2", + "net10", + "VDD" + ], + "params": {} + }, + { + "name": "M2", + "kind": "pfet", + "nets": [ + "net10", + "VB3", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "net9", + "VIN1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "nfet", + "nets": [ + "VOUT1", + "VB1", + "net9", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 38, + "files": [ + "Dataset/38/38.cir", + "Dataset/38/Port38.txt", + "Dataset/38/Pagenumber38.txt", + "Dataset/38/Book38.png", + "Dataset/38/Cadence38.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "88", + "device_name_map": { + "M1": "M1", + "M2": "M0", + "M3": "M3", + "M4": "M2" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/38/Book38.png", + "observation": "Razavi p.88 scan: M1/M2 NMOS cascode, M3/M4 PMOS cascode current source (Vb1..Vb3)" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/configurations.json new file mode 100644 index 00000000..0c79ae66 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/configurations.json @@ -0,0 +1,293 @@ +{ + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_ONLY", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C06", + "domain_id": "C06_cfg1", + "textbook_sizing_source": "presimulated size configuration cfg1 of the textbook benchmark", + "circuit_name": "cascode_amplifier_cascode_load", + "bench_category": "single", + "circuit_input_file": "configs/development/c06_cfg1_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M3": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M4": { + "w": 3.0, + "l": 0.3, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c06_cfg1_family/references/anchor.spice", + "contract_file": "configs/development/c06_cfg1_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M2": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M3": { + "w": 1.5, + "l": 0.3, + "nf": 3 + }, + "M4": { + "w": 1.5, + "l": 0.3, + "nf": 3 + } + } + }, + "reference_file": "configs/development/c06_cfg1_family/references/dev_nf_half.spice", + "contract_file": "configs/development/c06_cfg1_family/contracts/dev_nf_half.json" + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 9.0, + "l": 0.3, + "nf": 18 + }, + "M2": { + "w": 9.0, + "l": 0.3, + "nf": 18 + }, + "M3": { + "w": 4.5, + "l": 0.3, + "nf": 9 + }, + "M4": { + "w": 4.5, + "l": 0.3, + "nf": 9 + } + } + }, + "reference_file": "configs/development/c06_cfg1_family/references/dev_nf_1half.spice", + "contract_file": "configs/development/c06_cfg1_family/contracts/dev_nf_1half.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 12.0, + "l": 0.3, + "nf": 24 + }, + "M2": { + "w": 12.0, + "l": 0.3, + "nf": 24 + }, + "M3": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M4": { + "w": 6.0, + "l": 0.3, + "nf": 12 + } + } + }, + "reference_file": "configs/development/c06_cfg1_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c06_cfg1_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.225, + "nf": 12 + }, + "M2": { + "w": 6.0, + "l": 0.225, + "nf": 12 + }, + "M3": { + "w": 3.0, + "l": 0.225, + "nf": 6 + }, + "M4": { + "w": 3.0, + "l": 0.225, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c06_cfg1_family/references/dev_len075.spice", + "contract_file": "configs/development/c06_cfg1_family/contracts/dev_len075.json" + }, + { + "configuration_id": "dev_len150", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.45, + "nf": 12 + }, + "M2": { + "w": 6.0, + "l": 0.45, + "nf": 12 + }, + "M3": { + "w": 3.0, + "l": 0.45, + "nf": 6 + }, + "M4": { + "w": 3.0, + "l": 0.45, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c06_cfg1_family/references/dev_len150.spice", + "contract_file": "configs/development/c06_cfg1_family/contracts/dev_len150.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 9.0, + "l": 0.3, + "nf": 12 + }, + "M2": { + "w": 9.0, + "l": 0.3, + "nf": 12 + }, + "M3": { + "w": 4.5, + "l": 0.3, + "nf": 6 + }, + "M4": { + "w": 4.5, + "l": 0.3, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c06_cfg1_family/references/dev_unit075.spice", + "contract_file": "configs/development/c06_cfg1_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_unit100", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 12.0, + "l": 0.3, + "nf": 12 + }, + "M2": { + "w": 12.0, + "l": 0.3, + "nf": 12 + }, + "M3": { + "w": 6.0, + "l": 0.3, + "nf": 6 + }, + "M4": { + "w": 6.0, + "l": 0.3, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c06_cfg1_family/references/dev_unit100.spice", + "contract_file": "configs/development/c06_cfg1_family/contracts/dev_unit100.json" + }, + { + "configuration_id": "dev_len200", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.6, + "nf": 12 + }, + "M2": { + "w": 6.0, + "l": 0.6, + "nf": 12 + }, + "M3": { + "w": 3.0, + "l": 0.6, + "nf": 6 + }, + "M4": { + "w": 3.0, + "l": 0.6, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c06_cfg1_family/references/dev_len200.spice", + "contract_file": "configs/development/c06_cfg1_family/contracts/dev_len200.json" + } + ], + "textbook_specification_floors": { + "gain_lf": { + "min": 30.0 + }, + "f3db": { + "min": 100000.0 + } + }, + "declared_by": "scripts/prepare_textbook_train_domains.py", + "ancestry": "Same cropped universal compiler source; no new source lineage. Geometry and per-finger references are fixed before any layout." +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/anchor.json new file mode 100644 index 00000000..38f30f2e --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/anchor.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg1", + "configuration_id": "anchor", + "reference_id": "c06_cfg1_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_len075.json b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_len075.json new file mode 100644 index 00000000..c43cbc0f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_len075.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg1", + "configuration_id": "dev_len075", + "reference_id": "c06_cfg1_dev_len075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_len150.json b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_len150.json new file mode 100644 index 00000000..e2be5d11 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_len150.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg1", + "configuration_id": "dev_len150", + "reference_id": "c06_cfg1_dev_len150_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_len200.json b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_len200.json new file mode 100644 index 00000000..602a8b8e --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_len200.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg1", + "configuration_id": "dev_len200", + "reference_id": "c06_cfg1_dev_len200_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_nf_1half.json b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_nf_1half.json new file mode 100644 index 00000000..ad574d86 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_nf_1half.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg1", + "configuration_id": "dev_nf_1half", + "reference_id": "c06_cfg1_dev_nf_1half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..646cc0b0 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_nf_double.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg1", + "configuration_id": "dev_nf_double", + "reference_id": "c06_cfg1_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_nf_half.json b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_nf_half.json new file mode 100644 index 00000000..177e23ce --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_nf_half.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg1", + "configuration_id": "dev_nf_half", + "reference_id": "c06_cfg1_dev_nf_half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_unit075.json new file mode 100644 index 00000000..c0ace40b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_unit075.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg1", + "configuration_id": "dev_unit075", + "reference_id": "c06_cfg1_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_unit100.json b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_unit100.json new file mode 100644 index 00000000..4ba03a37 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/contracts/dev_unit100.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg1", + "configuration_id": "dev_unit100", + "reference_id": "c06_cfg1_dev_unit100_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/anchor.spice new file mode 100644 index 00000000..9a5a9521 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/anchor.spice @@ -0,0 +1,38 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f8 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f9 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f10 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f11 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f6 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f7 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f8 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f9 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f10 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f11 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f3 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f4 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f5 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f3 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f4 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f5 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_len075.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_len075.spice new file mode 100644 index 00000000..13bdbfde --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_len075.spice @@ -0,0 +1,38 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f6 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f7 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f8 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f9 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f10 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f11 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f6 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f7 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f8 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f9 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f10 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f11 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM3_f3 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM3_f4 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM3_f5 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM4_f3 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM4_f4 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM4_f5 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_len150.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_len150.spice new file mode 100644 index 00000000..3b50e6bc --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_len150.spice @@ -0,0 +1,38 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f6 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f7 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f8 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f9 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f10 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f11 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f6 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f7 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f8 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f9 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f10 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f11 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f3 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f4 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f5 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f3 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f4 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f5 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_len200.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_len200.spice new file mode 100644 index 00000000..4fc2353d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_len200.spice @@ -0,0 +1,38 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM1_f6 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM1_f7 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM1_f8 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM1_f9 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM1_f10 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM1_f11 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f6 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f7 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f8 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f9 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f10 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f11 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f3 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f4 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f5 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f3 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f4 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f5 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_nf_1half.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_nf_1half.spice new file mode 100644 index 00000000..631e304d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_nf_1half.spice @@ -0,0 +1,56 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f8 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f9 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f10 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f11 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f12 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f13 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f14 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f15 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f16 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f17 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f6 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f7 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f8 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f9 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f10 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f11 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f12 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f13 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f14 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f15 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f16 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f17 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f3 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f4 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f5 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f6 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f7 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f8 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f3 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f4 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f5 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f6 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f7 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f8 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_nf_double.spice new file mode 100644 index 00000000..a041ed5a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_nf_double.spice @@ -0,0 +1,74 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f8 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f9 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f10 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f11 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f12 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f13 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f14 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f15 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f16 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f17 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f18 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f19 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f20 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f21 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f22 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f23 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f6 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f7 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f8 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f9 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f10 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f11 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f12 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f13 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f14 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f15 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f16 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f17 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f18 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f19 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f20 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f21 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f22 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f23 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f3 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f4 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f5 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f6 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f7 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f8 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f9 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f10 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f11 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f3 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f4 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f5 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f6 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f7 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f8 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f9 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f10 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f11 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_nf_half.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_nf_half.spice new file mode 100644 index 00000000..fc457823 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_nf_half.spice @@ -0,0 +1,20 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_unit075.spice new file mode 100644 index 00000000..e62539cf --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_unit075.spice @@ -0,0 +1,38 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f6 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f7 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f8 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f9 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f10 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f11 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f6 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f7 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f8 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f9 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f10 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f11 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f3 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f4 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f5 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM4_f3 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM4_f4 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM4_f5 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_unit100.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_unit100.spice new file mode 100644 index 00000000..8ddc8475 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg1_family/references/dev_unit100.spice @@ -0,0 +1,38 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f6 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f7 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f8 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f9 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f10 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f11 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f6 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f7 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f8 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f9 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f10 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f11 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f3 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f4 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f5 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f3 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f4 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f5 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/circuit_input.json new file mode 100644 index 00000000..97acc72b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/circuit_input.json @@ -0,0 +1,90 @@ +{ + "circuit_id": "C06", + "name": "cascode_amplifier_cascode_load", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VOUT1", + "VB1", + "VB2", + "VB3" + ], + "devices": [ + { + "name": "M1", + "kind": "pfet", + "nets": [ + "VOUT1", + "VB2", + "net10", + "VDD" + ], + "params": {} + }, + { + "name": "M2", + "kind": "pfet", + "nets": [ + "net10", + "VB3", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "net9", + "VIN1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "nfet", + "nets": [ + "VOUT1", + "VB1", + "net9", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 38, + "files": [ + "Dataset/38/38.cir", + "Dataset/38/Port38.txt", + "Dataset/38/Pagenumber38.txt", + "Dataset/38/Book38.png", + "Dataset/38/Cadence38.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "88", + "device_name_map": { + "M1": "M1", + "M2": "M0", + "M3": "M3", + "M4": "M2" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/38/Book38.png", + "observation": "Razavi p.88 scan: M1/M2 NMOS cascode, M3/M4 PMOS cascode current source (Vb1..Vb3)" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/configurations.json new file mode 100644 index 00000000..50443e0a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/configurations.json @@ -0,0 +1,293 @@ +{ + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_ONLY", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C06", + "domain_id": "C06_cfg2", + "textbook_sizing_source": "presimulated size configuration cfg2 of the textbook benchmark", + "circuit_name": "cascode_amplifier_cascode_load", + "bench_category": "single", + "circuit_input_file": "configs/development/c06_cfg2_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 0.3, + "nf": 4 + }, + "M3": { + "w": 2.0, + "l": 0.3, + "nf": 2 + }, + "M4": { + "w": 2.0, + "l": 0.3, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c06_cfg2_family/references/anchor.spice", + "contract_file": "configs/development/c06_cfg2_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.3, + "nf": 2 + }, + "M2": { + "w": 2.0, + "l": 0.3, + "nf": 2 + }, + "M3": { + "w": 1.0, + "l": 0.3, + "nf": 1 + }, + "M4": { + "w": 1.0, + "l": 0.3, + "nf": 1 + } + } + }, + "reference_file": "configs/development/c06_cfg2_family/references/dev_nf_half.spice", + "contract_file": "configs/development/c06_cfg2_family/contracts/dev_nf_half.json" + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.3, + "nf": 6 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 6 + }, + "M3": { + "w": 3.0, + "l": 0.3, + "nf": 3 + }, + "M4": { + "w": 3.0, + "l": 0.3, + "nf": 3 + } + } + }, + "reference_file": "configs/development/c06_cfg2_family/references/dev_nf_1half.spice", + "contract_file": "configs/development/c06_cfg2_family/contracts/dev_nf_1half.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 8.0, + "l": 0.3, + "nf": 8 + }, + "M2": { + "w": 8.0, + "l": 0.3, + "nf": 8 + }, + "M3": { + "w": 4.0, + "l": 0.3, + "nf": 4 + }, + "M4": { + "w": 4.0, + "l": 0.3, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c06_cfg2_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c06_cfg2_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.225, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 0.225, + "nf": 4 + }, + "M3": { + "w": 2.0, + "l": 0.225, + "nf": 2 + }, + "M4": { + "w": 2.0, + "l": 0.225, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c06_cfg2_family/references/dev_len075.spice", + "contract_file": "configs/development/c06_cfg2_family/contracts/dev_len075.json" + }, + { + "configuration_id": "dev_len150", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.45, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 0.45, + "nf": 4 + }, + "M3": { + "w": 2.0, + "l": 0.45, + "nf": 2 + }, + "M4": { + "w": 2.0, + "l": 0.45, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c06_cfg2_family/references/dev_len150.spice", + "contract_file": "configs/development/c06_cfg2_family/contracts/dev_len150.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 3.0, + "l": 0.3, + "nf": 4 + }, + "M3": { + "w": 1.5, + "l": 0.3, + "nf": 2 + }, + "M4": { + "w": 1.5, + "l": 0.3, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c06_cfg2_family/references/dev_unit075.spice", + "contract_file": "configs/development/c06_cfg2_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_len200", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.6, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 0.6, + "nf": 4 + }, + "M3": { + "w": 2.0, + "l": 0.6, + "nf": 2 + }, + "M4": { + "w": 2.0, + "l": 0.6, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c06_cfg2_family/references/dev_len200.spice", + "contract_file": "configs/development/c06_cfg2_family/contracts/dev_len200.json" + }, + { + "configuration_id": "dev_nf_triple", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 12.0, + "l": 0.3, + "nf": 12 + }, + "M2": { + "w": 12.0, + "l": 0.3, + "nf": 12 + }, + "M3": { + "w": 6.0, + "l": 0.3, + "nf": 6 + }, + "M4": { + "w": 6.0, + "l": 0.3, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c06_cfg2_family/references/dev_nf_triple.spice", + "contract_file": "configs/development/c06_cfg2_family/contracts/dev_nf_triple.json" + } + ], + "textbook_specification_floors": { + "gain_lf": { + "min": 30.0 + }, + "f3db": { + "min": 100000.0 + } + }, + "declared_by": "scripts/prepare_textbook_train_domains.py", + "ancestry": "Same cropped universal compiler source; no new source lineage. Geometry and per-finger references are fixed before any layout." +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/anchor.json new file mode 100644 index 00000000..e0514154 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/anchor.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg2", + "configuration_id": "anchor", + "reference_id": "c06_cfg2_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_len075.json b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_len075.json new file mode 100644 index 00000000..9f4e00ed --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_len075.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg2", + "configuration_id": "dev_len075", + "reference_id": "c06_cfg2_dev_len075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_len150.json b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_len150.json new file mode 100644 index 00000000..aa57eb1e --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_len150.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg2", + "configuration_id": "dev_len150", + "reference_id": "c06_cfg2_dev_len150_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_len200.json b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_len200.json new file mode 100644 index 00000000..013332ff --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_len200.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg2", + "configuration_id": "dev_len200", + "reference_id": "c06_cfg2_dev_len200_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_nf_1half.json b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_nf_1half.json new file mode 100644 index 00000000..9d62222c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_nf_1half.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg2", + "configuration_id": "dev_nf_1half", + "reference_id": "c06_cfg2_dev_nf_1half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..d50dcc19 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_nf_double.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg2", + "configuration_id": "dev_nf_double", + "reference_id": "c06_cfg2_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_nf_half.json b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_nf_half.json new file mode 100644 index 00000000..06b501d6 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_nf_half.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg2", + "configuration_id": "dev_nf_half", + "reference_id": "c06_cfg2_dev_nf_half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_nf_triple.json b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_nf_triple.json new file mode 100644 index 00000000..0931e385 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_nf_triple.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg2", + "configuration_id": "dev_nf_triple", + "reference_id": "c06_cfg2_dev_nf_triple_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_unit075.json new file mode 100644 index 00000000..815789d4 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/contracts/dev_unit075.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg2", + "configuration_id": "dev_unit075", + "reference_id": "c06_cfg2_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/anchor.spice new file mode 100644 index 00000000..6fceaa0e --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/anchor.spice @@ -0,0 +1,14 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_len075.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_len075.spice new file mode 100644 index 00000000..7a730f01 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_len075.spice @@ -0,0 +1,14 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.225 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.225 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.225 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.225 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.225 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.225 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.225 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.225 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.225 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.225 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.225 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.225 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_len150.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_len150.spice new file mode 100644 index 00000000..64812a4e --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_len150.spice @@ -0,0 +1,14 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_len200.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_len200.spice new file mode 100644 index 00000000..91950162 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_len200.spice @@ -0,0 +1,14 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.6 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.6 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.6 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.6 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.6 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.6 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.6 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.6 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_nf_1half.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_nf_1half.spice new file mode 100644 index 00000000..b42f45b5 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_nf_1half.spice @@ -0,0 +1,20 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_nf_double.spice new file mode 100644 index 00000000..72b3d940 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_nf_double.spice @@ -0,0 +1,26 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f6 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f7 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f6 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f7 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f3 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f3 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_nf_half.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_nf_half.spice new file mode 100644 index 00000000..49afc9e8 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_nf_half.spice @@ -0,0 +1,8 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_nf_triple.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_nf_triple.spice new file mode 100644 index 00000000..8ddc8475 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_nf_triple.spice @@ -0,0 +1,38 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f6 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f7 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f8 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f9 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f10 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f11 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f6 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f7 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f8 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f9 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f10 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f11 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f3 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f4 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f5 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f3 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f4 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f5 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_unit075.spice new file mode 100644 index 00000000..2881f0e2 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg2_family/references/dev_unit075.spice @@ -0,0 +1,14 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/circuit_input.json new file mode 100644 index 00000000..97acc72b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/circuit_input.json @@ -0,0 +1,90 @@ +{ + "circuit_id": "C06", + "name": "cascode_amplifier_cascode_load", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VOUT1", + "VB1", + "VB2", + "VB3" + ], + "devices": [ + { + "name": "M1", + "kind": "pfet", + "nets": [ + "VOUT1", + "VB2", + "net10", + "VDD" + ], + "params": {} + }, + { + "name": "M2", + "kind": "pfet", + "nets": [ + "net10", + "VB3", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "net9", + "VIN1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "nfet", + "nets": [ + "VOUT1", + "VB1", + "net9", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 38, + "files": [ + "Dataset/38/38.cir", + "Dataset/38/Port38.txt", + "Dataset/38/Pagenumber38.txt", + "Dataset/38/Book38.png", + "Dataset/38/Cadence38.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "88", + "device_name_map": { + "M1": "M1", + "M2": "M0", + "M3": "M3", + "M4": "M2" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/38/Book38.png", + "observation": "Razavi p.88 scan: M1/M2 NMOS cascode, M3/M4 PMOS cascode current source (Vb1..Vb3)" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/configurations.json new file mode 100644 index 00000000..f33b1fee --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/configurations.json @@ -0,0 +1,293 @@ +{ + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_ONLY", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C06", + "domain_id": "C06_cfg3", + "textbook_sizing_source": "presimulated size configuration cfg3 of the textbook benchmark", + "circuit_name": "cascode_amplifier_cascode_load", + "bench_category": "single", + "circuit_input_file": "configs/development/c06_cfg3_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.45, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.45, + "nf": 8 + }, + "M3": { + "w": 2.0, + "l": 0.45, + "nf": 4 + }, + "M4": { + "w": 2.0, + "l": 0.45, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c06_cfg3_family/references/anchor.spice", + "contract_file": "configs/development/c06_cfg3_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.45, + "nf": 4 + }, + "M2": { + "w": 2.0, + "l": 0.45, + "nf": 4 + }, + "M3": { + "w": 1.0, + "l": 0.45, + "nf": 2 + }, + "M4": { + "w": 1.0, + "l": 0.45, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c06_cfg3_family/references/dev_nf_half.spice", + "contract_file": "configs/development/c06_cfg3_family/contracts/dev_nf_half.json" + }, + { + "configuration_id": "dev_nf_3quarters", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.45, + "nf": 6 + }, + "M2": { + "w": 3.0, + "l": 0.45, + "nf": 6 + }, + "M3": { + "w": 1.5, + "l": 0.45, + "nf": 3 + }, + "M4": { + "w": 1.5, + "l": 0.45, + "nf": 3 + } + } + }, + "reference_file": "configs/development/c06_cfg3_family/references/dev_nf_3quarters.spice", + "contract_file": "configs/development/c06_cfg3_family/contracts/dev_nf_3quarters.json" + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.45, + "nf": 12 + }, + "M2": { + "w": 6.0, + "l": 0.45, + "nf": 12 + }, + "M3": { + "w": 3.0, + "l": 0.45, + "nf": 6 + }, + "M4": { + "w": 3.0, + "l": 0.45, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c06_cfg3_family/references/dev_nf_1half.spice", + "contract_file": "configs/development/c06_cfg3_family/contracts/dev_nf_1half.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 8.0, + "l": 0.45, + "nf": 16 + }, + "M2": { + "w": 8.0, + "l": 0.45, + "nf": 16 + }, + "M3": { + "w": 4.0, + "l": 0.45, + "nf": 8 + }, + "M4": { + "w": 4.0, + "l": 0.45, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c06_cfg3_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c06_cfg3_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.338, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.338, + "nf": 8 + }, + "M3": { + "w": 2.0, + "l": 0.338, + "nf": 4 + }, + "M4": { + "w": 2.0, + "l": 0.338, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c06_cfg3_family/references/dev_len075.spice", + "contract_file": "configs/development/c06_cfg3_family/contracts/dev_len075.json" + }, + { + "configuration_id": "dev_len150", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.675, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.675, + "nf": 8 + }, + "M3": { + "w": 2.0, + "l": 0.675, + "nf": 4 + }, + "M4": { + "w": 2.0, + "l": 0.675, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c06_cfg3_family/references/dev_len150.spice", + "contract_file": "configs/development/c06_cfg3_family/contracts/dev_len150.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.45, + "nf": 8 + }, + "M2": { + "w": 6.0, + "l": 0.45, + "nf": 8 + }, + "M3": { + "w": 3.0, + "l": 0.45, + "nf": 4 + }, + "M4": { + "w": 3.0, + "l": 0.45, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c06_cfg3_family/references/dev_unit075.spice", + "contract_file": "configs/development/c06_cfg3_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_unit100", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 8.0, + "l": 0.45, + "nf": 8 + }, + "M2": { + "w": 8.0, + "l": 0.45, + "nf": 8 + }, + "M3": { + "w": 4.0, + "l": 0.45, + "nf": 4 + }, + "M4": { + "w": 4.0, + "l": 0.45, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c06_cfg3_family/references/dev_unit100.spice", + "contract_file": "configs/development/c06_cfg3_family/contracts/dev_unit100.json" + } + ], + "textbook_specification_floors": { + "gain_lf": { + "min": 30.0 + }, + "f3db": { + "min": 100000.0 + } + }, + "declared_by": "scripts/prepare_textbook_train_domains.py", + "ancestry": "Same cropped universal compiler source; no new source lineage. Geometry and per-finger references are fixed before any layout." +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/anchor.json new file mode 100644 index 00000000..7e99546e --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/anchor.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg3", + "configuration_id": "anchor", + "reference_id": "c06_cfg3_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_len075.json b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_len075.json new file mode 100644 index 00000000..acc3e876 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_len075.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg3", + "configuration_id": "dev_len075", + "reference_id": "c06_cfg3_dev_len075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_len150.json b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_len150.json new file mode 100644 index 00000000..12f94ff6 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_len150.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg3", + "configuration_id": "dev_len150", + "reference_id": "c06_cfg3_dev_len150_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_nf_1half.json b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_nf_1half.json new file mode 100644 index 00000000..9021f426 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_nf_1half.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg3", + "configuration_id": "dev_nf_1half", + "reference_id": "c06_cfg3_dev_nf_1half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_nf_3quarters.json b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_nf_3quarters.json new file mode 100644 index 00000000..d445cdba --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_nf_3quarters.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg3", + "configuration_id": "dev_nf_3quarters", + "reference_id": "c06_cfg3_dev_nf_3quarters_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..170f33fc --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_nf_double.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg3", + "configuration_id": "dev_nf_double", + "reference_id": "c06_cfg3_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_nf_half.json b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_nf_half.json new file mode 100644 index 00000000..f7e7a3ee --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_nf_half.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg3", + "configuration_id": "dev_nf_half", + "reference_id": "c06_cfg3_dev_nf_half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_unit075.json new file mode 100644 index 00000000..cbc104f7 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_unit075.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg3", + "configuration_id": "dev_unit075", + "reference_id": "c06_cfg3_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_unit100.json b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_unit100.json new file mode 100644 index 00000000..cf4f915b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/contracts/dev_unit100.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06_cfg3", + "configuration_id": "dev_unit100", + "reference_id": "c06_cfg3_dev_unit100_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/anchor.spice new file mode 100644 index 00000000..f379dfdf --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/anchor.spice @@ -0,0 +1,26 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f6 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f7 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f6 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f7 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f3 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f3 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_len075.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_len075.spice new file mode 100644 index 00000000..b57ef2b8 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_len075.spice @@ -0,0 +1,26 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM1_f6 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM1_f7 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM2_f6 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM2_f7 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM3_f3 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM4_f3 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_len150.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_len150.spice new file mode 100644 index 00000000..c6fa0723 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_len150.spice @@ -0,0 +1,26 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM1_f6 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM1_f7 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM2_f6 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM2_f7 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM3_f3 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM4_f3 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_nf_1half.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_nf_1half.spice new file mode 100644 index 00000000..3b50e6bc --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_nf_1half.spice @@ -0,0 +1,38 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f6 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f7 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f8 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f9 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f10 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f11 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f6 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f7 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f8 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f9 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f10 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f11 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f3 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f4 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f5 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f3 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f4 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f5 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_nf_3quarters.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_nf_3quarters.spice new file mode 100644 index 00000000..9c3bc14d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_nf_3quarters.spice @@ -0,0 +1,20 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_nf_double.spice new file mode 100644 index 00000000..e79fd18a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_nf_double.spice @@ -0,0 +1,50 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f6 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f7 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f8 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f9 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f10 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f11 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f12 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f13 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f14 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f15 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f6 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f7 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f8 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f9 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f10 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f11 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f12 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f13 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f14 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f15 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f3 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f4 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f5 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f6 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f7 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f3 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f4 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f5 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f6 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f7 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_nf_half.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_nf_half.spice new file mode 100644 index 00000000..2f051971 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_nf_half.spice @@ -0,0 +1,14 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_unit075.spice new file mode 100644 index 00000000..ca29fcaa --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_unit075.spice @@ -0,0 +1,26 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM1_f6 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM1_f7 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM2_f6 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM2_f7 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM3_f3 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM4_f3 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_unit100.spice b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_unit100.spice new file mode 100644 index 00000000..fb83c0ea --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_cfg3_family/references/dev_unit100.spice @@ -0,0 +1,26 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM1_f6 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM1_f7 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM2_f6 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM2_f7 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM3_f3 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM4_f3 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c06_family/circuit_input.json new file mode 100644 index 00000000..97acc72b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_family/circuit_input.json @@ -0,0 +1,90 @@ +{ + "circuit_id": "C06", + "name": "cascode_amplifier_cascode_load", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VOUT1", + "VB1", + "VB2", + "VB3" + ], + "devices": [ + { + "name": "M1", + "kind": "pfet", + "nets": [ + "VOUT1", + "VB2", + "net10", + "VDD" + ], + "params": {} + }, + { + "name": "M2", + "kind": "pfet", + "nets": [ + "net10", + "VB3", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "net9", + "VIN1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "nfet", + "nets": [ + "VOUT1", + "VB1", + "net9", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 38, + "files": [ + "Dataset/38/38.cir", + "Dataset/38/Port38.txt", + "Dataset/38/Pagenumber38.txt", + "Dataset/38/Book38.png", + "Dataset/38/Cadence38.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "88", + "device_name_map": { + "M1": "M1", + "M2": "M0", + "M3": "M3", + "M4": "M2" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/38/Book38.png", + "observation": "Razavi p.88 scan: M1/M2 NMOS cascode, M3/M4 PMOS cascode current source (Vb1..Vb3)" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c06_family/configurations.json new file mode 100644 index 00000000..61736b50 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_family/configurations.json @@ -0,0 +1,291 @@ +{ + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_ONLY", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C06", + "circuit_name": "cascode_amplifier_cascode_load", + "bench_category": "single", + "circuit_input_file": "configs/development/c06_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M3": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M4": { + "w": 2.0, + "l": 0.3, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c06_family/references/anchor.spice", + "contract_file": "configs/development/c06_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M3": { + "w": 1.0, + "l": 0.3, + "nf": 2 + }, + "M4": { + "w": 1.0, + "l": 0.3, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c06_family/references/dev_nf_half.spice", + "contract_file": "configs/development/c06_family/contracts/dev_nf_half.json" + }, + { + "configuration_id": "dev_nf_3quarters", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M2": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M3": { + "w": 1.5, + "l": 0.3, + "nf": 3 + }, + "M4": { + "w": 1.5, + "l": 0.3, + "nf": 3 + } + } + }, + "reference_file": "configs/development/c06_family/references/dev_nf_3quarters.spice", + "contract_file": "configs/development/c06_family/contracts/dev_nf_3quarters.json" + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M3": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M4": { + "w": 3.0, + "l": 0.3, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c06_family/references/dev_nf_1half.spice", + "contract_file": "configs/development/c06_family/contracts/dev_nf_1half.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 8.0, + "l": 0.3, + "nf": 16 + }, + "M2": { + "w": 8.0, + "l": 0.3, + "nf": 16 + }, + "M3": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M4": { + "w": 4.0, + "l": 0.3, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c06_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c06_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.225, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.225, + "nf": 8 + }, + "M3": { + "w": 2.0, + "l": 0.225, + "nf": 4 + }, + "M4": { + "w": 2.0, + "l": 0.225, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c06_family/references/dev_len075.spice", + "contract_file": "configs/development/c06_family/contracts/dev_len075.json" + }, + { + "configuration_id": "dev_len150", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.45, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.45, + "nf": 8 + }, + "M3": { + "w": 2.0, + "l": 0.45, + "nf": 4 + }, + "M4": { + "w": 2.0, + "l": 0.45, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c06_family/references/dev_len150.spice", + "contract_file": "configs/development/c06_family/contracts/dev_len150.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.3, + "nf": 8 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 8 + }, + "M3": { + "w": 3.0, + "l": 0.3, + "nf": 4 + }, + "M4": { + "w": 3.0, + "l": 0.3, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c06_family/references/dev_unit075.spice", + "contract_file": "configs/development/c06_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_unit100", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 8.0, + "l": 0.3, + "nf": 8 + }, + "M2": { + "w": 8.0, + "l": 0.3, + "nf": 8 + }, + "M3": { + "w": 4.0, + "l": 0.3, + "nf": 4 + }, + "M4": { + "w": 4.0, + "l": 0.3, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c06_family/references/dev_unit100.spice", + "contract_file": "configs/development/c06_family/contracts/dev_unit100.json" + } + ], + "textbook_specification_floors": { + "gain_lf": { + "min": 30.0 + }, + "f3db": { + "min": 100000.0 + } + }, + "declared_by": "scripts/prepare_textbook_train_domains.py", + "ancestry": "Same cropped universal compiler source; no new source lineage. Geometry and per-finger references are fixed before any layout." +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c06_family/contracts/anchor.json new file mode 100644 index 00000000..c213522f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_family/contracts/anchor.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06", + "configuration_id": "anchor", + "reference_id": "c06_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_len075.json b/benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_len075.json new file mode 100644 index 00000000..af1beede --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_len075.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06", + "configuration_id": "dev_len075", + "reference_id": "c06_dev_len075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_len150.json b/benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_len150.json new file mode 100644 index 00000000..b51db9f8 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_len150.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06", + "configuration_id": "dev_len150", + "reference_id": "c06_dev_len150_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_nf_1half.json b/benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_nf_1half.json new file mode 100644 index 00000000..83cb3b22 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_nf_1half.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06", + "configuration_id": "dev_nf_1half", + "reference_id": "c06_dev_nf_1half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_nf_3quarters.json b/benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_nf_3quarters.json new file mode 100644 index 00000000..0c4f79cf --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_nf_3quarters.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06", + "configuration_id": "dev_nf_3quarters", + "reference_id": "c06_dev_nf_3quarters_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..5aa1e6a5 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_nf_double.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06", + "configuration_id": "dev_nf_double", + "reference_id": "c06_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_nf_half.json b/benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_nf_half.json new file mode 100644 index 00000000..d998bcc4 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_nf_half.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06", + "configuration_id": "dev_nf_half", + "reference_id": "c06_dev_nf_half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_unit075.json new file mode 100644 index 00000000..f02e4bf5 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_unit075.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06", + "configuration_id": "dev_unit075", + "reference_id": "c06_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_unit100.json b/benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_unit100.json new file mode 100644 index 00000000..2359d55c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_family/contracts/dev_unit100.json @@ -0,0 +1,113 @@ +{ + "task_id": "development_train_domain_c06", + "configuration_id": "dev_unit100", + "reference_id": "c06_dev_unit100_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c06_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 30.0, + "f3db_Hz_min": 100000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05, + "kind": "diode" + } + }, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": { + "VB1": { + "replica": "M4", + "current": 2e-05, + "kind": "cascode" + }, + "VB2": { + "replica": "M1", + "current": 2e-05, + "kind": "cascode" + }, + "VB3": { + "replica": "M2", + "current": 2e-05 + } + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c06_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c06_family/references/anchor.spice new file mode 100644 index 00000000..707f0d87 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_family/references/anchor.spice @@ -0,0 +1,26 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f6 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f7 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f3 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f3 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_family/references/dev_len075.spice b/benchmarks/code_behind_layout/configs/development/c06_family/references/dev_len075.spice new file mode 100644 index 00000000..3950db11 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_family/references/dev_len075.spice @@ -0,0 +1,26 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f6 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM1_f7 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f6 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f7 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM3_f3 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM4_f3 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_family/references/dev_len150.spice b/benchmarks/code_behind_layout/configs/development/c06_family/references/dev_len150.spice new file mode 100644 index 00000000..f379dfdf --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_family/references/dev_len150.spice @@ -0,0 +1,26 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f6 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM1_f7 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f6 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f7 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f3 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f3 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_family/references/dev_nf_1half.spice b/benchmarks/code_behind_layout/configs/development/c06_family/references/dev_nf_1half.spice new file mode 100644 index 00000000..9a5a9521 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_family/references/dev_nf_1half.spice @@ -0,0 +1,38 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f8 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f9 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f10 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f11 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f6 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f7 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f8 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f9 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f10 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f11 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f3 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f4 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f5 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f3 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f4 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f5 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_family/references/dev_nf_3quarters.spice b/benchmarks/code_behind_layout/configs/development/c06_family/references/dev_nf_3quarters.spice new file mode 100644 index 00000000..fc457823 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_family/references/dev_nf_3quarters.spice @@ -0,0 +1,20 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c06_family/references/dev_nf_double.spice new file mode 100644 index 00000000..4f6a3fd3 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_family/references/dev_nf_double.spice @@ -0,0 +1,50 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f8 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f9 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f10 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f11 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f12 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f13 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f14 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f15 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f6 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f7 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f8 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f9 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f10 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f11 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f12 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f13 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f14 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f15 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f3 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f4 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f5 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f6 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f7 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f3 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f4 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f5 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f6 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f7 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_family/references/dev_nf_half.spice b/benchmarks/code_behind_layout/configs/development/c06_family/references/dev_nf_half.spice new file mode 100644 index 00000000..706694e5 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_family/references/dev_nf_half.spice @@ -0,0 +1,14 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c06_family/references/dev_unit075.spice new file mode 100644 index 00000000..2ff3504e --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_family/references/dev_unit075.spice @@ -0,0 +1,26 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f6 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM1_f7 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f6 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f7 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f3 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM4_f3 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c06_family/references/dev_unit100.spice b/benchmarks/code_behind_layout/configs/development/c06_family/references/dev_unit100.spice new file mode 100644 index 00000000..72b3d940 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c06_family/references/dev_unit100.spice @@ -0,0 +1,26 @@ +.subckt corpus_c06 VDD VSS VIN1 VOUT1 VB1 VB2 VB3 +XM1_f0 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f1 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f2 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f3 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f4 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f5 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f6 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM1_f7 VOUT1 VB2 net10 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f0 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f1 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f2 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f3 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f4 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f5 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f6 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f7 net10 VB3 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM3_f0 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f1 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f2 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f3 net9 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f0 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f1 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f2 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f3 VOUT1 VB1 net9 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +.ends corpus_c06 diff --git a/benchmarks/code_behind_layout/configs/development/c07_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c07_family/circuit_input.json new file mode 100644 index 00000000..8b3b4041 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c07_family/circuit_input.json @@ -0,0 +1,93 @@ +{ + "circuit_id": "C07", + "name": "diff_pair_current_source_loads", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VIN2", + "VOUT1", + "VOUT2", + "VB1", + "IB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN1", + "IB1", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VOUT2", + "VIN2", + "IB1", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "pfet", + "nets": [ + "VOUT1", + "VB1", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M4", + "kind": "pfet", + "nets": [ + "VOUT2", + "VB1", + "VDD", + "VDD" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 192, + "files": [ + "Dataset/192/192.cir", + "Dataset/192/Port192.txt", + "Dataset/192/Pagenumber192.txt", + "Dataset/192/Book192.png", + "Dataset/192/Cadence192.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "260", + "device_name_map": { + "M1": "M0", + "M2": "M1", + "M3": "M2", + "M4": "M3" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/192/Book192.png", + "observation": "Razavi p.260 scan: M1/M2 pair with ideal tail current source symbol, M3/M4 PMOS current sources (Vb)" + }, + "modifications": [ + "tail node IB1 is a port: the tail current source is an ideal (disclosed) testbench source" + ], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c07_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c07_family/configurations.json new file mode 100644 index 00000000..8b2ee827 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c07_family/configurations.json @@ -0,0 +1,280 @@ +{ + "scope": "development_only_train_component_qualification", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C07", + "circuit_input_file": "configs/development/c07_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M3": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M4": { + "w": 4.0, + "l": 0.3, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c07_family/references/anchor.spice", + "contract_file": "configs/development/c07_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M3": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M4": { + "w": 2.0, + "l": 0.3, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c07_family/references/dev_nf_half.spice", + "contract_file": "configs/development/c07_family/contracts/dev_nf_half.json" + }, + { + "configuration_id": "dev_nf_3quarters", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M2": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M3": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M4": { + "w": 3.0, + "l": 0.3, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c07_family/references/dev_nf_3quarters.spice", + "contract_file": "configs/development/c07_family/contracts/dev_nf_3quarters.json" + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M3": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M4": { + "w": 6.0, + "l": 0.3, + "nf": 12 + } + } + }, + "reference_file": "configs/development/c07_family/references/dev_nf_1half.spice", + "contract_file": "configs/development/c07_family/contracts/dev_nf_1half.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 8.0, + "l": 0.3, + "nf": 16 + }, + "M2": { + "w": 8.0, + "l": 0.3, + "nf": 16 + }, + "M3": { + "w": 8.0, + "l": 0.3, + "nf": 16 + }, + "M4": { + "w": 8.0, + "l": 0.3, + "nf": 16 + } + } + }, + "reference_file": "configs/development/c07_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c07_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len045", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.45, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.45, + "nf": 8 + }, + "M3": { + "w": 4.0, + "l": 0.45, + "nf": 8 + }, + "M4": { + "w": 4.0, + "l": 0.45, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c07_family/references/dev_len045.spice", + "contract_file": "configs/development/c07_family/contracts/dev_len045.json" + }, + { + "configuration_id": "dev_len060", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "M3": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "M4": { + "w": 4.0, + "l": 0.6, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c07_family/references/dev_len060.spice", + "contract_file": "configs/development/c07_family/contracts/dev_len060.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.3, + "nf": 8 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 8 + }, + "M3": { + "w": 6.0, + "l": 0.3, + "nf": 8 + }, + "M4": { + "w": 6.0, + "l": 0.3, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c07_family/references/dev_unit075.spice", + "contract_file": "configs/development/c07_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_unit100", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 8.0, + "l": 0.3, + "nf": 8 + }, + "M2": { + "w": 8.0, + "l": 0.3, + "nf": 8 + }, + "M3": { + "w": 8.0, + "l": 0.3, + "nf": 8 + }, + "M4": { + "w": 8.0, + "l": 0.3, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c07_family/references/dev_unit100.spice", + "contract_file": "configs/development/c07_family/contracts/dev_unit100.json" + } + ], + "ancestry": "One cropped public universal compiler source lineage; new descriptors and geometry configurations are not new source implementations." +} diff --git a/benchmarks/code_behind_layout/configs/development/c07_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c07_family/contracts/anchor.json new file mode 100644 index 00000000..f48d99c4 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c07_family/contracts/anchor.json @@ -0,0 +1,84 @@ +{ + "task_id": "development_train_domain_c07", + "configuration_id": "anchor", + "reference_id": "c07_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c07_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_common_mode_V": 0.9, + "clamped_outputs_V": [ + 0.9, + 0.9 + ], + "ideal_tail_sink_A": 4e-05, + "external_PMOS_replica_current_A": 2e-05, + "differential_AC_input_V": 1, + "differential_transient_levels_V": [ + -0.01, + 0.01 + ], + "differential_DC_sweep_V": [ + -0.1, + 0.1, + 0.005 + ], + "load_definition": "Each output has an ideal 0.9V clamp. Measure differential output-current transconductance, systematic offset and current steering, not free-output voltage gain or mismatch yield.", + "power_definition": "Main VDD supply power only; separate diode-reference and output-clamp port work are reported separately." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 6, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_len045.json b/benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_len045.json new file mode 100644 index 00000000..1f3f3f06 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_len045.json @@ -0,0 +1,84 @@ +{ + "task_id": "development_train_domain_c07", + "configuration_id": "dev_len045", + "reference_id": "c07_dev_len045_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c07_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_common_mode_V": 0.9, + "clamped_outputs_V": [ + 0.9, + 0.9 + ], + "ideal_tail_sink_A": 4e-05, + "external_PMOS_replica_current_A": 2e-05, + "differential_AC_input_V": 1, + "differential_transient_levels_V": [ + -0.01, + 0.01 + ], + "differential_DC_sweep_V": [ + -0.1, + 0.1, + 0.005 + ], + "load_definition": "Each output has an ideal 0.9V clamp. Measure differential output-current transconductance, systematic offset and current steering, not free-output voltage gain or mismatch yield.", + "power_definition": "Main VDD supply power only; separate diode-reference and output-clamp port work are reported separately." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 6, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_len060.json b/benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_len060.json new file mode 100644 index 00000000..8c18bac2 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_len060.json @@ -0,0 +1,84 @@ +{ + "task_id": "development_train_domain_c07", + "configuration_id": "dev_len060", + "reference_id": "c07_dev_len060_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c07_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_common_mode_V": 0.9, + "clamped_outputs_V": [ + 0.9, + 0.9 + ], + "ideal_tail_sink_A": 4e-05, + "external_PMOS_replica_current_A": 2e-05, + "differential_AC_input_V": 1, + "differential_transient_levels_V": [ + -0.01, + 0.01 + ], + "differential_DC_sweep_V": [ + -0.1, + 0.1, + 0.005 + ], + "load_definition": "Each output has an ideal 0.9V clamp. Measure differential output-current transconductance, systematic offset and current steering, not free-output voltage gain or mismatch yield.", + "power_definition": "Main VDD supply power only; separate diode-reference and output-clamp port work are reported separately." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 6, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_nf_1half.json b/benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_nf_1half.json new file mode 100644 index 00000000..4f4a5667 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_nf_1half.json @@ -0,0 +1,84 @@ +{ + "task_id": "development_train_domain_c07", + "configuration_id": "dev_nf_1half", + "reference_id": "c07_dev_nf_1half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c07_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_common_mode_V": 0.9, + "clamped_outputs_V": [ + 0.9, + 0.9 + ], + "ideal_tail_sink_A": 4e-05, + "external_PMOS_replica_current_A": 2e-05, + "differential_AC_input_V": 1, + "differential_transient_levels_V": [ + -0.01, + 0.01 + ], + "differential_DC_sweep_V": [ + -0.1, + 0.1, + 0.005 + ], + "load_definition": "Each output has an ideal 0.9V clamp. Measure differential output-current transconductance, systematic offset and current steering, not free-output voltage gain or mismatch yield.", + "power_definition": "Main VDD supply power only; separate diode-reference and output-clamp port work are reported separately." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 6, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_nf_3quarters.json b/benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_nf_3quarters.json new file mode 100644 index 00000000..91343a07 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_nf_3quarters.json @@ -0,0 +1,84 @@ +{ + "task_id": "development_train_domain_c07", + "configuration_id": "dev_nf_3quarters", + "reference_id": "c07_dev_nf_3quarters_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c07_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_common_mode_V": 0.9, + "clamped_outputs_V": [ + 0.9, + 0.9 + ], + "ideal_tail_sink_A": 4e-05, + "external_PMOS_replica_current_A": 2e-05, + "differential_AC_input_V": 1, + "differential_transient_levels_V": [ + -0.01, + 0.01 + ], + "differential_DC_sweep_V": [ + -0.1, + 0.1, + 0.005 + ], + "load_definition": "Each output has an ideal 0.9V clamp. Measure differential output-current transconductance, systematic offset and current steering, not free-output voltage gain or mismatch yield.", + "power_definition": "Main VDD supply power only; separate diode-reference and output-clamp port work are reported separately." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 6, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..fec8aabe --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_nf_double.json @@ -0,0 +1,84 @@ +{ + "task_id": "development_train_domain_c07", + "configuration_id": "dev_nf_double", + "reference_id": "c07_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c07_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_common_mode_V": 0.9, + "clamped_outputs_V": [ + 0.9, + 0.9 + ], + "ideal_tail_sink_A": 4e-05, + "external_PMOS_replica_current_A": 2e-05, + "differential_AC_input_V": 1, + "differential_transient_levels_V": [ + -0.01, + 0.01 + ], + "differential_DC_sweep_V": [ + -0.1, + 0.1, + 0.005 + ], + "load_definition": "Each output has an ideal 0.9V clamp. Measure differential output-current transconductance, systematic offset and current steering, not free-output voltage gain or mismatch yield.", + "power_definition": "Main VDD supply power only; separate diode-reference and output-clamp port work are reported separately." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 6, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_nf_half.json b/benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_nf_half.json new file mode 100644 index 00000000..9e4c9a16 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_nf_half.json @@ -0,0 +1,84 @@ +{ + "task_id": "development_train_domain_c07", + "configuration_id": "dev_nf_half", + "reference_id": "c07_dev_nf_half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c07_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_common_mode_V": 0.9, + "clamped_outputs_V": [ + 0.9, + 0.9 + ], + "ideal_tail_sink_A": 4e-05, + "external_PMOS_replica_current_A": 2e-05, + "differential_AC_input_V": 1, + "differential_transient_levels_V": [ + -0.01, + 0.01 + ], + "differential_DC_sweep_V": [ + -0.1, + 0.1, + 0.005 + ], + "load_definition": "Each output has an ideal 0.9V clamp. Measure differential output-current transconductance, systematic offset and current steering, not free-output voltage gain or mismatch yield.", + "power_definition": "Main VDD supply power only; separate diode-reference and output-clamp port work are reported separately." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 6, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_unit075.json new file mode 100644 index 00000000..d898ef77 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_unit075.json @@ -0,0 +1,84 @@ +{ + "task_id": "development_train_domain_c07", + "configuration_id": "dev_unit075", + "reference_id": "c07_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c07_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_common_mode_V": 0.9, + "clamped_outputs_V": [ + 0.9, + 0.9 + ], + "ideal_tail_sink_A": 4e-05, + "external_PMOS_replica_current_A": 2e-05, + "differential_AC_input_V": 1, + "differential_transient_levels_V": [ + -0.01, + 0.01 + ], + "differential_DC_sweep_V": [ + -0.1, + 0.1, + 0.005 + ], + "load_definition": "Each output has an ideal 0.9V clamp. Measure differential output-current transconductance, systematic offset and current steering, not free-output voltage gain or mismatch yield.", + "power_definition": "Main VDD supply power only; separate diode-reference and output-clamp port work are reported separately." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 6, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_unit100.json b/benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_unit100.json new file mode 100644 index 00000000..c71e5fe5 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c07_family/contracts/dev_unit100.json @@ -0,0 +1,84 @@ +{ + "task_id": "development_train_domain_c07", + "configuration_id": "dev_unit100", + "reference_id": "c07_dev_unit100_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c07_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_common_mode_V": 0.9, + "clamped_outputs_V": [ + 0.9, + 0.9 + ], + "ideal_tail_sink_A": 4e-05, + "external_PMOS_replica_current_A": 2e-05, + "differential_AC_input_V": 1, + "differential_transient_levels_V": [ + -0.01, + 0.01 + ], + "differential_DC_sweep_V": [ + -0.1, + 0.1, + 0.005 + ], + "load_definition": "Each output has an ideal 0.9V clamp. Measure differential output-current transconductance, systematic offset and current steering, not free-output voltage gain or mismatch yield.", + "power_definition": "Main VDD supply power only; separate diode-reference and output-clamp port work are reported separately." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 6, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c07_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c07_family/references/anchor.spice new file mode 100644 index 00000000..486f5c03 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c07_family/references/anchor.spice @@ -0,0 +1,34 @@ +.subckt corpus_c07 VDD VSS VIN1 VIN2 VOUT1 VOUT2 VB1 IB1 +XM1_f0 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f0 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f1 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f2 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f3 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f4 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f5 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f6 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f7 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_c07 diff --git a/benchmarks/code_behind_layout/configs/development/c07_family/references/dev_len045.spice b/benchmarks/code_behind_layout/configs/development/c07_family/references/dev_len045.spice new file mode 100644 index 00000000..648a73a1 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c07_family/references/dev_len045.spice @@ -0,0 +1,34 @@ +.subckt corpus_c07 VDD VSS VIN1 VIN2 VOUT1 VOUT2 VB1 IB1 +XM1_f0 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f1 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f2 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f3 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f4 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f5 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f6 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f7 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f0 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f1 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f2 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f3 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f4 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f5 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f6 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f7 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM3_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM3_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM3_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM3_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM3_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM3_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM3_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM4_f0 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM4_f1 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM4_f2 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM4_f3 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM4_f4 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM4_f5 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM4_f6 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM4_f7 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +.ends corpus_c07 diff --git a/benchmarks/code_behind_layout/configs/development/c07_family/references/dev_len060.spice b/benchmarks/code_behind_layout/configs/development/c07_family/references/dev_len060.spice new file mode 100644 index 00000000..908f7e4b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c07_family/references/dev_len060.spice @@ -0,0 +1,34 @@ +.subckt corpus_c07 VDD VSS VIN1 VIN2 VOUT1 VOUT2 VB1 IB1 +XM1_f0 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f4 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f5 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f6 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f7 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f4 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f5 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f6 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f7 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM3_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM3_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM3_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM3_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM3_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM3_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM3_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM4_f0 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM4_f1 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM4_f2 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM4_f3 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM4_f4 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM4_f5 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM4_f6 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM4_f7 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +.ends corpus_c07 diff --git a/benchmarks/code_behind_layout/configs/development/c07_family/references/dev_nf_1half.spice b/benchmarks/code_behind_layout/configs/development/c07_family/references/dev_nf_1half.spice new file mode 100644 index 00000000..9e4bd035 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c07_family/references/dev_nf_1half.spice @@ -0,0 +1,50 @@ +.subckt corpus_c07 VDD VSS VIN1 VIN2 VOUT1 VOUT2 VB1 IB1 +XM1_f0 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f8 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f9 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f10 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f11 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f8 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f9 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f10 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f11 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f8 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f9 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f10 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f11 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f0 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f1 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f2 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f3 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f4 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f5 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f6 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f7 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f8 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f9 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f10 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f11 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_c07 diff --git a/benchmarks/code_behind_layout/configs/development/c07_family/references/dev_nf_3quarters.spice b/benchmarks/code_behind_layout/configs/development/c07_family/references/dev_nf_3quarters.spice new file mode 100644 index 00000000..843188fe --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c07_family/references/dev_nf_3quarters.spice @@ -0,0 +1,26 @@ +.subckt corpus_c07 VDD VSS VIN1 VIN2 VOUT1 VOUT2 VB1 IB1 +XM1_f0 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f0 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f1 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f2 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f3 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f4 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f5 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_c07 diff --git a/benchmarks/code_behind_layout/configs/development/c07_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c07_family/references/dev_nf_double.spice new file mode 100644 index 00000000..dbfcb705 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c07_family/references/dev_nf_double.spice @@ -0,0 +1,66 @@ +.subckt corpus_c07 VDD VSS VIN1 VIN2 VOUT1 VOUT2 VB1 IB1 +XM1_f0 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f8 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f9 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f10 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f11 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f12 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f13 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f14 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f15 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f8 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f9 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f10 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f11 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f12 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f13 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f14 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f15 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f8 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f9 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f10 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f11 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f12 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f13 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f14 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f15 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f0 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f1 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f2 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f3 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f4 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f5 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f6 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f7 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f8 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f9 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f10 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f11 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f12 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f13 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f14 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f15 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_c07 diff --git a/benchmarks/code_behind_layout/configs/development/c07_family/references/dev_nf_half.spice b/benchmarks/code_behind_layout/configs/development/c07_family/references/dev_nf_half.spice new file mode 100644 index 00000000..dd1cf190 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c07_family/references/dev_nf_half.spice @@ -0,0 +1,18 @@ +.subckt corpus_c07 VDD VSS VIN1 VIN2 VOUT1 VOUT2 VB1 IB1 +XM1_f0 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f0 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f1 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f2 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f3 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_c07 diff --git a/benchmarks/code_behind_layout/configs/development/c07_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c07_family/references/dev_unit075.spice new file mode 100644 index 00000000..c487a65a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c07_family/references/dev_unit075.spice @@ -0,0 +1,34 @@ +.subckt corpus_c07 VDD VSS VIN1 VIN2 VOUT1 VOUT2 VB1 IB1 +XM1_f0 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f1 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f2 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f3 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f4 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f5 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f6 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f7 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f0 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f1 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f2 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f3 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f4 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f5 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f6 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f7 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM3_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM3_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM3_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM3_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM3_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM3_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM3_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM4_f0 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM4_f1 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM4_f2 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM4_f3 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM4_f4 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM4_f5 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM4_f6 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM4_f7 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +.ends corpus_c07 diff --git a/benchmarks/code_behind_layout/configs/development/c07_family/references/dev_unit100.spice b/benchmarks/code_behind_layout/configs/development/c07_family/references/dev_unit100.spice new file mode 100644 index 00000000..3946d90f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c07_family/references/dev_unit100.spice @@ -0,0 +1,34 @@ +.subckt corpus_c07 VDD VSS VIN1 VIN2 VOUT1 VOUT2 VB1 IB1 +XM1_f0 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f1 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f2 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f3 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f4 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f5 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f6 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f7 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f0 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f1 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f2 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f3 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f4 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f5 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f6 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f7 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM3_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM3_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM3_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM3_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM3_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM3_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM3_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM4_f0 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM4_f1 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM4_f2 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM4_f3 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM4_f4 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM4_f5 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM4_f6 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM4_f7 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +.ends corpus_c07 diff --git a/benchmarks/code_behind_layout/configs/development/c08_collection_preparation.json b/benchmarks/code_behind_layout/configs/development/c08_collection_preparation.json new file mode 100644 index 00000000..979f923f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c08_collection_preparation.json @@ -0,0 +1,2236 @@ +{ + "status": "DRAFT_READONLY_COLLECTION_CAPSULE_NOT_FROZEN", + "circuit_id": "C08", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "source_pack": "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1/source_pack", + "source_files": [ + "LICENSE", + "circuit_input.json", + "generator.py", + "glayout/__init__.py", + "glayout/backend/__init__.py", + "glayout/backend/_gdsfactory.py", + "glayout/backend/_gdstk.py", + "glayout/pdk/__init__.py", + "glayout/pdk/gf180_mapped/__init__.py", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x02p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x04p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x08p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x16p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_05p00x05p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_10p00x10p00.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_05p00x00p42.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_05p00x05p00.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_10p00x00p42.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_10p00x10p00.gds", + "glayout/pdk/gf180_mapped/gf180_grules.py", + "glayout/pdk/gf180_mapped/gf180_mapped.py", + "glayout/pdk/gf180_mapped/gf180mcu.drc", + "glayout/pdk/gf180_mapped/gf180mcu_drc.lydrc", + "glayout/pdk/gf180_mapped/gf180mcu_drc_wrapper.drc", + "glayout/pdk/gf180_mapped/gf180mcu_osu_sc_9T.spice", + "glayout/pdk/ihp130_mapped/__init__.py", + "glayout/pdk/ihp130_mapped/ihp130_drc.lydrc", + "glayout/pdk/ihp130_mapped/ihp130_grules.py", + "glayout/pdk/ihp130_mapped/ihp130_mapped.py", + "glayout/pdk/mappedpdk.py", + "glayout/pdk/sky130_mapped/__init__.py", + "glayout/pdk/sky130_mapped/sky130.lydrc", + "glayout/pdk/sky130_mapped/sky130_add_npc.py", + "glayout/pdk/sky130_mapped/sky130_fd_sc_hd.spice", + "glayout/pdk/sky130_mapped/sky130_grules.py", + "glayout/pdk/sky130_mapped/sky130_mapped.py", + "glayout/placement/__init__.py", + "glayout/placement/common_centroid_ab_ba.py", + "glayout/placement/four_transistor_interdigitized.py", + "glayout/placement/two_transistor_interdigitized.py", + "glayout/placement/two_transistor_place.py", + "glayout/primitives/__init__.py", + "glayout/primitives/bjt.py", + "glayout/primitives/fet.py", + "glayout/primitives/guardring.py", + "glayout/primitives/mimcap.py", + "glayout/primitives/resistor.py", + "glayout/primitives/via_gen.py", + "glayout/routing/L_route.py", + "glayout/routing/__init__.py", + "glayout/routing/c_route.py", + "glayout/routing/smart_route.py", + "glayout/routing/straight_route.py", + "glayout/sharing/README.md", + "glayout/sharing/__init__.py", + "glayout/sharing/enumeration.py", + "glayout/sharing/evidence.py", + "glayout/sharing/group.py", + "glayout/sharing/rules.py", + "glayout/sharing/spec.py", + "glayout/spice/__init__.py", + "glayout/spice/netlist.py", + "glayout/util/__init__.py", + "glayout/util/comp_utils.py", + "glayout/util/component_array_create.py", + "glayout/util/geometry.py", + "glayout/util/pattern.py", + "glayout/util/port_utils.py", + "glayout/util/print_rules.py", + "glayout/util/routing.py", + "glayout/util/snap_to_grid.py", + "sizing_input.json", + "textbook_sharing/__init__.py", + "textbook_sharing/assembly/__init__.py", + "textbook_sharing/assembly/adapters.py", + "textbook_sharing/assembly/engine.py", + "textbook_sharing/assembly/passives.py", + "textbook_sharing/assembly/pincell.py", + "textbook_sharing/layout.py", + "textbook_sharing/netlist.py" + ], + "editable_paths": [ + "textbook_sharing/layout.py" + ], + "trusted_bundle": "/srv/code-behind-layout/runtime/collection_preparation/c08_collection_20261019T015607178027Z/trusted", + "trusted_files": [ + "contracts/anchor.json", + "contracts/dev_len045.json", + "contracts/dev_len060.json", + "contracts/dev_nf_1half.json", + "contracts/dev_nf_3quarters.json", + "contracts/dev_nf_double.json", + "contracts/dev_nf_half.json", + "contracts/dev_unit075.json", + "contracts/dev_unit100.json", + "evaluate.py", + "physical.py", + "references/anchor.spice", + "references/dev_len045.spice", + "references/dev_len060.spice", + "references/dev_nf_1half.spice", + "references/dev_nf_3quarters.spice", + "references/dev_nf_double.spice", + "references/dev_nf_half.spice", + "references/dev_unit075.spice", + "references/dev_unit100.spice", + "run_pex.sh", + "src/__init__.py", + "src/corpus_metrics.py", + "src/measurement.py", + "src/physical_drc.py", + "src/report_parsers.py", + "src/spice_validation.py" + ], + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "reference_id": "c08_anchor_independent_perfinger", + "contract": { + "task_id": "train_collection_c08", + "configuration_id": "anchor", + "reference_id": "c08_anchor_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_COLLECTION_AFTER_ACTUAL_NINE_POINT_QUALIFICATION", + "objective": { + "id": "c08_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_dB", + "unit": "dB", + "min": 25 + }, + { + "name": "ugb_Hz", + "unit": "Hz", + "min": 10000000.0 + }, + { + "name": "phase_margin_deg", + "unit": "deg", + "min": 60 + }, + { + "name": "settled_tracking_error_V", + "unit": "V", + "max": 0.015 + }, + { + "name": "DUT_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 0.9, + "load_C_F": 1e-12, + "replica_current_A": 4e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.6, + "end": 1.2, + "points": 7, + "scale": "linear" + } + } + }, + "parameters": { + "configuration_id": "anchor", + "circuit": { + "circuit_id": "C08", + "name": "five_transistor_ota", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VIN2", + "VOUT1", + "VB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "net22", + "VIN1", + "net23", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN2", + "net23", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "net23", + "VB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "pfet", + "nets": [ + "net22", + "net22", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M5", + "kind": "pfet", + "nets": [ + "VOUT1", + "net22", + "VDD", + "VDD" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 157, + "files": [ + "Dataset/157/157.cir", + "Dataset/157/Port157.txt", + "Dataset/157/Pagenumber157.txt", + "Dataset/157/Book157.png", + "Dataset/157/Cadence157.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "171", + "device_name_map": { + "M1": "M2", + "M2": "M3", + "M3": "M4", + "M4": "M0", + "M5": "M1" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/157/Book157.png", + "observation": "Razavi p.171 scan: M1/M2 pair, M3 diode / M4 mirror PMOS load, M5 tail (Vb)" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M3": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M4": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M5": { + "w": 2.0, + "l": 0.3, + "nf": 4 + } + }, + "top_cell": "corpus_c08" + } + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "reference_id": "c08_dev_nf_half_independent_perfinger", + "contract": { + "task_id": "train_collection_c08", + "configuration_id": "dev_nf_half", + "reference_id": "c08_dev_nf_half_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_COLLECTION_AFTER_ACTUAL_NINE_POINT_QUALIFICATION", + "objective": { + "id": "c08_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_dB", + "unit": "dB", + "min": 25 + }, + { + "name": "ugb_Hz", + "unit": "Hz", + "min": 10000000.0 + }, + { + "name": "phase_margin_deg", + "unit": "deg", + "min": 60 + }, + { + "name": "settled_tracking_error_V", + "unit": "V", + "max": 0.015 + }, + { + "name": "DUT_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 0.9, + "load_C_F": 1e-12, + "replica_current_A": 4e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.6, + "end": 1.2, + "points": 7, + "scale": "linear" + } + } + }, + "parameters": { + "configuration_id": "dev_nf_half", + "circuit": { + "circuit_id": "C08", + "name": "five_transistor_ota", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VIN2", + "VOUT1", + "VB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "net22", + "VIN1", + "net23", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN2", + "net23", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "net23", + "VB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "pfet", + "nets": [ + "net22", + "net22", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M5", + "kind": "pfet", + "nets": [ + "VOUT1", + "net22", + "VDD", + "VDD" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 157, + "files": [ + "Dataset/157/157.cir", + "Dataset/157/Port157.txt", + "Dataset/157/Pagenumber157.txt", + "Dataset/157/Book157.png", + "Dataset/157/Cadence157.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "171", + "device_name_map": { + "M1": "M2", + "M2": "M3", + "M3": "M4", + "M4": "M0", + "M5": "M1" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/157/Book157.png", + "observation": "Razavi p.171 scan: M1/M2 pair, M3 diode / M4 mirror PMOS load, M5 tail (Vb)" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M3": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M4": { + "w": 1.0, + "l": 0.3, + "nf": 2 + }, + "M5": { + "w": 1.0, + "l": 0.3, + "nf": 2 + } + }, + "top_cell": "corpus_c08" + } + }, + { + "configuration_id": "dev_nf_3quarters", + "role": "development", + "reference_id": "c08_dev_nf_3quarters_independent_perfinger", + "contract": { + "task_id": "train_collection_c08", + "configuration_id": "dev_nf_3quarters", + "reference_id": "c08_dev_nf_3quarters_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_COLLECTION_AFTER_ACTUAL_NINE_POINT_QUALIFICATION", + "objective": { + "id": "c08_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_dB", + "unit": "dB", + "min": 25 + }, + { + "name": "ugb_Hz", + "unit": "Hz", + "min": 10000000.0 + }, + { + "name": "phase_margin_deg", + "unit": "deg", + "min": 60 + }, + { + "name": "settled_tracking_error_V", + "unit": "V", + "max": 0.015 + }, + { + "name": "DUT_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 0.9, + "load_C_F": 1e-12, + "replica_current_A": 4e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.6, + "end": 1.2, + "points": 7, + "scale": "linear" + } + } + }, + "parameters": { + "configuration_id": "dev_nf_3quarters", + "circuit": { + "circuit_id": "C08", + "name": "five_transistor_ota", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VIN2", + "VOUT1", + "VB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "net22", + "VIN1", + "net23", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN2", + "net23", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "net23", + "VB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "pfet", + "nets": [ + "net22", + "net22", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M5", + "kind": "pfet", + "nets": [ + "VOUT1", + "net22", + "VDD", + "VDD" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 157, + "files": [ + "Dataset/157/157.cir", + "Dataset/157/Port157.txt", + "Dataset/157/Pagenumber157.txt", + "Dataset/157/Book157.png", + "Dataset/157/Cadence157.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "171", + "device_name_map": { + "M1": "M2", + "M2": "M3", + "M3": "M4", + "M4": "M0", + "M5": "M1" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/157/Book157.png", + "observation": "Razavi p.171 scan: M1/M2 pair, M3 diode / M4 mirror PMOS load, M5 tail (Vb)" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M2": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M3": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M4": { + "w": 1.5, + "l": 0.3, + "nf": 3 + }, + "M5": { + "w": 1.5, + "l": 0.3, + "nf": 3 + } + }, + "top_cell": "corpus_c08" + } + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "reference_id": "c08_dev_nf_1half_independent_perfinger", + "contract": { + "task_id": "train_collection_c08", + "configuration_id": "dev_nf_1half", + "reference_id": "c08_dev_nf_1half_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_COLLECTION_AFTER_ACTUAL_NINE_POINT_QUALIFICATION", + "objective": { + "id": "c08_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_dB", + "unit": "dB", + "min": 25 + }, + { + "name": "ugb_Hz", + "unit": "Hz", + "min": 10000000.0 + }, + { + "name": "phase_margin_deg", + "unit": "deg", + "min": 60 + }, + { + "name": "settled_tracking_error_V", + "unit": "V", + "max": 0.015 + }, + { + "name": "DUT_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 0.9, + "load_C_F": 1e-12, + "replica_current_A": 4e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.6, + "end": 1.2, + "points": 7, + "scale": "linear" + } + } + }, + "parameters": { + "configuration_id": "dev_nf_1half", + "circuit": { + "circuit_id": "C08", + "name": "five_transistor_ota", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VIN2", + "VOUT1", + "VB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "net22", + "VIN1", + "net23", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN2", + "net23", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "net23", + "VB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "pfet", + "nets": [ + "net22", + "net22", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M5", + "kind": "pfet", + "nets": [ + "VOUT1", + "net22", + "VDD", + "VDD" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 157, + "files": [ + "Dataset/157/157.cir", + "Dataset/157/Port157.txt", + "Dataset/157/Pagenumber157.txt", + "Dataset/157/Book157.png", + "Dataset/157/Cadence157.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "171", + "device_name_map": { + "M1": "M2", + "M2": "M3", + "M3": "M4", + "M4": "M0", + "M5": "M1" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/157/Book157.png", + "observation": "Razavi p.171 scan: M1/M2 pair, M3 diode / M4 mirror PMOS load, M5 tail (Vb)" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M3": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M4": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M5": { + "w": 3.0, + "l": 0.3, + "nf": 6 + } + }, + "top_cell": "corpus_c08" + } + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "reference_id": "c08_dev_nf_double_independent_perfinger", + "contract": { + "task_id": "train_collection_c08", + "configuration_id": "dev_nf_double", + "reference_id": "c08_dev_nf_double_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_COLLECTION_AFTER_ACTUAL_NINE_POINT_QUALIFICATION", + "objective": { + "id": "c08_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_dB", + "unit": "dB", + "min": 25 + }, + { + "name": "ugb_Hz", + "unit": "Hz", + "min": 10000000.0 + }, + { + "name": "phase_margin_deg", + "unit": "deg", + "min": 60 + }, + { + "name": "settled_tracking_error_V", + "unit": "V", + "max": 0.015 + }, + { + "name": "DUT_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 0.9, + "load_C_F": 1e-12, + "replica_current_A": 4e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.6, + "end": 1.2, + "points": 7, + "scale": "linear" + } + } + }, + "parameters": { + "configuration_id": "dev_nf_double", + "circuit": { + "circuit_id": "C08", + "name": "five_transistor_ota", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VIN2", + "VOUT1", + "VB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "net22", + "VIN1", + "net23", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN2", + "net23", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "net23", + "VB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "pfet", + "nets": [ + "net22", + "net22", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M5", + "kind": "pfet", + "nets": [ + "VOUT1", + "net22", + "VDD", + "VDD" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 157, + "files": [ + "Dataset/157/157.cir", + "Dataset/157/Port157.txt", + "Dataset/157/Pagenumber157.txt", + "Dataset/157/Book157.png", + "Dataset/157/Cadence157.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "171", + "device_name_map": { + "M1": "M2", + "M2": "M3", + "M3": "M4", + "M4": "M0", + "M5": "M1" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/157/Book157.png", + "observation": "Razavi p.171 scan: M1/M2 pair, M3 diode / M4 mirror PMOS load, M5 tail (Vb)" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 8.0, + "l": 0.3, + "nf": 16 + }, + "M2": { + "w": 8.0, + "l": 0.3, + "nf": 16 + }, + "M3": { + "w": 8.0, + "l": 0.3, + "nf": 16 + }, + "M4": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M5": { + "w": 4.0, + "l": 0.3, + "nf": 8 + } + }, + "top_cell": "corpus_c08" + } + }, + { + "configuration_id": "dev_len045", + "role": "development", + "reference_id": "c08_dev_len045_independent_perfinger", + "contract": { + "task_id": "train_collection_c08", + "configuration_id": "dev_len045", + "reference_id": "c08_dev_len045_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_COLLECTION_AFTER_ACTUAL_NINE_POINT_QUALIFICATION", + "objective": { + "id": "c08_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_dB", + "unit": "dB", + "min": 25 + }, + { + "name": "ugb_Hz", + "unit": "Hz", + "min": 10000000.0 + }, + { + "name": "phase_margin_deg", + "unit": "deg", + "min": 60 + }, + { + "name": "settled_tracking_error_V", + "unit": "V", + "max": 0.015 + }, + { + "name": "DUT_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 0.9, + "load_C_F": 1e-12, + "replica_current_A": 4e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.6, + "end": 1.2, + "points": 7, + "scale": "linear" + } + } + }, + "parameters": { + "configuration_id": "dev_len045", + "circuit": { + "circuit_id": "C08", + "name": "five_transistor_ota", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VIN2", + "VOUT1", + "VB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "net22", + "VIN1", + "net23", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN2", + "net23", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "net23", + "VB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "pfet", + "nets": [ + "net22", + "net22", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M5", + "kind": "pfet", + "nets": [ + "VOUT1", + "net22", + "VDD", + "VDD" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 157, + "files": [ + "Dataset/157/157.cir", + "Dataset/157/Port157.txt", + "Dataset/157/Pagenumber157.txt", + "Dataset/157/Book157.png", + "Dataset/157/Cadence157.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "171", + "device_name_map": { + "M1": "M2", + "M2": "M3", + "M3": "M4", + "M4": "M0", + "M5": "M1" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/157/Book157.png", + "observation": "Razavi p.171 scan: M1/M2 pair, M3 diode / M4 mirror PMOS load, M5 tail (Vb)" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 4.0, + "l": 0.45, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.45, + "nf": 8 + }, + "M3": { + "w": 4.0, + "l": 0.45, + "nf": 8 + }, + "M4": { + "w": 2.0, + "l": 0.45, + "nf": 4 + }, + "M5": { + "w": 2.0, + "l": 0.45, + "nf": 4 + } + }, + "top_cell": "corpus_c08" + } + }, + { + "configuration_id": "dev_len060", + "role": "development", + "reference_id": "c08_dev_len060_independent_perfinger", + "contract": { + "task_id": "train_collection_c08", + "configuration_id": "dev_len060", + "reference_id": "c08_dev_len060_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_COLLECTION_AFTER_ACTUAL_NINE_POINT_QUALIFICATION", + "objective": { + "id": "c08_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_dB", + "unit": "dB", + "min": 25 + }, + { + "name": "ugb_Hz", + "unit": "Hz", + "min": 10000000.0 + }, + { + "name": "phase_margin_deg", + "unit": "deg", + "min": 60 + }, + { + "name": "settled_tracking_error_V", + "unit": "V", + "max": 0.015 + }, + { + "name": "DUT_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 0.9, + "load_C_F": 1e-12, + "replica_current_A": 4e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.6, + "end": 1.2, + "points": 7, + "scale": "linear" + } + } + }, + "parameters": { + "configuration_id": "dev_len060", + "circuit": { + "circuit_id": "C08", + "name": "five_transistor_ota", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VIN2", + "VOUT1", + "VB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "net22", + "VIN1", + "net23", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN2", + "net23", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "net23", + "VB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "pfet", + "nets": [ + "net22", + "net22", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M5", + "kind": "pfet", + "nets": [ + "VOUT1", + "net22", + "VDD", + "VDD" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 157, + "files": [ + "Dataset/157/157.cir", + "Dataset/157/Port157.txt", + "Dataset/157/Pagenumber157.txt", + "Dataset/157/Book157.png", + "Dataset/157/Cadence157.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "171", + "device_name_map": { + "M1": "M2", + "M2": "M3", + "M3": "M4", + "M4": "M0", + "M5": "M1" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/157/Book157.png", + "observation": "Razavi p.171 scan: M1/M2 pair, M3 diode / M4 mirror PMOS load, M5 tail (Vb)" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "M3": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "M4": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M5": { + "w": 2.0, + "l": 0.6, + "nf": 4 + } + }, + "top_cell": "corpus_c08" + } + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "reference_id": "c08_dev_unit075_independent_perfinger", + "contract": { + "task_id": "train_collection_c08", + "configuration_id": "dev_unit075", + "reference_id": "c08_dev_unit075_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_COLLECTION_AFTER_ACTUAL_NINE_POINT_QUALIFICATION", + "objective": { + "id": "c08_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_dB", + "unit": "dB", + "min": 25 + }, + { + "name": "ugb_Hz", + "unit": "Hz", + "min": 10000000.0 + }, + { + "name": "phase_margin_deg", + "unit": "deg", + "min": 60 + }, + { + "name": "settled_tracking_error_V", + "unit": "V", + "max": 0.015 + }, + { + "name": "DUT_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 0.9, + "load_C_F": 1e-12, + "replica_current_A": 4e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.6, + "end": 1.2, + "points": 7, + "scale": "linear" + } + } + }, + "parameters": { + "configuration_id": "dev_unit075", + "circuit": { + "circuit_id": "C08", + "name": "five_transistor_ota", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VIN2", + "VOUT1", + "VB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "net22", + "VIN1", + "net23", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN2", + "net23", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "net23", + "VB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "pfet", + "nets": [ + "net22", + "net22", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M5", + "kind": "pfet", + "nets": [ + "VOUT1", + "net22", + "VDD", + "VDD" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 157, + "files": [ + "Dataset/157/157.cir", + "Dataset/157/Port157.txt", + "Dataset/157/Pagenumber157.txt", + "Dataset/157/Book157.png", + "Dataset/157/Cadence157.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "171", + "device_name_map": { + "M1": "M2", + "M2": "M3", + "M3": "M4", + "M4": "M0", + "M5": "M1" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/157/Book157.png", + "observation": "Razavi p.171 scan: M1/M2 pair, M3 diode / M4 mirror PMOS load, M5 tail (Vb)" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 6.0, + "l": 0.3, + "nf": 8 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 8 + }, + "M3": { + "w": 6.0, + "l": 0.3, + "nf": 8 + }, + "M4": { + "w": 3.0, + "l": 0.3, + "nf": 4 + }, + "M5": { + "w": 3.0, + "l": 0.3, + "nf": 4 + } + }, + "top_cell": "corpus_c08" + } + }, + { + "configuration_id": "dev_unit100", + "role": "development", + "reference_id": "c08_dev_unit100_independent_perfinger", + "contract": { + "task_id": "train_collection_c08", + "configuration_id": "dev_unit100", + "reference_id": "c08_dev_unit100_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_COLLECTION_AFTER_ACTUAL_NINE_POINT_QUALIFICATION", + "objective": { + "id": "c08_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_dB", + "unit": "dB", + "min": 25 + }, + { + "name": "ugb_Hz", + "unit": "Hz", + "min": 10000000.0 + }, + { + "name": "phase_margin_deg", + "unit": "deg", + "min": 60 + }, + { + "name": "settled_tracking_error_V", + "unit": "V", + "max": 0.015 + }, + { + "name": "DUT_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 0.9, + "load_C_F": 1e-12, + "replica_current_A": 4e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.6, + "end": 1.2, + "points": 7, + "scale": "linear" + } + } + }, + "parameters": { + "configuration_id": "dev_unit100", + "circuit": { + "circuit_id": "C08", + "name": "five_transistor_ota", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VIN2", + "VOUT1", + "VB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "net22", + "VIN1", + "net23", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN2", + "net23", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "net23", + "VB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "pfet", + "nets": [ + "net22", + "net22", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M5", + "kind": "pfet", + "nets": [ + "VOUT1", + "net22", + "VDD", + "VDD" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 157, + "files": [ + "Dataset/157/157.cir", + "Dataset/157/Port157.txt", + "Dataset/157/Pagenumber157.txt", + "Dataset/157/Book157.png", + "Dataset/157/Cadence157.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "171", + "device_name_map": { + "M1": "M2", + "M2": "M3", + "M3": "M4", + "M4": "M0", + "M5": "M1" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/157/Book157.png", + "observation": "Razavi p.171 scan: M1/M2 pair, M3 diode / M4 mirror PMOS load, M5 tail (Vb)" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 8.0, + "l": 0.3, + "nf": 8 + }, + "M2": { + "w": 8.0, + "l": 0.3, + "nf": 8 + }, + "M3": { + "w": 8.0, + "l": 0.3, + "nf": 8 + }, + "M4": { + "w": 4.0, + "l": 0.3, + "nf": 4 + }, + "M5": { + "w": 4.0, + "l": 0.3, + "nf": 4 + } + }, + "top_cell": "corpus_c08" + } + } + ], + "qualification_path": "/srv/code-behind-layout/results/derived/C05_C08_domain_development_qualification.json", + "prospective_hard_specifications": [ + { + "name": "gain_10Hz_dB", + "unit": "dB", + "min": 25 + }, + { + "name": "ugb_Hz", + "unit": "Hz", + "min": 10000000.0 + }, + { + "name": "phase_margin_deg", + "unit": "deg", + "min": 60 + }, + { + "name": "settled_tracking_error_V", + "unit": "V", + "max": 0.015 + }, + { + "name": "DUT_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "objective": { + "id": "c08_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "label_rule_draft": { + "objectives": { + "c08_area_min": { + "metric": "area", + "unit": "um2", + "direction": "min", + "quality_absolute_tolerance": 1e-08, + "quality_relative_tolerance": 1e-06, + "quality_minimum_relative_effect": 0.01 + } + } + }, + "source_scope_note": "Actual generic C01-v1 source capsule is reused byte-for-byte; generator.py consumes the host configuration, not the unused frozen circuit_input.json. The sole editable layout.py is the same compiler lineage.", + "power_scope": "DUT supply only; external20uA/40uA diode-bias power recorded separately. Three process corners at1.8V/27C.", + "formal_collection_started": false, + "old_development_evidence_relabelled": false +} diff --git a/benchmarks/code_behind_layout/configs/development/c08_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c08_family/configurations.json new file mode 100644 index 00000000..3364f1c2 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c08_family/configurations.json @@ -0,0 +1,324 @@ +{ + "scope": "development_only_train_domain_qualification_not_frozen", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C08", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M3": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M4": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M5": { + "w": 2.0, + "l": 0.3, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c08_family/references/anchor.spice", + "contract_file": "configs/development/c08_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M3": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M4": { + "w": 1.0, + "l": 0.3, + "nf": 2 + }, + "M5": { + "w": 1.0, + "l": 0.3, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c08_family/references/dev_nf_half.spice", + "contract_file": "configs/development/c08_family/contracts/dev_nf_half.json" + }, + { + "configuration_id": "dev_nf_3quarters", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M2": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M3": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M4": { + "w": 1.5, + "l": 0.3, + "nf": 3 + }, + "M5": { + "w": 1.5, + "l": 0.3, + "nf": 3 + } + } + }, + "reference_file": "configs/development/c08_family/references/dev_nf_3quarters.spice", + "contract_file": "configs/development/c08_family/contracts/dev_nf_3quarters.json" + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M3": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M4": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M5": { + "w": 3.0, + "l": 0.3, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c08_family/references/dev_nf_1half.spice", + "contract_file": "configs/development/c08_family/contracts/dev_nf_1half.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 8.0, + "l": 0.3, + "nf": 16 + }, + "M2": { + "w": 8.0, + "l": 0.3, + "nf": 16 + }, + "M3": { + "w": 8.0, + "l": 0.3, + "nf": 16 + }, + "M4": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M5": { + "w": 4.0, + "l": 0.3, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c08_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c08_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len045", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.45, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.45, + "nf": 8 + }, + "M3": { + "w": 4.0, + "l": 0.45, + "nf": 8 + }, + "M4": { + "w": 2.0, + "l": 0.45, + "nf": 4 + }, + "M5": { + "w": 2.0, + "l": 0.45, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c08_family/references/dev_len045.spice", + "contract_file": "configs/development/c08_family/contracts/dev_len045.json" + }, + { + "configuration_id": "dev_len060", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "M3": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "M4": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M5": { + "w": 2.0, + "l": 0.6, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c08_family/references/dev_len060.spice", + "contract_file": "configs/development/c08_family/contracts/dev_len060.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.3, + "nf": 8 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 8 + }, + "M3": { + "w": 6.0, + "l": 0.3, + "nf": 8 + }, + "M4": { + "w": 3.0, + "l": 0.3, + "nf": 4 + }, + "M5": { + "w": 3.0, + "l": 0.3, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c08_family/references/dev_unit075.spice", + "contract_file": "configs/development/c08_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_unit100", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 8.0, + "l": 0.3, + "nf": 8 + }, + "M2": { + "w": 8.0, + "l": 0.3, + "nf": 8 + }, + "M3": { + "w": 8.0, + "l": 0.3, + "nf": 8 + }, + "M4": { + "w": 4.0, + "l": 0.3, + "nf": 4 + }, + "M5": { + "w": 4.0, + "l": 0.3, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c08_family/references/dev_unit100.spice", + "contract_file": "configs/development/c08_family/contracts/dev_unit100.json" + } + ], + "identity_note": "One universal compiler lineage; geometry points are not independent source programs. No old data are relabeled." +} diff --git a/benchmarks/code_behind_layout/configs/development/c08_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c08_family/contracts/anchor.json new file mode 100644 index 00000000..65ba174f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c08_family/contracts/anchor.json @@ -0,0 +1,86 @@ +{ + "task_id": "development_train_domain_C08", + "configuration_id": "anchor", + "reference_id": "c08_anchor_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c08_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_dB", + "unit": "dB", + "min": 25 + }, + { + "name": "phase_margin_deg", + "unit": "deg", + "min": 60 + }, + { + "name": "settled_tracking_error_V", + "unit": "V", + "max": 0.015 + } + ], + "pending_before_freeze": [ + "bandwidth_floor_Hz_from_actual_baseline_qualification", + "DUT_supply_power_ceiling_W_from_actual_baseline_qualification" + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 0.9, + "load_C_F": 1e-12, + "replica_current_A": 4e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.6, + "end": 1.2, + "points": 7, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_len045.json b/benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_len045.json new file mode 100644 index 00000000..62dd48b0 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_len045.json @@ -0,0 +1,86 @@ +{ + "task_id": "development_train_domain_C08", + "configuration_id": "dev_len045", + "reference_id": "c08_dev_len045_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c08_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_dB", + "unit": "dB", + "min": 25 + }, + { + "name": "phase_margin_deg", + "unit": "deg", + "min": 60 + }, + { + "name": "settled_tracking_error_V", + "unit": "V", + "max": 0.015 + } + ], + "pending_before_freeze": [ + "bandwidth_floor_Hz_from_actual_baseline_qualification", + "DUT_supply_power_ceiling_W_from_actual_baseline_qualification" + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 0.9, + "load_C_F": 1e-12, + "replica_current_A": 4e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.6, + "end": 1.2, + "points": 7, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_len060.json b/benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_len060.json new file mode 100644 index 00000000..206c7489 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_len060.json @@ -0,0 +1,86 @@ +{ + "task_id": "development_train_domain_C08", + "configuration_id": "dev_len060", + "reference_id": "c08_dev_len060_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c08_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_dB", + "unit": "dB", + "min": 25 + }, + { + "name": "phase_margin_deg", + "unit": "deg", + "min": 60 + }, + { + "name": "settled_tracking_error_V", + "unit": "V", + "max": 0.015 + } + ], + "pending_before_freeze": [ + "bandwidth_floor_Hz_from_actual_baseline_qualification", + "DUT_supply_power_ceiling_W_from_actual_baseline_qualification" + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 0.9, + "load_C_F": 1e-12, + "replica_current_A": 4e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.6, + "end": 1.2, + "points": 7, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_nf_1half.json b/benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_nf_1half.json new file mode 100644 index 00000000..d2dd6c0d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_nf_1half.json @@ -0,0 +1,86 @@ +{ + "task_id": "development_train_domain_C08", + "configuration_id": "dev_nf_1half", + "reference_id": "c08_dev_nf_1half_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c08_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_dB", + "unit": "dB", + "min": 25 + }, + { + "name": "phase_margin_deg", + "unit": "deg", + "min": 60 + }, + { + "name": "settled_tracking_error_V", + "unit": "V", + "max": 0.015 + } + ], + "pending_before_freeze": [ + "bandwidth_floor_Hz_from_actual_baseline_qualification", + "DUT_supply_power_ceiling_W_from_actual_baseline_qualification" + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 0.9, + "load_C_F": 1e-12, + "replica_current_A": 4e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.6, + "end": 1.2, + "points": 7, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_nf_3quarters.json b/benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_nf_3quarters.json new file mode 100644 index 00000000..b59f3b74 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_nf_3quarters.json @@ -0,0 +1,86 @@ +{ + "task_id": "development_train_domain_C08", + "configuration_id": "dev_nf_3quarters", + "reference_id": "c08_dev_nf_3quarters_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c08_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_dB", + "unit": "dB", + "min": 25 + }, + { + "name": "phase_margin_deg", + "unit": "deg", + "min": 60 + }, + { + "name": "settled_tracking_error_V", + "unit": "V", + "max": 0.015 + } + ], + "pending_before_freeze": [ + "bandwidth_floor_Hz_from_actual_baseline_qualification", + "DUT_supply_power_ceiling_W_from_actual_baseline_qualification" + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 0.9, + "load_C_F": 1e-12, + "replica_current_A": 4e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.6, + "end": 1.2, + "points": 7, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..c34bccf6 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_nf_double.json @@ -0,0 +1,86 @@ +{ + "task_id": "development_train_domain_C08", + "configuration_id": "dev_nf_double", + "reference_id": "c08_dev_nf_double_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c08_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_dB", + "unit": "dB", + "min": 25 + }, + { + "name": "phase_margin_deg", + "unit": "deg", + "min": 60 + }, + { + "name": "settled_tracking_error_V", + "unit": "V", + "max": 0.015 + } + ], + "pending_before_freeze": [ + "bandwidth_floor_Hz_from_actual_baseline_qualification", + "DUT_supply_power_ceiling_W_from_actual_baseline_qualification" + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 0.9, + "load_C_F": 1e-12, + "replica_current_A": 4e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.6, + "end": 1.2, + "points": 7, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_nf_half.json b/benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_nf_half.json new file mode 100644 index 00000000..0a3f1f38 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_nf_half.json @@ -0,0 +1,86 @@ +{ + "task_id": "development_train_domain_C08", + "configuration_id": "dev_nf_half", + "reference_id": "c08_dev_nf_half_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c08_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_dB", + "unit": "dB", + "min": 25 + }, + { + "name": "phase_margin_deg", + "unit": "deg", + "min": 60 + }, + { + "name": "settled_tracking_error_V", + "unit": "V", + "max": 0.015 + } + ], + "pending_before_freeze": [ + "bandwidth_floor_Hz_from_actual_baseline_qualification", + "DUT_supply_power_ceiling_W_from_actual_baseline_qualification" + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 0.9, + "load_C_F": 1e-12, + "replica_current_A": 4e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.6, + "end": 1.2, + "points": 7, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_unit075.json new file mode 100644 index 00000000..be845b70 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_unit075.json @@ -0,0 +1,86 @@ +{ + "task_id": "development_train_domain_C08", + "configuration_id": "dev_unit075", + "reference_id": "c08_dev_unit075_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c08_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_dB", + "unit": "dB", + "min": 25 + }, + { + "name": "phase_margin_deg", + "unit": "deg", + "min": 60 + }, + { + "name": "settled_tracking_error_V", + "unit": "V", + "max": 0.015 + } + ], + "pending_before_freeze": [ + "bandwidth_floor_Hz_from_actual_baseline_qualification", + "DUT_supply_power_ceiling_W_from_actual_baseline_qualification" + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 0.9, + "load_C_F": 1e-12, + "replica_current_A": 4e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.6, + "end": 1.2, + "points": 7, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_unit100.json b/benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_unit100.json new file mode 100644 index 00000000..d0789532 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c08_family/contracts/dev_unit100.json @@ -0,0 +1,86 @@ +{ + "task_id": "development_train_domain_C08", + "configuration_id": "dev_unit100", + "reference_id": "c08_dev_unit100_independent_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "c08_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "gain_10Hz_dB", + "unit": "dB", + "min": 25 + }, + { + "name": "phase_margin_deg", + "unit": "deg", + "min": 60 + }, + { + "name": "settled_tracking_error_V", + "unit": "V", + "max": 0.015 + } + ], + "pending_before_freeze": [ + "bandwidth_floor_Hz_from_actual_baseline_qualification", + "DUT_supply_power_ceiling_W_from_actual_baseline_qualification" + ], + "power_definition": "VSUPPLY supplies DUT only; separate VBIASSUPPLY feeds external diode replica. Power is -1.8*i(VSUPPLY).", + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_V": 0.9, + "load_C_F": 1e-12, + "replica_current_A": 4e-05 + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.6, + "end": 1.2, + "points": 7, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c08_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c08_family/references/anchor.spice new file mode 100644 index 00000000..a966968e --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c08_family/references/anchor.spice @@ -0,0 +1,34 @@ +.subckt corpus_c08 VDD VSS VIN1 VIN2 VOUT1 VB1 +XM1_f0 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f6 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f7 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f0 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f1 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f2 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f3 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f4 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f5 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f6 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f7 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f0 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f1 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f2 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f3 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM5_f0 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM5_f1 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM5_f2 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM5_f3 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_c08 diff --git a/benchmarks/code_behind_layout/configs/development/c08_family/references/dev_len045.spice b/benchmarks/code_behind_layout/configs/development/c08_family/references/dev_len045.spice new file mode 100644 index 00000000..810b61c0 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c08_family/references/dev_len045.spice @@ -0,0 +1,34 @@ +.subckt corpus_c08 VDD VSS VIN1 VIN2 VOUT1 VB1 +XM1_f0 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f1 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f2 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f3 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f4 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f5 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f6 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f7 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f0 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f1 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f2 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f3 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f4 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f5 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f6 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f7 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f0 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f1 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f2 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f3 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f4 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f5 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f6 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f7 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f0 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM4_f1 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM4_f2 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM4_f3 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM5_f0 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM5_f1 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM5_f2 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM5_f3 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +.ends corpus_c08 diff --git a/benchmarks/code_behind_layout/configs/development/c08_family/references/dev_len060.spice b/benchmarks/code_behind_layout/configs/development/c08_family/references/dev_len060.spice new file mode 100644 index 00000000..e12577c1 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c08_family/references/dev_len060.spice @@ -0,0 +1,34 @@ +.subckt corpus_c08 VDD VSS VIN1 VIN2 VOUT1 VB1 +XM1_f0 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f4 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f5 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f6 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f7 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f4 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f5 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f6 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f7 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f0 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f1 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f2 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f3 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f4 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f5 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f6 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f7 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f0 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM4_f1 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM4_f2 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM4_f3 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM5_f0 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM5_f1 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM5_f2 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM5_f3 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +.ends corpus_c08 diff --git a/benchmarks/code_behind_layout/configs/development/c08_family/references/dev_nf_1half.spice b/benchmarks/code_behind_layout/configs/development/c08_family/references/dev_nf_1half.spice new file mode 100644 index 00000000..8c31eacf --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c08_family/references/dev_nf_1half.spice @@ -0,0 +1,50 @@ +.subckt corpus_c08 VDD VSS VIN1 VIN2 VOUT1 VB1 +XM1_f0 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f6 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f7 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f8 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f9 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f10 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f11 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f8 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f9 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f10 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f11 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f0 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f1 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f2 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f3 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f4 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f5 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f6 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f7 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f8 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f9 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f10 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f11 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f0 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f1 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f2 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f3 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f4 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f5 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM5_f0 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM5_f1 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM5_f2 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM5_f3 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM5_f4 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM5_f5 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_c08 diff --git a/benchmarks/code_behind_layout/configs/development/c08_family/references/dev_nf_3quarters.spice b/benchmarks/code_behind_layout/configs/development/c08_family/references/dev_nf_3quarters.spice new file mode 100644 index 00000000..96c0dfb8 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c08_family/references/dev_nf_3quarters.spice @@ -0,0 +1,26 @@ +.subckt corpus_c08 VDD VSS VIN1 VIN2 VOUT1 VB1 +XM1_f0 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f0 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f1 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f2 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f3 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f4 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f5 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f0 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f1 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f2 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM5_f0 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM5_f1 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM5_f2 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_c08 diff --git a/benchmarks/code_behind_layout/configs/development/c08_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c08_family/references/dev_nf_double.spice new file mode 100644 index 00000000..050e1664 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c08_family/references/dev_nf_double.spice @@ -0,0 +1,66 @@ +.subckt corpus_c08 VDD VSS VIN1 VIN2 VOUT1 VB1 +XM1_f0 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f6 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f7 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f8 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f9 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f10 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f11 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f12 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f13 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f14 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f15 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f8 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f9 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f10 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f11 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f12 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f13 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f14 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f15 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f0 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f1 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f2 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f3 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f4 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f5 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f6 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f7 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f8 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f9 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f10 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f11 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f12 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f13 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f14 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f15 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f0 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f1 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f2 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f3 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f4 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f5 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f6 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f7 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM5_f0 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM5_f1 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM5_f2 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM5_f3 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM5_f4 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM5_f5 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM5_f6 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM5_f7 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_c08 diff --git a/benchmarks/code_behind_layout/configs/development/c08_family/references/dev_nf_half.spice b/benchmarks/code_behind_layout/configs/development/c08_family/references/dev_nf_half.spice new file mode 100644 index 00000000..ad2dbd3d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c08_family/references/dev_nf_half.spice @@ -0,0 +1,18 @@ +.subckt corpus_c08 VDD VSS VIN1 VIN2 VOUT1 VB1 +XM1_f0 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f0 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f1 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f2 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f3 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f0 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f1 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM5_f0 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM5_f1 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_c08 diff --git a/benchmarks/code_behind_layout/configs/development/c08_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c08_family/references/dev_unit075.spice new file mode 100644 index 00000000..3938f21f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c08_family/references/dev_unit075.spice @@ -0,0 +1,34 @@ +.subckt corpus_c08 VDD VSS VIN1 VIN2 VOUT1 VB1 +XM1_f0 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f1 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f2 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f3 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f4 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f5 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f6 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f7 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f0 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f1 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f2 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f3 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f4 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f5 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f6 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f7 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f0 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f1 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f2 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f3 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f4 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f5 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f6 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f7 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM4_f0 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM4_f1 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM4_f2 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM4_f3 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM5_f0 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM5_f1 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM5_f2 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM5_f3 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +.ends corpus_c08 diff --git a/benchmarks/code_behind_layout/configs/development/c08_family/references/dev_unit100.spice b/benchmarks/code_behind_layout/configs/development/c08_family/references/dev_unit100.spice new file mode 100644 index 00000000..d7ed5f53 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c08_family/references/dev_unit100.spice @@ -0,0 +1,34 @@ +.subckt corpus_c08 VDD VSS VIN1 VIN2 VOUT1 VB1 +XM1_f0 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f1 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f2 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f3 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f4 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f5 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f6 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f7 net22 VIN1 net23 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f0 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f1 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f2 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f3 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f4 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f5 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f6 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f7 VOUT1 VIN2 net23 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f0 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f1 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f2 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f3 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f4 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f5 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f6 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f7 net23 VB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f0 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM4_f1 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM4_f2 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM4_f3 net22 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM5_f0 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM5_f1 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM5_f2 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM5_f3 VOUT1 net22 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +.ends corpus_c08 diff --git a/benchmarks/code_behind_layout/configs/development/c08_minimal_gpt_teacher_preparation.json b/benchmarks/code_behind_layout/configs/development/c08_minimal_gpt_teacher_preparation.json new file mode 100644 index 00000000..4c0053bc --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c08_minimal_gpt_teacher_preparation.json @@ -0,0 +1,75 @@ +{ + "status": "DRAFT_NOT_FROZEN", + "role": "train_collection", + "collection_id": "c08_minimal_gpt_teacher_v1", + "base_collection_manifest": "/srv/code-behind-layout/runtime/train_collections/c08_collection_v1/collection.json", + "source_pack": "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1/source_pack", + "trusted_bundle": "/srv/code-behind-layout/runtime/train_collections/c08_collection_v1/trusted", + "registry_path": "/srv/code-behind-layout/runtime/train_collections/c08_collection_v1/registry.json", + "label_rule_path": "/srv/code-behind-layout/runtime/train_collections/c08_collection_v1/label_rule.json", + "initial_states_path": "/srv/code-behind-layout/runtime/collection_preparation/c08_minimal_gpt_teacher_v1_20261019T021018631546Z/initial_states.jsonl", + "initial_state_count": 3, + "editable_paths": [ + "textbook_sharing/layout.py" + ], + "gold_controls": {}, + "teacher_instruction_version": "minimal_source_edit_v1", + "student_preselection": { + "student_interface_version": "ordinary_policy_action_v1", + "max_new_tokens": 1024, + "max_context_tokens": 8192, + "stage": "before_physics" + }, + "sampling": { + "mode": "train_collection_source_gpt", + "backend": "isolated_gpt_cli", + "model": "gpt-6.1-sol", + "reasoning_effort": "high", + "trials": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8 + ], + "proposal_workers": 2, + "seed": null, + "seed_control_available": false, + "proposal_format": "full_source_teacher", + "max_new_tokens": 3072, + "max_context_tokens": 8192, + "timeout_seconds": 240 + }, + "physical": { + "workers": 2, + "cpus_per_job": 2, + "generation_timeout_seconds": 240, + "evaluator_timeout_seconds": 720 + }, + "budget": { + "proposals_per_initial_state": 8, + "configurations_per_candidate": 9, + "effective_example_pipeline_pilot_target": 1000, + "initial_batch_initial_states": 3 + }, + "deduplication": { + "method": "exact_ast_dump", + "include_attributes": false, + "numeric_normalization": false + }, + "prospective_change": "Preserve every unaffected line/comment/docstring/import/name/order. Reject oversized canonical ordinary actions before physics, retaining complete raw source and all generation costs. Never repair/shorten a proposal.", + "output_budget_scope": "3072 pinned student-tokenizer tokens for complete source JSON + EOS. Distinct student preselection is ordinary ACTION_JSON <=1024 and complete source/contract/action <=8192.", + "isolation": { + "fresh_ephemeral_session_per_trial": true, + "native_tools": false, + "no_sampling_seed_exposed": true, + "concurrent_slots_global": 2 + }, + "source_program_counting": "New teacher contexts do not create independent source programs or lineages. Count useful initial programs and unique terminal ASTs separately from pair counts.", + "new_baseline9_per_state_and_new_teacher_proposals_required": true, + "old_development_outcomes_admitted": false, + "formal_collection_launched": false +} diff --git a/benchmarks/code_behind_layout/configs/development/c08_observed_states_preparation.json b/benchmarks/code_behind_layout/configs/development/c08_observed_states_preparation.json new file mode 100644 index 00000000..3243eab4 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c08_observed_states_preparation.json @@ -0,0 +1,14 @@ +{ + "status": "DRAFT_NEW_INITIAL_STATES_NOT_FROZEN", + "circuit_id": "C08", + "capsule_preparation": "/srv/code-behind-layout/runtime/collection_preparation/c08_collection_20261019T015607178027Z/preparation.json", + "initial_states_path": "/srv/code-behind-layout/runtime/collection_preparation/c08_observed_states_20261019T015857390853Z/initial_states.jsonl", + "initial_state_count": 3, + "complete_editable_paths": [ + "textbook_sharing/layout.py" + ], + "old_evidence_labels_admitted": false, + "fresh_baselines_and_new_proposals_required": true, + "source_counting": "One universal compiler lineage. Identical source ASTs across topologies/teachers are the same program, even when task contexts differ.", + "inverse_injection_note": "Each intermediate is byte-exact actual T0 output, bound by its raw diff and real executed source; no artificial fault or hand-written repair supplied." +} diff --git a/benchmarks/code_behind_layout/configs/development/c08_rule_collection_preparation.json b/benchmarks/code_behind_layout/configs/development/c08_rule_collection_preparation.json new file mode 100644 index 00000000..a0bb0e7b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c08_rule_collection_preparation.json @@ -0,0 +1,118 @@ +{ + "status": "DRAFT_PROSPECTIVE_RULE_COLLECTION_NOT_FROZEN", + "role": "train_collection", + "circuit_id": "C08", + "collection_id": "c08_rules_v1", + "capsule_preparation": "/srv/code-behind-layout/runtime/collection_preparation/c08_collection_20261019T015607178027Z/preparation.json", + "source_pack": "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1/source_pack", + "trusted_bundle": "/srv/code-behind-layout/runtime/collection_preparation/c08_collection_20261019T015607178027Z/trusted", + "initial_states_path": "/srv/code-behind-layout/runtime/collection_preparation/c08_rule_collection_20261019T020138716813Z/initial_states.jsonl", + "initial_state_count": 1, + "editable_paths": [ + "textbook_sharing/layout.py" + ], + "parent_lineage": "textbook_universal_compiler_cropped", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "rule_proposer_path": "/srv/code-behind-layout/runtime/collection_preparation/c08_rule_collection_20261019T020138716813Z/rule_proposer.py", + "rule_ids": [ + "diffusion_plan", + "gate_plan", + "combined_plan", + "reverse_device_order", + "gate_order", + "reverse_port_track_order", + "reverse_devices_combined", + "reverse_ports_combined" + ], + "borrowed_from": "scripts/corpus_yield_pilot.py:variants; same eight development planning rules", + "candidates": [ + { + "rule_id": "diffusion_plan", + "complete_source_file": "/srv/code-behind-layout/runtime/collection_preparation/c08_rule_collection_20261019T020138716813Z/diffusion_plan.py", + "candidate_patch": "--- a/textbook_sharing/layout.py\n+++ b/textbook_sharing/layout.py\n@@ -84,7 +84,7 @@\n plan = SharingPlan.from_json(plans[str(gi)]); src = \"explicit\"\n else:\n nm = named_plans(pdk, g)\n- plan = nm.get(mode) or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n+ plan = nm.get(\"diffusion_only\") or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n res = build_mos_group(pdk, g, plan=plan, name=f\"grp{gi}\")\n rows[pol].append(from_group_result(res, f\"grp{gi}\", pol, g[0].b))\n applied.append({\"group\": gi, \"devices\": [d.logical_id for d in g], \"plan\": res.applied_plan, \"mode_requested\": mode, \"plan_source\": src,\n", + "draft_generation_wall_seconds": 0.0053077819757163525, + "draft_generation_process_cpu_seconds": 0.005306909999999998 + }, + { + "rule_id": "gate_plan", + "complete_source_file": "/srv/code-behind-layout/runtime/collection_preparation/c08_rule_collection_20261019T020138716813Z/gate_plan.py", + "candidate_patch": "--- a/textbook_sharing/layout.py\n+++ b/textbook_sharing/layout.py\n@@ -84,7 +84,7 @@\n plan = SharingPlan.from_json(plans[str(gi)]); src = \"explicit\"\n else:\n nm = named_plans(pdk, g)\n- plan = nm.get(mode) or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n+ plan = nm.get(\"gate_only\") or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n res = build_mos_group(pdk, g, plan=plan, name=f\"grp{gi}\")\n rows[pol].append(from_group_result(res, f\"grp{gi}\", pol, g[0].b))\n applied.append({\"group\": gi, \"devices\": [d.logical_id for d in g], \"plan\": res.applied_plan, \"mode_requested\": mode, \"plan_source\": src,\n", + "draft_generation_wall_seconds": 0.005020533222705126, + "draft_generation_process_cpu_seconds": 0.005021339 + }, + { + "rule_id": "combined_plan", + "complete_source_file": "/srv/code-behind-layout/runtime/collection_preparation/c08_rule_collection_20261019T020138716813Z/combined_plan.py", + "candidate_patch": "--- a/textbook_sharing/layout.py\n+++ b/textbook_sharing/layout.py\n@@ -84,7 +84,7 @@\n plan = SharingPlan.from_json(plans[str(gi)]); src = \"explicit\"\n else:\n nm = named_plans(pdk, g)\n- plan = nm.get(mode) or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n+ plan = nm.get(\"combined\") or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n res = build_mos_group(pdk, g, plan=plan, name=f\"grp{gi}\")\n rows[pol].append(from_group_result(res, f\"grp{gi}\", pol, g[0].b))\n applied.append({\"group\": gi, \"devices\": [d.logical_id for d in g], \"plan\": res.applied_plan, \"mode_requested\": mode, \"plan_source\": src,\n", + "draft_generation_wall_seconds": 0.005022286903113127, + "draft_generation_process_cpu_seconds": 0.005022967999999989 + }, + { + "rule_id": "reverse_device_order", + "complete_source_file": "/srv/code-behind-layout/runtime/collection_preparation/c08_rule_collection_20261019T020138716813Z/reverse_device_order.py", + "candidate_patch": "--- a/textbook_sharing/layout.py\n+++ b/textbook_sharing/layout.py\n@@ -26,7 +26,7 @@\n if d.kind in (\"nfet\", \"pfet\"):\n sz = sizing[d.name]\n out.append(DeviceSpec(d.name, d.kind, d.nets[0], d.nets[1], d.nets[2], d.nets[3], float(sz[\"w\"]), float(sz[\"l\"]), int(sz.get(\"nf\", 1))))\n- return out\n+ return list(reversed(out))\n \n \n def sharing_groups(devs: list[DeviceSpec]) -> list[list[DeviceSpec]]:\n", + "draft_generation_wall_seconds": 0.004902302287518978, + "draft_generation_process_cpu_seconds": 0.004903041999999996 + }, + { + "rule_id": "gate_order", + "complete_source_file": "/srv/code-behind-layout/runtime/collection_preparation/c08_rule_collection_20261019T020138716813Z/gate_order.py", + "candidate_patch": "--- a/textbook_sharing/layout.py\n+++ b/textbook_sharing/layout.py\n@@ -26,7 +26,7 @@\n if d.kind in (\"nfet\", \"pfet\"):\n sz = sizing[d.name]\n out.append(DeviceSpec(d.name, d.kind, d.nets[0], d.nets[1], d.nets[2], d.nets[3], float(sz[\"w\"]), float(sz[\"l\"]), int(sz.get(\"nf\", 1))))\n- return out\n+ return sorted(out, key=lambda d: (d.g, d.d, d.logical_id))\n \n \n def sharing_groups(devs: list[DeviceSpec]) -> list[list[DeviceSpec]]:\n", + "draft_generation_wall_seconds": 0.005653881002217531, + "draft_generation_process_cpu_seconds": 0.005654936999999999 + }, + { + "rule_id": "reverse_port_track_order", + "complete_source_file": "/srv/code-behind-layout/runtime/collection_preparation/c08_rule_collection_20261019T020138716813Z/reverse_port_track_order.py", + "candidate_patch": "--- a/textbook_sharing/layout.py\n+++ b/textbook_sharing/layout.py\n@@ -95,6 +95,6 @@\n if rows[\"p\"]: row_specs.append(RowSpec(rows[\"p\"], \"p\", True, rows[\"p\"][0].body_net))\n if rows[\"passive\"]: row_specs.append(RowSpec(rows[\"passive\"], \"passive\", True, None, taps=False))\n top = name or f\"{circuit.circuit_id}_{pdk.name}_{mode}\"\n- asm = assemble(pdk, row_specs, circuit.ports, name=top)\n+ asm = assemble(pdk, row_specs, list(reversed(circuit.ports)), name=top)\n return {\"component\": asm[\"component\"], \"name\": top, \"groups\": [[d.logical_id for d in g] for g in groups], \"applied_plans\": applied, \"evidence\": evidence,\n \"assembly_stats\": asm[\"stats\"], \"expected_fingers\": nf_total, \"trunks\": asm[\"trunks\"]}\n", + "draft_generation_wall_seconds": 0.008803903590887785, + "draft_generation_process_cpu_seconds": 0.008805643000000002 + }, + { + "rule_id": "reverse_devices_combined", + "complete_source_file": "/srv/code-behind-layout/runtime/collection_preparation/c08_rule_collection_20261019T020138716813Z/reverse_devices_combined.py", + "candidate_patch": "--- a/textbook_sharing/layout.py\n+++ b/textbook_sharing/layout.py\n@@ -26,7 +26,7 @@\n if d.kind in (\"nfet\", \"pfet\"):\n sz = sizing[d.name]\n out.append(DeviceSpec(d.name, d.kind, d.nets[0], d.nets[1], d.nets[2], d.nets[3], float(sz[\"w\"]), float(sz[\"l\"]), int(sz.get(\"nf\", 1))))\n- return out\n+ return list(reversed(out))\n \n \n def sharing_groups(devs: list[DeviceSpec]) -> list[list[DeviceSpec]]:\n@@ -84,7 +84,7 @@\n plan = SharingPlan.from_json(plans[str(gi)]); src = \"explicit\"\n else:\n nm = named_plans(pdk, g)\n- plan = nm.get(mode) or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n+ plan = nm.get(\"combined\") or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n res = build_mos_group(pdk, g, plan=plan, name=f\"grp{gi}\")\n rows[pol].append(from_group_result(res, f\"grp{gi}\", pol, g[0].b))\n applied.append({\"group\": gi, \"devices\": [d.logical_id for d in g], \"plan\": res.applied_plan, \"mode_requested\": mode, \"plan_source\": src,\n", + "draft_generation_wall_seconds": 0.008854269050061703, + "draft_generation_process_cpu_seconds": 0.008855976999999987 + }, + { + "rule_id": "reverse_ports_combined", + "complete_source_file": "/srv/code-behind-layout/runtime/collection_preparation/c08_rule_collection_20261019T020138716813Z/reverse_ports_combined.py", + "candidate_patch": "--- a/textbook_sharing/layout.py\n+++ b/textbook_sharing/layout.py\n@@ -84,7 +84,7 @@\n plan = SharingPlan.from_json(plans[str(gi)]); src = \"explicit\"\n else:\n nm = named_plans(pdk, g)\n- plan = nm.get(mode) or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n+ plan = nm.get(\"combined\") or nm[\"independent\"]; src = \"named\" if nm.get(mode) else \"named_fallback_independent\"\n res = build_mos_group(pdk, g, plan=plan, name=f\"grp{gi}\")\n rows[pol].append(from_group_result(res, f\"grp{gi}\", pol, g[0].b))\n applied.append({\"group\": gi, \"devices\": [d.logical_id for d in g], \"plan\": res.applied_plan, \"mode_requested\": mode, \"plan_source\": src,\n@@ -95,6 +95,6 @@\n if rows[\"p\"]: row_specs.append(RowSpec(rows[\"p\"], \"p\", True, rows[\"p\"][0].body_net))\n if rows[\"passive\"]: row_specs.append(RowSpec(rows[\"passive\"], \"passive\", True, None, taps=False))\n top = name or f\"{circuit.circuit_id}_{pdk.name}_{mode}\"\n- asm = assemble(pdk, row_specs, circuit.ports, name=top)\n+ asm = assemble(pdk, row_specs, list(reversed(circuit.ports)), name=top)\n return {\"component\": asm[\"component\"], \"name\": top, \"groups\": [[d.logical_id for d in g] for g in groups], \"applied_plans\": applied, \"evidence\": evidence,\n \"assembly_stats\": asm[\"stats\"], \"expected_fingers\": nf_total, \"trunks\": asm[\"trunks\"]}\n", + "draft_generation_wall_seconds": 0.009075683075934649, + "draft_generation_process_cpu_seconds": 0.009076849999999997 + } + ], + "proposed_collection_mode": "train_collection_rules", + "sampling": { + "backend": "frozen_rule_proposer", + "rule_ids": [ + "diffusion_plan", + "gate_plan", + "combined_plan", + "reverse_device_order", + "gate_order", + "reverse_port_track_order", + "reverse_devices_combined", + "reverse_ports_combined" + ], + "model": null, + "seed": null, + "model_inferences": 0, + "generation_timeout_seconds": 5 + }, + "physical": { + "workers": 2, + "cpus_per_job": 2, + "generation_timeout_seconds": 240, + "evaluator_timeout_seconds": 720 + }, + "new_physical_point_budget": 81, + "source_diversity": "Eight programs, one original initial AST and the same one public compiler lineage; no extra lineage from rule count.", + "label_scope": "Use new frozen-contract physical runs only, with one fresh nine-point baseline and every candidate at all nine points. Old development outcomes stay excluded.", + "student_context": "Teacher source/format is provenance. Student supervision must retain full source/contract/feedback while requesting the frozen unified-diff action format.", + "counting": "Report unique useful initial states, unique terminal ASTs, per-method matched examples, anchor versus family winners, opposite non-tie pair preferences, and ties separately.", + "no_inverse_fault_injection": true, + "formal_collection_started": false, + "old_outcomes_relabelled": false +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/circuit_input.json new file mode 100644 index 00000000..879fe8f3 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/circuit_input.json @@ -0,0 +1,63 @@ +{ + "circuit_id": "C12", + "name": "cmos_inverter_amplifier", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "pfet", + "nets": [ + "VOUT1", + "VIN1", + "VDD", + "VDD" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 195, + "files": [ + "Dataset/195/195.cir", + "Dataset/195/Port195.txt", + "Dataset/195/Pagenumber195.txt", + "Dataset/195/Book195.png", + "Dataset/195/Cadence195.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "268", + "device_name_map": { + "M1": "M0", + "M2": "M1" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/195/Book195.png", + "observation": "Razavi p.268 scan: M1 NMOS and M2 PMOS with common gate input and common drain output (inverter amplifier)" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/configurations.json new file mode 100644 index 00000000..6f0d955d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/configurations.json @@ -0,0 +1,203 @@ +{ + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_ONLY", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C12", + "domain_id": "C12_cfg1", + "textbook_sizing_source": "presimulated size configuration cfg1 of the textbook benchmark", + "circuit_name": "cmos_inverter_amplifier", + "bench_category": "single", + "circuit_input_file": "configs/development/c12_cfg1_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 12 + } + } + }, + "reference_file": "configs/development/c12_cfg1_family/references/anchor.spice", + "contract_file": "configs/development/c12_cfg1_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.5, + "l": 0.3, + "nf": 3 + }, + "M2": { + "w": 3.0, + "l": 0.3, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c12_cfg1_family/references/dev_nf_half.spice", + "contract_file": "configs/development/c12_cfg1_family/contracts/dev_nf_half.json" + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.5, + "l": 0.3, + "nf": 9 + }, + "M2": { + "w": 9.0, + "l": 0.3, + "nf": 18 + } + } + }, + "reference_file": "configs/development/c12_cfg1_family/references/dev_nf_1half.spice", + "contract_file": "configs/development/c12_cfg1_family/contracts/dev_nf_1half.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M2": { + "w": 12.0, + "l": 0.3, + "nf": 24 + } + } + }, + "reference_file": "configs/development/c12_cfg1_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c12_cfg1_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.225, + "nf": 6 + }, + "M2": { + "w": 6.0, + "l": 0.225, + "nf": 12 + } + } + }, + "reference_file": "configs/development/c12_cfg1_family/references/dev_len075.spice", + "contract_file": "configs/development/c12_cfg1_family/contracts/dev_len075.json" + }, + { + "configuration_id": "dev_len150", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.45, + "nf": 6 + }, + "M2": { + "w": 6.0, + "l": 0.45, + "nf": 12 + } + } + }, + "reference_file": "configs/development/c12_cfg1_family/references/dev_len150.spice", + "contract_file": "configs/development/c12_cfg1_family/contracts/dev_len150.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.5, + "l": 0.3, + "nf": 6 + }, + "M2": { + "w": 9.0, + "l": 0.3, + "nf": 12 + } + } + }, + "reference_file": "configs/development/c12_cfg1_family/references/dev_unit075.spice", + "contract_file": "configs/development/c12_cfg1_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_unit100", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.3, + "nf": 6 + }, + "M2": { + "w": 12.0, + "l": 0.3, + "nf": 12 + } + } + }, + "reference_file": "configs/development/c12_cfg1_family/references/dev_unit100.spice", + "contract_file": "configs/development/c12_cfg1_family/contracts/dev_unit100.json" + }, + { + "configuration_id": "dev_len200", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.6, + "nf": 6 + }, + "M2": { + "w": 6.0, + "l": 0.6, + "nf": 12 + } + } + }, + "reference_file": "configs/development/c12_cfg1_family/references/dev_len200.spice", + "contract_file": "configs/development/c12_cfg1_family/contracts/dev_len200.json" + } + ], + "textbook_specification_floors": { + "gain_lf": { + "min": 15.0 + }, + "f3db": { + "min": 1000000.0 + } + }, + "declared_by": "scripts/prepare_textbook_train_domains.py", + "ancestry": "Same cropped universal compiler source; no new source lineage. Geometry and per-finger references are fixed before any layout." +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/anchor.json new file mode 100644 index 00000000..6c467f7e --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/anchor.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg1", + "configuration_id": "anchor", + "reference_id": "c12_cfg1_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_len075.json b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_len075.json new file mode 100644 index 00000000..cf46765a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_len075.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg1", + "configuration_id": "dev_len075", + "reference_id": "c12_cfg1_dev_len075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_len150.json b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_len150.json new file mode 100644 index 00000000..76d1a6a4 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_len150.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg1", + "configuration_id": "dev_len150", + "reference_id": "c12_cfg1_dev_len150_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_len200.json b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_len200.json new file mode 100644 index 00000000..7c01c840 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_len200.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg1", + "configuration_id": "dev_len200", + "reference_id": "c12_cfg1_dev_len200_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_nf_1half.json b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_nf_1half.json new file mode 100644 index 00000000..dacaaa46 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_nf_1half.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg1", + "configuration_id": "dev_nf_1half", + "reference_id": "c12_cfg1_dev_nf_1half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..051dbf4c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_nf_double.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg1", + "configuration_id": "dev_nf_double", + "reference_id": "c12_cfg1_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_nf_half.json b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_nf_half.json new file mode 100644 index 00000000..420e5acd --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_nf_half.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg1", + "configuration_id": "dev_nf_half", + "reference_id": "c12_cfg1_dev_nf_half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_unit075.json new file mode 100644 index 00000000..be19a87f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_unit075.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg1", + "configuration_id": "dev_unit075", + "reference_id": "c12_cfg1_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_unit100.json b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_unit100.json new file mode 100644 index 00000000..f53ea0ed --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/contracts/dev_unit100.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg1", + "configuration_id": "dev_unit100", + "reference_id": "c12_cfg1_dev_unit100_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/anchor.spice new file mode 100644 index 00000000..7b399343 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/anchor.spice @@ -0,0 +1,20 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f8 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f9 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f10 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f11 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_len075.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_len075.spice new file mode 100644 index 00000000..bfeeba39 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_len075.spice @@ -0,0 +1,20 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM1_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM1_f4 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM1_f5 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f6 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f7 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f8 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f9 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f10 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f11 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_len150.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_len150.spice new file mode 100644 index 00000000..a5394015 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_len150.spice @@ -0,0 +1,20 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f4 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f5 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f6 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f7 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f8 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f9 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f10 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f11 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_len200.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_len200.spice new file mode 100644 index 00000000..bd4a27e9 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_len200.spice @@ -0,0 +1,20 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f4 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f5 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f6 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f7 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f8 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f9 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f10 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f11 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_nf_1half.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_nf_1half.spice new file mode 100644 index 00000000..7c8de3fa --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_nf_1half.spice @@ -0,0 +1,29 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f8 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f8 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f9 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f10 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f11 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f12 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f13 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f14 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f15 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f16 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f17 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_nf_double.spice new file mode 100644 index 00000000..982b948c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_nf_double.spice @@ -0,0 +1,38 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f8 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f9 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f10 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f11 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f8 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f9 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f10 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f11 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f12 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f13 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f14 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f15 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f16 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f17 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f18 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f19 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f20 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f21 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f22 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f23 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_nf_half.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_nf_half.spice new file mode 100644 index 00000000..bf59f5ad --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_nf_half.spice @@ -0,0 +1,11 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_unit075.spice new file mode 100644 index 00000000..366d0c8c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_unit075.spice @@ -0,0 +1,20 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f4 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f5 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f6 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f7 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f8 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f9 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f10 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f11 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_unit100.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_unit100.spice new file mode 100644 index 00000000..8e3d6431 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg1_family/references/dev_unit100.spice @@ -0,0 +1,20 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f4 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f5 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f6 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f7 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f8 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f9 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f10 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f11 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/circuit_input.json new file mode 100644 index 00000000..879fe8f3 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/circuit_input.json @@ -0,0 +1,63 @@ +{ + "circuit_id": "C12", + "name": "cmos_inverter_amplifier", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "pfet", + "nets": [ + "VOUT1", + "VIN1", + "VDD", + "VDD" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 195, + "files": [ + "Dataset/195/195.cir", + "Dataset/195/Port195.txt", + "Dataset/195/Pagenumber195.txt", + "Dataset/195/Book195.png", + "Dataset/195/Cadence195.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "268", + "device_name_map": { + "M1": "M0", + "M2": "M1" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/195/Book195.png", + "observation": "Razavi p.268 scan: M1 NMOS and M2 PMOS with common gate input and common drain output (inverter amplifier)" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/configurations.json new file mode 100644 index 00000000..16a1658b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/configurations.json @@ -0,0 +1,203 @@ +{ + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_ONLY", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C12", + "domain_id": "C12_cfg2", + "textbook_sizing_source": "presimulated size configuration cfg2 of the textbook benchmark", + "circuit_name": "cmos_inverter_amplifier", + "bench_category": "single", + "circuit_input_file": "configs/development/c12_cfg2_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.3, + "nf": 2 + }, + "M2": { + "w": 4.0, + "l": 0.3, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c12_cfg2_family/references/anchor.spice", + "contract_file": "configs/development/c12_cfg2_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.0, + "l": 0.3, + "nf": 1 + }, + "M2": { + "w": 2.0, + "l": 0.3, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c12_cfg2_family/references/dev_nf_half.spice", + "contract_file": "configs/development/c12_cfg2_family/contracts/dev_nf_half.json" + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.3, + "nf": 3 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c12_cfg2_family/references/dev_nf_1half.spice", + "contract_file": "configs/development/c12_cfg2_family/contracts/dev_nf_1half.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 8.0, + "l": 0.3, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c12_cfg2_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c12_cfg2_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.225, + "nf": 2 + }, + "M2": { + "w": 4.0, + "l": 0.225, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c12_cfg2_family/references/dev_len075.spice", + "contract_file": "configs/development/c12_cfg2_family/contracts/dev_len075.json" + }, + { + "configuration_id": "dev_len150", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.45, + "nf": 2 + }, + "M2": { + "w": 4.0, + "l": 0.45, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c12_cfg2_family/references/dev_len150.spice", + "contract_file": "configs/development/c12_cfg2_family/contracts/dev_len150.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.5, + "l": 0.3, + "nf": 2 + }, + "M2": { + "w": 3.0, + "l": 0.3, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c12_cfg2_family/references/dev_unit075.spice", + "contract_file": "configs/development/c12_cfg2_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_len200", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.6, + "nf": 2 + }, + "M2": { + "w": 4.0, + "l": 0.6, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c12_cfg2_family/references/dev_len200.spice", + "contract_file": "configs/development/c12_cfg2_family/contracts/dev_len200.json" + }, + { + "configuration_id": "dev_nf_triple", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.3, + "nf": 6 + }, + "M2": { + "w": 12.0, + "l": 0.3, + "nf": 12 + } + } + }, + "reference_file": "configs/development/c12_cfg2_family/references/dev_nf_triple.spice", + "contract_file": "configs/development/c12_cfg2_family/contracts/dev_nf_triple.json" + } + ], + "textbook_specification_floors": { + "gain_lf": { + "min": 15.0 + }, + "f3db": { + "min": 1000000.0 + } + }, + "declared_by": "scripts/prepare_textbook_train_domains.py", + "ancestry": "Same cropped universal compiler source; no new source lineage. Geometry and per-finger references are fixed before any layout." +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/anchor.json new file mode 100644 index 00000000..4bb68ec8 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/anchor.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg2", + "configuration_id": "anchor", + "reference_id": "c12_cfg2_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_len075.json b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_len075.json new file mode 100644 index 00000000..6b780bbc --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_len075.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg2", + "configuration_id": "dev_len075", + "reference_id": "c12_cfg2_dev_len075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_len150.json b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_len150.json new file mode 100644 index 00000000..434e38e3 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_len150.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg2", + "configuration_id": "dev_len150", + "reference_id": "c12_cfg2_dev_len150_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_len200.json b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_len200.json new file mode 100644 index 00000000..b9537c5a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_len200.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg2", + "configuration_id": "dev_len200", + "reference_id": "c12_cfg2_dev_len200_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_nf_1half.json b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_nf_1half.json new file mode 100644 index 00000000..b9753d50 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_nf_1half.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg2", + "configuration_id": "dev_nf_1half", + "reference_id": "c12_cfg2_dev_nf_1half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..ab5009e4 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_nf_double.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg2", + "configuration_id": "dev_nf_double", + "reference_id": "c12_cfg2_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_nf_half.json b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_nf_half.json new file mode 100644 index 00000000..d924f002 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_nf_half.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg2", + "configuration_id": "dev_nf_half", + "reference_id": "c12_cfg2_dev_nf_half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_nf_triple.json b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_nf_triple.json new file mode 100644 index 00000000..d8663d5c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_nf_triple.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg2", + "configuration_id": "dev_nf_triple", + "reference_id": "c12_cfg2_dev_nf_triple_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_unit075.json new file mode 100644 index 00000000..892cf2ad --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/contracts/dev_unit075.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg2", + "configuration_id": "dev_unit075", + "reference_id": "c12_cfg2_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/anchor.spice new file mode 100644 index 00000000..72378b75 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/anchor.spice @@ -0,0 +1,8 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_len075.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_len075.spice new file mode 100644 index 00000000..0f998095 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_len075.spice @@ -0,0 +1,8 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.225 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.225 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.225 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.225 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.225 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.225 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_len150.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_len150.spice new file mode 100644 index 00000000..26b5d035 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_len150.spice @@ -0,0 +1,8 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_len200.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_len200.spice new file mode 100644 index 00000000..8b101854 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_len200.spice @@ -0,0 +1,8 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.6 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.6 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.6 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.6 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_nf_1half.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_nf_1half.spice new file mode 100644 index 00000000..b3868316 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_nf_1half.spice @@ -0,0 +1,11 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_nf_double.spice new file mode 100644 index 00000000..650d75fd --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_nf_double.spice @@ -0,0 +1,14 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f6 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f7 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_nf_half.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_nf_half.spice new file mode 100644 index 00000000..3dfc1fa4 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_nf_half.spice @@ -0,0 +1,5 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_nf_triple.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_nf_triple.spice new file mode 100644 index 00000000..8e3d6431 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_nf_triple.spice @@ -0,0 +1,20 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f4 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f5 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f6 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f7 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f8 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f9 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f10 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f11 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_unit075.spice new file mode 100644 index 00000000..67178c84 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg2_family/references/dev_unit075.spice @@ -0,0 +1,8 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/circuit_input.json new file mode 100644 index 00000000..879fe8f3 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/circuit_input.json @@ -0,0 +1,63 @@ +{ + "circuit_id": "C12", + "name": "cmos_inverter_amplifier", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "pfet", + "nets": [ + "VOUT1", + "VIN1", + "VDD", + "VDD" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 195, + "files": [ + "Dataset/195/195.cir", + "Dataset/195/Port195.txt", + "Dataset/195/Pagenumber195.txt", + "Dataset/195/Book195.png", + "Dataset/195/Cadence195.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "268", + "device_name_map": { + "M1": "M0", + "M2": "M1" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/195/Book195.png", + "observation": "Razavi p.268 scan: M1 NMOS and M2 PMOS with common gate input and common drain output (inverter amplifier)" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/configurations.json new file mode 100644 index 00000000..442c5d2d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/configurations.json @@ -0,0 +1,203 @@ +{ + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_ONLY", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C12", + "domain_id": "C12_cfg3", + "textbook_sizing_source": "presimulated size configuration cfg3 of the textbook benchmark", + "circuit_name": "cmos_inverter_amplifier", + "bench_category": "single", + "circuit_input_file": "configs/development/c12_cfg3_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.45, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 0.45, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c12_cfg3_family/references/anchor.spice", + "contract_file": "configs/development/c12_cfg3_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.0, + "l": 0.45, + "nf": 2 + }, + "M2": { + "w": 2.0, + "l": 0.45, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c12_cfg3_family/references/dev_nf_half.spice", + "contract_file": "configs/development/c12_cfg3_family/contracts/dev_nf_half.json" + }, + { + "configuration_id": "dev_nf_3quarters", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.5, + "l": 0.45, + "nf": 3 + }, + "M2": { + "w": 3.0, + "l": 0.45, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c12_cfg3_family/references/dev_nf_3quarters.spice", + "contract_file": "configs/development/c12_cfg3_family/contracts/dev_nf_3quarters.json" + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.45, + "nf": 6 + }, + "M2": { + "w": 6.0, + "l": 0.45, + "nf": 12 + } + } + }, + "reference_file": "configs/development/c12_cfg3_family/references/dev_nf_1half.spice", + "contract_file": "configs/development/c12_cfg3_family/contracts/dev_nf_1half.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.45, + "nf": 8 + }, + "M2": { + "w": 8.0, + "l": 0.45, + "nf": 16 + } + } + }, + "reference_file": "configs/development/c12_cfg3_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c12_cfg3_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.338, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 0.338, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c12_cfg3_family/references/dev_len075.spice", + "contract_file": "configs/development/c12_cfg3_family/contracts/dev_len075.json" + }, + { + "configuration_id": "dev_len150", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.675, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 0.675, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c12_cfg3_family/references/dev_len150.spice", + "contract_file": "configs/development/c12_cfg3_family/contracts/dev_len150.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.45, + "nf": 4 + }, + "M2": { + "w": 6.0, + "l": 0.45, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c12_cfg3_family/references/dev_unit075.spice", + "contract_file": "configs/development/c12_cfg3_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_unit100", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.45, + "nf": 4 + }, + "M2": { + "w": 8.0, + "l": 0.45, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c12_cfg3_family/references/dev_unit100.spice", + "contract_file": "configs/development/c12_cfg3_family/contracts/dev_unit100.json" + } + ], + "textbook_specification_floors": { + "gain_lf": { + "min": 15.0 + }, + "f3db": { + "min": 1000000.0 + } + }, + "declared_by": "scripts/prepare_textbook_train_domains.py", + "ancestry": "Same cropped universal compiler source; no new source lineage. Geometry and per-finger references are fixed before any layout." +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/anchor.json new file mode 100644 index 00000000..81cc492c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/anchor.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg3", + "configuration_id": "anchor", + "reference_id": "c12_cfg3_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_len075.json b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_len075.json new file mode 100644 index 00000000..5e2a9d9d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_len075.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg3", + "configuration_id": "dev_len075", + "reference_id": "c12_cfg3_dev_len075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_len150.json b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_len150.json new file mode 100644 index 00000000..e3ff2662 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_len150.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg3", + "configuration_id": "dev_len150", + "reference_id": "c12_cfg3_dev_len150_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_nf_1half.json b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_nf_1half.json new file mode 100644 index 00000000..921a7d2b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_nf_1half.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg3", + "configuration_id": "dev_nf_1half", + "reference_id": "c12_cfg3_dev_nf_1half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_nf_3quarters.json b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_nf_3quarters.json new file mode 100644 index 00000000..86e46f62 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_nf_3quarters.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg3", + "configuration_id": "dev_nf_3quarters", + "reference_id": "c12_cfg3_dev_nf_3quarters_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..f2f96c60 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_nf_double.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg3", + "configuration_id": "dev_nf_double", + "reference_id": "c12_cfg3_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_nf_half.json b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_nf_half.json new file mode 100644 index 00000000..6b41abbc --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_nf_half.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg3", + "configuration_id": "dev_nf_half", + "reference_id": "c12_cfg3_dev_nf_half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_unit075.json new file mode 100644 index 00000000..81ce5650 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_unit075.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg3", + "configuration_id": "dev_unit075", + "reference_id": "c12_cfg3_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_unit100.json b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_unit100.json new file mode 100644 index 00000000..2ca2a4f9 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/contracts/dev_unit100.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12_cfg3", + "configuration_id": "dev_unit100", + "reference_id": "c12_cfg3_dev_unit100_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/anchor.spice new file mode 100644 index 00000000..7a898180 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/anchor.spice @@ -0,0 +1,14 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f6 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f7 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_len075.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_len075.spice new file mode 100644 index 00000000..3bc04ea3 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_len075.spice @@ -0,0 +1,14 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM1_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM2_f6 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +XM2_f7 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.338 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_len150.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_len150.spice new file mode 100644 index 00000000..37815dc0 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_len150.spice @@ -0,0 +1,14 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM1_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM2_f6 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +XM2_f7 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.675 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_nf_1half.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_nf_1half.spice new file mode 100644 index 00000000..a5394015 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_nf_1half.spice @@ -0,0 +1,20 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f4 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f5 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f6 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f7 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f8 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f9 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f10 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f11 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_nf_3quarters.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_nf_3quarters.spice new file mode 100644 index 00000000..c6cd00af --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_nf_3quarters.spice @@ -0,0 +1,11 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_nf_double.spice new file mode 100644 index 00000000..5d2d7bfc --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_nf_double.spice @@ -0,0 +1,26 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f4 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f5 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f6 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f7 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f6 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f7 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f8 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f9 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f10 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f11 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f12 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f13 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f14 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f15 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_nf_half.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_nf_half.spice new file mode 100644 index 00000000..3a3f54f2 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_nf_half.spice @@ -0,0 +1,8 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_unit075.spice new file mode 100644 index 00000000..1d609044 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_unit075.spice @@ -0,0 +1,14 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM1_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM2_f6 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +XM2_f7 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.45 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_unit100.spice b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_unit100.spice new file mode 100644 index 00000000..aaab5993 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_cfg3_family/references/dev_unit100.spice @@ -0,0 +1,14 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM1_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM2_f6 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +XM2_f7 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.45 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c12_family/circuit_input.json new file mode 100644 index 00000000..879fe8f3 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_family/circuit_input.json @@ -0,0 +1,63 @@ +{ + "circuit_id": "C12", + "name": "cmos_inverter_amplifier", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "pfet", + "nets": [ + "VOUT1", + "VIN1", + "VDD", + "VDD" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 195, + "files": [ + "Dataset/195/195.cir", + "Dataset/195/Port195.txt", + "Dataset/195/Pagenumber195.txt", + "Dataset/195/Book195.png", + "Dataset/195/Cadence195.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "268", + "device_name_map": { + "M1": "M0", + "M2": "M1" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/195/Book195.png", + "observation": "Razavi p.268 scan: M1 NMOS and M2 PMOS with common gate input and common drain output (inverter amplifier)" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c12_family/configurations.json new file mode 100644 index 00000000..a95093ff --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_family/configurations.json @@ -0,0 +1,201 @@ +{ + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_ONLY", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C12", + "circuit_name": "cmos_inverter_amplifier", + "bench_category": "single", + "circuit_input_file": "configs/development/c12_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 0.3, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c12_family/references/anchor.spice", + "contract_file": "configs/development/c12_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.0, + "l": 0.3, + "nf": 2 + }, + "M2": { + "w": 2.0, + "l": 0.3, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c12_family/references/dev_nf_half.spice", + "contract_file": "configs/development/c12_family/contracts/dev_nf_half.json" + }, + { + "configuration_id": "dev_nf_3quarters", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.5, + "l": 0.3, + "nf": 3 + }, + "M2": { + "w": 3.0, + "l": 0.3, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c12_family/references/dev_nf_3quarters.spice", + "contract_file": "configs/development/c12_family/contracts/dev_nf_3quarters.json" + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 12 + } + } + }, + "reference_file": "configs/development/c12_family/references/dev_nf_1half.spice", + "contract_file": "configs/development/c12_family/contracts/dev_nf_1half.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M2": { + "w": 8.0, + "l": 0.3, + "nf": 16 + } + } + }, + "reference_file": "configs/development/c12_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c12_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.225, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 0.225, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c12_family/references/dev_len075.spice", + "contract_file": "configs/development/c12_family/contracts/dev_len075.json" + }, + { + "configuration_id": "dev_len150", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.45, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 0.45, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c12_family/references/dev_len150.spice", + "contract_file": "configs/development/c12_family/contracts/dev_len150.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c12_family/references/dev_unit075.spice", + "contract_file": "configs/development/c12_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_unit100", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 8.0, + "l": 0.3, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c12_family/references/dev_unit100.spice", + "contract_file": "configs/development/c12_family/contracts/dev_unit100.json" + } + ], + "textbook_specification_floors": { + "gain_lf": { + "min": 15.0 + }, + "f3db": { + "min": 1000000.0 + } + }, + "declared_by": "scripts/prepare_textbook_train_domains.py", + "ancestry": "Same cropped universal compiler source; no new source lineage. Geometry and per-finger references are fixed before any layout." +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c12_family/contracts/anchor.json new file mode 100644 index 00000000..c9b69b85 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_family/contracts/anchor.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12", + "configuration_id": "anchor", + "reference_id": "c12_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_len075.json b/benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_len075.json new file mode 100644 index 00000000..fa067f61 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_len075.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12", + "configuration_id": "dev_len075", + "reference_id": "c12_dev_len075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_len150.json b/benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_len150.json new file mode 100644 index 00000000..667889ce --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_len150.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12", + "configuration_id": "dev_len150", + "reference_id": "c12_dev_len150_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_nf_1half.json b/benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_nf_1half.json new file mode 100644 index 00000000..be5039c1 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_nf_1half.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12", + "configuration_id": "dev_nf_1half", + "reference_id": "c12_dev_nf_1half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_nf_3quarters.json b/benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_nf_3quarters.json new file mode 100644 index 00000000..44a94de1 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_nf_3quarters.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12", + "configuration_id": "dev_nf_3quarters", + "reference_id": "c12_dev_nf_3quarters_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..fd4021b3 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_nf_double.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12", + "configuration_id": "dev_nf_double", + "reference_id": "c12_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_nf_half.json b/benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_nf_half.json new file mode 100644 index 00000000..d5db60ac --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_nf_half.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12", + "configuration_id": "dev_nf_half", + "reference_id": "c12_dev_nf_half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_unit075.json new file mode 100644 index 00000000..89fbbfc9 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_unit075.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12", + "configuration_id": "dev_unit075", + "reference_id": "c12_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_unit100.json b/benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_unit100.json new file mode 100644 index 00000000..a51c6e1f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_family/contracts/dev_unit100.json @@ -0,0 +1,82 @@ +{ + "task_id": "development_train_domain_c12", + "configuration_id": "dev_unit100", + "reference_id": "c12_dev_unit100_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "single", + "objective": { + "id": "c12_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "gain_lf_dB_min": 15.0, + "f3db_Hz_min": 1000000.0 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "load_capacitance_F": 1e-13, + "input_step_V": 0.001, + "replica_bias": {}, + "dc_servo": "Disclosed DC servo of the textbook benchmark: a 1e6 H inductor from VOUT1 to VIN1 and a 1e6 F capacitor from the AC/step source to VIN1 fix V_in,dc = V_out,dc and leave AC and step behaviour untouched; the DC transfer sweep drives VIN1 directly.", + "power_definition": "Main 1.8 V supply current of the DUT; replica bias generators are fed from a separate 1.8 V bias supply.", + "textbook_case": { + "load": { + "CL": 1e-13 + }, + "bias": {}, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c12_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c12_family/references/anchor.spice new file mode 100644 index 00000000..0d0a819e --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_family/references/anchor.spice @@ -0,0 +1,14 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_family/references/dev_len075.spice b/benchmarks/code_behind_layout/configs/development/c12_family/references/dev_len075.spice new file mode 100644 index 00000000..693834c0 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_family/references/dev_len075.spice @@ -0,0 +1,14 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM1_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f6 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +XM2_f7 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.225 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_family/references/dev_len150.spice b/benchmarks/code_behind_layout/configs/development/c12_family/references/dev_len150.spice new file mode 100644 index 00000000..7a898180 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_family/references/dev_len150.spice @@ -0,0 +1,14 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f6 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f7 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_family/references/dev_nf_1half.spice b/benchmarks/code_behind_layout/configs/development/c12_family/references/dev_nf_1half.spice new file mode 100644 index 00000000..7b399343 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_family/references/dev_nf_1half.spice @@ -0,0 +1,20 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f8 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f9 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f10 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f11 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_family/references/dev_nf_3quarters.spice b/benchmarks/code_behind_layout/configs/development/c12_family/references/dev_nf_3quarters.spice new file mode 100644 index 00000000..bf59f5ad --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_family/references/dev_nf_3quarters.spice @@ -0,0 +1,11 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c12_family/references/dev_nf_double.spice new file mode 100644 index 00000000..708a61f5 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_family/references/dev_nf_double.spice @@ -0,0 +1,26 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f8 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f9 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f10 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f11 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f12 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f13 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f14 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f15 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_family/references/dev_nf_half.spice b/benchmarks/code_behind_layout/configs/development/c12_family/references/dev_nf_half.spice new file mode 100644 index 00000000..0145e745 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_family/references/dev_nf_half.spice @@ -0,0 +1,8 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c12_family/references/dev_unit075.spice new file mode 100644 index 00000000..de6d6493 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_family/references/dev_unit075.spice @@ -0,0 +1,14 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f6 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f7 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c12_family/references/dev_unit100.spice b/benchmarks/code_behind_layout/configs/development/c12_family/references/dev_unit100.spice new file mode 100644 index 00000000..650d75fd --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c12_family/references/dev_unit100.spice @@ -0,0 +1,14 @@ +.subckt corpus_c12 VDD VSS VIN1 VOUT1 +XM1_f0 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f1 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f2 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f3 VOUT1 VIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f0 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f1 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f2 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f3 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f4 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f5 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f6 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f7 VOUT1 VIN1 VDD VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +.ends corpus_c12 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/circuit_input.json new file mode 100644 index 00000000..ca9635a7 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/circuit_input.json @@ -0,0 +1,105 @@ +{ + "circuit_id": "C13", + "name": "wide_swing_cascode_current_mirror", + "ports": [ + "VSS", + "IIN1", + "IOUT1", + "IB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IB1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "IIN1", + "IB1", + "net15", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "net15", + "IIN1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "nfet", + "nets": [ + "IOUT1", + "IB1", + "net14", + "VSS" + ], + "params": {} + }, + { + "name": "M5", + "kind": "nfet", + "nets": [ + "net14", + "IIN1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 709, + "files": [ + "Dataset/709/709.cir", + "Dataset/709/Port709.txt", + "Dataset/709/Pagenumber709.txt", + "Dataset/709/Book709.png", + "Dataset/709/Cadence709.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "261", + "device_name_map": { + "M1": "M4", + "M2": "M1", + "M3": "M0", + "M4": "M3", + "M5": "M2" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/709/Book709.png", + "observation": "Johns p.261 scan: Q5 bias diode (W/L)/(n+1)^2, Q4/Q1 cascodes (W/L)/n^2, Q3/Q2 bottom devices W/L; wide-swing cascode mirror with Ibias and Iin sources" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here.", + "corroborating_entry": { + "analoggenie_id": 934, + "book": "P. E. Allen, D. R. Holberg, CMOS Analog Circuit Design, 3rd ed., Oxford University Press, 2012", + "page_ref": "135", + "note": "same connection graph (IREF1<->IB1, IREF2<->IIN1)" + } + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/configurations.json new file mode 100644 index 00000000..e5375357 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/configurations.json @@ -0,0 +1,338 @@ +{ + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_ONLY", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C13", + "domain_id": "C13_cfg1", + "textbook_sizing_source": "presimulated size configuration cfg1 of the textbook benchmark", + "circuit_name": "wide_swing_cascode_current_mirror", + "bench_category": "mirror", + "circuit_input_file": "configs/development/c13_cfg1_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 1.0, + "l": 0.3, + "nf": 2 + }, + "M2": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M3": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M4": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M5": { + "w": 3.0, + "l": 0.3, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c13_cfg1_family/references/anchor.spice", + "contract_file": "configs/development/c13_cfg1_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 0.5, + "l": 0.3, + "nf": 1 + }, + "M2": { + "w": 1.5, + "l": 0.3, + "nf": 3 + }, + "M3": { + "w": 1.5, + "l": 0.3, + "nf": 3 + }, + "M4": { + "w": 1.5, + "l": 0.3, + "nf": 3 + }, + "M5": { + "w": 1.5, + "l": 0.3, + "nf": 3 + } + } + }, + "reference_file": "configs/development/c13_cfg1_family/references/dev_nf_half.spice", + "contract_file": "configs/development/c13_cfg1_family/contracts/dev_nf_half.json" + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.5, + "l": 0.3, + "nf": 3 + }, + "M2": { + "w": 4.5, + "l": 0.3, + "nf": 9 + }, + "M3": { + "w": 4.5, + "l": 0.3, + "nf": 9 + }, + "M4": { + "w": 4.5, + "l": 0.3, + "nf": 9 + }, + "M5": { + "w": 4.5, + "l": 0.3, + "nf": 9 + } + } + }, + "reference_file": "configs/development/c13_cfg1_family/references/dev_nf_1half.spice", + "contract_file": "configs/development/c13_cfg1_family/contracts/dev_nf_1half.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M3": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M4": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M5": { + "w": 6.0, + "l": 0.3, + "nf": 12 + } + } + }, + "reference_file": "configs/development/c13_cfg1_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c13_cfg1_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.0, + "l": 0.225, + "nf": 2 + }, + "M2": { + "w": 3.0, + "l": 0.225, + "nf": 6 + }, + "M3": { + "w": 3.0, + "l": 0.225, + "nf": 6 + }, + "M4": { + "w": 3.0, + "l": 0.225, + "nf": 6 + }, + "M5": { + "w": 3.0, + "l": 0.225, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c13_cfg1_family/references/dev_len075.spice", + "contract_file": "configs/development/c13_cfg1_family/contracts/dev_len075.json" + }, + { + "configuration_id": "dev_len150", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.0, + "l": 0.45, + "nf": 2 + }, + "M2": { + "w": 3.0, + "l": 0.45, + "nf": 6 + }, + "M3": { + "w": 3.0, + "l": 0.45, + "nf": 6 + }, + "M4": { + "w": 3.0, + "l": 0.45, + "nf": 6 + }, + "M5": { + "w": 3.0, + "l": 0.45, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c13_cfg1_family/references/dev_len150.spice", + "contract_file": "configs/development/c13_cfg1_family/contracts/dev_len150.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.5, + "l": 0.3, + "nf": 2 + }, + "M2": { + "w": 4.5, + "l": 0.3, + "nf": 6 + }, + "M3": { + "w": 4.5, + "l": 0.3, + "nf": 6 + }, + "M4": { + "w": 4.5, + "l": 0.3, + "nf": 6 + }, + "M5": { + "w": 4.5, + "l": 0.3, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c13_cfg1_family/references/dev_unit075.spice", + "contract_file": "configs/development/c13_cfg1_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_unit100", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.3, + "nf": 2 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 6 + }, + "M3": { + "w": 6.0, + "l": 0.3, + "nf": 6 + }, + "M4": { + "w": 6.0, + "l": 0.3, + "nf": 6 + }, + "M5": { + "w": 6.0, + "l": 0.3, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c13_cfg1_family/references/dev_unit100.spice", + "contract_file": "configs/development/c13_cfg1_family/contracts/dev_unit100.json" + }, + { + "configuration_id": "dev_len200", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.0, + "l": 0.6, + "nf": 2 + }, + "M2": { + "w": 3.0, + "l": 0.6, + "nf": 6 + }, + "M3": { + "w": 3.0, + "l": 0.6, + "nf": 6 + }, + "M4": { + "w": 3.0, + "l": 0.6, + "nf": 6 + }, + "M5": { + "w": 3.0, + "l": 0.6, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c13_cfg1_family/references/dev_len200.spice", + "contract_file": "configs/development/c13_cfg1_family/contracts/dev_len200.json" + } + ], + "textbook_specification_floors": { + "err": { + "abs_max": 0.03 + }, + "vmin": { + "max": 0.7200000000000001 + } + }, + "declared_by": "scripts/prepare_textbook_train_domains.py", + "ancestry": "Same cropped universal compiler source; no new source lineage. Geometry and per-finger references are fixed before any layout." +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/anchor.json new file mode 100644 index 00000000..ebf4ddf3 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/anchor.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg1", + "configuration_id": "anchor", + "reference_id": "c13_cfg1_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_len075.json b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_len075.json new file mode 100644 index 00000000..f85d1bef --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_len075.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg1", + "configuration_id": "dev_len075", + "reference_id": "c13_cfg1_dev_len075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_len150.json b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_len150.json new file mode 100644 index 00000000..902d72ac --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_len150.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg1", + "configuration_id": "dev_len150", + "reference_id": "c13_cfg1_dev_len150_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_len200.json b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_len200.json new file mode 100644 index 00000000..d16631b6 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_len200.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg1", + "configuration_id": "dev_len200", + "reference_id": "c13_cfg1_dev_len200_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_nf_1half.json b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_nf_1half.json new file mode 100644 index 00000000..690c578e --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_nf_1half.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg1", + "configuration_id": "dev_nf_1half", + "reference_id": "c13_cfg1_dev_nf_1half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..396c3319 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_nf_double.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg1", + "configuration_id": "dev_nf_double", + "reference_id": "c13_cfg1_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_nf_half.json b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_nf_half.json new file mode 100644 index 00000000..edf75a0f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_nf_half.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg1", + "configuration_id": "dev_nf_half", + "reference_id": "c13_cfg1_dev_nf_half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_unit075.json new file mode 100644 index 00000000..2e93b398 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_unit075.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg1", + "configuration_id": "dev_unit075", + "reference_id": "c13_cfg1_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_unit100.json b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_unit100.json new file mode 100644 index 00000000..f6b40789 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/contracts/dev_unit100.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg1", + "configuration_id": "dev_unit100", + "reference_id": "c13_cfg1_dev_unit100_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/anchor.spice new file mode 100644 index 00000000..6c869750 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/anchor.spice @@ -0,0 +1,28 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f4 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f5 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f4 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f5 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f4 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f5 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_len075.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_len075.spice new file mode 100644 index 00000000..75856681 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_len075.spice @@ -0,0 +1,28 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM2_f4 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM2_f5 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM3_f4 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM3_f5 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM4_f4 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM4_f5 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM5_f4 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM5_f5 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_len150.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_len150.spice new file mode 100644 index 00000000..07cba22a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_len150.spice @@ -0,0 +1,28 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f4 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f5 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f4 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f5 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f4 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f5 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f4 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f5 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_len200.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_len200.spice new file mode 100644 index 00000000..1ef9bbf2 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_len200.spice @@ -0,0 +1,28 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f4 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f5 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f4 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f5 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f4 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f5 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM5_f4 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM5_f5 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_nf_1half.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_nf_1half.spice new file mode 100644 index 00000000..23a8444c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_nf_1half.spice @@ -0,0 +1,41 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f6 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f7 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f8 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f4 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f5 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f6 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f7 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f8 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f4 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f5 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f6 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f7 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f8 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f4 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f5 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f6 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f7 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f8 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_nf_double.spice new file mode 100644 index 00000000..5e474288 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_nf_double.spice @@ -0,0 +1,54 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f6 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f7 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f8 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f9 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f10 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f11 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f4 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f5 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f6 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f7 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f8 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f9 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f10 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f11 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f4 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f5 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f6 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f7 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f8 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f9 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f10 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f11 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f4 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f5 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f6 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f7 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f8 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f9 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f10 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f11 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_nf_half.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_nf_half.spice new file mode 100644 index 00000000..c380c3c6 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_nf_half.spice @@ -0,0 +1,15 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_unit075.spice new file mode 100644 index 00000000..a2f8ec25 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_unit075.spice @@ -0,0 +1,28 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f4 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f5 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f4 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f5 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM4_f4 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM4_f5 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM5_f4 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM5_f5 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_unit100.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_unit100.spice new file mode 100644 index 00000000..afd95cda --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg1_family/references/dev_unit100.spice @@ -0,0 +1,28 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f4 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f5 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f4 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f5 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f4 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f5 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM5_f4 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM5_f5 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/circuit_input.json new file mode 100644 index 00000000..ca9635a7 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/circuit_input.json @@ -0,0 +1,105 @@ +{ + "circuit_id": "C13", + "name": "wide_swing_cascode_current_mirror", + "ports": [ + "VSS", + "IIN1", + "IOUT1", + "IB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IB1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "IIN1", + "IB1", + "net15", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "net15", + "IIN1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "nfet", + "nets": [ + "IOUT1", + "IB1", + "net14", + "VSS" + ], + "params": {} + }, + { + "name": "M5", + "kind": "nfet", + "nets": [ + "net14", + "IIN1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 709, + "files": [ + "Dataset/709/709.cir", + "Dataset/709/Port709.txt", + "Dataset/709/Pagenumber709.txt", + "Dataset/709/Book709.png", + "Dataset/709/Cadence709.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "261", + "device_name_map": { + "M1": "M4", + "M2": "M1", + "M3": "M0", + "M4": "M3", + "M5": "M2" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/709/Book709.png", + "observation": "Johns p.261 scan: Q5 bias diode (W/L)/(n+1)^2, Q4/Q1 cascodes (W/L)/n^2, Q3/Q2 bottom devices W/L; wide-swing cascode mirror with Ibias and Iin sources" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here.", + "corroborating_entry": { + "analoggenie_id": 934, + "book": "P. E. Allen, D. R. Holberg, CMOS Analog Circuit Design, 3rd ed., Oxford University Press, 2012", + "page_ref": "135", + "note": "same connection graph (IREF1<->IB1, IREF2<->IIN1)" + } + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/configurations.json new file mode 100644 index 00000000..3e522e55 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/configurations.json @@ -0,0 +1,338 @@ +{ + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_ONLY", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C13", + "domain_id": "C13_cfg2", + "textbook_sizing_source": "presimulated size configuration cfg2 of the textbook benchmark", + "circuit_name": "wide_swing_cascode_current_mirror", + "bench_category": "mirror", + "circuit_input_file": "configs/development/c13_cfg2_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 0.5, + "l": 0.3, + "nf": 1 + }, + "M2": { + "w": 2.0, + "l": 0.3, + "nf": 2 + }, + "M3": { + "w": 2.0, + "l": 0.3, + "nf": 2 + }, + "M4": { + "w": 2.0, + "l": 0.3, + "nf": 2 + }, + "M5": { + "w": 2.0, + "l": 0.3, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c13_cfg2_family/references/anchor.spice", + "contract_file": "configs/development/c13_cfg2_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.0, + "l": 0.3, + "nf": 2 + }, + "M2": { + "w": 4.0, + "l": 0.3, + "nf": 4 + }, + "M3": { + "w": 4.0, + "l": 0.3, + "nf": 4 + }, + "M4": { + "w": 4.0, + "l": 0.3, + "nf": 4 + }, + "M5": { + "w": 4.0, + "l": 0.3, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c13_cfg2_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c13_cfg2_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 0.5, + "l": 0.225, + "nf": 1 + }, + "M2": { + "w": 2.0, + "l": 0.225, + "nf": 2 + }, + "M3": { + "w": 2.0, + "l": 0.225, + "nf": 2 + }, + "M4": { + "w": 2.0, + "l": 0.225, + "nf": 2 + }, + "M5": { + "w": 2.0, + "l": 0.225, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c13_cfg2_family/references/dev_len075.spice", + "contract_file": "configs/development/c13_cfg2_family/contracts/dev_len075.json" + }, + { + "configuration_id": "dev_len150", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 0.5, + "l": 0.45, + "nf": 1 + }, + "M2": { + "w": 2.0, + "l": 0.45, + "nf": 2 + }, + "M3": { + "w": 2.0, + "l": 0.45, + "nf": 2 + }, + "M4": { + "w": 2.0, + "l": 0.45, + "nf": 2 + }, + "M5": { + "w": 2.0, + "l": 0.45, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c13_cfg2_family/references/dev_len150.spice", + "contract_file": "configs/development/c13_cfg2_family/contracts/dev_len150.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 0.75, + "l": 0.3, + "nf": 1 + }, + "M2": { + "w": 1.5, + "l": 0.3, + "nf": 2 + }, + "M3": { + "w": 1.5, + "l": 0.3, + "nf": 2 + }, + "M4": { + "w": 1.5, + "l": 0.3, + "nf": 2 + }, + "M5": { + "w": 1.5, + "l": 0.3, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c13_cfg2_family/references/dev_unit075.spice", + "contract_file": "configs/development/c13_cfg2_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_unit100", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.0, + "l": 0.3, + "nf": 1 + }, + "M2": { + "w": 2.0, + "l": 0.3, + "nf": 2 + }, + "M3": { + "w": 2.0, + "l": 0.3, + "nf": 2 + }, + "M4": { + "w": 2.0, + "l": 0.3, + "nf": 2 + }, + "M5": { + "w": 2.0, + "l": 0.3, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c13_cfg2_family/references/dev_unit100.spice", + "contract_file": "configs/development/c13_cfg2_family/contracts/dev_unit100.json" + }, + { + "configuration_id": "dev_len200", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 0.5, + "l": 0.6, + "nf": 1 + }, + "M2": { + "w": 2.0, + "l": 0.6, + "nf": 2 + }, + "M3": { + "w": 2.0, + "l": 0.6, + "nf": 2 + }, + "M4": { + "w": 2.0, + "l": 0.6, + "nf": 2 + }, + "M5": { + "w": 2.0, + "l": 0.6, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c13_cfg2_family/references/dev_len200.spice", + "contract_file": "configs/development/c13_cfg2_family/contracts/dev_len200.json" + }, + { + "configuration_id": "dev_nf_triple", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.5, + "l": 0.3, + "nf": 3 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 6 + }, + "M3": { + "w": 6.0, + "l": 0.3, + "nf": 6 + }, + "M4": { + "w": 6.0, + "l": 0.3, + "nf": 6 + }, + "M5": { + "w": 6.0, + "l": 0.3, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c13_cfg2_family/references/dev_nf_triple.spice", + "contract_file": "configs/development/c13_cfg2_family/contracts/dev_nf_triple.json" + }, + { + "configuration_id": "dev_unit125", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.25, + "l": 0.3, + "nf": 1 + }, + "M2": { + "w": 2.5, + "l": 0.3, + "nf": 2 + }, + "M3": { + "w": 2.5, + "l": 0.3, + "nf": 2 + }, + "M4": { + "w": 2.5, + "l": 0.3, + "nf": 2 + }, + "M5": { + "w": 2.5, + "l": 0.3, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c13_cfg2_family/references/dev_unit125.spice", + "contract_file": "configs/development/c13_cfg2_family/contracts/dev_unit125.json" + } + ], + "textbook_specification_floors": { + "err": { + "abs_max": 0.03 + }, + "vmin": { + "max": 0.7200000000000001 + } + }, + "declared_by": "scripts/prepare_textbook_train_domains.py", + "ancestry": "Same cropped universal compiler source; no new source lineage. Geometry and per-finger references are fixed before any layout." +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/anchor.json new file mode 100644 index 00000000..a6d7461a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/anchor.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg2", + "configuration_id": "anchor", + "reference_id": "c13_cfg2_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_len075.json b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_len075.json new file mode 100644 index 00000000..5c4b2aa8 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_len075.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg2", + "configuration_id": "dev_len075", + "reference_id": "c13_cfg2_dev_len075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_len150.json b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_len150.json new file mode 100644 index 00000000..1f4bb59b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_len150.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg2", + "configuration_id": "dev_len150", + "reference_id": "c13_cfg2_dev_len150_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_len200.json b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_len200.json new file mode 100644 index 00000000..2732ac98 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_len200.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg2", + "configuration_id": "dev_len200", + "reference_id": "c13_cfg2_dev_len200_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..26cfd2b3 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_nf_double.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg2", + "configuration_id": "dev_nf_double", + "reference_id": "c13_cfg2_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_nf_triple.json b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_nf_triple.json new file mode 100644 index 00000000..f3249db2 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_nf_triple.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg2", + "configuration_id": "dev_nf_triple", + "reference_id": "c13_cfg2_dev_nf_triple_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_unit075.json new file mode 100644 index 00000000..d4eb8d5d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_unit075.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg2", + "configuration_id": "dev_unit075", + "reference_id": "c13_cfg2_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_unit100.json b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_unit100.json new file mode 100644 index 00000000..18acca6d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_unit100.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg2", + "configuration_id": "dev_unit100", + "reference_id": "c13_cfg2_dev_unit100_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_unit125.json b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_unit125.json new file mode 100644 index 00000000..45519a9c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/contracts/dev_unit125.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg2", + "configuration_id": "dev_unit125", + "reference_id": "c13_cfg2_dev_unit125_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/anchor.spice new file mode 100644 index 00000000..3afccc32 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/anchor.spice @@ -0,0 +1,11 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_len075.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_len075.spice new file mode 100644 index 00000000..c1e517fa --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_len075.spice @@ -0,0 +1,11 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.225 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.225 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.225 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.225 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.225 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.225 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.225 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.225 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_len150.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_len150.spice new file mode 100644 index 00000000..90abdd51 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_len150.spice @@ -0,0 +1,11 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_len200.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_len200.spice new file mode 100644 index 00000000..160c6f49 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_len200.spice @@ -0,0 +1,11 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_nf_double.spice new file mode 100644 index 00000000..d13b1875 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_nf_double.spice @@ -0,0 +1,20 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_nf_triple.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_nf_triple.spice new file mode 100644 index 00000000..4ab69ddf --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_nf_triple.spice @@ -0,0 +1,29 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f4 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f5 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f4 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f5 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f4 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f5 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM5_f4 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM5_f5 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_unit075.spice new file mode 100644 index 00000000..5c1b6b30 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_unit075.spice @@ -0,0 +1,11 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_unit100.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_unit100.spice new file mode 100644 index 00000000..72fcc0bb --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_unit100.spice @@ -0,0 +1,11 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_unit125.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_unit125.spice new file mode 100644 index 00000000..1283ace5 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg2_family/references/dev_unit125.spice @@ -0,0 +1,11 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.3 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.3 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.3 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.3 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.3 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.3 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.3 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.3 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.3 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/circuit_input.json new file mode 100644 index 00000000..ca9635a7 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/circuit_input.json @@ -0,0 +1,105 @@ +{ + "circuit_id": "C13", + "name": "wide_swing_cascode_current_mirror", + "ports": [ + "VSS", + "IIN1", + "IOUT1", + "IB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IB1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "IIN1", + "IB1", + "net15", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "net15", + "IIN1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "nfet", + "nets": [ + "IOUT1", + "IB1", + "net14", + "VSS" + ], + "params": {} + }, + { + "name": "M5", + "kind": "nfet", + "nets": [ + "net14", + "IIN1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 709, + "files": [ + "Dataset/709/709.cir", + "Dataset/709/Port709.txt", + "Dataset/709/Pagenumber709.txt", + "Dataset/709/Book709.png", + "Dataset/709/Cadence709.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "261", + "device_name_map": { + "M1": "M4", + "M2": "M1", + "M3": "M0", + "M4": "M3", + "M5": "M2" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/709/Book709.png", + "observation": "Johns p.261 scan: Q5 bias diode (W/L)/(n+1)^2, Q4/Q1 cascodes (W/L)/n^2, Q3/Q2 bottom devices W/L; wide-swing cascode mirror with Ibias and Iin sources" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here.", + "corroborating_entry": { + "analoggenie_id": 934, + "book": "P. E. Allen, D. R. Holberg, CMOS Analog Circuit Design, 3rd ed., Oxford University Press, 2012", + "page_ref": "135", + "note": "same connection graph (IREF1<->IB1, IREF2<->IIN1)" + } + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/configurations.json new file mode 100644 index 00000000..d22d38b0 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/configurations.json @@ -0,0 +1,338 @@ +{ + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_ONLY", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C13", + "domain_id": "C13_cfg3", + "textbook_sizing_source": "presimulated size configuration cfg3 of the textbook benchmark", + "circuit_name": "wide_swing_cascode_current_mirror", + "bench_category": "mirror", + "circuit_input_file": "configs/development/c13_cfg3_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 0.5, + "l": 0.45, + "nf": 1 + }, + "M2": { + "w": 2.0, + "l": 0.45, + "nf": 4 + }, + "M3": { + "w": 2.0, + "l": 0.45, + "nf": 4 + }, + "M4": { + "w": 2.0, + "l": 0.45, + "nf": 4 + }, + "M5": { + "w": 2.0, + "l": 0.45, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c13_cfg3_family/references/anchor.spice", + "contract_file": "configs/development/c13_cfg3_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.0, + "l": 0.45, + "nf": 2 + }, + "M2": { + "w": 4.0, + "l": 0.45, + "nf": 8 + }, + "M3": { + "w": 4.0, + "l": 0.45, + "nf": 8 + }, + "M4": { + "w": 4.0, + "l": 0.45, + "nf": 8 + }, + "M5": { + "w": 4.0, + "l": 0.45, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c13_cfg3_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c13_cfg3_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 0.5, + "l": 0.338, + "nf": 1 + }, + "M2": { + "w": 2.0, + "l": 0.338, + "nf": 4 + }, + "M3": { + "w": 2.0, + "l": 0.338, + "nf": 4 + }, + "M4": { + "w": 2.0, + "l": 0.338, + "nf": 4 + }, + "M5": { + "w": 2.0, + "l": 0.338, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c13_cfg3_family/references/dev_len075.spice", + "contract_file": "configs/development/c13_cfg3_family/contracts/dev_len075.json" + }, + { + "configuration_id": "dev_len150", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 0.5, + "l": 0.675, + "nf": 1 + }, + "M2": { + "w": 2.0, + "l": 0.675, + "nf": 4 + }, + "M3": { + "w": 2.0, + "l": 0.675, + "nf": 4 + }, + "M4": { + "w": 2.0, + "l": 0.675, + "nf": 4 + }, + "M5": { + "w": 2.0, + "l": 0.675, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c13_cfg3_family/references/dev_len150.spice", + "contract_file": "configs/development/c13_cfg3_family/contracts/dev_len150.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 0.75, + "l": 0.45, + "nf": 1 + }, + "M2": { + "w": 3.0, + "l": 0.45, + "nf": 4 + }, + "M3": { + "w": 3.0, + "l": 0.45, + "nf": 4 + }, + "M4": { + "w": 3.0, + "l": 0.45, + "nf": 4 + }, + "M5": { + "w": 3.0, + "l": 0.45, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c13_cfg3_family/references/dev_unit075.spice", + "contract_file": "configs/development/c13_cfg3_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_unit100", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.0, + "l": 0.45, + "nf": 1 + }, + "M2": { + "w": 4.0, + "l": 0.45, + "nf": 4 + }, + "M3": { + "w": 4.0, + "l": 0.45, + "nf": 4 + }, + "M4": { + "w": 4.0, + "l": 0.45, + "nf": 4 + }, + "M5": { + "w": 4.0, + "l": 0.45, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c13_cfg3_family/references/dev_unit100.spice", + "contract_file": "configs/development/c13_cfg3_family/contracts/dev_unit100.json" + }, + { + "configuration_id": "dev_len200", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 0.5, + "l": 0.9, + "nf": 1 + }, + "M2": { + "w": 2.0, + "l": 0.9, + "nf": 4 + }, + "M3": { + "w": 2.0, + "l": 0.9, + "nf": 4 + }, + "M4": { + "w": 2.0, + "l": 0.9, + "nf": 4 + }, + "M5": { + "w": 2.0, + "l": 0.9, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c13_cfg3_family/references/dev_len200.spice", + "contract_file": "configs/development/c13_cfg3_family/contracts/dev_len200.json" + }, + { + "configuration_id": "dev_nf_triple", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.5, + "l": 0.45, + "nf": 3 + }, + "M2": { + "w": 6.0, + "l": 0.45, + "nf": 12 + }, + "M3": { + "w": 6.0, + "l": 0.45, + "nf": 12 + }, + "M4": { + "w": 6.0, + "l": 0.45, + "nf": 12 + }, + "M5": { + "w": 6.0, + "l": 0.45, + "nf": 12 + } + } + }, + "reference_file": "configs/development/c13_cfg3_family/references/dev_nf_triple.spice", + "contract_file": "configs/development/c13_cfg3_family/contracts/dev_nf_triple.json" + }, + { + "configuration_id": "dev_unit125", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.25, + "l": 0.45, + "nf": 1 + }, + "M2": { + "w": 5.0, + "l": 0.45, + "nf": 4 + }, + "M3": { + "w": 5.0, + "l": 0.45, + "nf": 4 + }, + "M4": { + "w": 5.0, + "l": 0.45, + "nf": 4 + }, + "M5": { + "w": 5.0, + "l": 0.45, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c13_cfg3_family/references/dev_unit125.spice", + "contract_file": "configs/development/c13_cfg3_family/contracts/dev_unit125.json" + } + ], + "textbook_specification_floors": { + "err": { + "abs_max": 0.03 + }, + "vmin": { + "max": 0.7200000000000001 + } + }, + "declared_by": "scripts/prepare_textbook_train_domains.py", + "ancestry": "Same cropped universal compiler source; no new source lineage. Geometry and per-finger references are fixed before any layout." +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/anchor.json new file mode 100644 index 00000000..692d31b4 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/anchor.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg3", + "configuration_id": "anchor", + "reference_id": "c13_cfg3_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_len075.json b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_len075.json new file mode 100644 index 00000000..3395a036 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_len075.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg3", + "configuration_id": "dev_len075", + "reference_id": "c13_cfg3_dev_len075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_len150.json b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_len150.json new file mode 100644 index 00000000..92b4a353 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_len150.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg3", + "configuration_id": "dev_len150", + "reference_id": "c13_cfg3_dev_len150_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_len200.json b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_len200.json new file mode 100644 index 00000000..20891557 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_len200.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg3", + "configuration_id": "dev_len200", + "reference_id": "c13_cfg3_dev_len200_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..14eef894 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_nf_double.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg3", + "configuration_id": "dev_nf_double", + "reference_id": "c13_cfg3_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_nf_triple.json b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_nf_triple.json new file mode 100644 index 00000000..a45b2e85 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_nf_triple.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg3", + "configuration_id": "dev_nf_triple", + "reference_id": "c13_cfg3_dev_nf_triple_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_unit075.json new file mode 100644 index 00000000..f01006f5 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_unit075.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg3", + "configuration_id": "dev_unit075", + "reference_id": "c13_cfg3_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_unit100.json b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_unit100.json new file mode 100644 index 00000000..a9f19a0b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_unit100.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg3", + "configuration_id": "dev_unit100", + "reference_id": "c13_cfg3_dev_unit100_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_unit125.json b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_unit125.json new file mode 100644 index 00000000..e4ae0a4d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/contracts/dev_unit125.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c13_cfg3", + "configuration_id": "dev_unit125", + "reference_id": "c13_cfg3_dev_unit125_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_cfg3_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/anchor.spice new file mode 100644 index 00000000..56f61a9f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/anchor.spice @@ -0,0 +1,19 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/dev_len075.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/dev_len075.spice new file mode 100644 index 00000000..fc8c5928 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/dev_len075.spice @@ -0,0 +1,19 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.338 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/dev_len150.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/dev_len150.spice new file mode 100644 index 00000000..8779abc9 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/dev_len150.spice @@ -0,0 +1,19 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.675 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/dev_len200.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/dev_len200.spice new file mode 100644 index 00000000..e8c50d2a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/dev_len200.spice @@ -0,0 +1,19 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/dev_nf_double.spice new file mode 100644 index 00000000..1625725d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/dev_nf_double.spice @@ -0,0 +1,36 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f4 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f5 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f6 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f7 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f4 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f5 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f6 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f7 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f4 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f5 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f6 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f7 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f4 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f5 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f6 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f7 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/dev_nf_triple.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/dev_nf_triple.spice new file mode 100644 index 00000000..ac7d725b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/dev_nf_triple.spice @@ -0,0 +1,53 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f4 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f5 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f6 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f7 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f8 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f9 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f10 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f11 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f4 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f5 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f6 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f7 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f8 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f9 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f10 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f11 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f4 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f5 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f6 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f7 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f8 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f9 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f10 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f11 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f4 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f5 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f6 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f7 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f8 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f9 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f10 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f11 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/dev_unit075.spice new file mode 100644 index 00000000..8ade3250 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/dev_unit075.spice @@ -0,0 +1,19 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.45 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/dev_unit100.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/dev_unit100.spice new file mode 100644 index 00000000..250cddc6 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/dev_unit100.spice @@ -0,0 +1,19 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/dev_unit125.spice b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/dev_unit125.spice new file mode 100644 index 00000000..78c95cf7 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_cfg3_family/references/dev_unit125.spice @@ -0,0 +1,19 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.45 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.45 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.45 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.45 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.45 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.45 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.45 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.45 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.45 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.45 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.45 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.45 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.45 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.45 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.45 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.45 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.45 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c13_family/circuit_input.json new file mode 100644 index 00000000..ca9635a7 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_family/circuit_input.json @@ -0,0 +1,105 @@ +{ + "circuit_id": "C13", + "name": "wide_swing_cascode_current_mirror", + "ports": [ + "VSS", + "IIN1", + "IOUT1", + "IB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IB1", + "IB1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "IIN1", + "IB1", + "net15", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "net15", + "IIN1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "nfet", + "nets": [ + "IOUT1", + "IB1", + "net14", + "VSS" + ], + "params": {} + }, + { + "name": "M5", + "kind": "nfet", + "nets": [ + "net14", + "IIN1", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 709, + "files": [ + "Dataset/709/709.cir", + "Dataset/709/Port709.txt", + "Dataset/709/Pagenumber709.txt", + "Dataset/709/Book709.png", + "Dataset/709/Cadence709.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "261", + "device_name_map": { + "M1": "M4", + "M2": "M1", + "M3": "M0", + "M4": "M3", + "M5": "M2" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/709/Book709.png", + "observation": "Johns p.261 scan: Q5 bias diode (W/L)/(n+1)^2, Q4/Q1 cascodes (W/L)/n^2, Q3/Q2 bottom devices W/L; wide-swing cascode mirror with Ibias and Iin sources" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here.", + "corroborating_entry": { + "analoggenie_id": 934, + "book": "P. E. Allen, D. R. Holberg, CMOS Analog Circuit Design, 3rd ed., Oxford University Press, 2012", + "page_ref": "135", + "note": "same connection graph (IREF1<->IB1, IREF2<->IIN1)" + } + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c13_family/configurations.json new file mode 100644 index 00000000..058a8e42 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_family/configurations.json @@ -0,0 +1,336 @@ +{ + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_ONLY", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C13", + "circuit_name": "wide_swing_cascode_current_mirror", + "bench_category": "mirror", + "circuit_input_file": "configs/development/c13_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 0.5, + "l": 0.3, + "nf": 1 + }, + "M2": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M3": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M4": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M5": { + "w": 2.0, + "l": 0.3, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c13_family/references/anchor.spice", + "contract_file": "configs/development/c13_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.0, + "l": 0.3, + "nf": 2 + }, + "M2": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M3": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M4": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M5": { + "w": 4.0, + "l": 0.3, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c13_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c13_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 0.5, + "l": 0.225, + "nf": 1 + }, + "M2": { + "w": 2.0, + "l": 0.225, + "nf": 4 + }, + "M3": { + "w": 2.0, + "l": 0.225, + "nf": 4 + }, + "M4": { + "w": 2.0, + "l": 0.225, + "nf": 4 + }, + "M5": { + "w": 2.0, + "l": 0.225, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c13_family/references/dev_len075.spice", + "contract_file": "configs/development/c13_family/contracts/dev_len075.json" + }, + { + "configuration_id": "dev_len150", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 0.5, + "l": 0.45, + "nf": 1 + }, + "M2": { + "w": 2.0, + "l": 0.45, + "nf": 4 + }, + "M3": { + "w": 2.0, + "l": 0.45, + "nf": 4 + }, + "M4": { + "w": 2.0, + "l": 0.45, + "nf": 4 + }, + "M5": { + "w": 2.0, + "l": 0.45, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c13_family/references/dev_len150.spice", + "contract_file": "configs/development/c13_family/contracts/dev_len150.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 0.75, + "l": 0.3, + "nf": 1 + }, + "M2": { + "w": 3.0, + "l": 0.3, + "nf": 4 + }, + "M3": { + "w": 3.0, + "l": 0.3, + "nf": 4 + }, + "M4": { + "w": 3.0, + "l": 0.3, + "nf": 4 + }, + "M5": { + "w": 3.0, + "l": 0.3, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c13_family/references/dev_unit075.spice", + "contract_file": "configs/development/c13_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_unit100", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.0, + "l": 0.3, + "nf": 1 + }, + "M2": { + "w": 4.0, + "l": 0.3, + "nf": 4 + }, + "M3": { + "w": 4.0, + "l": 0.3, + "nf": 4 + }, + "M4": { + "w": 4.0, + "l": 0.3, + "nf": 4 + }, + "M5": { + "w": 4.0, + "l": 0.3, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c13_family/references/dev_unit100.spice", + "contract_file": "configs/development/c13_family/contracts/dev_unit100.json" + }, + { + "configuration_id": "dev_len200", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 0.5, + "l": 0.6, + "nf": 1 + }, + "M2": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M3": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M4": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M5": { + "w": 2.0, + "l": 0.6, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c13_family/references/dev_len200.spice", + "contract_file": "configs/development/c13_family/contracts/dev_len200.json" + }, + { + "configuration_id": "dev_nf_triple", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.5, + "l": 0.3, + "nf": 3 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M3": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M4": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M5": { + "w": 6.0, + "l": 0.3, + "nf": 12 + } + } + }, + "reference_file": "configs/development/c13_family/references/dev_nf_triple.spice", + "contract_file": "configs/development/c13_family/contracts/dev_nf_triple.json" + }, + { + "configuration_id": "dev_unit125", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.25, + "l": 0.3, + "nf": 1 + }, + "M2": { + "w": 5.0, + "l": 0.3, + "nf": 4 + }, + "M3": { + "w": 5.0, + "l": 0.3, + "nf": 4 + }, + "M4": { + "w": 5.0, + "l": 0.3, + "nf": 4 + }, + "M5": { + "w": 5.0, + "l": 0.3, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c13_family/references/dev_unit125.spice", + "contract_file": "configs/development/c13_family/contracts/dev_unit125.json" + } + ], + "textbook_specification_floors": { + "err": { + "abs_max": 0.03 + }, + "vmin": { + "max": 0.7200000000000001 + } + }, + "declared_by": "scripts/prepare_textbook_train_domains.py", + "ancestry": "Same cropped universal compiler source; no new source lineage. Geometry and per-finger references are fixed before any layout." +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c13_family/contracts/anchor.json new file mode 100644 index 00000000..6c9061ae --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_family/contracts/anchor.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c13", + "configuration_id": "anchor", + "reference_id": "c13_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_family/contracts/dev_len075.json b/benchmarks/code_behind_layout/configs/development/c13_family/contracts/dev_len075.json new file mode 100644 index 00000000..1cff54a5 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_family/contracts/dev_len075.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c13", + "configuration_id": "dev_len075", + "reference_id": "c13_dev_len075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_family/contracts/dev_len150.json b/benchmarks/code_behind_layout/configs/development/c13_family/contracts/dev_len150.json new file mode 100644 index 00000000..ba6c2f4b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_family/contracts/dev_len150.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c13", + "configuration_id": "dev_len150", + "reference_id": "c13_dev_len150_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_family/contracts/dev_len200.json b/benchmarks/code_behind_layout/configs/development/c13_family/contracts/dev_len200.json new file mode 100644 index 00000000..a1740600 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_family/contracts/dev_len200.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c13", + "configuration_id": "dev_len200", + "reference_id": "c13_dev_len200_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c13_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..340c3889 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_family/contracts/dev_nf_double.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c13", + "configuration_id": "dev_nf_double", + "reference_id": "c13_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_family/contracts/dev_nf_triple.json b/benchmarks/code_behind_layout/configs/development/c13_family/contracts/dev_nf_triple.json new file mode 100644 index 00000000..37a74189 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_family/contracts/dev_nf_triple.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c13", + "configuration_id": "dev_nf_triple", + "reference_id": "c13_dev_nf_triple_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c13_family/contracts/dev_unit075.json new file mode 100644 index 00000000..48e45eeb --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_family/contracts/dev_unit075.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c13", + "configuration_id": "dev_unit075", + "reference_id": "c13_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_family/contracts/dev_unit100.json b/benchmarks/code_behind_layout/configs/development/c13_family/contracts/dev_unit100.json new file mode 100644 index 00000000..3c3c54b5 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_family/contracts/dev_unit100.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c13", + "configuration_id": "dev_unit100", + "reference_id": "c13_dev_unit100_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_family/contracts/dev_unit125.json b/benchmarks/code_behind_layout/configs/development/c13_family/contracts/dev_unit125.json new file mode 100644 index 00000000..67d1af1b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_family/contracts/dev_unit125.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c13", + "configuration_id": "dev_unit125", + "reference_id": "c13_dev_unit125_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c13_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 0.72 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IB1": 2e-05 + }, + "output_test_V": 0.9, + "tolerance": 0.03, + "output_transient_levels_V": [ + 0.875, + 0.925 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 0.9, + "tol": 0.03 + }, + "bias": { + "IB1": { + "i": 2e-05, + "from": "VDD" + }, + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c13_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c13_family/references/anchor.spice new file mode 100644 index 00000000..417a3526 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_family/references/anchor.spice @@ -0,0 +1,19 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_family/references/dev_len075.spice b/benchmarks/code_behind_layout/configs/development/c13_family/references/dev_len075.spice new file mode 100644 index 00000000..cfc29287 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_family/references/dev_len075.spice @@ -0,0 +1,19 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.225 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_family/references/dev_len150.spice b/benchmarks/code_behind_layout/configs/development/c13_family/references/dev_len150.spice new file mode 100644 index 00000000..56f61a9f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_family/references/dev_len150.spice @@ -0,0 +1,19 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_family/references/dev_len200.spice b/benchmarks/code_behind_layout/configs/development/c13_family/references/dev_len200.spice new file mode 100644 index 00000000..2ff8d5d9 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_family/references/dev_len200.spice @@ -0,0 +1,19 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c13_family/references/dev_nf_double.spice new file mode 100644 index 00000000..89340d86 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_family/references/dev_nf_double.spice @@ -0,0 +1,36 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f6 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f7 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f4 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f5 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f6 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f7 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f4 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f5 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f6 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f7 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f4 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f5 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f6 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f7 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_family/references/dev_nf_triple.spice b/benchmarks/code_behind_layout/configs/development/c13_family/references/dev_nf_triple.spice new file mode 100644 index 00000000..ca0854c6 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_family/references/dev_nf_triple.spice @@ -0,0 +1,53 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f6 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f7 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f8 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f9 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f10 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f11 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f4 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f5 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f6 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f7 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f8 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f9 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f10 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f11 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f4 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f5 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f6 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f7 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f8 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f9 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f10 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM4_f11 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f4 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f5 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f6 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f7 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f8 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f9 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f10 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM5_f11 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c13_family/references/dev_unit075.spice new file mode 100644 index 00000000..53c25409 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_family/references/dev_unit075.spice @@ -0,0 +1,19 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_family/references/dev_unit100.spice b/benchmarks/code_behind_layout/configs/development/c13_family/references/dev_unit100.spice new file mode 100644 index 00000000..79eaba0b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_family/references/dev_unit100.spice @@ -0,0 +1,19 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c13_family/references/dev_unit125.spice b/benchmarks/code_behind_layout/configs/development/c13_family/references/dev_unit125.spice new file mode 100644 index 00000000..c83d671e --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c13_family/references/dev_unit125.spice @@ -0,0 +1,19 @@ +.subckt corpus_c13 VSS IIN1 IOUT1 IB1 +XM1_f0 IB1 IB1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.3 +XM2_f0 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.3 +XM2_f1 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.3 +XM2_f2 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.3 +XM2_f3 IIN1 IB1 net15 VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.3 +XM3_f0 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.3 +XM3_f1 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.3 +XM3_f2 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.3 +XM3_f3 net15 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.3 +XM4_f0 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.3 +XM4_f1 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.3 +XM4_f2 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.3 +XM4_f3 IOUT1 IB1 net14 VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.3 +XM5_f0 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.3 +XM5_f1 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.3 +XM5_f2 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.3 +XM5_f3 net14 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.3 +.ends corpus_c13 diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/circuit_input.json new file mode 100644 index 00000000..33b35815 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/circuit_input.json @@ -0,0 +1,87 @@ +{ + "circuit_id": "C14", + "name": "regulated_cascode_current_mirror", + "ports": [ + "VSS", + "IIN1", + "IOUT1", + "IREF1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IIN1", + "IIN1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "net11", + "IIN1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "IREF1", + "net11", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "nfet", + "nets": [ + "IOUT1", + "IREF1", + "net11", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 936, + "files": [ + "Dataset/936/936.cir", + "Dataset/936/Port936.txt", + "Dataset/936/Pagenumber936.txt", + "Dataset/936/Book936.png", + "Dataset/936/Cadence936.png" + ], + "book": "P. E. Allen, D. R. Holberg, CMOS Analog Circuit Design, 3rd ed., Oxford University Press, 2012", + "book_key": "allen", + "page_ref": "147", + "device_name_map": { + "M1": "M3", + "M2": "M1", + "M3": "M2", + "M4": "M0" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/936/Book936.png", + "observation": "Allen p.147 scan: M4 diode (II), M2 mirror, M1 regulating device biased by IREG, M3 output cascode; regulated cascode" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/configurations.json new file mode 100644 index 00000000..7487007b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/configurations.json @@ -0,0 +1,293 @@ +{ + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_ONLY", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C14", + "domain_id": "C14_cfg1", + "textbook_sizing_source": "presimulated size configuration cfg1 of the textbook benchmark", + "circuit_name": "regulated_cascode_current_mirror", + "bench_category": "mirror", + "circuit_input_file": "configs/development/c14_cfg1_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.6, + "nf": 6 + }, + "M2": { + "w": 3.0, + "l": 0.6, + "nf": 6 + }, + "M3": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M4": { + "w": 3.0, + "l": 0.6, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c14_cfg1_family/references/anchor.spice", + "contract_file": "configs/development/c14_cfg1_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.5, + "l": 0.6, + "nf": 3 + }, + "M2": { + "w": 1.5, + "l": 0.6, + "nf": 3 + }, + "M3": { + "w": 1.0, + "l": 0.6, + "nf": 2 + }, + "M4": { + "w": 1.5, + "l": 0.6, + "nf": 3 + } + } + }, + "reference_file": "configs/development/c14_cfg1_family/references/dev_nf_half.spice", + "contract_file": "configs/development/c14_cfg1_family/contracts/dev_nf_half.json" + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.5, + "l": 0.6, + "nf": 9 + }, + "M2": { + "w": 4.5, + "l": 0.6, + "nf": 9 + }, + "M3": { + "w": 3.0, + "l": 0.6, + "nf": 6 + }, + "M4": { + "w": 4.5, + "l": 0.6, + "nf": 9 + } + } + }, + "reference_file": "configs/development/c14_cfg1_family/references/dev_nf_1half.spice", + "contract_file": "configs/development/c14_cfg1_family/contracts/dev_nf_1half.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.6, + "nf": 12 + }, + "M2": { + "w": 6.0, + "l": 0.6, + "nf": 12 + }, + "M3": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "M4": { + "w": 6.0, + "l": 0.6, + "nf": 12 + } + } + }, + "reference_file": "configs/development/c14_cfg1_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c14_cfg1_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.45, + "nf": 6 + }, + "M2": { + "w": 3.0, + "l": 0.45, + "nf": 6 + }, + "M3": { + "w": 2.0, + "l": 0.45, + "nf": 4 + }, + "M4": { + "w": 3.0, + "l": 0.45, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c14_cfg1_family/references/dev_len075.spice", + "contract_file": "configs/development/c14_cfg1_family/contracts/dev_len075.json" + }, + { + "configuration_id": "dev_len150", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.9, + "nf": 6 + }, + "M2": { + "w": 3.0, + "l": 0.9, + "nf": 6 + }, + "M3": { + "w": 2.0, + "l": 0.9, + "nf": 4 + }, + "M4": { + "w": 3.0, + "l": 0.9, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c14_cfg1_family/references/dev_len150.spice", + "contract_file": "configs/development/c14_cfg1_family/contracts/dev_len150.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.5, + "l": 0.6, + "nf": 6 + }, + "M2": { + "w": 4.5, + "l": 0.6, + "nf": 6 + }, + "M3": { + "w": 3.0, + "l": 0.6, + "nf": 4 + }, + "M4": { + "w": 4.5, + "l": 0.6, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c14_cfg1_family/references/dev_unit075.spice", + "contract_file": "configs/development/c14_cfg1_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_unit100", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.6, + "nf": 6 + }, + "M2": { + "w": 6.0, + "l": 0.6, + "nf": 6 + }, + "M3": { + "w": 4.0, + "l": 0.6, + "nf": 4 + }, + "M4": { + "w": 6.0, + "l": 0.6, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c14_cfg1_family/references/dev_unit100.spice", + "contract_file": "configs/development/c14_cfg1_family/contracts/dev_unit100.json" + }, + { + "configuration_id": "dev_len200", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 1.2, + "nf": 6 + }, + "M2": { + "w": 3.0, + "l": 1.2, + "nf": 6 + }, + "M3": { + "w": 2.0, + "l": 1.2, + "nf": 4 + }, + "M4": { + "w": 3.0, + "l": 1.2, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c14_cfg1_family/references/dev_len200.spice", + "contract_file": "configs/development/c14_cfg1_family/contracts/dev_len200.json" + } + ], + "textbook_specification_floors": { + "err": { + "abs_max": 0.03 + }, + "vmin": { + "max": 1.08 + } + }, + "declared_by": "scripts/prepare_textbook_train_domains.py", + "ancestry": "Same cropped universal compiler source; no new source lineage. Geometry and per-finger references are fixed before any layout." +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/anchor.json new file mode 100644 index 00000000..1b214c95 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/anchor.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c14_cfg1", + "configuration_id": "anchor", + "reference_id": "c14_cfg1_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/dev_len075.json b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/dev_len075.json new file mode 100644 index 00000000..0314860a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/dev_len075.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c14_cfg1", + "configuration_id": "dev_len075", + "reference_id": "c14_cfg1_dev_len075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/dev_len150.json b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/dev_len150.json new file mode 100644 index 00000000..575b3ac4 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/dev_len150.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c14_cfg1", + "configuration_id": "dev_len150", + "reference_id": "c14_cfg1_dev_len150_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/dev_len200.json b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/dev_len200.json new file mode 100644 index 00000000..2868d59a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/dev_len200.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c14_cfg1", + "configuration_id": "dev_len200", + "reference_id": "c14_cfg1_dev_len200_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/dev_nf_1half.json b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/dev_nf_1half.json new file mode 100644 index 00000000..2cc2a07a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/dev_nf_1half.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c14_cfg1", + "configuration_id": "dev_nf_1half", + "reference_id": "c14_cfg1_dev_nf_1half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..6b93de12 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/dev_nf_double.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c14_cfg1", + "configuration_id": "dev_nf_double", + "reference_id": "c14_cfg1_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/dev_nf_half.json b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/dev_nf_half.json new file mode 100644 index 00000000..4a97c227 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/dev_nf_half.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c14_cfg1", + "configuration_id": "dev_nf_half", + "reference_id": "c14_cfg1_dev_nf_half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/dev_unit075.json new file mode 100644 index 00000000..8043e50d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/dev_unit075.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c14_cfg1", + "configuration_id": "dev_unit075", + "reference_id": "c14_cfg1_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/dev_unit100.json b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/dev_unit100.json new file mode 100644 index 00000000..46940c6d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/contracts/dev_unit100.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c14_cfg1", + "configuration_id": "dev_unit100", + "reference_id": "c14_cfg1_dev_unit100_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_cfg1_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/anchor.spice new file mode 100644 index 00000000..52966bb2 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/anchor.spice @@ -0,0 +1,24 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f4 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f5 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f4 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f5 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f1 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f2 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f3 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f2 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f3 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f4 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f5 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/dev_len075.spice b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/dev_len075.spice new file mode 100644 index 00000000..a53d71db --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/dev_len075.spice @@ -0,0 +1,24 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f2 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f3 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f4 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f5 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f2 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f3 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f4 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f5 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f1 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f2 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f3 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f2 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f3 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f4 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f5 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/dev_len150.spice b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/dev_len150.spice new file mode 100644 index 00000000..7a8c5d76 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/dev_len150.spice @@ -0,0 +1,24 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f2 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f3 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f4 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f5 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f2 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f3 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f4 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f5 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f1 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f2 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f3 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM4_f2 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM4_f3 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM4_f4 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM4_f5 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/dev_len200.spice b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/dev_len200.spice new file mode 100644 index 00000000..b7e53ba3 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/dev_len200.spice @@ -0,0 +1,24 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f2 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f3 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f4 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f5 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f2 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f3 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f4 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f5 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f1 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f2 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f3 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM4_f2 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM4_f3 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM4_f4 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM4_f5 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/dev_nf_1half.spice b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/dev_nf_1half.spice new file mode 100644 index 00000000..fc49cb45 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/dev_nf_1half.spice @@ -0,0 +1,35 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f4 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f5 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f6 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f7 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f8 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f4 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f5 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f6 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f7 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f8 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f1 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f2 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f3 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f4 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f5 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f2 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f3 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f4 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f5 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f6 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f7 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f8 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/dev_nf_double.spice new file mode 100644 index 00000000..faf79932 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/dev_nf_double.spice @@ -0,0 +1,46 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f4 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f5 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f6 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f7 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f8 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f9 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f10 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f11 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f4 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f5 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f6 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f7 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f8 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f9 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f10 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f11 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f1 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f2 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f3 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f4 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f5 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f6 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f7 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f2 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f3 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f4 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f5 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f6 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f7 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f8 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f9 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f10 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f11 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/dev_nf_half.spice b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/dev_nf_half.spice new file mode 100644 index 00000000..cc9956b3 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/dev_nf_half.spice @@ -0,0 +1,13 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f1 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f2 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/dev_unit075.spice new file mode 100644 index 00000000..2e52a222 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/dev_unit075.spice @@ -0,0 +1,24 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f2 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f3 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f4 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f5 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f2 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f3 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f4 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f5 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM3_f1 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM3_f2 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM3_f3 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM4_f2 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM4_f3 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM4_f4 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM4_f5 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/dev_unit100.spice b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/dev_unit100.spice new file mode 100644 index 00000000..69c8e310 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg1_family/references/dev_unit100.spice @@ -0,0 +1,24 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f2 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f3 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f4 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f5 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f2 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f3 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f4 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f5 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM3_f1 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM3_f2 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM3_f3 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f2 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f3 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f4 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f5 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/circuit_input.json new file mode 100644 index 00000000..33b35815 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/circuit_input.json @@ -0,0 +1,87 @@ +{ + "circuit_id": "C14", + "name": "regulated_cascode_current_mirror", + "ports": [ + "VSS", + "IIN1", + "IOUT1", + "IREF1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IIN1", + "IIN1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "net11", + "IIN1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "IREF1", + "net11", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "nfet", + "nets": [ + "IOUT1", + "IREF1", + "net11", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 936, + "files": [ + "Dataset/936/936.cir", + "Dataset/936/Port936.txt", + "Dataset/936/Pagenumber936.txt", + "Dataset/936/Book936.png", + "Dataset/936/Cadence936.png" + ], + "book": "P. E. Allen, D. R. Holberg, CMOS Analog Circuit Design, 3rd ed., Oxford University Press, 2012", + "book_key": "allen", + "page_ref": "147", + "device_name_map": { + "M1": "M3", + "M2": "M1", + "M3": "M2", + "M4": "M0" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/936/Book936.png", + "observation": "Allen p.147 scan: M4 diode (II), M2 mirror, M1 regulating device biased by IREG, M3 output cascode; regulated cascode" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/configurations.json new file mode 100644 index 00000000..03b5232c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/configurations.json @@ -0,0 +1,293 @@ +{ + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_ONLY", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C14", + "domain_id": "C14_cfg2", + "textbook_sizing_source": "presimulated size configuration cfg2 of the textbook benchmark", + "circuit_name": "regulated_cascode_current_mirror", + "bench_category": "mirror", + "circuit_input_file": "configs/development/c14_cfg2_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.6, + "nf": 2 + }, + "M2": { + "w": 2.0, + "l": 0.6, + "nf": 2 + }, + "M3": { + "w": 1.0, + "l": 0.6, + "nf": 1 + }, + "M4": { + "w": 2.0, + "l": 0.6, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c14_cfg2_family/references/anchor.spice", + "contract_file": "configs/development/c14_cfg2_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.6, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 0.6, + "nf": 4 + }, + "M3": { + "w": 2.0, + "l": 0.6, + "nf": 2 + }, + "M4": { + "w": 4.0, + "l": 0.6, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c14_cfg2_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c14_cfg2_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.45, + "nf": 2 + }, + "M2": { + "w": 2.0, + "l": 0.45, + "nf": 2 + }, + "M3": { + "w": 1.0, + "l": 0.45, + "nf": 1 + }, + "M4": { + "w": 2.0, + "l": 0.45, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c14_cfg2_family/references/dev_len075.spice", + "contract_file": "configs/development/c14_cfg2_family/contracts/dev_len075.json" + }, + { + "configuration_id": "dev_len150", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.9, + "nf": 2 + }, + "M2": { + "w": 2.0, + "l": 0.9, + "nf": 2 + }, + "M3": { + "w": 1.0, + "l": 0.9, + "nf": 1 + }, + "M4": { + "w": 2.0, + "l": 0.9, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c14_cfg2_family/references/dev_len150.spice", + "contract_file": "configs/development/c14_cfg2_family/contracts/dev_len150.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.5, + "l": 0.6, + "nf": 2 + }, + "M2": { + "w": 1.5, + "l": 0.6, + "nf": 2 + }, + "M3": { + "w": 0.75, + "l": 0.6, + "nf": 1 + }, + "M4": { + "w": 1.5, + "l": 0.6, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c14_cfg2_family/references/dev_unit075.spice", + "contract_file": "configs/development/c14_cfg2_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_len200", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 1.2, + "nf": 2 + }, + "M2": { + "w": 2.0, + "l": 1.2, + "nf": 2 + }, + "M3": { + "w": 1.0, + "l": 1.2, + "nf": 1 + }, + "M4": { + "w": 2.0, + "l": 1.2, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c14_cfg2_family/references/dev_len200.spice", + "contract_file": "configs/development/c14_cfg2_family/contracts/dev_len200.json" + }, + { + "configuration_id": "dev_nf_triple", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.6, + "nf": 6 + }, + "M2": { + "w": 6.0, + "l": 0.6, + "nf": 6 + }, + "M3": { + "w": 3.0, + "l": 0.6, + "nf": 3 + }, + "M4": { + "w": 6.0, + "l": 0.6, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c14_cfg2_family/references/dev_nf_triple.spice", + "contract_file": "configs/development/c14_cfg2_family/contracts/dev_nf_triple.json" + }, + { + "configuration_id": "dev_unit125", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.5, + "l": 0.6, + "nf": 2 + }, + "M2": { + "w": 2.5, + "l": 0.6, + "nf": 2 + }, + "M3": { + "w": 1.25, + "l": 0.6, + "nf": 1 + }, + "M4": { + "w": 2.5, + "l": 0.6, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c14_cfg2_family/references/dev_unit125.spice", + "contract_file": "configs/development/c14_cfg2_family/contracts/dev_unit125.json" + }, + { + "configuration_id": "dev_len125", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.75, + "nf": 2 + }, + "M2": { + "w": 2.0, + "l": 0.75, + "nf": 2 + }, + "M3": { + "w": 1.0, + "l": 0.75, + "nf": 1 + }, + "M4": { + "w": 2.0, + "l": 0.75, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c14_cfg2_family/references/dev_len125.spice", + "contract_file": "configs/development/c14_cfg2_family/contracts/dev_len125.json" + } + ], + "textbook_specification_floors": { + "err": { + "abs_max": 0.03 + }, + "vmin": { + "max": 1.08 + } + }, + "declared_by": "scripts/prepare_textbook_train_domains.py", + "ancestry": "Same cropped universal compiler source; no new source lineage. Geometry and per-finger references are fixed before any layout." +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/anchor.json new file mode 100644 index 00000000..b883d419 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/anchor.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c14_cfg2", + "configuration_id": "anchor", + "reference_id": "c14_cfg2_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/dev_len075.json b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/dev_len075.json new file mode 100644 index 00000000..ccad3f25 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/dev_len075.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c14_cfg2", + "configuration_id": "dev_len075", + "reference_id": "c14_cfg2_dev_len075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/dev_len125.json b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/dev_len125.json new file mode 100644 index 00000000..14e2066d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/dev_len125.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c14_cfg2", + "configuration_id": "dev_len125", + "reference_id": "c14_cfg2_dev_len125_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/dev_len150.json b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/dev_len150.json new file mode 100644 index 00000000..b7c65fcb --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/dev_len150.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c14_cfg2", + "configuration_id": "dev_len150", + "reference_id": "c14_cfg2_dev_len150_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/dev_len200.json b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/dev_len200.json new file mode 100644 index 00000000..67733f70 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/dev_len200.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c14_cfg2", + "configuration_id": "dev_len200", + "reference_id": "c14_cfg2_dev_len200_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..e8663f9b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/dev_nf_double.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c14_cfg2", + "configuration_id": "dev_nf_double", + "reference_id": "c14_cfg2_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/dev_nf_triple.json b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/dev_nf_triple.json new file mode 100644 index 00000000..d56b5dfc --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/dev_nf_triple.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c14_cfg2", + "configuration_id": "dev_nf_triple", + "reference_id": "c14_cfg2_dev_nf_triple_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/dev_unit075.json new file mode 100644 index 00000000..c4410d5a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/dev_unit075.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c14_cfg2", + "configuration_id": "dev_unit075", + "reference_id": "c14_cfg2_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/dev_unit125.json b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/dev_unit125.json new file mode 100644 index 00000000..b84fc1f0 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/contracts/dev_unit125.json @@ -0,0 +1,106 @@ +{ + "task_id": "development_train_domain_c14_cfg2", + "configuration_id": "dev_unit125", + "reference_id": "c14_cfg2_dev_unit125_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_cfg2_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + }, + "declared_deviation": null + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/anchor.spice new file mode 100644 index 00000000..5c335406 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/anchor.spice @@ -0,0 +1,9 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/dev_len075.spice b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/dev_len075.spice new file mode 100644 index 00000000..c25cdacb --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/dev_len075.spice @@ -0,0 +1,9 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.45 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/dev_len125.spice b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/dev_len125.spice new file mode 100644 index 00000000..3ade99dd --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/dev_len125.spice @@ -0,0 +1,9 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.75 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.75 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.75 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.75 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.75 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.75 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.75 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/dev_len150.spice b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/dev_len150.spice new file mode 100644 index 00000000..48cf39f0 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/dev_len150.spice @@ -0,0 +1,9 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.9 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.9 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.9 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.9 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.9 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.9 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.9 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/dev_len200.spice b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/dev_len200.spice new file mode 100644 index 00000000..cec56277 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/dev_len200.spice @@ -0,0 +1,9 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=1.2 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/dev_nf_double.spice new file mode 100644 index 00000000..543194d8 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/dev_nf_double.spice @@ -0,0 +1,16 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f2 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f3 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f2 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f3 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM3_f1 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f2 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f3 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/dev_nf_triple.spice b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/dev_nf_triple.spice new file mode 100644 index 00000000..a746cf73 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/dev_nf_triple.spice @@ -0,0 +1,23 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f2 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f3 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f4 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f5 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f2 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f3 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f4 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f5 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM3_f1 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM3_f2 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f2 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f3 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f4 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f5 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/dev_unit075.spice new file mode 100644 index 00000000..e5687f5d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/dev_unit075.spice @@ -0,0 +1,9 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/dev_unit125.spice b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/dev_unit125.spice new file mode 100644 index 00000000..9891c1aa --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_cfg2_family/references/dev_unit125.spice @@ -0,0 +1,9 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.6 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.6 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.6 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.6 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.6 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.6 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1.25 l=0.6 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/c14_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/c14_family/circuit_input.json new file mode 100644 index 00000000..33b35815 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_family/circuit_input.json @@ -0,0 +1,87 @@ +{ + "circuit_id": "C14", + "name": "regulated_cascode_current_mirror", + "ports": [ + "VSS", + "IIN1", + "IOUT1", + "IREF1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IIN1", + "IIN1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "net11", + "IIN1", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "IREF1", + "net11", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "nfet", + "nets": [ + "IOUT1", + "IREF1", + "net11", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 936, + "files": [ + "Dataset/936/936.cir", + "Dataset/936/Port936.txt", + "Dataset/936/Pagenumber936.txt", + "Dataset/936/Book936.png", + "Dataset/936/Cadence936.png" + ], + "book": "P. E. Allen, D. R. Holberg, CMOS Analog Circuit Design, 3rd ed., Oxford University Press, 2012", + "book_key": "allen", + "page_ref": "147", + "device_name_map": { + "M1": "M3", + "M2": "M1", + "M3": "M2", + "M4": "M0" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/936/Book936.png", + "observation": "Allen p.147 scan: M4 diode (II), M2 mirror, M1 regulating device biased by IREG, M3 output cascode; regulated cascode" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_family/configurations.json b/benchmarks/code_behind_layout/configs/development/c14_family/configurations.json new file mode 100644 index 00000000..b8a45148 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_family/configurations.json @@ -0,0 +1,291 @@ +{ + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_ONLY", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "C14", + "circuit_name": "regulated_cascode_current_mirror", + "bench_category": "mirror", + "circuit_input_file": "configs/development/c14_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M2": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M3": { + "w": 1.0, + "l": 0.6, + "nf": 2 + }, + "M4": { + "w": 2.0, + "l": 0.6, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c14_family/references/anchor.spice", + "contract_file": "configs/development/c14_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.0, + "l": 0.6, + "nf": 2 + }, + "M2": { + "w": 1.0, + "l": 0.6, + "nf": 2 + }, + "M3": { + "w": 0.5, + "l": 0.6, + "nf": 1 + }, + "M4": { + "w": 1.0, + "l": 0.6, + "nf": 2 + } + } + }, + "reference_file": "configs/development/c14_family/references/dev_nf_half.spice", + "contract_file": "configs/development/c14_family/contracts/dev_nf_half.json" + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.6, + "nf": 6 + }, + "M2": { + "w": 3.0, + "l": 0.6, + "nf": 6 + }, + "M3": { + "w": 1.5, + "l": 0.6, + "nf": 3 + }, + "M4": { + "w": 3.0, + "l": 0.6, + "nf": 6 + } + } + }, + "reference_file": "configs/development/c14_family/references/dev_nf_1half.spice", + "contract_file": "configs/development/c14_family/contracts/dev_nf_1half.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "M3": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M4": { + "w": 4.0, + "l": 0.6, + "nf": 8 + } + } + }, + "reference_file": "configs/development/c14_family/references/dev_nf_double.spice", + "contract_file": "configs/development/c14_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.45, + "nf": 4 + }, + "M2": { + "w": 2.0, + "l": 0.45, + "nf": 4 + }, + "M3": { + "w": 1.0, + "l": 0.45, + "nf": 2 + }, + "M4": { + "w": 2.0, + "l": 0.45, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c14_family/references/dev_len075.spice", + "contract_file": "configs/development/c14_family/contracts/dev_len075.json" + }, + { + "configuration_id": "dev_len150", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.9, + "nf": 4 + }, + "M2": { + "w": 2.0, + "l": 0.9, + "nf": 4 + }, + "M3": { + "w": 1.0, + "l": 0.9, + "nf": 2 + }, + "M4": { + "w": 2.0, + "l": 0.9, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c14_family/references/dev_len150.spice", + "contract_file": "configs/development/c14_family/contracts/dev_len150.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.6, + "nf": 4 + }, + "M2": { + "w": 3.0, + "l": 0.6, + "nf": 4 + }, + "M3": { + "w": 1.5, + "l": 0.6, + "nf": 2 + }, + "M4": { + "w": 3.0, + "l": 0.6, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c14_family/references/dev_unit075.spice", + "contract_file": "configs/development/c14_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_unit100", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.6, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 0.6, + "nf": 4 + }, + "M3": { + "w": 2.0, + "l": 0.6, + "nf": 2 + }, + "M4": { + "w": 4.0, + "l": 0.6, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c14_family/references/dev_unit100.spice", + "contract_file": "configs/development/c14_family/contracts/dev_unit100.json" + }, + { + "configuration_id": "dev_len200", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 1.2, + "nf": 4 + }, + "M2": { + "w": 2.0, + "l": 1.2, + "nf": 4 + }, + "M3": { + "w": 1.0, + "l": 1.2, + "nf": 2 + }, + "M4": { + "w": 2.0, + "l": 1.2, + "nf": 4 + } + } + }, + "reference_file": "configs/development/c14_family/references/dev_len200.spice", + "contract_file": "configs/development/c14_family/contracts/dev_len200.json" + } + ], + "textbook_specification_floors": { + "err": { + "abs_max": 0.03 + }, + "vmin": { + "max": 1.08 + } + }, + "declared_by": "scripts/prepare_textbook_train_domains.py", + "ancestry": "Same cropped universal compiler source; no new source lineage. Geometry and per-finger references are fixed before any layout." +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/c14_family/contracts/anchor.json new file mode 100644 index 00000000..142f6f4b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_family/contracts/anchor.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c14", + "configuration_id": "anchor", + "reference_id": "c14_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_len075.json b/benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_len075.json new file mode 100644 index 00000000..085d3f02 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_len075.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c14", + "configuration_id": "dev_len075", + "reference_id": "c14_dev_len075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_len150.json b/benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_len150.json new file mode 100644 index 00000000..8719613d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_len150.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c14", + "configuration_id": "dev_len150", + "reference_id": "c14_dev_len150_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_len200.json b/benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_len200.json new file mode 100644 index 00000000..1afa52f0 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_len200.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c14", + "configuration_id": "dev_len200", + "reference_id": "c14_dev_len200_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_nf_1half.json b/benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_nf_1half.json new file mode 100644 index 00000000..ad6f3ea1 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_nf_1half.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c14", + "configuration_id": "dev_nf_1half", + "reference_id": "c14_dev_nf_1half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..3efe7ce9 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_nf_double.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c14", + "configuration_id": "dev_nf_double", + "reference_id": "c14_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_nf_half.json b/benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_nf_half.json new file mode 100644 index 00000000..b0b8e354 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_nf_half.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c14", + "configuration_id": "dev_nf_half", + "reference_id": "c14_dev_nf_half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_unit075.json new file mode 100644 index 00000000..663b2ff0 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_unit075.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c14", + "configuration_id": "dev_unit075", + "reference_id": "c14_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_unit100.json b/benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_unit100.json new file mode 100644 index 00000000..5e052004 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_family/contracts/dev_unit100.json @@ -0,0 +1,105 @@ +{ + "task_id": "development_train_domain_c14", + "configuration_id": "dev_unit100", + "reference_id": "c14_dev_unit100_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "bench_category": "mirror", + "objective": { + "id": "c14_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual schematic and full physical domain qualification; prospective application constraints are not formal labels." + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.03, + "compliance_low_V_max": 1.08 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 2e-05, + "extra_current_sources_A": { + "IREF1": 5e-06 + }, + "output_test_V": 1.17, + "tolerance": 0.03, + "output_transient_levels_V": [ + 1.145, + 1.195 + ], + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "load_definition": "Output voltage source swept over the full supply range; output-port current is measured. The reference current enters IIN1 from the 1.8 V supply; declared extra bias currents enter their ports from the same supply.", + "power_definition": "DUT has no VDD pin. Report input-port and output-port dissipation and the external reference-supply work separately.", + "textbook_case": { + "load": { + "vout_nom": 1.1700000000000002, + "tol": 0.03 + }, + "bias": { + "IIN1": { + "i": 2e-05, + "from": "VDD" + }, + "IREF1": { + "i": 5e-06, + "from": "VDD" + }, + "IREF": 2e-05 + }, + "rule": "textbook_sharing.nominal first-pass point" + } + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/c14_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/c14_family/references/anchor.spice new file mode 100644 index 00000000..963712a0 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_family/references/anchor.spice @@ -0,0 +1,16 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f1 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f2 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f3 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/c14_family/references/dev_len075.spice b/benchmarks/code_behind_layout/configs/development/c14_family/references/dev_len075.spice new file mode 100644 index 00000000..ceca81e3 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_family/references/dev_len075.spice @@ -0,0 +1,16 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f2 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f3 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f2 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f3 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM3_f1 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f2 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM4_f3 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/c14_family/references/dev_len150.spice b/benchmarks/code_behind_layout/configs/development/c14_family/references/dev_len150.spice new file mode 100644 index 00000000..951ad10a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_family/references/dev_len150.spice @@ -0,0 +1,16 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f2 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM1_f3 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f2 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM2_f3 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM3_f1 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM4_f2 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +XM4_f3 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.9 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/c14_family/references/dev_len200.spice b/benchmarks/code_behind_layout/configs/development/c14_family/references/dev_len200.spice new file mode 100644 index 00000000..a85bed8f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_family/references/dev_len200.spice @@ -0,0 +1,16 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f2 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM1_f3 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f2 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM2_f3 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM3_f1 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM4_f2 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +XM4_f3 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=1.2 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/c14_family/references/dev_nf_1half.spice b/benchmarks/code_behind_layout/configs/development/c14_family/references/dev_nf_1half.spice new file mode 100644 index 00000000..0d6790a5 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_family/references/dev_nf_1half.spice @@ -0,0 +1,23 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f4 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f5 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f4 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f5 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f1 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f2 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f2 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f3 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f4 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f5 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/c14_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/c14_family/references/dev_nf_double.spice new file mode 100644 index 00000000..5b29c864 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_family/references/dev_nf_double.spice @@ -0,0 +1,30 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f4 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f5 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f6 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f7 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f4 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f5 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f6 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f7 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f1 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f2 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f3 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f2 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f3 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f4 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f5 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f6 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f7 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/c14_family/references/dev_nf_half.spice b/benchmarks/code_behind_layout/configs/development/c14_family/references/dev_nf_half.spice new file mode 100644 index 00000000..c53e8aac --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_family/references/dev_nf_half.spice @@ -0,0 +1,9 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/c14_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/c14_family/references/dev_unit075.spice new file mode 100644 index 00000000..09220515 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_family/references/dev_unit075.spice @@ -0,0 +1,16 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f2 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM1_f3 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f2 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM2_f3 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM3_f1 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM4_f2 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +XM4_f3 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.6 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/c14_family/references/dev_unit100.spice b/benchmarks/code_behind_layout/configs/development/c14_family/references/dev_unit100.spice new file mode 100644 index 00000000..543194d8 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/c14_family/references/dev_unit100.spice @@ -0,0 +1,16 @@ +.subckt corpus_c14 VSS IIN1 IOUT1 IREF1 +XM1_f0 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f1 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f2 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM1_f3 IIN1 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f0 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f1 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f2 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM2_f3 net11 IIN1 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM3_f0 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM3_f1 IREF1 net11 VSS VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f0 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f1 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f2 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +XM4_f3 IOUT1 IREF1 net11 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.6 +.ends corpus_c14 diff --git a/benchmarks/code_behind_layout/configs/development/candidate_task_catalog.json b/benchmarks/code_behind_layout/configs/development/candidate_task_catalog.json new file mode 100644 index 00000000..1bf384c4 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/candidate_task_catalog.json @@ -0,0 +1,636 @@ +{ + "status": "DRAFT_CANDIDATE_CATALOG_NOT_FORMAL_TASKS", + "scope": "E1_E3_shared_circuit_targets_E2_OTA_subset", + "actual_formal_tasks": 0, + "candidate_slots": 24, + "qualified_independent_evaluation_lineages": null, + "candidate_target_implementations": [ + { + "lineage_id": "glayout_mirror", + "target_kind": "current_mirror", + "source": "src/glayout/cells/elementary/current_mirror/current_mirror.py", + "topology_family": "mirror", + "qualification": "three_corner_OP_available_DC_characterization_active", + "independence": "candidate_target_implementation_not_yet_qualified_independent_cluster", + "source_root": "remote_research_glayout", + "editable_paths_pending_source_snapshot": true + }, + { + "lineage_id": "glayout_pair", + "target_kind": "differential_pair", + "source": "src/glayout/cells/elementary/diff_pair/diff_pair.py", + "topology_family": "differential_pair", + "qualification": "independent_full_characterization_required", + "independence": "candidate_target_implementation_not_yet_qualified_independent_cluster", + "source_root": "remote_research_glayout", + "editable_paths_pending_source_snapshot": true + }, + { + "lineage_id": "glayout_fvf", + "target_kind": "flipped_voltage_follower", + "source": "src/glayout/cells/elementary/FVF/fvf.py", + "topology_family": "fvf_feedback", + "qualification": "full_physical_OP_available_dynamic_domain_required", + "independence": "candidate_target_implementation_not_yet_qualified_independent_cluster", + "source_root": "remote_research_glayout", + "editable_paths_pending_source_snapshot": true + }, + { + "lineage_id": "glayout_tg", + "target_kind": "transmission_gate", + "source": "src/glayout/cells/elementary/transmission_gate/transmission_gate.py", + "topology_family": "transmission_gate", + "qualification": "full_physical_OP_available_Ron_leakage_contract_required", + "independence": "candidate_target_implementation_not_yet_qualified_independent_cluster", + "source_root": "remote_research_glayout", + "editable_paths_pending_source_snapshot": true + }, + { + "lineage_id": "glayout_miller", + "target_kind": "two_stage_ota", + "source": "src/glayout/cells/composite/opamp/opamp_twostage.py", + "topology_family": "miller_ota", + "qualification": "full_three_corner_flow_available_performance_feasible_domain_pending", + "independence": "candidate_target_implementation_not_yet_qualified_independent_cluster", + "source_root": "remote_research_glayout", + "editable_paths_pending_source_snapshot": true + }, + { + "lineage_id": "glayout_fvf_ota", + "target_kind": "fvf_class_ab_ota", + "source": "src/glayout/cells/composite/fvf_based_ota/ota.py", + "topology_family": "fvf_feedback", + "qualification": "full_three_corner_flow_available_58_to66deg_PM_at10p_development", + "independence": "candidate_target_implementation_not_yet_qualified_independent_cluster", + "source_root": "remote_research_glayout", + "editable_paths_pending_source_snapshot": true + }, + { + "lineage_id": "research_five_t", + "target_kind": "five_transistor_ota", + "source": "src/generators/five_t.py", + "topology_family": "five_t_ota", + "qualification": "full_three_corner_flow_available", + "independence": "candidate_target_implementation_not_yet_qualified_independent_cluster", + "source_root": "research_local", + "editable_paths_pending_source_snapshot": true + }, + { + "lineage_id": "research_compact_miller", + "target_kind": "compact_two_stage_ota", + "source": "src/generators/compact_miller.py", + "topology_family": "miller_ota", + "qualification": "physical_qualification_active", + "independence": "candidate_target_implementation_not_yet_qualified_independent_cluster", + "source_root": "research_local", + "editable_paths_pending_source_snapshot": true + } + ], + "candidate_tasks": [ + { + "task_id": "mirror_01", + "parent_lineage": "glayout_mirror", + "topology_family": "mirror", + "editing_face": "geometry_at_legal_boundaries", + "status": "DEVELOPMENT_CANDIDATE_REQUIRES_ACTUAL_CASE_HARVEST", + "origin": null, + "origin_requirement": "observed_natural_failure_or_shortfall_preferred", + "E1_stratum": "reuse", + "domain_shape": { + "anchor": 1, + "development": 8, + "hidden": 16 + }, + "actual_configurations": [], + "contract": null, + "baseline_evidence": [], + "known_feasible_evidence": [], + "formal_admission": false, + "engineering_pilot_cases_must_be_excluded": true + }, + { + "task_id": "mirror_02", + "parent_lineage": "glayout_mirror", + "topology_family": "mirror", + "editing_face": "terminal_connectivity_and_port_routing", + "status": "DEVELOPMENT_CANDIDATE_REQUIRES_ACTUAL_CASE_HARVEST", + "origin": null, + "origin_requirement": "natural_or_disclosed_controlled_injection", + "E1_stratum": "composition", + "domain_shape": { + "anchor": 1, + "development": 8, + "hidden": 16 + }, + "actual_configurations": [], + "contract": null, + "baseline_evidence": [], + "known_feasible_evidence": [], + "formal_admission": false, + "engineering_pilot_cases_must_be_excluded": true + }, + { + "task_id": "mirror_03", + "parent_lineage": "glayout_mirror", + "topology_family": "mirror", + "editing_face": "post_RC_quality_and_regression", + "status": "DEVELOPMENT_CANDIDATE_REQUIRES_ACTUAL_CASE_HARVEST", + "origin": null, + "origin_requirement": "observed_natural_failure_or_shortfall_preferred", + "E1_stratum": "reuse", + "domain_shape": { + "anchor": 1, + "development": 8, + "hidden": 16 + }, + "actual_configurations": [], + "contract": null, + "baseline_evidence": [], + "known_feasible_evidence": [], + "formal_admission": false, + "engineering_pilot_cases_must_be_excluded": true + }, + { + "task_id": "pair_01", + "parent_lineage": "glayout_pair", + "topology_family": "differential_pair", + "editing_face": "geometry_at_legal_boundaries", + "status": "DEVELOPMENT_CANDIDATE_REQUIRES_ACTUAL_CASE_HARVEST", + "origin": null, + "origin_requirement": "observed_natural_failure_or_shortfall_preferred", + "E1_stratum": "composition", + "domain_shape": { + "anchor": 1, + "development": 8, + "hidden": 16 + }, + "actual_configurations": [], + "contract": null, + "baseline_evidence": [], + "known_feasible_evidence": [], + "formal_admission": false, + "engineering_pilot_cases_must_be_excluded": true + }, + { + "task_id": "pair_02", + "parent_lineage": "glayout_pair", + "topology_family": "differential_pair", + "editing_face": "terminal_connectivity_and_port_routing", + "status": "DEVELOPMENT_CANDIDATE_REQUIRES_ACTUAL_CASE_HARVEST", + "origin": null, + "origin_requirement": "natural_or_disclosed_controlled_injection", + "E1_stratum": "reuse", + "domain_shape": { + "anchor": 1, + "development": 8, + "hidden": 16 + }, + "actual_configurations": [], + "contract": null, + "baseline_evidence": [], + "known_feasible_evidence": [], + "formal_admission": false, + "engineering_pilot_cases_must_be_excluded": true + }, + { + "task_id": "pair_03", + "parent_lineage": "glayout_pair", + "topology_family": "differential_pair", + "editing_face": "post_RC_quality_and_regression", + "status": "DEVELOPMENT_CANDIDATE_REQUIRES_ACTUAL_CASE_HARVEST", + "origin": null, + "origin_requirement": "observed_natural_failure_or_shortfall_preferred", + "E1_stratum": "composition", + "domain_shape": { + "anchor": 1, + "development": 8, + "hidden": 16 + }, + "actual_configurations": [], + "contract": null, + "baseline_evidence": [], + "known_feasible_evidence": [], + "formal_admission": false, + "engineering_pilot_cases_must_be_excluded": true + }, + { + "task_id": "follower_01", + "parent_lineage": "glayout_fvf", + "topology_family": "fvf_feedback", + "editing_face": "geometry_at_legal_boundaries", + "status": "DEVELOPMENT_CANDIDATE_REQUIRES_ACTUAL_CASE_HARVEST", + "origin": null, + "origin_requirement": "observed_natural_failure_or_shortfall_preferred", + "E1_stratum": "reuse", + "domain_shape": { + "anchor": 1, + "development": 8, + "hidden": 16 + }, + "actual_configurations": [], + "contract": null, + "baseline_evidence": [], + "known_feasible_evidence": [], + "formal_admission": false, + "engineering_pilot_cases_must_be_excluded": true + }, + { + "task_id": "follower_02", + "parent_lineage": "glayout_fvf", + "topology_family": "fvf_feedback", + "editing_face": "terminal_connectivity_and_port_routing", + "status": "DEVELOPMENT_CANDIDATE_REQUIRES_ACTUAL_CASE_HARVEST", + "origin": null, + "origin_requirement": "natural_or_disclosed_controlled_injection", + "E1_stratum": "composition", + "domain_shape": { + "anchor": 1, + "development": 8, + "hidden": 16 + }, + "actual_configurations": [], + "contract": null, + "baseline_evidence": [], + "known_feasible_evidence": [], + "formal_admission": false, + "engineering_pilot_cases_must_be_excluded": true + }, + { + "task_id": "follower_03", + "parent_lineage": "glayout_fvf", + "topology_family": "fvf_feedback", + "editing_face": "post_RC_quality_and_regression", + "status": "DEVELOPMENT_CANDIDATE_REQUIRES_ACTUAL_CASE_HARVEST", + "origin": null, + "origin_requirement": "observed_natural_failure_or_shortfall_preferred", + "E1_stratum": "reuse", + "domain_shape": { + "anchor": 1, + "development": 8, + "hidden": 16 + }, + "actual_configurations": [], + "contract": null, + "baseline_evidence": [], + "known_feasible_evidence": [], + "formal_admission": false, + "engineering_pilot_cases_must_be_excluded": true + }, + { + "task_id": "passgate_01", + "parent_lineage": "glayout_tg", + "topology_family": "transmission_gate", + "editing_face": "geometry_at_legal_boundaries", + "status": "DEVELOPMENT_CANDIDATE_REQUIRES_ACTUAL_CASE_HARVEST", + "origin": null, + "origin_requirement": "observed_natural_failure_or_shortfall_preferred", + "E1_stratum": "composition", + "domain_shape": { + "anchor": 1, + "development": 8, + "hidden": 16 + }, + "actual_configurations": [], + "contract": null, + "baseline_evidence": [], + "known_feasible_evidence": [], + "formal_admission": false, + "engineering_pilot_cases_must_be_excluded": true + }, + { + "task_id": "passgate_02", + "parent_lineage": "glayout_tg", + "topology_family": "transmission_gate", + "editing_face": "terminal_connectivity_and_port_routing", + "status": "DEVELOPMENT_CANDIDATE_REQUIRES_ACTUAL_CASE_HARVEST", + "origin": null, + "origin_requirement": "natural_or_disclosed_controlled_injection", + "E1_stratum": "reuse", + "domain_shape": { + "anchor": 1, + "development": 8, + "hidden": 16 + }, + "actual_configurations": [], + "contract": null, + "baseline_evidence": [], + "known_feasible_evidence": [], + "formal_admission": false, + "engineering_pilot_cases_must_be_excluded": true + }, + { + "task_id": "passgate_03", + "parent_lineage": "glayout_tg", + "topology_family": "transmission_gate", + "editing_face": "post_RC_quality_and_regression", + "status": "DEVELOPMENT_CANDIDATE_REQUIRES_ACTUAL_CASE_HARVEST", + "origin": null, + "origin_requirement": "observed_natural_failure_or_shortfall_preferred", + "E1_stratum": "composition", + "domain_shape": { + "anchor": 1, + "development": 8, + "hidden": 16 + }, + "actual_configurations": [], + "contract": null, + "baseline_evidence": [], + "known_feasible_evidence": [], + "formal_admission": false, + "engineering_pilot_cases_must_be_excluded": true + }, + { + "task_id": "legacy_ota_01", + "parent_lineage": "glayout_miller", + "topology_family": "miller_ota", + "editing_face": "geometry_at_legal_boundaries", + "status": "DEVELOPMENT_CANDIDATE_REQUIRES_ACTUAL_CASE_HARVEST", + "origin": null, + "origin_requirement": "observed_natural_failure_or_shortfall_preferred", + "E1_stratum": "reuse", + "domain_shape": { + "anchor": 1, + "development": 8, + "hidden": 16 + }, + "actual_configurations": [], + "contract": null, + "baseline_evidence": [], + "known_feasible_evidence": [], + "formal_admission": false, + "engineering_pilot_cases_must_be_excluded": true + }, + { + "task_id": "legacy_ota_02", + "parent_lineage": "glayout_miller", + "topology_family": "miller_ota", + "editing_face": "terminal_connectivity_and_port_routing", + "status": "DEVELOPMENT_CANDIDATE_REQUIRES_ACTUAL_CASE_HARVEST", + "origin": null, + "origin_requirement": "natural_or_disclosed_controlled_injection", + "E1_stratum": "composition", + "domain_shape": { + "anchor": 1, + "development": 8, + "hidden": 16 + }, + "actual_configurations": [], + "contract": null, + "baseline_evidence": [], + "known_feasible_evidence": [], + "formal_admission": false, + "engineering_pilot_cases_must_be_excluded": true + }, + { + "task_id": "legacy_ota_03", + "parent_lineage": "glayout_miller", + "topology_family": "miller_ota", + "editing_face": "post_RC_quality_and_regression", + "status": "DEVELOPMENT_CANDIDATE_REQUIRES_ACTUAL_CASE_HARVEST", + "origin": null, + "origin_requirement": "observed_natural_failure_or_shortfall_preferred", + "E1_stratum": "reuse", + "domain_shape": { + "anchor": 1, + "development": 8, + "hidden": 16 + }, + "actual_configurations": [], + "contract": null, + "baseline_evidence": [], + "known_feasible_evidence": [], + "formal_admission": false, + "engineering_pilot_cases_must_be_excluded": true + }, + { + "task_id": "fvf_ota_01", + "parent_lineage": "glayout_fvf_ota", + "topology_family": "fvf_feedback", + "editing_face": "geometry_at_legal_boundaries", + "status": "DEVELOPMENT_CANDIDATE_REQUIRES_ACTUAL_CASE_HARVEST", + "origin": null, + "origin_requirement": "observed_natural_failure_or_shortfall_preferred", + "E1_stratum": "composition", + "domain_shape": { + "anchor": 1, + "development": 8, + "hidden": 16 + }, + "actual_configurations": [], + "contract": null, + "baseline_evidence": [], + "known_feasible_evidence": [], + "formal_admission": false, + "engineering_pilot_cases_must_be_excluded": true + }, + { + "task_id": "fvf_ota_02", + "parent_lineage": "glayout_fvf_ota", + "topology_family": "fvf_feedback", + "editing_face": "terminal_connectivity_and_port_routing", + "status": "DEVELOPMENT_CANDIDATE_REQUIRES_ACTUAL_CASE_HARVEST", + "origin": null, + "origin_requirement": "natural_or_disclosed_controlled_injection", + "E1_stratum": "reuse", + "domain_shape": { + "anchor": 1, + "development": 8, + "hidden": 16 + }, + "actual_configurations": [], + "contract": null, + "baseline_evidence": [], + "known_feasible_evidence": [], + "formal_admission": false, + "engineering_pilot_cases_must_be_excluded": true + }, + { + "task_id": "fvf_ota_03", + "parent_lineage": "glayout_fvf_ota", + "topology_family": "fvf_feedback", + "editing_face": "post_RC_quality_and_regression", + "status": "DEVELOPMENT_CANDIDATE_REQUIRES_ACTUAL_CASE_HARVEST", + "origin": null, + "origin_requirement": "observed_natural_failure_or_shortfall_preferred", + "E1_stratum": "composition", + "domain_shape": { + "anchor": 1, + "development": 8, + "hidden": 16 + }, + "actual_configurations": [], + "contract": null, + "baseline_evidence": [], + "known_feasible_evidence": [], + "formal_admission": false, + "engineering_pilot_cases_must_be_excluded": true + }, + { + "task_id": "five_t_01", + "parent_lineage": "research_five_t", + "topology_family": "five_t_ota", + "editing_face": "geometry_at_legal_boundaries", + "status": "DEVELOPMENT_CANDIDATE_REQUIRES_ACTUAL_CASE_HARVEST", + "origin": null, + "origin_requirement": "observed_natural_failure_or_shortfall_preferred", + "E1_stratum": "reuse", + "domain_shape": { + "anchor": 1, + "development": 8, + "hidden": 16 + }, + "actual_configurations": [], + "contract": null, + "baseline_evidence": [], + "known_feasible_evidence": [], + "formal_admission": false, + "engineering_pilot_cases_must_be_excluded": true + }, + { + "task_id": "five_t_02", + "parent_lineage": "research_five_t", + "topology_family": "five_t_ota", + "editing_face": "terminal_connectivity_and_port_routing", + "status": "DEVELOPMENT_CANDIDATE_REQUIRES_ACTUAL_CASE_HARVEST", + "origin": null, + "origin_requirement": "natural_or_disclosed_controlled_injection", + "E1_stratum": "composition", + "domain_shape": { + "anchor": 1, + "development": 8, + "hidden": 16 + }, + "actual_configurations": [], + "contract": null, + "baseline_evidence": [], + "known_feasible_evidence": [], + "formal_admission": false, + "engineering_pilot_cases_must_be_excluded": true + }, + { + "task_id": "five_t_03", + "parent_lineage": "research_five_t", + "topology_family": "five_t_ota", + "editing_face": "post_RC_quality_and_regression", + "status": "DEVELOPMENT_CANDIDATE_REQUIRES_ACTUAL_CASE_HARVEST", + "origin": null, + "origin_requirement": "observed_natural_failure_or_shortfall_preferred", + "E1_stratum": "reuse", + "domain_shape": { + "anchor": 1, + "development": 8, + "hidden": 16 + }, + "actual_configurations": [], + "contract": null, + "baseline_evidence": [], + "known_feasible_evidence": [], + "formal_admission": false, + "engineering_pilot_cases_must_be_excluded": true + }, + { + "task_id": "compact_miller_01", + "parent_lineage": "research_compact_miller", + "topology_family": "miller_ota", + "editing_face": "geometry_at_legal_boundaries", + "status": "DEVELOPMENT_CANDIDATE_REQUIRES_ACTUAL_CASE_HARVEST", + "origin": null, + "origin_requirement": "observed_natural_failure_or_shortfall_preferred", + "E1_stratum": "composition", + "domain_shape": { + "anchor": 1, + "development": 8, + "hidden": 16 + }, + "actual_configurations": [], + "contract": null, + "baseline_evidence": [], + "known_feasible_evidence": [], + "formal_admission": false, + "engineering_pilot_cases_must_be_excluded": true + }, + { + "task_id": "compact_miller_02", + "parent_lineage": "research_compact_miller", + "topology_family": "miller_ota", + "editing_face": "terminal_connectivity_and_port_routing", + "status": "DEVELOPMENT_CANDIDATE_REQUIRES_ACTUAL_CASE_HARVEST", + "origin": null, + "origin_requirement": "natural_or_disclosed_controlled_injection", + "E1_stratum": "reuse", + "domain_shape": { + "anchor": 1, + "development": 8, + "hidden": 16 + }, + "actual_configurations": [], + "contract": null, + "baseline_evidence": [], + "known_feasible_evidence": [], + "formal_admission": false, + "engineering_pilot_cases_must_be_excluded": true + }, + { + "task_id": "compact_miller_03", + "parent_lineage": "research_compact_miller", + "topology_family": "miller_ota", + "editing_face": "post_RC_quality_and_regression", + "status": "DEVELOPMENT_CANDIDATE_REQUIRES_ACTUAL_CASE_HARVEST", + "origin": null, + "origin_requirement": "observed_natural_failure_or_shortfall_preferred", + "E1_stratum": "composition", + "domain_shape": { + "anchor": 1, + "development": 8, + "hidden": 16 + }, + "actual_configurations": [], + "contract": null, + "baseline_evidence": [], + "known_feasible_evidence": [], + "formal_admission": false, + "engineering_pilot_cases_must_be_excluded": true + } + ], + "E2_candidate_source_programs": [ + "glayout_miller", + "glayout_fvf_ota", + "research_five_t", + "research_compact_miller" + ], + "split_proposal": { + "train": [ + "textbook_universal_compiler_cropped" + ], + "validation": [], + "test": [ + "glayout_mirror", + "glayout_pair", + "glayout_fvf", + "glayout_tg", + "glayout_miller", + "glayout_fvf_ota", + "research_five_t", + "research_compact_miller" + ], + "topology_holdouts": [ + "miller_ota", + "fvf_feedback" + ] + }, + "live_admission_gaps": [ + "independent_validation_source", + "source_similarity_and_cross_target_ancestry_clustering", + "observed_case_harvest_for_at_least_half_natural_tasks", + "per_configuration_independent_N_z_and_feasible_specs", + "25_new_configurations_per_task_not_prior_engineering_points", + "E1_same_task_G0_G1_G2_budget_pilot", + "1000_train_domain_candidate_yield_pilot_before_formal_counts" + ], + "hard_constraints": [ + "No formal success/coverage inferred from candidate slots", + "No width/finger/copy variant counted as new source lineage", + "Frozen circuit-specific helper closures stay within split", + "Training compiler pack excludes evaluation target source and Miller/FVF descriptors" + ] +} diff --git a/benchmarks/code_behind_layout/configs/development/e1_freeze_manifest_draft.json b/benchmarks/code_behind_layout/configs/development/e1_freeze_manifest_draft.json new file mode 100644 index 00000000..0e6bcd4f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/e1_freeze_manifest_draft.json @@ -0,0 +1,18 @@ +{ + "status": "DRAFT_E1_RUNNER", + "formal_dispatch": false, + "phase": "development_E1_matched_runner", + "packet_root": "runtime/task_preparation/e1_matched_20261019T032634463771Z", + "task_catalog": "runtime/task_preparation/e1_matched_20261019T032634463771Z/public/catalog.json", + "task_ids": [], + "methods": ["G0", "G1", "G2"], + "trials": 5, + "model_config": "configs/models/gpt_bounded.draft.json", + "visible_history_policy": "current_source_and_feedback_v1", + "budget": {"wall_seconds": 1200, "decisions": 10, "physical_evaluations": 3, "maximum_context_tokens": 8192, "maximum_output_tokens": 1024}, + "runtime": {"EDA": "runtime/GLdev", "magic": "runtime/magic-8.3.685", "candidate_CPUs": 2, "simultaneous_point_workers_per_episode": 1}, + "trusted_bench_bindings": "Built independently per task by scripts/e1_matched_runner.py; no target assembly enters the trusted evaluator.", + "post_freeze": {"visible": "Fill current-source anchor plus eight development points without policy feedback; separately charge post_freeze_diagnostic.", "hidden": "Evaluate sixteen points once after source sealing; all raw hidden results stay on trusted backend.", "incomplete": "Stop affected episode on unknown/infrastructure, retain observed denominators and label no missing outcomes."}, + "grouping": {"target_logics": 8, "primary_groups": 8, "merged_sensitivity_groups": 7, "strata": {"reuse": 12, "composition": 12}, "shared_domains": "Three sized tasks per target rotate roles of the same25 points, explicitly linked in private/shared_domain_relationships.json. Fresh isolated trials receive only their own fixed nine visible points."}, + "freeze_blockers": ["Final trustedbench bindings and complete run-ready mechanical smoke", "Root review and explicit E1-only freeze; no formal dispatch has occurred"] +} diff --git a/benchmarks/code_behind_layout/configs/development/e1_permission_amendment_20261019.json b/benchmarks/code_behind_layout/configs/development/e1_permission_amendment_20261019.json new file mode 100644 index 00000000..e30f0a02 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/e1_permission_amendment_20261019.json @@ -0,0 +1,15 @@ +{ + "kind": "working_copy_directory_permission_only", + "prior_manifest": "runtime/protocol_freezes/E1_20261019T0410Z/manifest.json", + "prior_freeze_id": "E1_20261019T0410Z", + "scope": "Exactly one destination source.chmod(0o755) after copytree; no policy, information, budget or electrical change", + "original_planned_trials": 360, + "already_dispatched_trials": 3, + "remaining_undispatched_trials": 357, + "automatic_or_engineering_model_retries": 0, + "retained_prior_trials": [ + {"task_id": "draft_E1_compact_miller_s03", "method": "G2", "trial_id": "5", "episode_directory": "runs/formal/E1/20261019T043205046362Z_080d610c", "post_freeze": "INCOMPLETE_UNKNOWN_CAPSULE_PERMISSION_FAILURE"}, + {"task_id": "draft_E1_compact_miller_s03", "method": "G1", "trial_id": "5", "episode_directory": "runs/formal/E1/20261019T043211851907Z_712ecd32", "post_freeze": "COMPLETE"}, + {"task_id": "draft_E1_compact_miller_s03", "method": "G0", "trial_id": "5", "episode_directory": "runs/formal/E1/20261019T043218444555Z_3f96cf4e", "post_freeze": "COMPLETE"} + ] +} diff --git a/benchmarks/code_behind_layout/configs/development/e1_scope_candidate_error_classification.patch b/benchmarks/code_behind_layout/configs/development/e1_scope_candidate_error_classification.patch new file mode 100644 index 00000000..49b296a7 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/e1_scope_candidate_error_classification.patch @@ -0,0 +1,59 @@ +--- a/scripts/e1_scope_runner.py ++++ b/scripts/e1_scope_runner.py +@@ -21,6 +21,16 @@ + from src.model_adapter import GptDecisionAdapter, check_utc_budget + + SSH = original.SSH[:-1]+['-o', 'ControlPath=/tmp/cbl-ssh-control']+original.SSH[-1:] ++ ++ ++class CandidateActionError(ValueError): ++ pass ++ ++ ++def bad_patch_error(error): ++ return (isinstance(error, subprocess.CalledProcessError) and ++ error.cmd == ['git', 'apply', '--check', '--whitespace=nowarn', '-'] and ++ isinstance(error.stderr, str) and re.fullmatch(r'error: corrupt patch at line [0-9]+\s*', error.stderr) is not None) + + + def now():return datetime.now(timezone.utc) +@@ -88,6 +98,13 @@ + + + class Backend(original.Backend): ++ def action(self, action): ++ try:return super().action(action) ++ except subprocess.CalledProcessError as error: ++ if action.get('action') == 'propose_patch' and bad_patch_error(error): ++ raise CandidateActionError('candidate_bad_patch: '+error.stderr.strip()) from error ++ raise ++ + def summary(self): + return {**super().summary(), 'cohort_id': self.state['cohort_id'], 'interface_version': COHORT, + 'freeze_id': self.state['freeze_id'], 'interface_pilot': self.state['interface_pilot']} +@@ -124,7 +141,7 @@ + if process.returncode:raise original.BackendInfrastructureError(process.stderr[-1500:]) + result = json.loads(process.stdout) + if result.get('error'): +- kind = {'TimeoutError': TimeoutError, 'ValueError': ValueError}.get(result['error_type'], original.BackendInfrastructureError) ++ kind = {'TimeoutError': TimeoutError, 'ValueError': ValueError, 'CandidateActionError': CandidateActionError}.get(result['error_type'], original.BackendInfrastructureError) + raise kind(result['error']) + return result['result'] + +@@ -152,6 +169,7 @@ + current = transport({'op': 'current', 'episode_directory': directory}) + action = adapter.step(session, observation, current_sources=current['current_sources']);check_utc_budget(packet) + try:observation = transport({'op': 'action', 'episode_directory': directory, 'action': action}) ++ except CandidateActionError:raise + except ValueError as error:observation = {'error': type(error).__name__+': '+str(error)} + save(out/'latest_observation.json', observation) + if action['action'] == 'finish':status = 'SEARCH_FINISHED';break +@@ -163,6 +181,8 @@ + if any(isinstance(value, dict) and value.get('execution_integrity') == 'incomplete' for value in observation.values()): + status = 'INCOMPLETE_UNKNOWN';break + except TimeoutError:status = 'BUDGET_EXHAUSTED' ++ except CandidateActionError as error: ++ status = 'MODEL_FAILED';save(out/'policy_error.json', {'failure_class': 'candidate_invalid_action', 'error': str(error)}) + except original.BackendInfrastructureError as error: + status = 'INCOMPLETE_UNKNOWN';save(out/'backend_error.json', {'error': str(error)}) + except Exception as error: diff --git a/benchmarks/code_behind_layout/configs/development/e2_analysis.json b/benchmarks/code_behind_layout/configs/development/e2_analysis.json new file mode 100644 index 00000000..267e5cac --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/e2_analysis.json @@ -0,0 +1,13 @@ +{ + "status": "development_analysis_rule_v1_not_formal_protocol", + "objective": "worst_corner_ugb_Hz", + "unit": "Hz", + "direction": "max", + "numerical_tie": {"absolute_Hz": 1.0, "relative": 0.00001}, + "calibration_evidence": "phase0_20261018T231220337791Z_ota_precision_calibration/validation.json", + "calibration_basis": "Tight KLU versus Sparse UGB differed by 0.057609Hz at 16.1007MHz; retain the predeclared 1e-5 waveform agreement scale and a 1Hz floor. This is a development transfer tolerance, not a new per-source noise estimate.", + "near_frontier": {"fraction": 0.2, "selection": "smallest_L0_footprint_area_um2", "ties": "candidate_id_ascending"}, + "geometry_analysis": "descriptive association only; area and wirelength are not circuit-objective predictions", + "post_PEX_proxy": "1/(2*pi*sum_R_ohm*sum_C_F), an unfitted one-pole frequency heuristic; not a calibrated circuit model or cheap fidelity", + "nominal_proxy": "actual nominal-corner UGB used as an estimate of worst-corner UGB; requires nominal PEX/SPICE acquisition" +} diff --git a/benchmarks/code_behind_layout/configs/development/e2_formal_draft.json b/benchmarks/code_behind_layout/configs/development/e2_formal_draft.json new file mode 100644 index 00000000..6a62967b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/e2_formal_draft.json @@ -0,0 +1,12237 @@ +{ + "status": "DRAFT_NOT_FROZEN_NO_FORMAL_MEASUREMENTS", + "created_at_utc": "2026-10-19T02:17:47.272223+00:00", + "source_pack": "/srv/code-behind-layout/runtime/e2_draft_preparation/20261019T021747204896Z", + "target": { + "source_programs": 4, + "sizings_per_source": 3, + "geometry_distinct_candidates_per_sizing": 64, + "target_measured_candidates": 768 + }, + "source_independence": "Four distinct high-level OTA source programs; vendor FVF and Miller share circuit helpers and the vendor-connected dependency cluster. These are not four independent ancestry clusters. Report high-level-program results plus source-closure sensitivity.", + "development_labels_reused_as_formal": false, + "formal_execution_allowed": false, + "generation_or_dedup_is_not_S0_S1_S2_measurement": true, + "sizing_rule": "One declared transistor category varied symmetrically about each qualified default; every sizing has separate intended gold. No sizing is selected by a new outcome. Nondefault sizing qualification remains pending.", + "layout_stream_rule": "First64=4x4x2x2, then remaining4^4 combinations in fixed lexicographic order. Geometry only selects first64 mask-distinct successful GDS. All generation failures and duplicates consume cost and stay in denominators. Never replace a DRC/LVS/PEX/electrical failure. Stop after256 generation attempts; insufficient64distinct is an admission failure, not permission to search further.", + "development_overlap_control": "The second layout control has four new interior levels, disjoint from the old development endpoints; exact Boolean-mask dedup must still exclude any actual old geometry matches. Old labels and raw trials are never copied into this pool. Baseline control is separate known development context and is not one of the64 new combinations.", + "geometry_equality": { + "implementation": "src/e2_mask_geometry.py", + "operation": "Flatten including paths/repetitions; convert physical coordinates to um; use original GDS precision; ignore text and PDK pin/label annotation layers; union each physical layer/datatype; remove common translation; exact XOR-empty equality on every layer. Area/bbox can reject but cannot certify equality.", + "PDK_exclusion_binding": "At main freeze enumerate the exact SKY130 glayers ending _pin/_label plus(64,44); save this explicit list. No physical conductor/device layer excluded.", + "prohibited_distinctness": [ + "translation", + "cell names", + "text labels", + "polygon partitioning or orientation", + "renaming devices" + ], + "comparison_scope": "each source/sizing plus known development masks; cross-source or different-N equivalence is separately reported, never a new source lineage" + }, + "objective": { + "metric": "ugb_Hz", + "direction": "maximize", + "unit": "Hz", + "aggregation": "minimum over tt/ss/ff after all constraints pass" + }, + "no_feasible_oracle": { + "regret": null, + "report": "observed feasible fraction, budgeted unresolved/censored fraction and complete electrical infeasible fraction separately; no finite made-up penalty or fake regret" + }, + "fidelities": [ + { + "id": "geometry", + "observes": [ + "GDS footprint area_um2", + "rectilinear conductor proxy_um", + "exact mask distinctness" + ], + "requires": "actual source-to-GDS generation", + "target_prediction": null, + "interpretation": "Descriptive geometry, not calibrated UGB prediction" + }, + { + "id": "physical_and_PEX", + "observes": [ + "full DRC", + "independent unique LVS", + "complete actual positive fullRC", + "R_sum_ohm", + "C_sum_F" + ], + "requires": "actual DRC/LVS/PEX", + "target_prediction": null, + "interpretation": "R*C features have actual PEX acquisition cost; not a cheap pre-PEX L1" + }, + { + "id": "nominal_OP_AC", + "observes": [ + "tt OP", + "tt AC at source-specific declared grid", + "tt UGB_Hz" + ], + "requires": "admitted actual PEX", + "target_prediction": "Only after train/validation calibration to worst-cornerUGB; otherwise descriptive nominal metric" + }, + { + "id": "complete_three_corner", + "observes": [ + "tt/ss/ff OP", + "AC", + "transient", + "declared complete DC" + ], + "requires": "strict completion/axis/finite/log gates", + "interpretation": "Only this establishes complete constrained objective/S2" + } + ], + "cost_contract": { + "per_stage": [ + "generation", + "mask_union_and_duplicate_comparison", + "DRC", + "LVS", + "PEX", + "each corner/analysis" + ], + "required_actual_fields": [ + "monotonic_wall_seconds", + "self_user_cpu_seconds", + "self_system_cpu_seconds", + "children_user_cpu_seconds", + "children_system_cpu_seconds", + "returncode_or_timeout", + "attempt_id", + "input_artifact_reuse", + "queue_wait_seconds" + ], + "allocation": "Charge source-to-GDS and PEX once on actual first acquisition, then reference dependencies. A reused artifact saves repeated work but retains its first acquisition cost. Global CPU samples are shared scheduling context, never summed across pools.", + "development_cost_limits": "Existing pilots record stage wall times and total process/child CPU; they do not retrospectively establish missing per-stageCPU. New cost instrumentation and calibrated formal budgets remain pending.", + "failure_accounting": "Include syntax/generation failures, duplicates, physical failures, PEX failures, incomplete numeric traces and timeout CPU/wall/queue costs; unresolved is not intrinsic infeasible." + }, + "promotion_methods": { + "status": "DRAFT_IMPLEMENTATION_AND_BUDGET_CALIBRATION_PENDING", + "required": [ + "all candidate full evaluation oracle", + "fixed promotion", + "adaptive promotion", + "matched verification resources" + ], + "calibration": "Fit same-target predictions and selection thresholds on separately assigned train/validation source groups only. Never fit or retune on these E2 evaluation pool labels." + }, + "families": { + "five_t": { + "source_snapshot": "/srv/code-behind-layout/runtime/e2_draft_preparation/20261019T021747204896Z/five_t/generator_snapshot.py", + "dependency_revision": "d092211d7996c99159402451bc7141931d6a93c3", + "source_origin": "/srv/code-behind-layout/src/generators/five_t.py", + "contract": { + "supply_V": 1.8, + "load_F": 2e-12, + "common_mode_V": 1.1, + "reference_current_A": 2e-05, + "temperature_C": 27, + "corners": [ + "tt", + "ss", + "ff" + ], + "bench_source_unchanged": "testbench_snapshot.py", + "numerics": { + "reltol": 1e-06, + "abstol": 1e-14, + "vntol": 1e-08, + "chgtol": 1e-16 + }, + "analysis_coverage": { + "OP_rows": 1, + "AC_rows": 401, + "AC_Hz": [ + 10, + 1000000000.0 + ], + "transient_s": [ + 0, + 4e-06 + ], + "DC_points": 9, + "DC_V": [ + 0.9, + 1.3 + ] + }, + "existing_development_feasibility": { + "tail_V_open_interval": [ + 0.15, + 0.8 + ], + "mirror_V_open_interval": [ + 0.4, + 1.6 + ], + "nominal_tracking_abs_V_lt": 0.01, + "supply_current_A_open_interval": [ + 2e-05, + 8e-05 + ], + "phase_margin_deg_closed_interval": [ + 60, + 180 + ], + "positive_low_frequency_gain": true, + "gain_10Hz_dB_min": 30, + "ugb_Hz_min": 1000000.0, + "settled_tracking_error_V_lt": 0.01 + }, + "DC_sweep_interpretation": "The complete broad tracking sweep is retained; no extra output-swing or maximum-DC-error constraint is added." + }, + "control_levels": { + "channel_gap_um": [ + 22, + 24, + 28, + 30 + ], + "drop_width_um": [ + 0.68, + 0.76, + 0.84, + 0.92 + ], + "trunk_width_um": [ + 0.8, + 1.4, + 1, + 1.2 + ], + "bus_pitch_um": [ + 3, + 4, + 3.25, + 3.75 + ] + }, + "sizings": [ + { + "id": "s0", + "sizing": { + "input_width": 2.5, + "input_fingers": 2, + "input_length": 1.0, + "load_width": 3.0, + "load_fingers": 4, + "load_length": 1.0, + "tail_width": 3.0, + "tail_fingers": 4, + "tail_length": 1.0 + }, + "generator_arguments": { + "config": { + "input_width": 2.5, + "input_fingers": 2, + "input_length": 1.0, + "load_width": 3.0, + "load_fingers": 4, + "load_length": 1.0, + "tail_width": 3.0, + "tail_fingers": 4, + "tail_length": 1.0 + } + }, + "intended_gold": "/srv/code-behind-layout/runtime/e2_draft_preparation/20261019T021747204896Z/five_t/sizing_0/gold.spice", + "gold_bound_before_GDS": true, + "physical_qualification": "pending" + }, + { + "id": "s1", + "sizing": { + "input_width": 3, + "input_fingers": 2, + "input_length": 1.0, + "load_width": 3.0, + "load_fingers": 4, + "load_length": 1.0, + "tail_width": 3.0, + "tail_fingers": 4, + "tail_length": 1.0 + }, + "generator_arguments": { + "config": { + "input_width": 3, + "input_fingers": 2, + "input_length": 1.0, + "load_width": 3.0, + "load_fingers": 4, + "load_length": 1.0, + "tail_width": 3.0, + "tail_fingers": 4, + "tail_length": 1.0 + } + }, + "intended_gold": "/srv/code-behind-layout/runtime/e2_draft_preparation/20261019T021747204896Z/five_t/sizing_1/gold.spice", + "gold_bound_before_GDS": true, + "physical_qualification": "qualified default at declared development application only; no formal trial" + }, + { + "id": "s2", + "sizing": { + "input_width": 3.5, + "input_fingers": 2, + "input_length": 1.0, + "load_width": 3.0, + "load_fingers": 4, + "load_length": 1.0, + "tail_width": 3.0, + "tail_fingers": 4, + "tail_length": 1.0 + }, + "generator_arguments": { + "config": { + "input_width": 3.5, + "input_fingers": 2, + "input_length": 1.0, + "load_width": 3.0, + "load_fingers": 4, + "load_length": 1.0, + "tail_width": 3.0, + "tail_fingers": 4, + "tail_length": 1.0 + } + }, + "intended_gold": "/srv/code-behind-layout/runtime/e2_draft_preparation/20261019T021747204896Z/five_t/sizing_2/gold.spice", + "gold_bound_before_GDS": true, + "physical_qualification": "pending" + } + ], + "candidate_stream": [ + { + "stream_index": 0, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_000.patch" + }, + { + "stream_index": 1, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_001.patch" + }, + { + "stream_index": 2, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_002.patch" + }, + { + "stream_index": 3, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_003.patch" + }, + { + "stream_index": 4, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_004.patch" + }, + { + "stream_index": 5, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_005.patch" + }, + { + "stream_index": 6, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_006.patch" + }, + { + "stream_index": 7, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_007.patch" + }, + { + "stream_index": 8, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_008.patch" + }, + { + "stream_index": 9, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_009.patch" + }, + { + "stream_index": 10, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_010.patch" + }, + { + "stream_index": 11, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_011.patch" + }, + { + "stream_index": 12, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_012.patch" + }, + { + "stream_index": 13, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_013.patch" + }, + { + "stream_index": 14, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_014.patch" + }, + { + "stream_index": 15, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_015.patch" + }, + { + "stream_index": 16, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_016.patch" + }, + { + "stream_index": 17, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_017.patch" + }, + { + "stream_index": 18, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_018.patch" + }, + { + "stream_index": 19, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_019.patch" + }, + { + "stream_index": 20, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_020.patch" + }, + { + "stream_index": 21, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_021.patch" + }, + { + "stream_index": 22, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_022.patch" + }, + { + "stream_index": 23, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_023.patch" + }, + { + "stream_index": 24, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_024.patch" + }, + { + "stream_index": 25, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_025.patch" + }, + { + "stream_index": 26, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_026.patch" + }, + { + "stream_index": 27, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_027.patch" + }, + { + "stream_index": 28, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_028.patch" + }, + { + "stream_index": 29, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_029.patch" + }, + { + "stream_index": 30, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_030.patch" + }, + { + "stream_index": 31, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_031.patch" + }, + { + "stream_index": 32, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_032.patch" + }, + { + "stream_index": 33, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_033.patch" + }, + { + "stream_index": 34, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_034.patch" + }, + { + "stream_index": 35, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_035.patch" + }, + { + "stream_index": 36, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_036.patch" + }, + { + "stream_index": 37, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_037.patch" + }, + { + "stream_index": 38, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_038.patch" + }, + { + "stream_index": 39, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_039.patch" + }, + { + "stream_index": 40, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_040.patch" + }, + { + "stream_index": 41, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_041.patch" + }, + { + "stream_index": 42, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_042.patch" + }, + { + "stream_index": 43, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_043.patch" + }, + { + "stream_index": 44, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_044.patch" + }, + { + "stream_index": 45, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_045.patch" + }, + { + "stream_index": 46, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_046.patch" + }, + { + "stream_index": 47, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_047.patch" + }, + { + "stream_index": 48, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_048.patch" + }, + { + "stream_index": 49, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_049.patch" + }, + { + "stream_index": 50, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_050.patch" + }, + { + "stream_index": 51, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_051.patch" + }, + { + "stream_index": 52, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_052.patch" + }, + { + "stream_index": 53, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_053.patch" + }, + { + "stream_index": 54, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_054.patch" + }, + { + "stream_index": 55, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_055.patch" + }, + { + "stream_index": 56, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_056.patch" + }, + { + "stream_index": 57, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_057.patch" + }, + { + "stream_index": 58, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_058.patch" + }, + { + "stream_index": 59, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_059.patch" + }, + { + "stream_index": 60, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_060.patch" + }, + { + "stream_index": 61, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_061.patch" + }, + { + "stream_index": 62, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial64": true, + "patch": "layout_patches/layout_062.patch" + }, + { + "stream_index": 63, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_063.patch" + }, + { + "stream_index": 64, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_064.patch" + }, + { + "stream_index": 65, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_065.patch" + }, + { + "stream_index": 66, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_066.patch" + }, + { + "stream_index": 67, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_067.patch" + }, + { + "stream_index": 68, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_068.patch" + }, + { + "stream_index": 69, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_069.patch" + }, + { + "stream_index": 70, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_070.patch" + }, + { + "stream_index": 71, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_071.patch" + }, + { + "stream_index": 72, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_072.patch" + }, + { + "stream_index": 73, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_073.patch" + }, + { + "stream_index": 74, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_074.patch" + }, + { + "stream_index": 75, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_075.patch" + }, + { + "stream_index": 76, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_076.patch" + }, + { + "stream_index": 77, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_077.patch" + }, + { + "stream_index": 78, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_078.patch" + }, + { + "stream_index": 79, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_079.patch" + }, + { + "stream_index": 80, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_080.patch" + }, + { + "stream_index": 81, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_081.patch" + }, + { + "stream_index": 82, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_082.patch" + }, + { + "stream_index": 83, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_083.patch" + }, + { + "stream_index": 84, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_084.patch" + }, + { + "stream_index": 85, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_085.patch" + }, + { + "stream_index": 86, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_086.patch" + }, + { + "stream_index": 87, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_087.patch" + }, + { + "stream_index": 88, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_088.patch" + }, + { + "stream_index": 89, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_089.patch" + }, + { + "stream_index": 90, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_090.patch" + }, + { + "stream_index": 91, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_091.patch" + }, + { + "stream_index": 92, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_092.patch" + }, + { + "stream_index": 93, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_093.patch" + }, + { + "stream_index": 94, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_094.patch" + }, + { + "stream_index": 95, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_095.patch" + }, + { + "stream_index": 96, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_096.patch" + }, + { + "stream_index": 97, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_097.patch" + }, + { + "stream_index": 98, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_098.patch" + }, + { + "stream_index": 99, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_099.patch" + }, + { + "stream_index": 100, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_100.patch" + }, + { + "stream_index": 101, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_101.patch" + }, + { + "stream_index": 102, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_102.patch" + }, + { + "stream_index": 103, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_103.patch" + }, + { + "stream_index": 104, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_104.patch" + }, + { + "stream_index": 105, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_105.patch" + }, + { + "stream_index": 106, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_106.patch" + }, + { + "stream_index": 107, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_107.patch" + }, + { + "stream_index": 108, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_108.patch" + }, + { + "stream_index": 109, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_109.patch" + }, + { + "stream_index": 110, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_110.patch" + }, + { + "stream_index": 111, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_111.patch" + }, + { + "stream_index": 112, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_112.patch" + }, + { + "stream_index": 113, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_113.patch" + }, + { + "stream_index": 114, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_114.patch" + }, + { + "stream_index": 115, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_115.patch" + }, + { + "stream_index": 116, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_116.patch" + }, + { + "stream_index": 117, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_117.patch" + }, + { + "stream_index": 118, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_118.patch" + }, + { + "stream_index": 119, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_119.patch" + }, + { + "stream_index": 120, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_120.patch" + }, + { + "stream_index": 121, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_121.patch" + }, + { + "stream_index": 122, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_122.patch" + }, + { + "stream_index": 123, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_123.patch" + }, + { + "stream_index": 124, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_124.patch" + }, + { + "stream_index": 125, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_125.patch" + }, + { + "stream_index": 126, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_126.patch" + }, + { + "stream_index": 127, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_127.patch" + }, + { + "stream_index": 128, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_128.patch" + }, + { + "stream_index": 129, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_129.patch" + }, + { + "stream_index": 130, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_130.patch" + }, + { + "stream_index": 131, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_131.patch" + }, + { + "stream_index": 132, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_132.patch" + }, + { + "stream_index": 133, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_133.patch" + }, + { + "stream_index": 134, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_134.patch" + }, + { + "stream_index": 135, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_135.patch" + }, + { + "stream_index": 136, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_136.patch" + }, + { + "stream_index": 137, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_137.patch" + }, + { + "stream_index": 138, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_138.patch" + }, + { + "stream_index": 139, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_139.patch" + }, + { + "stream_index": 140, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_140.patch" + }, + { + "stream_index": 141, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_141.patch" + }, + { + "stream_index": 142, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_142.patch" + }, + { + "stream_index": 143, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_143.patch" + }, + { + "stream_index": 144, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_144.patch" + }, + { + "stream_index": 145, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_145.patch" + }, + { + "stream_index": 146, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_146.patch" + }, + { + "stream_index": 147, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_147.patch" + }, + { + "stream_index": 148, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_148.patch" + }, + { + "stream_index": 149, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_149.patch" + }, + { + "stream_index": 150, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_150.patch" + }, + { + "stream_index": 151, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_151.patch" + }, + { + "stream_index": 152, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_152.patch" + }, + { + "stream_index": 153, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_153.patch" + }, + { + "stream_index": 154, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_154.patch" + }, + { + "stream_index": 155, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_155.patch" + }, + { + "stream_index": 156, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_156.patch" + }, + { + "stream_index": 157, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_157.patch" + }, + { + "stream_index": 158, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_158.patch" + }, + { + "stream_index": 159, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_159.patch" + }, + { + "stream_index": 160, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_160.patch" + }, + { + "stream_index": 161, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_161.patch" + }, + { + "stream_index": 162, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_162.patch" + }, + { + "stream_index": 163, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_163.patch" + }, + { + "stream_index": 164, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_164.patch" + }, + { + "stream_index": 165, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_165.patch" + }, + { + "stream_index": 166, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_166.patch" + }, + { + "stream_index": 167, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_167.patch" + }, + { + "stream_index": 168, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_168.patch" + }, + { + "stream_index": 169, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_169.patch" + }, + { + "stream_index": 170, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_170.patch" + }, + { + "stream_index": 171, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_171.patch" + }, + { + "stream_index": 172, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_172.patch" + }, + { + "stream_index": 173, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_173.patch" + }, + { + "stream_index": 174, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_174.patch" + }, + { + "stream_index": 175, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_175.patch" + }, + { + "stream_index": 176, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_176.patch" + }, + { + "stream_index": 177, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_177.patch" + }, + { + "stream_index": 178, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_178.patch" + }, + { + "stream_index": 179, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_179.patch" + }, + { + "stream_index": 180, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_180.patch" + }, + { + "stream_index": 181, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_181.patch" + }, + { + "stream_index": 182, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_182.patch" + }, + { + "stream_index": 183, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_183.patch" + }, + { + "stream_index": 184, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_184.patch" + }, + { + "stream_index": 185, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_185.patch" + }, + { + "stream_index": 186, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_186.patch" + }, + { + "stream_index": 187, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_187.patch" + }, + { + "stream_index": 188, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_188.patch" + }, + { + "stream_index": 189, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_189.patch" + }, + { + "stream_index": 190, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_190.patch" + }, + { + "stream_index": 191, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_191.patch" + }, + { + "stream_index": 192, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_192.patch" + }, + { + "stream_index": 193, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_193.patch" + }, + { + "stream_index": 194, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_194.patch" + }, + { + "stream_index": 195, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_195.patch" + }, + { + "stream_index": 196, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_196.patch" + }, + { + "stream_index": 197, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_197.patch" + }, + { + "stream_index": 198, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_198.patch" + }, + { + "stream_index": 199, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_199.patch" + }, + { + "stream_index": 200, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_200.patch" + }, + { + "stream_index": 201, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_201.patch" + }, + { + "stream_index": 202, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_202.patch" + }, + { + "stream_index": 203, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_203.patch" + }, + { + "stream_index": 204, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_204.patch" + }, + { + "stream_index": 205, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_205.patch" + }, + { + "stream_index": 206, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_206.patch" + }, + { + "stream_index": 207, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_207.patch" + }, + { + "stream_index": 208, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_208.patch" + }, + { + "stream_index": 209, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_209.patch" + }, + { + "stream_index": 210, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_210.patch" + }, + { + "stream_index": 211, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_211.patch" + }, + { + "stream_index": 212, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_212.patch" + }, + { + "stream_index": 213, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_213.patch" + }, + { + "stream_index": 214, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_214.patch" + }, + { + "stream_index": 215, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_215.patch" + }, + { + "stream_index": 216, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_216.patch" + }, + { + "stream_index": 217, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_217.patch" + }, + { + "stream_index": 218, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_218.patch" + }, + { + "stream_index": 219, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_219.patch" + }, + { + "stream_index": 220, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_220.patch" + }, + { + "stream_index": 221, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_221.patch" + }, + { + "stream_index": 222, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_222.patch" + }, + { + "stream_index": 223, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_223.patch" + }, + { + "stream_index": 224, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_224.patch" + }, + { + "stream_index": 225, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_225.patch" + }, + { + "stream_index": 226, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_226.patch" + }, + { + "stream_index": 227, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_227.patch" + }, + { + "stream_index": 228, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_228.patch" + }, + { + "stream_index": 229, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_229.patch" + }, + { + "stream_index": 230, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_230.patch" + }, + { + "stream_index": 231, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_231.patch" + }, + { + "stream_index": 232, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_232.patch" + }, + { + "stream_index": 233, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_233.patch" + }, + { + "stream_index": 234, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_234.patch" + }, + { + "stream_index": 235, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_235.patch" + }, + { + "stream_index": 236, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_236.patch" + }, + { + "stream_index": 237, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_237.patch" + }, + { + "stream_index": 238, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_238.patch" + }, + { + "stream_index": 239, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_239.patch" + }, + { + "stream_index": 240, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_240.patch" + }, + { + "stream_index": 241, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_241.patch" + }, + { + "stream_index": 242, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_242.patch" + }, + { + "stream_index": 243, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_243.patch" + }, + { + "stream_index": 244, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_244.patch" + }, + { + "stream_index": 245, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_245.patch" + }, + { + "stream_index": 246, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_246.patch" + }, + { + "stream_index": 247, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_247.patch" + }, + { + "stream_index": 248, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_248.patch" + }, + { + "stream_index": 249, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_249.patch" + }, + { + "stream_index": 250, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_250.patch" + }, + { + "stream_index": 251, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_251.patch" + }, + { + "stream_index": 252, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial64": false, + "patch": "layout_patches/layout_252.patch" + }, + { + "stream_index": 253, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_253.patch" + }, + { + "stream_index": 254, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial64": false, + "patch": "layout_patches/layout_254.patch" + }, + { + "stream_index": 255, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial64": false, + "patch": "layout_patches/layout_255.patch" + } + ], + "initial_designed_combinations": 64, + "maximum_geometry_attempts": 256, + "development_selection_disclosure": { + "observed_plan": "phase0_20261019T011122226634Z_e2_development_pilot", + "observed_terminal_attempts": 16, + "observed_status_counts": { + "COMPLETE_FEASIBLE": 14, + "INCOMPLETE_SIMULATION": 2 + }, + "observed_actual_stage_wall_seconds_sum": { + "generation": 290.54281815327704, + "geometry": 0.9520350708626211, + "DRC": 12.207254630047828, + "LVS": 17.236127626616508, + "PEX": 6.438218367751688, + "electrical": 1798.1531425025314 + }, + "effect_on_proposal": "Preserve source control sites and development endpoint ranges; add declared interior levels before formal labels. No exclusion of known failing endpoint(s), no reruns chosen by prior success. Three symmetric sizing points chosen now; no nondefault-size postRC outcome observed.", + "application_selection": "FVF15pF chosen after10pF SS58.59 failed60deg; positive-control PMmin67.11 known. Legacy15pF is a one-time load hypothesis after.5pF lowPM; outcome pending. These are explicit development-informed application choices, not a blind posthoc comparison.", + "timeout_selection": "Old5T/compact incomplete90/120s transients stay unresolved; longer formal budgets, if adopted, must be calibrated and frozen before any formal candidate labels. Old outcomes never relabeled." + } + }, + "compact_miller": { + "source_snapshot": "/srv/code-behind-layout/runtime/e2_draft_preparation/20261019T021747204896Z/compact_miller/generator_snapshot.py", + "dependency_revision": "d092211d7996c99159402451bc7141931d6a93c3", + "source_origin": "/work/runs/phase0/phase0_20261018T234425820562Z_custom_ota_miller_build/compact_miller.py", + "contract": { + "supply_V": 1.8, + "load_F": 2e-12, + "common_mode_V": 1.05, + "temperature_C": 27, + "corners": [ + "tt", + "ss", + "ff" + ], + "bench_source_unchanged": "testbench_snapshot.py", + "numerics": { + "reltol": 1e-06, + "abstol": 1e-14, + "vntol": 1e-08, + "chgtol": 1e-16 + }, + "analysis_coverage": { + "OP_rows": 1, + "AC_rows": 401, + "AC_Hz": [ + 10, + 1000000000.0 + ], + "transient_s": [ + 0, + 4e-06 + ], + "DC_points": 5, + "DC_V": [ + 0.95, + 1.15 + ] + }, + "existing_development_feasibility": { + "gain_10Hz_dB_min": 55, + "phase_margin_deg_closed_interval": [ + 60, + 180 + ], + "ugb_Hz_min": 1000000.0, + "nominal_tracking_abs_V_lt": 0.005, + "settled_tracking_error_V_lt": 0.005, + "tail_V_open_interval": [ + 0.15, + 0.8 + ], + "stage1_V_open_interval": [ + 0.3, + 1.2 + ], + "supply_current_A_open_interval": [ + 5e-05, + 0.00016 + ] + }, + "DC_sweep_interpretation": "The complete broad tracking sweep is retained; no extra output-swing or maximum-DC-error constraint is added.", + "n_reference_current_A": 2e-05, + "p_reference_current_A": 1e-05 + }, + "control_levels": { + "spine_width_um": [ + 0.6, + 0.7, + 0.8, + 0.9 + ], + "bus_width_um": [ + 0.88, + 0.96, + 1.04, + 1.12 + ], + "capacitor_center_x_um": [ + 130, + 146, + 134, + 142 + ], + "output_landing_clearance_um": [ + 4, + 8, + 5, + 7 + ] + }, + "sizings": [ + { + "id": "s0", + "sizing": { + "input_width": 2.5, + "input_fingers": 2, + "input_length": 1.0, + "load_width": 3.0, + "load_fingers": 4, + "load_length": 1.0, + "tail_width": 3.0, + "tail_fingers": 4, + "tail_length": 1.0, + "second_n_width": 3.0, + "second_n_fingers": 12, + "second_n_length": 0.5, + "second_p_width": 3.0, + "second_p_fingers": 16, + "second_p_length": 1.0, + "p_ref_width": 3.0, + "p_ref_fingers": 4, + "p_ref_length": 1.0, + "cap_size": 30.0 + }, + "generator_arguments": { + "config": { + "input_width": 2.5, + "input_fingers": 2, + "input_length": 1.0, + "load_width": 3.0, + "load_fingers": 4, + "load_length": 1.0, + "tail_width": 3.0, + "tail_fingers": 4, + "tail_length": 1.0, + "second_n_width": 3.0, + "second_n_fingers": 12, + "second_n_length": 0.5, + "second_p_width": 3.0, + "second_p_fingers": 16, + "second_p_length": 1.0, + "p_ref_width": 3.0, + "p_ref_fingers": 4, + "p_ref_length": 1.0, + "cap_size": 30.0 + } + }, + "intended_gold": "/srv/code-behind-layout/runtime/e2_draft_preparation/20261019T021747204896Z/compact_miller/sizing_0/gold.spice", + "gold_bound_before_GDS": true, + "physical_qualification": "pending" + }, + { + "id": "s1", + "sizing": { + "input_width": 3, + "input_fingers": 2, + "input_length": 1.0, + "load_width": 3.0, + "load_fingers": 4, + "load_length": 1.0, + "tail_width": 3.0, + "tail_fingers": 4, + "tail_length": 1.0, + "second_n_width": 3.0, + "second_n_fingers": 12, + "second_n_length": 0.5, + "second_p_width": 3.0, + "second_p_fingers": 16, + "second_p_length": 1.0, + "p_ref_width": 3.0, + "p_ref_fingers": 4, + "p_ref_length": 1.0, + "cap_size": 30.0 + }, + "generator_arguments": { + "config": { + "input_width": 3, + "input_fingers": 2, + "input_length": 1.0, + "load_width": 3.0, + "load_fingers": 4, + "load_length": 1.0, + "tail_width": 3.0, + "tail_fingers": 4, + "tail_length": 1.0, + "second_n_width": 3.0, + "second_n_fingers": 12, + "second_n_length": 0.5, + "second_p_width": 3.0, + "second_p_fingers": 16, + "second_p_length": 1.0, + "p_ref_width": 3.0, + "p_ref_fingers": 4, + "p_ref_length": 1.0, + "cap_size": 30.0 + } + }, + "intended_gold": "/srv/code-behind-layout/runtime/e2_draft_preparation/20261019T021747204896Z/compact_miller/sizing_1/gold.spice", + "gold_bound_before_GDS": true, + "physical_qualification": "qualified default at declared development application only; no formal trial" + }, + { + "id": "s2", + "sizing": { + "input_width": 3.5, + "input_fingers": 2, + "input_length": 1.0, + "load_width": 3.0, + "load_fingers": 4, + "load_length": 1.0, + "tail_width": 3.0, + "tail_fingers": 4, + "tail_length": 1.0, + "second_n_width": 3.0, + "second_n_fingers": 12, + "second_n_length": 0.5, + "second_p_width": 3.0, + "second_p_fingers": 16, + "second_p_length": 1.0, + "p_ref_width": 3.0, + "p_ref_fingers": 4, + "p_ref_length": 1.0, + "cap_size": 30.0 + }, + "generator_arguments": { + "config": { + "input_width": 3.5, + "input_fingers": 2, + "input_length": 1.0, + "load_width": 3.0, + "load_fingers": 4, + "load_length": 1.0, + "tail_width": 3.0, + "tail_fingers": 4, + "tail_length": 1.0, + "second_n_width": 3.0, + "second_n_fingers": 12, + "second_n_length": 0.5, + "second_p_width": 3.0, + "second_p_fingers": 16, + "second_p_length": 1.0, + "p_ref_width": 3.0, + "p_ref_fingers": 4, + "p_ref_length": 1.0, + "cap_size": 30.0 + } + }, + "intended_gold": "/srv/code-behind-layout/runtime/e2_draft_preparation/20261019T021747204896Z/compact_miller/sizing_2/gold.spice", + "gold_bound_before_GDS": true, + "physical_qualification": "pending" + } + ], + "candidate_stream": [ + { + "stream_index": 0, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_000.patch" + }, + { + "stream_index": 1, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_001.patch" + }, + { + "stream_index": 2, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_002.patch" + }, + { + "stream_index": 3, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_003.patch" + }, + { + "stream_index": 4, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_004.patch" + }, + { + "stream_index": 5, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_005.patch" + }, + { + "stream_index": 6, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_006.patch" + }, + { + "stream_index": 7, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_007.patch" + }, + { + "stream_index": 8, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_008.patch" + }, + { + "stream_index": 9, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_009.patch" + }, + { + "stream_index": 10, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_010.patch" + }, + { + "stream_index": 11, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_011.patch" + }, + { + "stream_index": 12, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_012.patch" + }, + { + "stream_index": 13, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_013.patch" + }, + { + "stream_index": 14, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_014.patch" + }, + { + "stream_index": 15, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_015.patch" + }, + { + "stream_index": 16, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_016.patch" + }, + { + "stream_index": 17, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_017.patch" + }, + { + "stream_index": 18, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_018.patch" + }, + { + "stream_index": 19, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_019.patch" + }, + { + "stream_index": 20, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_020.patch" + }, + { + "stream_index": 21, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_021.patch" + }, + { + "stream_index": 22, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_022.patch" + }, + { + "stream_index": 23, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_023.patch" + }, + { + "stream_index": 24, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_024.patch" + }, + { + "stream_index": 25, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_025.patch" + }, + { + "stream_index": 26, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_026.patch" + }, + { + "stream_index": 27, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_027.patch" + }, + { + "stream_index": 28, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_028.patch" + }, + { + "stream_index": 29, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_029.patch" + }, + { + "stream_index": 30, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_030.patch" + }, + { + "stream_index": 31, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_031.patch" + }, + { + "stream_index": 32, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_032.patch" + }, + { + "stream_index": 33, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_033.patch" + }, + { + "stream_index": 34, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_034.patch" + }, + { + "stream_index": 35, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_035.patch" + }, + { + "stream_index": 36, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_036.patch" + }, + { + "stream_index": 37, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_037.patch" + }, + { + "stream_index": 38, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_038.patch" + }, + { + "stream_index": 39, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_039.patch" + }, + { + "stream_index": 40, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_040.patch" + }, + { + "stream_index": 41, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_041.patch" + }, + { + "stream_index": 42, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_042.patch" + }, + { + "stream_index": 43, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_043.patch" + }, + { + "stream_index": 44, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_044.patch" + }, + { + "stream_index": 45, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_045.patch" + }, + { + "stream_index": 46, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_046.patch" + }, + { + "stream_index": 47, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_047.patch" + }, + { + "stream_index": 48, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_048.patch" + }, + { + "stream_index": 49, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_049.patch" + }, + { + "stream_index": 50, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_050.patch" + }, + { + "stream_index": 51, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_051.patch" + }, + { + "stream_index": 52, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_052.patch" + }, + { + "stream_index": 53, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_053.patch" + }, + { + "stream_index": 54, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_054.patch" + }, + { + "stream_index": 55, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_055.patch" + }, + { + "stream_index": 56, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_056.patch" + }, + { + "stream_index": 57, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_057.patch" + }, + { + "stream_index": 58, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_058.patch" + }, + { + "stream_index": 59, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_059.patch" + }, + { + "stream_index": 60, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_060.patch" + }, + { + "stream_index": 61, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_061.patch" + }, + { + "stream_index": 62, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial64": true, + "patch": "layout_patches/layout_062.patch" + }, + { + "stream_index": 63, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial64": true, + "patch": "layout_patches/layout_063.patch" + }, + { + "stream_index": 64, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_064.patch" + }, + { + "stream_index": 65, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_065.patch" + }, + { + "stream_index": 66, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_066.patch" + }, + { + "stream_index": 67, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_067.patch" + }, + { + "stream_index": 68, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_068.patch" + }, + { + "stream_index": 69, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_069.patch" + }, + { + "stream_index": 70, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_070.patch" + }, + { + "stream_index": 71, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_071.patch" + }, + { + "stream_index": 72, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_072.patch" + }, + { + "stream_index": 73, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_073.patch" + }, + { + "stream_index": 74, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_074.patch" + }, + { + "stream_index": 75, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_075.patch" + }, + { + "stream_index": 76, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_076.patch" + }, + { + "stream_index": 77, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_077.patch" + }, + { + "stream_index": 78, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_078.patch" + }, + { + "stream_index": 79, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_079.patch" + }, + { + "stream_index": 80, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_080.patch" + }, + { + "stream_index": 81, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_081.patch" + }, + { + "stream_index": 82, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_082.patch" + }, + { + "stream_index": 83, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_083.patch" + }, + { + "stream_index": 84, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_084.patch" + }, + { + "stream_index": 85, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_085.patch" + }, + { + "stream_index": 86, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_086.patch" + }, + { + "stream_index": 87, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_087.patch" + }, + { + "stream_index": 88, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_088.patch" + }, + { + "stream_index": 89, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_089.patch" + }, + { + "stream_index": 90, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_090.patch" + }, + { + "stream_index": 91, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_091.patch" + }, + { + "stream_index": 92, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_092.patch" + }, + { + "stream_index": 93, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_093.patch" + }, + { + "stream_index": 94, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_094.patch" + }, + { + "stream_index": 95, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_095.patch" + }, + { + "stream_index": 96, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_096.patch" + }, + { + "stream_index": 97, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_097.patch" + }, + { + "stream_index": 98, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_098.patch" + }, + { + "stream_index": 99, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_099.patch" + }, + { + "stream_index": 100, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_100.patch" + }, + { + "stream_index": 101, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_101.patch" + }, + { + "stream_index": 102, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_102.patch" + }, + { + "stream_index": 103, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_103.patch" + }, + { + "stream_index": 104, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_104.patch" + }, + { + "stream_index": 105, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_105.patch" + }, + { + "stream_index": 106, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_106.patch" + }, + { + "stream_index": 107, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_107.patch" + }, + { + "stream_index": 108, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_108.patch" + }, + { + "stream_index": 109, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_109.patch" + }, + { + "stream_index": 110, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_110.patch" + }, + { + "stream_index": 111, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_111.patch" + }, + { + "stream_index": 112, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_112.patch" + }, + { + "stream_index": 113, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_113.patch" + }, + { + "stream_index": 114, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_114.patch" + }, + { + "stream_index": 115, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_115.patch" + }, + { + "stream_index": 116, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_116.patch" + }, + { + "stream_index": 117, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_117.patch" + }, + { + "stream_index": 118, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_118.patch" + }, + { + "stream_index": 119, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_119.patch" + }, + { + "stream_index": 120, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_120.patch" + }, + { + "stream_index": 121, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_121.patch" + }, + { + "stream_index": 122, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_122.patch" + }, + { + "stream_index": 123, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_123.patch" + }, + { + "stream_index": 124, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_124.patch" + }, + { + "stream_index": 125, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_125.patch" + }, + { + "stream_index": 126, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_126.patch" + }, + { + "stream_index": 127, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_127.patch" + }, + { + "stream_index": 128, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_128.patch" + }, + { + "stream_index": 129, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_129.patch" + }, + { + "stream_index": 130, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_130.patch" + }, + { + "stream_index": 131, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_131.patch" + }, + { + "stream_index": 132, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_132.patch" + }, + { + "stream_index": 133, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_133.patch" + }, + { + "stream_index": 134, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_134.patch" + }, + { + "stream_index": 135, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_135.patch" + }, + { + "stream_index": 136, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_136.patch" + }, + { + "stream_index": 137, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_137.patch" + }, + { + "stream_index": 138, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_138.patch" + }, + { + "stream_index": 139, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_139.patch" + }, + { + "stream_index": 140, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_140.patch" + }, + { + "stream_index": 141, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_141.patch" + }, + { + "stream_index": 142, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_142.patch" + }, + { + "stream_index": 143, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_143.patch" + }, + { + "stream_index": 144, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_144.patch" + }, + { + "stream_index": 145, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_145.patch" + }, + { + "stream_index": 146, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_146.patch" + }, + { + "stream_index": 147, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_147.patch" + }, + { + "stream_index": 148, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_148.patch" + }, + { + "stream_index": 149, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_149.patch" + }, + { + "stream_index": 150, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_150.patch" + }, + { + "stream_index": 151, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_151.patch" + }, + { + "stream_index": 152, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_152.patch" + }, + { + "stream_index": 153, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_153.patch" + }, + { + "stream_index": 154, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_154.patch" + }, + { + "stream_index": 155, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_155.patch" + }, + { + "stream_index": 156, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_156.patch" + }, + { + "stream_index": 157, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_157.patch" + }, + { + "stream_index": 158, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_158.patch" + }, + { + "stream_index": 159, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_159.patch" + }, + { + "stream_index": 160, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_160.patch" + }, + { + "stream_index": 161, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_161.patch" + }, + { + "stream_index": 162, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_162.patch" + }, + { + "stream_index": 163, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_163.patch" + }, + { + "stream_index": 164, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_164.patch" + }, + { + "stream_index": 165, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_165.patch" + }, + { + "stream_index": 166, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_166.patch" + }, + { + "stream_index": 167, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_167.patch" + }, + { + "stream_index": 168, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_168.patch" + }, + { + "stream_index": 169, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_169.patch" + }, + { + "stream_index": 170, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_170.patch" + }, + { + "stream_index": 171, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_171.patch" + }, + { + "stream_index": 172, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_172.patch" + }, + { + "stream_index": 173, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_173.patch" + }, + { + "stream_index": 174, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_174.patch" + }, + { + "stream_index": 175, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_175.patch" + }, + { + "stream_index": 176, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_176.patch" + }, + { + "stream_index": 177, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_177.patch" + }, + { + "stream_index": 178, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_178.patch" + }, + { + "stream_index": 179, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_179.patch" + }, + { + "stream_index": 180, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_180.patch" + }, + { + "stream_index": 181, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_181.patch" + }, + { + "stream_index": 182, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_182.patch" + }, + { + "stream_index": 183, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_183.patch" + }, + { + "stream_index": 184, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_184.patch" + }, + { + "stream_index": 185, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_185.patch" + }, + { + "stream_index": 186, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_186.patch" + }, + { + "stream_index": 187, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_187.patch" + }, + { + "stream_index": 188, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_188.patch" + }, + { + "stream_index": 189, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_189.patch" + }, + { + "stream_index": 190, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_190.patch" + }, + { + "stream_index": 191, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_191.patch" + }, + { + "stream_index": 192, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_192.patch" + }, + { + "stream_index": 193, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_193.patch" + }, + { + "stream_index": 194, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_194.patch" + }, + { + "stream_index": 195, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_195.patch" + }, + { + "stream_index": 196, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_196.patch" + }, + { + "stream_index": 197, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_197.patch" + }, + { + "stream_index": 198, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_198.patch" + }, + { + "stream_index": 199, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_199.patch" + }, + { + "stream_index": 200, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_200.patch" + }, + { + "stream_index": 201, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_201.patch" + }, + { + "stream_index": 202, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_202.patch" + }, + { + "stream_index": 203, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_203.patch" + }, + { + "stream_index": 204, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_204.patch" + }, + { + "stream_index": 205, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_205.patch" + }, + { + "stream_index": 206, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_206.patch" + }, + { + "stream_index": 207, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_207.patch" + }, + { + "stream_index": 208, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_208.patch" + }, + { + "stream_index": 209, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_209.patch" + }, + { + "stream_index": 210, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_210.patch" + }, + { + "stream_index": 211, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_211.patch" + }, + { + "stream_index": 212, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_212.patch" + }, + { + "stream_index": 213, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_213.patch" + }, + { + "stream_index": 214, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_214.patch" + }, + { + "stream_index": 215, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_215.patch" + }, + { + "stream_index": 216, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_216.patch" + }, + { + "stream_index": 217, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_217.patch" + }, + { + "stream_index": 218, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_218.patch" + }, + { + "stream_index": 219, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_219.patch" + }, + { + "stream_index": 220, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_220.patch" + }, + { + "stream_index": 221, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_221.patch" + }, + { + "stream_index": 222, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_222.patch" + }, + { + "stream_index": 223, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_223.patch" + }, + { + "stream_index": 224, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_224.patch" + }, + { + "stream_index": 225, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_225.patch" + }, + { + "stream_index": 226, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_226.patch" + }, + { + "stream_index": 227, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_227.patch" + }, + { + "stream_index": 228, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_228.patch" + }, + { + "stream_index": 229, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_229.patch" + }, + { + "stream_index": 230, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_230.patch" + }, + { + "stream_index": 231, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_231.patch" + }, + { + "stream_index": 232, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_232.patch" + }, + { + "stream_index": 233, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_233.patch" + }, + { + "stream_index": 234, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_234.patch" + }, + { + "stream_index": 235, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_235.patch" + }, + { + "stream_index": 236, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_236.patch" + }, + { + "stream_index": 237, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_237.patch" + }, + { + "stream_index": 238, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_238.patch" + }, + { + "stream_index": 239, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_239.patch" + }, + { + "stream_index": 240, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_240.patch" + }, + { + "stream_index": 241, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_241.patch" + }, + { + "stream_index": 242, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_242.patch" + }, + { + "stream_index": 243, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_243.patch" + }, + { + "stream_index": 244, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_244.patch" + }, + { + "stream_index": 245, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_245.patch" + }, + { + "stream_index": 246, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_246.patch" + }, + { + "stream_index": 247, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_247.patch" + }, + { + "stream_index": 248, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_248.patch" + }, + { + "stream_index": 249, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_249.patch" + }, + { + "stream_index": 250, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_250.patch" + }, + { + "stream_index": 251, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_251.patch" + }, + { + "stream_index": 252, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial64": false, + "patch": "layout_patches/layout_252.patch" + }, + { + "stream_index": 253, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial64": false, + "patch": "layout_patches/layout_253.patch" + }, + { + "stream_index": 254, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial64": false, + "patch": "layout_patches/layout_254.patch" + }, + { + "stream_index": 255, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial64": false, + "patch": "layout_patches/layout_255.patch" + } + ], + "initial_designed_combinations": 64, + "maximum_geometry_attempts": 256, + "development_selection_disclosure": { + "observed_plan": "phase0_20261019T012051320824Z_e2_development_pilot", + "observed_terminal_attempts": 16, + "observed_status_counts": { + "COMPLETE_FEASIBLE": 3, + "INCOMPLETE_SIMULATION": 5, + "PHYSICAL_CORRECTNESS_FAILURE": 8 + }, + "observed_actual_stage_wall_seconds_sum": { + "generation": 609.9871089779772, + "geometry": 5.148403265979141, + "DRC": 13.687622816301882, + "LVS": 27.38197941845283, + "PEX": 5.3266015611588955, + "electrical": 2045.6257181959227 + }, + "effect_on_proposal": "Preserve source control sites and development endpoint ranges; add declared interior levels before formal labels. No exclusion of known failing endpoint(s), no reruns chosen by prior success. Three symmetric sizing points chosen now; no nondefault-size postRC outcome observed.", + "application_selection": "FVF15pF chosen after10pF SS58.59 failed60deg; positive-control PMmin67.11 known. Legacy15pF is a one-time load hypothesis after.5pF lowPM; outcome pending. These are explicit development-informed application choices, not a blind posthoc comparison.", + "timeout_selection": "Old5T/compact incomplete90/120s transients stay unresolved; longer formal budgets, if adopted, must be calibrated and frozen before any formal candidate labels. Old outcomes never relabeled." + } + }, + "fvf": { + "source_snapshot": "/srv/code-behind-layout/runtime/e2_draft_preparation/20261019T021747204896Z/fvf/generator_snapshot.py", + "dependency_revision": "d092211d7996c99159402451bc7141931d6a93c3", + "source_origin": "/work/vendor/glayout-e2-development/src/glayout/cells/composite/fvf_based_ota/ota.py", + "contract": { + "supply_V": 1.8, + "load_F": 1.5e-11, + "common_mode_V": 0.9, + "temperature_C": 27, + "corners": [ + "tt", + "ss", + "ff" + ], + "bench_source_unchanged": "testbench_snapshot.py", + "numerics": { + "reltol": 1e-06, + "abstol": 1e-14, + "vntol": 1e-08, + "chgtol": 1e-16 + }, + "analysis_coverage": { + "OP_rows": 1, + "AC_rows": 241, + "AC_Hz": [ + 10, + 1000000000.0 + ], + "transient_s": [ + 0, + 4e-06 + ], + "DC_points": 7, + "DC_V": [ + 0.6, + 1.2 + ] + }, + "existing_development_feasibility": { + "gain_10Hz_dB_min": 30, + "phase_margin_deg_closed_interval": [ + 60, + 180 + ], + "ugb_Hz_min": 1000000.0, + "nominal_tracking_abs_V_lt": 0.01, + "settled_plateau_mean_tracking_abs_V_lt": 0.01, + "positive_low_frequency_gain": true, + "power_W_max": 0.001 + }, + "DC_sweep_interpretation": "The complete broad tracking sweep is retained; no extra output-swing or maximum-DC-error constraint is added.", + "bias_currents_A": [ + 1e-05, + 1e-05 + ], + "qualification": "Separate15pF positive control phase0_20261019T012047189356Z_fvf_validate; never relabel old10pF E2" + }, + "control_levels": { + "pblock_gap_um": [ + 8, + 9, + 11, + 12 + ], + "bias_route_extension_um": [ + 8.8, + 9.6, + 10.4, + 11.2 + ], + "source_tie_width_um": [ + 0.6, + 0.9, + 0.7, + 0.8 + ], + "lcmfb_route_width_um": [ + 0.9, + 1.2, + 1, + 1.1 + ] + }, + "sizings": [ + { + "id": "s0", + "sizing": { + "local_current_bias_params": [ + 3.76, + 2.5 + ], + "all_other_arguments": "unchanged defaults" + }, + "generator_arguments": { + "local_current_bias_params": [ + 3.76, + 2.5 + ] + }, + "intended_gold": "/srv/code-behind-layout/runtime/e2_draft_preparation/20261019T021747204896Z/fvf/sizing_0/gold.spice", + "gold_bound_before_GDS": true, + "physical_qualification": "pending" + }, + { + "id": "s1", + "sizing": { + "local_current_bias_params": [ + 3.76, + 3 + ], + "all_other_arguments": "unchanged defaults" + }, + "generator_arguments": { + "local_current_bias_params": [ + 3.76, + 3 + ] + }, + "intended_gold": "/srv/code-behind-layout/runtime/e2_draft_preparation/20261019T021747204896Z/fvf/sizing_1/gold.spice", + "gold_bound_before_GDS": true, + "physical_qualification": "qualified default at declared development application only; no formal trial" + }, + { + "id": "s2", + "sizing": { + "local_current_bias_params": [ + 3.76, + 3.5 + ], + "all_other_arguments": "unchanged defaults" + }, + "generator_arguments": { + "local_current_bias_params": [ + 3.76, + 3.5 + ] + }, + "intended_gold": "/srv/code-behind-layout/runtime/e2_draft_preparation/20261019T021747204896Z/fvf/sizing_2/gold.spice", + "gold_bound_before_GDS": true, + "physical_qualification": "pending" + } + ], + "candidate_stream": [ + { + "stream_index": 0, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_000.patch" + }, + { + "stream_index": 1, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_001.patch" + }, + { + "stream_index": 2, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_002.patch" + }, + { + "stream_index": 3, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_003.patch" + }, + { + "stream_index": 4, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_004.patch" + }, + { + "stream_index": 5, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_005.patch" + }, + { + "stream_index": 6, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_006.patch" + }, + { + "stream_index": 7, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_007.patch" + }, + { + "stream_index": 8, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_008.patch" + }, + { + "stream_index": 9, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_009.patch" + }, + { + "stream_index": 10, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_010.patch" + }, + { + "stream_index": 11, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_011.patch" + }, + { + "stream_index": 12, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_012.patch" + }, + { + "stream_index": 13, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_013.patch" + }, + { + "stream_index": 14, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_014.patch" + }, + { + "stream_index": 15, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_015.patch" + }, + { + "stream_index": 16, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_016.patch" + }, + { + "stream_index": 17, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_017.patch" + }, + { + "stream_index": 18, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_018.patch" + }, + { + "stream_index": 19, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_019.patch" + }, + { + "stream_index": 20, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_020.patch" + }, + { + "stream_index": 21, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_021.patch" + }, + { + "stream_index": 22, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_022.patch" + }, + { + "stream_index": 23, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_023.patch" + }, + { + "stream_index": 24, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_024.patch" + }, + { + "stream_index": 25, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_025.patch" + }, + { + "stream_index": 26, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_026.patch" + }, + { + "stream_index": 27, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_027.patch" + }, + { + "stream_index": 28, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_028.patch" + }, + { + "stream_index": 29, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_029.patch" + }, + { + "stream_index": 30, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_030.patch" + }, + { + "stream_index": 31, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_031.patch" + }, + { + "stream_index": 32, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_032.patch" + }, + { + "stream_index": 33, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_033.patch" + }, + { + "stream_index": 34, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_034.patch" + }, + { + "stream_index": 35, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_035.patch" + }, + { + "stream_index": 36, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_036.patch" + }, + { + "stream_index": 37, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_037.patch" + }, + { + "stream_index": 38, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_038.patch" + }, + { + "stream_index": 39, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_039.patch" + }, + { + "stream_index": 40, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_040.patch" + }, + { + "stream_index": 41, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_041.patch" + }, + { + "stream_index": 42, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_042.patch" + }, + { + "stream_index": 43, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_043.patch" + }, + { + "stream_index": 44, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_044.patch" + }, + { + "stream_index": 45, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_045.patch" + }, + { + "stream_index": 46, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_046.patch" + }, + { + "stream_index": 47, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_047.patch" + }, + { + "stream_index": 48, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_048.patch" + }, + { + "stream_index": 49, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_049.patch" + }, + { + "stream_index": 50, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_050.patch" + }, + { + "stream_index": 51, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_051.patch" + }, + { + "stream_index": 52, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_052.patch" + }, + { + "stream_index": 53, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_053.patch" + }, + { + "stream_index": 54, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_054.patch" + }, + { + "stream_index": 55, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_055.patch" + }, + { + "stream_index": 56, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_056.patch" + }, + { + "stream_index": 57, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_057.patch" + }, + { + "stream_index": 58, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_058.patch" + }, + { + "stream_index": 59, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_059.patch" + }, + { + "stream_index": 60, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_060.patch" + }, + { + "stream_index": 61, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_061.patch" + }, + { + "stream_index": 62, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial64": true, + "patch": "layout_patches/layout_062.patch" + }, + { + "stream_index": 63, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial64": true, + "patch": "layout_patches/layout_063.patch" + }, + { + "stream_index": 64, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_064.patch" + }, + { + "stream_index": 65, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_065.patch" + }, + { + "stream_index": 66, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_066.patch" + }, + { + "stream_index": 67, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_067.patch" + }, + { + "stream_index": 68, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_068.patch" + }, + { + "stream_index": 69, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_069.patch" + }, + { + "stream_index": 70, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_070.patch" + }, + { + "stream_index": 71, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_071.patch" + }, + { + "stream_index": 72, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_072.patch" + }, + { + "stream_index": 73, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_073.patch" + }, + { + "stream_index": 74, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_074.patch" + }, + { + "stream_index": 75, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_075.patch" + }, + { + "stream_index": 76, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_076.patch" + }, + { + "stream_index": 77, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_077.patch" + }, + { + "stream_index": 78, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_078.patch" + }, + { + "stream_index": 79, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_079.patch" + }, + { + "stream_index": 80, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_080.patch" + }, + { + "stream_index": 81, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_081.patch" + }, + { + "stream_index": 82, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_082.patch" + }, + { + "stream_index": 83, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_083.patch" + }, + { + "stream_index": 84, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_084.patch" + }, + { + "stream_index": 85, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_085.patch" + }, + { + "stream_index": 86, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_086.patch" + }, + { + "stream_index": 87, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_087.patch" + }, + { + "stream_index": 88, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_088.patch" + }, + { + "stream_index": 89, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_089.patch" + }, + { + "stream_index": 90, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_090.patch" + }, + { + "stream_index": 91, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_091.patch" + }, + { + "stream_index": 92, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_092.patch" + }, + { + "stream_index": 93, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_093.patch" + }, + { + "stream_index": 94, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_094.patch" + }, + { + "stream_index": 95, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_095.patch" + }, + { + "stream_index": 96, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_096.patch" + }, + { + "stream_index": 97, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_097.patch" + }, + { + "stream_index": 98, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_098.patch" + }, + { + "stream_index": 99, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_099.patch" + }, + { + "stream_index": 100, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_100.patch" + }, + { + "stream_index": 101, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_101.patch" + }, + { + "stream_index": 102, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_102.patch" + }, + { + "stream_index": 103, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_103.patch" + }, + { + "stream_index": 104, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_104.patch" + }, + { + "stream_index": 105, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_105.patch" + }, + { + "stream_index": 106, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_106.patch" + }, + { + "stream_index": 107, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_107.patch" + }, + { + "stream_index": 108, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_108.patch" + }, + { + "stream_index": 109, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_109.patch" + }, + { + "stream_index": 110, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_110.patch" + }, + { + "stream_index": 111, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_111.patch" + }, + { + "stream_index": 112, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_112.patch" + }, + { + "stream_index": 113, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_113.patch" + }, + { + "stream_index": 114, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_114.patch" + }, + { + "stream_index": 115, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_115.patch" + }, + { + "stream_index": 116, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_116.patch" + }, + { + "stream_index": 117, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_117.patch" + }, + { + "stream_index": 118, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_118.patch" + }, + { + "stream_index": 119, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_119.patch" + }, + { + "stream_index": 120, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_120.patch" + }, + { + "stream_index": 121, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_121.patch" + }, + { + "stream_index": 122, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_122.patch" + }, + { + "stream_index": 123, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_123.patch" + }, + { + "stream_index": 124, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_124.patch" + }, + { + "stream_index": 125, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_125.patch" + }, + { + "stream_index": 126, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_126.patch" + }, + { + "stream_index": 127, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_127.patch" + }, + { + "stream_index": 128, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_128.patch" + }, + { + "stream_index": 129, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_129.patch" + }, + { + "stream_index": 130, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_130.patch" + }, + { + "stream_index": 131, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_131.patch" + }, + { + "stream_index": 132, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_132.patch" + }, + { + "stream_index": 133, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_133.patch" + }, + { + "stream_index": 134, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_134.patch" + }, + { + "stream_index": 135, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_135.patch" + }, + { + "stream_index": 136, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_136.patch" + }, + { + "stream_index": 137, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_137.patch" + }, + { + "stream_index": 138, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_138.patch" + }, + { + "stream_index": 139, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_139.patch" + }, + { + "stream_index": 140, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_140.patch" + }, + { + "stream_index": 141, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_141.patch" + }, + { + "stream_index": 142, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_142.patch" + }, + { + "stream_index": 143, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_143.patch" + }, + { + "stream_index": 144, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_144.patch" + }, + { + "stream_index": 145, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_145.patch" + }, + { + "stream_index": 146, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_146.patch" + }, + { + "stream_index": 147, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_147.patch" + }, + { + "stream_index": 148, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_148.patch" + }, + { + "stream_index": 149, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_149.patch" + }, + { + "stream_index": 150, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_150.patch" + }, + { + "stream_index": 151, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_151.patch" + }, + { + "stream_index": 152, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_152.patch" + }, + { + "stream_index": 153, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_153.patch" + }, + { + "stream_index": 154, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_154.patch" + }, + { + "stream_index": 155, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_155.patch" + }, + { + "stream_index": 156, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_156.patch" + }, + { + "stream_index": 157, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_157.patch" + }, + { + "stream_index": 158, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_158.patch" + }, + { + "stream_index": 159, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_159.patch" + }, + { + "stream_index": 160, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_160.patch" + }, + { + "stream_index": 161, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_161.patch" + }, + { + "stream_index": 162, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_162.patch" + }, + { + "stream_index": 163, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_163.patch" + }, + { + "stream_index": 164, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_164.patch" + }, + { + "stream_index": 165, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_165.patch" + }, + { + "stream_index": 166, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_166.patch" + }, + { + "stream_index": 167, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_167.patch" + }, + { + "stream_index": 168, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_168.patch" + }, + { + "stream_index": 169, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_169.patch" + }, + { + "stream_index": 170, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_170.patch" + }, + { + "stream_index": 171, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_171.patch" + }, + { + "stream_index": 172, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_172.patch" + }, + { + "stream_index": 173, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_173.patch" + }, + { + "stream_index": 174, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_174.patch" + }, + { + "stream_index": 175, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_175.patch" + }, + { + "stream_index": 176, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_176.patch" + }, + { + "stream_index": 177, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_177.patch" + }, + { + "stream_index": 178, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_178.patch" + }, + { + "stream_index": 179, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_179.patch" + }, + { + "stream_index": 180, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_180.patch" + }, + { + "stream_index": 181, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_181.patch" + }, + { + "stream_index": 182, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_182.patch" + }, + { + "stream_index": 183, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_183.patch" + }, + { + "stream_index": 184, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_184.patch" + }, + { + "stream_index": 185, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_185.patch" + }, + { + "stream_index": 186, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_186.patch" + }, + { + "stream_index": 187, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_187.patch" + }, + { + "stream_index": 188, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_188.patch" + }, + { + "stream_index": 189, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_189.patch" + }, + { + "stream_index": 190, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_190.patch" + }, + { + "stream_index": 191, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_191.patch" + }, + { + "stream_index": 192, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_192.patch" + }, + { + "stream_index": 193, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_193.patch" + }, + { + "stream_index": 194, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_194.patch" + }, + { + "stream_index": 195, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_195.patch" + }, + { + "stream_index": 196, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_196.patch" + }, + { + "stream_index": 197, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_197.patch" + }, + { + "stream_index": 198, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_198.patch" + }, + { + "stream_index": 199, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_199.patch" + }, + { + "stream_index": 200, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_200.patch" + }, + { + "stream_index": 201, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_201.patch" + }, + { + "stream_index": 202, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_202.patch" + }, + { + "stream_index": 203, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_203.patch" + }, + { + "stream_index": 204, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_204.patch" + }, + { + "stream_index": 205, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_205.patch" + }, + { + "stream_index": 206, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_206.patch" + }, + { + "stream_index": 207, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_207.patch" + }, + { + "stream_index": 208, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_208.patch" + }, + { + "stream_index": 209, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_209.patch" + }, + { + "stream_index": 210, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_210.patch" + }, + { + "stream_index": 211, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_211.patch" + }, + { + "stream_index": 212, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_212.patch" + }, + { + "stream_index": 213, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_213.patch" + }, + { + "stream_index": 214, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_214.patch" + }, + { + "stream_index": 215, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_215.patch" + }, + { + "stream_index": 216, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_216.patch" + }, + { + "stream_index": 217, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_217.patch" + }, + { + "stream_index": 218, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_218.patch" + }, + { + "stream_index": 219, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_219.patch" + }, + { + "stream_index": 220, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_220.patch" + }, + { + "stream_index": 221, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_221.patch" + }, + { + "stream_index": 222, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_222.patch" + }, + { + "stream_index": 223, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_223.patch" + }, + { + "stream_index": 224, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_224.patch" + }, + { + "stream_index": 225, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_225.patch" + }, + { + "stream_index": 226, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_226.patch" + }, + { + "stream_index": 227, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_227.patch" + }, + { + "stream_index": 228, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_228.patch" + }, + { + "stream_index": 229, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_229.patch" + }, + { + "stream_index": 230, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_230.patch" + }, + { + "stream_index": 231, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_231.patch" + }, + { + "stream_index": 232, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_232.patch" + }, + { + "stream_index": 233, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_233.patch" + }, + { + "stream_index": 234, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_234.patch" + }, + { + "stream_index": 235, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_235.patch" + }, + { + "stream_index": 236, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_236.patch" + }, + { + "stream_index": 237, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_237.patch" + }, + { + "stream_index": 238, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_238.patch" + }, + { + "stream_index": 239, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_239.patch" + }, + { + "stream_index": 240, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_240.patch" + }, + { + "stream_index": 241, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_241.patch" + }, + { + "stream_index": 242, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_242.patch" + }, + { + "stream_index": 243, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_243.patch" + }, + { + "stream_index": 244, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_244.patch" + }, + { + "stream_index": 245, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_245.patch" + }, + { + "stream_index": 246, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_246.patch" + }, + { + "stream_index": 247, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_247.patch" + }, + { + "stream_index": 248, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_248.patch" + }, + { + "stream_index": 249, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_249.patch" + }, + { + "stream_index": 250, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_250.patch" + }, + { + "stream_index": 251, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_251.patch" + }, + { + "stream_index": 252, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial64": false, + "patch": "layout_patches/layout_252.patch" + }, + { + "stream_index": 253, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial64": false, + "patch": "layout_patches/layout_253.patch" + }, + { + "stream_index": 254, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial64": false, + "patch": "layout_patches/layout_254.patch" + }, + { + "stream_index": 255, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial64": false, + "patch": "layout_patches/layout_255.patch" + } + ], + "initial_designed_combinations": 64, + "maximum_geometry_attempts": 256, + "development_selection_disclosure": { + "observed_plan": "phase0_20261019T012053961469Z_e2_development_pilot", + "observed_terminal_attempts": 10, + "observed_status_counts": { + "COMPLETE_INFEASIBLE": 10 + }, + "observed_actual_stage_wall_seconds_sum": { + "generation": 1200.8287399858236, + "geometry": 7.109317692928016, + "DRC": 11.730797891505063, + "LVS": 21.691459759138525, + "PEX": 8.324352533556521, + "electrical": 6094.370055863634 + }, + "effect_on_proposal": "Preserve source control sites and development endpoint ranges; add declared interior levels before formal labels. No exclusion of known failing endpoint(s), no reruns chosen by prior success. Three symmetric sizing points chosen now; no nondefault-size postRC outcome observed.", + "application_selection": "FVF15pF chosen after10pF SS58.59 failed60deg; positive-control PMmin67.11 known. Legacy15pF is a one-time load hypothesis after.5pF lowPM; outcome pending. These are explicit development-informed application choices, not a blind posthoc comparison.", + "timeout_selection": "Old5T/compact incomplete90/120s transients stay unresolved; longer formal budgets, if adopted, must be calibrated and frozen before any formal candidate labels. Old outcomes never relabeled." + } + }, + "legacy_miller": { + "source_snapshot": "/srv/code-behind-layout/runtime/e2_draft_preparation/20261019T021747204896Z/legacy_miller/generator_snapshot.py", + "dependency_revision": "d092211d7996c99159402451bc7141931d6a93c3", + "source_origin": "/work/vendor/glayout-e2-development/src/glayout/cells/composite/opamp/opamp_twostage.py", + "contract": { + "supply_V": 1.8, + "load_F": 1.5e-11, + "common_mode_V": 0.9, + "temperature_C": 27, + "corners": [ + "tt", + "ss", + "ff" + ], + "numerics": { + "reltol": 1e-06, + "abstol": 1e-14, + "vntol": 1e-08, + "chgtol": 1e-16 + }, + "analysis_coverage": { + "OP_rows": 1, + "AC_rows": 241, + "AC_Hz": [ + 10, + 1000000000.0 + ], + "transient_s": [ + 0, + 2e-05 + ], + "DC_points": 7, + "DC_V": [ + 0.6, + 1.2 + ] + }, + "existing_development_feasibility": { + "gain_10Hz_dB_min": 30, + "phase_margin_deg_closed_interval": [ + 60, + 180 + ], + "ugb_Hz_min": 1000000.0, + "nominal_tracking_abs_V_lt": 0.01, + "settled_plateau_mean_tracking_abs_V_lt": 0.01, + "positive_low_frequency_gain": true, + "power_W_max": 0.001 + }, + "DC_sweep_interpretation": "The complete broad tracking sweep is retained; no extra output-swing or maximum-DC-error constraint is added.", + "bias_currents_A": [ + 1e-05, + 1e-05 + ], + "bench_source_base": "testbench_snapshot.py", + "prospective_window_adapter": "independent_legacy_domain.py retained in draft source pack", + "transient_window_binding": "scripts/independent_legacy_domain.py:5us delay/5us plateau/10us period;5ns step;8.5..9.9us and13.5..14.9us settled windows", + "qualification": "Single15pF actual qualification pending. Failure remains in draft; no load/spec search. UGB>=1MHz and PM>=60 unchanged." + }, + "control_levels": { + "stage_gap_um": [ + 10, + 11, + 13, + 14 + ], + "output_route_width_um": [ + 2.2, + 2.4, + 2.6, + 2.8 + ], + "output_route_extension_um": [ + 2, + 6, + 3, + 5 + ], + "input_antenna_span_multiplier": [ + 9, + 13, + 10, + 12 + ] + }, + "sizings": [ + { + "id": "s0", + "sizing": { + "half_diffpair_params": [ + 5, + 1, + 4 + ], + "mim_cap_size": [ + 30, + 30 + ], + "rmult": 2, + "all_other_arguments": "unchanged defaults" + }, + "generator_arguments": { + "half_diffpair_params": [ + 5, + 1, + 4 + ], + "mim_cap_size": [ + 30, + 30 + ], + "rmult": 2 + }, + "intended_gold": "/srv/code-behind-layout/runtime/e2_draft_preparation/20261019T021747204896Z/legacy_miller/sizing_0/gold.spice", + "gold_bound_before_GDS": true, + "physical_qualification": "pending" + }, + { + "id": "s1", + "sizing": { + "half_diffpair_params": [ + 6, + 1, + 4 + ], + "mim_cap_size": [ + 30, + 30 + ], + "rmult": 2, + "all_other_arguments": "unchanged defaults" + }, + "generator_arguments": { + "half_diffpair_params": [ + 6, + 1, + 4 + ], + "mim_cap_size": [ + 30, + 30 + ], + "rmult": 2 + }, + "intended_gold": "/srv/code-behind-layout/runtime/e2_draft_preparation/20261019T021747204896Z/legacy_miller/sizing_1/gold.spice", + "gold_bound_before_GDS": true, + "physical_qualification": "source and sizing qualified at old.5pF only; prospective15pF pending" + }, + { + "id": "s2", + "sizing": { + "half_diffpair_params": [ + 7, + 1, + 4 + ], + "mim_cap_size": [ + 30, + 30 + ], + "rmult": 2, + "all_other_arguments": "unchanged defaults" + }, + "generator_arguments": { + "half_diffpair_params": [ + 7, + 1, + 4 + ], + "mim_cap_size": [ + 30, + 30 + ], + "rmult": 2 + }, + "intended_gold": "/srv/code-behind-layout/runtime/e2_draft_preparation/20261019T021747204896Z/legacy_miller/sizing_2/gold.spice", + "gold_bound_before_GDS": true, + "physical_qualification": "pending" + } + ], + "candidate_stream": [ + { + "stream_index": 0, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.2, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_000.patch" + }, + { + "stream_index": 1, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.2, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_001.patch" + }, + { + "stream_index": 2, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.2, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_002.patch" + }, + { + "stream_index": 3, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.2, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_003.patch" + }, + { + "stream_index": 4, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.4, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_004.patch" + }, + { + "stream_index": 5, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.4, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_005.patch" + }, + { + "stream_index": 6, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.4, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_006.patch" + }, + { + "stream_index": 7, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.4, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_007.patch" + }, + { + "stream_index": 8, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.6, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_008.patch" + }, + { + "stream_index": 9, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.6, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_009.patch" + }, + { + "stream_index": 10, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.6, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_010.patch" + }, + { + "stream_index": 11, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.6, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_011.patch" + }, + { + "stream_index": 12, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.8, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_012.patch" + }, + { + "stream_index": 13, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.8, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_013.patch" + }, + { + "stream_index": 14, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.8, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_014.patch" + }, + { + "stream_index": 15, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.8, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_015.patch" + }, + { + "stream_index": 16, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.2, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_016.patch" + }, + { + "stream_index": 17, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.2, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_017.patch" + }, + { + "stream_index": 18, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.2, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_018.patch" + }, + { + "stream_index": 19, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.2, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_019.patch" + }, + { + "stream_index": 20, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.4, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_020.patch" + }, + { + "stream_index": 21, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.4, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_021.patch" + }, + { + "stream_index": 22, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.4, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_022.patch" + }, + { + "stream_index": 23, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.4, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_023.patch" + }, + { + "stream_index": 24, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.6, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_024.patch" + }, + { + "stream_index": 25, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.6, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_025.patch" + }, + { + "stream_index": 26, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.6, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_026.patch" + }, + { + "stream_index": 27, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.6, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_027.patch" + }, + { + "stream_index": 28, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.8, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_028.patch" + }, + { + "stream_index": 29, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.8, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_029.patch" + }, + { + "stream_index": 30, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.8, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_030.patch" + }, + { + "stream_index": 31, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.8, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_031.patch" + }, + { + "stream_index": 32, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.2, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_032.patch" + }, + { + "stream_index": 33, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.2, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_033.patch" + }, + { + "stream_index": 34, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.2, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_034.patch" + }, + { + "stream_index": 35, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.2, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_035.patch" + }, + { + "stream_index": 36, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.4, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_036.patch" + }, + { + "stream_index": 37, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.4, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_037.patch" + }, + { + "stream_index": 38, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.4, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_038.patch" + }, + { + "stream_index": 39, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.4, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_039.patch" + }, + { + "stream_index": 40, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.6, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_040.patch" + }, + { + "stream_index": 41, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.6, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_041.patch" + }, + { + "stream_index": 42, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.6, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_042.patch" + }, + { + "stream_index": 43, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.6, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_043.patch" + }, + { + "stream_index": 44, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.8, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_044.patch" + }, + { + "stream_index": 45, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.8, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_045.patch" + }, + { + "stream_index": 46, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.8, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_046.patch" + }, + { + "stream_index": 47, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.8, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_047.patch" + }, + { + "stream_index": 48, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.2, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_048.patch" + }, + { + "stream_index": 49, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.2, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_049.patch" + }, + { + "stream_index": 50, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.2, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_050.patch" + }, + { + "stream_index": 51, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.2, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_051.patch" + }, + { + "stream_index": 52, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.4, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_052.patch" + }, + { + "stream_index": 53, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.4, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_053.patch" + }, + { + "stream_index": 54, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.4, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_054.patch" + }, + { + "stream_index": 55, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.4, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_055.patch" + }, + { + "stream_index": 56, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.6, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_056.patch" + }, + { + "stream_index": 57, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.6, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_057.patch" + }, + { + "stream_index": 58, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.6, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_058.patch" + }, + { + "stream_index": 59, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.6, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_059.patch" + }, + { + "stream_index": 60, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.8, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_060.patch" + }, + { + "stream_index": 61, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.8, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_061.patch" + }, + { + "stream_index": 62, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.8, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 9 + }, + "initial64": true, + "patch": "layout_patches/layout_062.patch" + }, + { + "stream_index": 63, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.8, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 13 + }, + "initial64": true, + "patch": "layout_patches/layout_063.patch" + }, + { + "stream_index": 64, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.2, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_064.patch" + }, + { + "stream_index": 65, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.2, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_065.patch" + }, + { + "stream_index": 66, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.2, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_066.patch" + }, + { + "stream_index": 67, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.2, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_067.patch" + }, + { + "stream_index": 68, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.2, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_068.patch" + }, + { + "stream_index": 69, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.2, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_069.patch" + }, + { + "stream_index": 70, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.2, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_070.patch" + }, + { + "stream_index": 71, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.2, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_071.patch" + }, + { + "stream_index": 72, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.2, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_072.patch" + }, + { + "stream_index": 73, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.2, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_073.patch" + }, + { + "stream_index": 74, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.2, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_074.patch" + }, + { + "stream_index": 75, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.2, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_075.patch" + }, + { + "stream_index": 76, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.4, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_076.patch" + }, + { + "stream_index": 77, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.4, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_077.patch" + }, + { + "stream_index": 78, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.4, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_078.patch" + }, + { + "stream_index": 79, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.4, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_079.patch" + }, + { + "stream_index": 80, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.4, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_080.patch" + }, + { + "stream_index": 81, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.4, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_081.patch" + }, + { + "stream_index": 82, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.4, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_082.patch" + }, + { + "stream_index": 83, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.4, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_083.patch" + }, + { + "stream_index": 84, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.4, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_084.patch" + }, + { + "stream_index": 85, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.4, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_085.patch" + }, + { + "stream_index": 86, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.4, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_086.patch" + }, + { + "stream_index": 87, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.4, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_087.patch" + }, + { + "stream_index": 88, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.6, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_088.patch" + }, + { + "stream_index": 89, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.6, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_089.patch" + }, + { + "stream_index": 90, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.6, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_090.patch" + }, + { + "stream_index": 91, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.6, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_091.patch" + }, + { + "stream_index": 92, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.6, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_092.patch" + }, + { + "stream_index": 93, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.6, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_093.patch" + }, + { + "stream_index": 94, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.6, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_094.patch" + }, + { + "stream_index": 95, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.6, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_095.patch" + }, + { + "stream_index": 96, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.6, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_096.patch" + }, + { + "stream_index": 97, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.6, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_097.patch" + }, + { + "stream_index": 98, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.6, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_098.patch" + }, + { + "stream_index": 99, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.6, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_099.patch" + }, + { + "stream_index": 100, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.8, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_100.patch" + }, + { + "stream_index": 101, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.8, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_101.patch" + }, + { + "stream_index": 102, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.8, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_102.patch" + }, + { + "stream_index": 103, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.8, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_103.patch" + }, + { + "stream_index": 104, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.8, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_104.patch" + }, + { + "stream_index": 105, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.8, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_105.patch" + }, + { + "stream_index": 106, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.8, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_106.patch" + }, + { + "stream_index": 107, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.8, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_107.patch" + }, + { + "stream_index": 108, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.8, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_108.patch" + }, + { + "stream_index": 109, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.8, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_109.patch" + }, + { + "stream_index": 110, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.8, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_110.patch" + }, + { + "stream_index": 111, + "controls": { + "stage_gap_um": 10, + "output_route_width_um": 2.8, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_111.patch" + }, + { + "stream_index": 112, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.2, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_112.patch" + }, + { + "stream_index": 113, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.2, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_113.patch" + }, + { + "stream_index": 114, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.2, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_114.patch" + }, + { + "stream_index": 115, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.2, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_115.patch" + }, + { + "stream_index": 116, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.2, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_116.patch" + }, + { + "stream_index": 117, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.2, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_117.patch" + }, + { + "stream_index": 118, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.2, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_118.patch" + }, + { + "stream_index": 119, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.2, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_119.patch" + }, + { + "stream_index": 120, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.2, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_120.patch" + }, + { + "stream_index": 121, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.2, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_121.patch" + }, + { + "stream_index": 122, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.2, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_122.patch" + }, + { + "stream_index": 123, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.2, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_123.patch" + }, + { + "stream_index": 124, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.4, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_124.patch" + }, + { + "stream_index": 125, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.4, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_125.patch" + }, + { + "stream_index": 126, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.4, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_126.patch" + }, + { + "stream_index": 127, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.4, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_127.patch" + }, + { + "stream_index": 128, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.4, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_128.patch" + }, + { + "stream_index": 129, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.4, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_129.patch" + }, + { + "stream_index": 130, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.4, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_130.patch" + }, + { + "stream_index": 131, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.4, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_131.patch" + }, + { + "stream_index": 132, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.4, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_132.patch" + }, + { + "stream_index": 133, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.4, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_133.patch" + }, + { + "stream_index": 134, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.4, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_134.patch" + }, + { + "stream_index": 135, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.4, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_135.patch" + }, + { + "stream_index": 136, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.6, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_136.patch" + }, + { + "stream_index": 137, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.6, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_137.patch" + }, + { + "stream_index": 138, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.6, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_138.patch" + }, + { + "stream_index": 139, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.6, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_139.patch" + }, + { + "stream_index": 140, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.6, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_140.patch" + }, + { + "stream_index": 141, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.6, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_141.patch" + }, + { + "stream_index": 142, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.6, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_142.patch" + }, + { + "stream_index": 143, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.6, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_143.patch" + }, + { + "stream_index": 144, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.6, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_144.patch" + }, + { + "stream_index": 145, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.6, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_145.patch" + }, + { + "stream_index": 146, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.6, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_146.patch" + }, + { + "stream_index": 147, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.6, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_147.patch" + }, + { + "stream_index": 148, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.8, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_148.patch" + }, + { + "stream_index": 149, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.8, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_149.patch" + }, + { + "stream_index": 150, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.8, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_150.patch" + }, + { + "stream_index": 151, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.8, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_151.patch" + }, + { + "stream_index": 152, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.8, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_152.patch" + }, + { + "stream_index": 153, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.8, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_153.patch" + }, + { + "stream_index": 154, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.8, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_154.patch" + }, + { + "stream_index": 155, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.8, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_155.patch" + }, + { + "stream_index": 156, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.8, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_156.patch" + }, + { + "stream_index": 157, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.8, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_157.patch" + }, + { + "stream_index": 158, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.8, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_158.patch" + }, + { + "stream_index": 159, + "controls": { + "stage_gap_um": 11, + "output_route_width_um": 2.8, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_159.patch" + }, + { + "stream_index": 160, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.2, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_160.patch" + }, + { + "stream_index": 161, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.2, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_161.patch" + }, + { + "stream_index": 162, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.2, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_162.patch" + }, + { + "stream_index": 163, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.2, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_163.patch" + }, + { + "stream_index": 164, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.2, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_164.patch" + }, + { + "stream_index": 165, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.2, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_165.patch" + }, + { + "stream_index": 166, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.2, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_166.patch" + }, + { + "stream_index": 167, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.2, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_167.patch" + }, + { + "stream_index": 168, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.2, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_168.patch" + }, + { + "stream_index": 169, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.2, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_169.patch" + }, + { + "stream_index": 170, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.2, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_170.patch" + }, + { + "stream_index": 171, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.2, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_171.patch" + }, + { + "stream_index": 172, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.4, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_172.patch" + }, + { + "stream_index": 173, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.4, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_173.patch" + }, + { + "stream_index": 174, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.4, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_174.patch" + }, + { + "stream_index": 175, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.4, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_175.patch" + }, + { + "stream_index": 176, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.4, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_176.patch" + }, + { + "stream_index": 177, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.4, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_177.patch" + }, + { + "stream_index": 178, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.4, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_178.patch" + }, + { + "stream_index": 179, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.4, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_179.patch" + }, + { + "stream_index": 180, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.4, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_180.patch" + }, + { + "stream_index": 181, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.4, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_181.patch" + }, + { + "stream_index": 182, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.4, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_182.patch" + }, + { + "stream_index": 183, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.4, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_183.patch" + }, + { + "stream_index": 184, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.6, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_184.patch" + }, + { + "stream_index": 185, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.6, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_185.patch" + }, + { + "stream_index": 186, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.6, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_186.patch" + }, + { + "stream_index": 187, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.6, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_187.patch" + }, + { + "stream_index": 188, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.6, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_188.patch" + }, + { + "stream_index": 189, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.6, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_189.patch" + }, + { + "stream_index": 190, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.6, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_190.patch" + }, + { + "stream_index": 191, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.6, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_191.patch" + }, + { + "stream_index": 192, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.6, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_192.patch" + }, + { + "stream_index": 193, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.6, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_193.patch" + }, + { + "stream_index": 194, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.6, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_194.patch" + }, + { + "stream_index": 195, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.6, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_195.patch" + }, + { + "stream_index": 196, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.8, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_196.patch" + }, + { + "stream_index": 197, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.8, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_197.patch" + }, + { + "stream_index": 198, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.8, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_198.patch" + }, + { + "stream_index": 199, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.8, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_199.patch" + }, + { + "stream_index": 200, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.8, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_200.patch" + }, + { + "stream_index": 201, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.8, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_201.patch" + }, + { + "stream_index": 202, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.8, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_202.patch" + }, + { + "stream_index": 203, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.8, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_203.patch" + }, + { + "stream_index": 204, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.8, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_204.patch" + }, + { + "stream_index": 205, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.8, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_205.patch" + }, + { + "stream_index": 206, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.8, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_206.patch" + }, + { + "stream_index": 207, + "controls": { + "stage_gap_um": 13, + "output_route_width_um": 2.8, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_207.patch" + }, + { + "stream_index": 208, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.2, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_208.patch" + }, + { + "stream_index": 209, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.2, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_209.patch" + }, + { + "stream_index": 210, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.2, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_210.patch" + }, + { + "stream_index": 211, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.2, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_211.patch" + }, + { + "stream_index": 212, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.2, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_212.patch" + }, + { + "stream_index": 213, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.2, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_213.patch" + }, + { + "stream_index": 214, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.2, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_214.patch" + }, + { + "stream_index": 215, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.2, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_215.patch" + }, + { + "stream_index": 216, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.2, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_216.patch" + }, + { + "stream_index": 217, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.2, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_217.patch" + }, + { + "stream_index": 218, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.2, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_218.patch" + }, + { + "stream_index": 219, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.2, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_219.patch" + }, + { + "stream_index": 220, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.4, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_220.patch" + }, + { + "stream_index": 221, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.4, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_221.patch" + }, + { + "stream_index": 222, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.4, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_222.patch" + }, + { + "stream_index": 223, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.4, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_223.patch" + }, + { + "stream_index": 224, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.4, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_224.patch" + }, + { + "stream_index": 225, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.4, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_225.patch" + }, + { + "stream_index": 226, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.4, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_226.patch" + }, + { + "stream_index": 227, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.4, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_227.patch" + }, + { + "stream_index": 228, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.4, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_228.patch" + }, + { + "stream_index": 229, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.4, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_229.patch" + }, + { + "stream_index": 230, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.4, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_230.patch" + }, + { + "stream_index": 231, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.4, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_231.patch" + }, + { + "stream_index": 232, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.6, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_232.patch" + }, + { + "stream_index": 233, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.6, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_233.patch" + }, + { + "stream_index": 234, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.6, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_234.patch" + }, + { + "stream_index": 235, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.6, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_235.patch" + }, + { + "stream_index": 236, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.6, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_236.patch" + }, + { + "stream_index": 237, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.6, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_237.patch" + }, + { + "stream_index": 238, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.6, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_238.patch" + }, + { + "stream_index": 239, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.6, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_239.patch" + }, + { + "stream_index": 240, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.6, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_240.patch" + }, + { + "stream_index": 241, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.6, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_241.patch" + }, + { + "stream_index": 242, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.6, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_242.patch" + }, + { + "stream_index": 243, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.6, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_243.patch" + }, + { + "stream_index": 244, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.8, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_244.patch" + }, + { + "stream_index": 245, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.8, + "output_route_extension_um": 2, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_245.patch" + }, + { + "stream_index": 246, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.8, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_246.patch" + }, + { + "stream_index": 247, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.8, + "output_route_extension_um": 6, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_247.patch" + }, + { + "stream_index": 248, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.8, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_248.patch" + }, + { + "stream_index": 249, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.8, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_249.patch" + }, + { + "stream_index": 250, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.8, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_250.patch" + }, + { + "stream_index": 251, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.8, + "output_route_extension_um": 3, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_251.patch" + }, + { + "stream_index": 252, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.8, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 9 + }, + "initial64": false, + "patch": "layout_patches/layout_252.patch" + }, + { + "stream_index": 253, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.8, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 13 + }, + "initial64": false, + "patch": "layout_patches/layout_253.patch" + }, + { + "stream_index": 254, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.8, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 10 + }, + "initial64": false, + "patch": "layout_patches/layout_254.patch" + }, + { + "stream_index": 255, + "controls": { + "stage_gap_um": 14, + "output_route_width_um": 2.8, + "output_route_extension_um": 5, + "input_antenna_span_multiplier": 12 + }, + "initial64": false, + "patch": "layout_patches/layout_255.patch" + } + ], + "initial_designed_combinations": 64, + "maximum_geometry_attempts": 256, + "development_selection_disclosure": { + "observed_plan": "phase0_20261019T012056202713Z_e2_development_pilot", + "observed_terminal_attempts": 9, + "observed_status_counts": { + "COMPLETE_INFEASIBLE": 9 + }, + "observed_actual_stage_wall_seconds_sum": { + "generation": 1114.4706216482446, + "geometry": 6.9513076869770885, + "DRC": 18.245582858100533, + "LVS": 54.213228933513165, + "PEX": 21.626988356001675, + "electrical": 7559.7716880161315 + }, + "effect_on_proposal": "Preserve source control sites and development endpoint ranges; add declared interior levels before formal labels. No exclusion of known failing endpoint(s), no reruns chosen by prior success. Three symmetric sizing points chosen now; no nondefault-size postRC outcome observed.", + "application_selection": "FVF15pF chosen after10pF SS58.59 failed60deg; positive-control PMmin67.11 known. Legacy15pF is a one-time load hypothesis after.5pF lowPM; outcome pending. These are explicit development-informed application choices, not a blind posthoc comparison.", + "timeout_selection": "Old5T/compact incomplete90/120s transients stay unresolved; longer formal budgets, if adopted, must be calibrated and frozen before any formal candidate labels. Old outcomes never relabeled." + } + } + }, + "blocking_before_main_freeze": [ + "all12sizing references need application-specific admission;8nondefault sizing points have no physical qualification", + "64exact mask-distinct GDS perN not yet generated", + "explicit PDK mask exclusions not yet frozen", + "calibrated cross-fidelity predictions/promotion budgets not yet frozen", + "formal per-stageCPU and immutable isolated sampler executor not yet wired", + "legacy15pF single qualification still pending; no further load search allowed" + ] +} diff --git a/benchmarks/code_behind_layout/configs/development/e3_16k_8full_capacity.json b/benchmarks/code_behind_layout/configs/development/e3_16k_8full_capacity.json new file mode 100644 index 00000000..b2c7f18c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/e3_16k_8full_capacity.json @@ -0,0 +1,178 @@ +{ + "status": "DRAFT_E3_RUNNER", + "formal_dispatch": false, + "preparation": "runtime/task_preparation/e3_expanded_P_20261019T035505371049Z", + "task_ids": [ + "draft_E3_mirror_edit01", + "draft_E3_mirror_edit02", + "draft_E3_mirror_edit03", + "draft_E3_cascode_mirror_edit01", + "draft_E3_cascode_mirror_edit02", + "draft_E3_cascode_mirror_edit03", + "draft_E3_source_follower_edit01", + "draft_E3_source_follower_edit02", + "draft_E3_source_follower_edit03", + "draft_E3_stacked_switch_edit01", + "draft_E3_stacked_switch_edit02", + "draft_E3_stacked_switch_edit03", + "draft_E3_common_source_stage_edit01", + "draft_E3_common_source_stage_edit02", + "draft_E3_common_source_stage_edit03", + "draft_E3_resistive_diff_edit01", + "draft_E3_resistive_diff_edit02", + "draft_E3_resistive_diff_edit03", + "draft_E3_five_t_edit01", + "draft_E3_five_t_edit02", + "draft_E3_five_t_edit03", + "draft_E3_compact_miller_edit01", + "draft_E3_compact_miller_edit02", + "draft_E3_compact_miller_edit03" + ], + "methods": [ + "A", + "R", + "B", + "C" + ], + "trials": 5, + "selection_seeds": [ + 41, + 73, + 109, + 167, + 223 + ], + "model_config": "configs/models/gpt_e3_12k.draft.json", + "risk_model": "results/derived/e3_visible_risk_rule_status_predicate_v1.json", + "risk_weights": { + "failure_probability": 0, + "uncertainty": 1, + "changed_call_coverage": 0, + "low_margin": 1 + }, + "weight_status": "PREDECLARED_EQUAL_WEIGHT_TRANSPARENT_RULE_NOT_VALIDATION_TUNED", + "fidelity_policy": "F0_actual_full_each_selected_configuration", + "budget_status": "CAPACITY_CONTROL_ONLY_NOT_FORMAL", + "budget": { + "wall_seconds": 14400, + "decisions": 24, + "patches": 8, + "full_evaluations": 8, + "maximum_context_tokens": 16384, + "maximum_output_tokens": 1024 + }, + "parameter_baseline": { + "configuration_selector": "C", + "strategies": [ + "random", + "gpt_feedback" + ], + "interface": "prospective_expanded_layout_grid_v1" + }, + "freeze_blockers": [ + "24 actually qualified editing states and at least12 genuine natural or clean-poor shortfalls", + "Actual near-full12k H100 SFT/DPO/checkpoint restore and consistent serving", + "Complete source plus actual feedback history calibration and real gateway control", + "Prospectively frozen transparent-rule artifact and explicitly disclosed unavailable probabilistic variant", + "All24 exact initial parameter-render byte bindings", + "Immutable original-program baseline plan; actual hidden vectors after global sealing release", + "E3 own registry, implementation, analysis and dispatch freeze" + ], + "parameter_task_ids": [ + "draft_E3_mirror_edit02", + "draft_E3_cascode_mirror_edit02", + "draft_E3_source_follower_edit02", + "draft_E3_stacked_switch_edit02", + "draft_E3_common_source_stage_edit02", + "draft_E3_resistive_diff_edit02", + "draft_E3_five_t_edit02", + "draft_E3_compact_miller_edit02" + ], + "instance_task_ids": [ + "draft_E3_mirror_edit02", + "draft_E3_cascode_mirror_edit02", + "draft_E3_source_follower_edit02", + "draft_E3_stacked_switch_edit02", + "draft_E3_common_source_stage_edit02", + "draft_E3_resistive_diff_edit02", + "draft_E3_five_t_edit02", + "draft_E3_compact_miller_edit02" + ], + "instance_trials": 1, + "dispatch_order_seed": 20261019, + "e4_methods_manifest": "runtime/protocol_freezes/E4_primary/manifest.json", + "global_release_parts": [ + "gpt", + "parameter", + "local", + "signals", + "fidelity" + ], + "global_release_requires_fidelity_freeze": true, + "fidelity_manifest": "runtime/protocol_freezes/E3_F3_primary/manifest.json", + "e4_evaluation": { + "variants": [ + "T0", + "T1", + "T2", + "T3", + "T4" + ], + "matched_evaluation_seed_slots": [ + 41, + 73, + 109 + ], + "inference_trials": 3, + "T0_actual_model_count": 1, + "T0_independent_training_seeds": 0 + }, + "instance_baseline": { + "algorithm": "independent_arrivals_with_verified_library_exact_cache_v1", + "warm_start": "nearest_previous_verified_configuration_then_latest", + "cache": "exact_source_configuration_reference_PDK_deck_tools_fidelity", + "arrival_order": "configs/experiments/e3_instance_arrivals_draft.json", + "deployment_verification_maximum_physical_calls": 1, + "budget": { + "wall_seconds": 14400, + "decisions": 24, + "patches": 8, + "full_evaluations": 8, + "maximum_context_tokens": 16384, + "maximum_output_tokens": 1024 + }, + "budget_scope": "Same per-arrival search limits as one shared-code episode; every arrival, cache, verification and library cost is charged separately for cumulative cost comparison." + }, + "signal_task_ids": [ + "draft_E3_mirror_edit02", + "draft_E3_cascode_mirror_edit02", + "draft_E3_source_follower_edit02", + "draft_E3_stacked_switch_edit02", + "draft_E3_common_source_stage_edit02", + "draft_E3_resistive_diff_edit02", + "draft_E3_five_t_edit02", + "draft_E3_compact_miller_edit02" + ], + "selector_ablation_weights": { + "without_distance": { + "failure_probability": 0, + "uncertainty": 0, + "changed_call_coverage": 0, + "low_margin": 1 + }, + "without_margin": { + "failure_probability": 0, + "uncertainty": 1, + "changed_call_coverage": 0, + "low_margin": 0 + } + }, + "unavailable_signal_ablation": { + "changed_call_coverage": "No validated current impact map; weight0 in main, so a duplicate run would not identify an effect", + "failure_probability": "No qualified mixed-label family vectors; transparent-rule fallback has weight0" + }, + "fidelity_task_ids": [ + "draft_E3_five_t_edit02", + "draft_E3_compact_miller_edit02" + ] +} diff --git a/benchmarks/code_behind_layout/configs/development/gpt_teacher_collection_preparation.json b/benchmarks/code_behind_layout/configs/development/gpt_teacher_collection_preparation.json new file mode 100644 index 00000000..d004ba9e --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/gpt_teacher_collection_preparation.json @@ -0,0 +1,111 @@ +{ + "status": "DRAFT_NOT_FROZEN", + "role": "train_collection", + "collection_id": "c01_gpt_teacher_v1", + "base_collection_manifest": "/srv/code-behind-layout/runtime/train_collections/c01_collection_v2/collection.json", + "source_pack": "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1/source_pack", + "trusted_bundle": "/srv/code-behind-layout/runtime/train_collections/c01_collection_v1/trusted", + "registry_path": "/srv/code-behind-layout/runtime/train_collections/c01_collection_v2/registry.json", + "label_rule_path": "/srv/code-behind-layout/runtime/train_collections/c01_collection_v2/label_rule.json", + "initial_states_path": "/srv/code-behind-layout/runtime/collection_preparation/gpt_teacher_20261019T014518616458Z/initial_states.jsonl", + "initial_state_count": 3, + "editable_paths": [ + "textbook_sharing/layout.py" + ], + "gold_controls": { + "train_c01_anchor": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012544091046Z_6c219e3a" + }, + "train_c01_dev_nf1_l030": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012544092418Z_161ea9e6" + }, + "train_c01_dev_nf2_l060": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012544093787Z_6705eaed" + }, + "train_c01_dev_nf3_l045": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012544093569Z_aaa07f75" + }, + "train_c01_dev_nf6_l060": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012653089230Z_2548a079" + }, + "train_c01_dev_nf8_l090": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012653288313Z_be3e9898" + }, + "train_c01_dev_w075_l045": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012653860895Z_024176ee" + }, + "train_c01_dev_w100_l060": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012653893490Z_b05add66" + }, + "train_c01_dev_l120": { + "run_directory": "/srv/code-behind-layout/runs/train_collection/c01_collection_v1/physical/executor_20261019T012757942044Z_ed71443f" + } + }, + "sampling": { + "backend": "isolated_gpt_cli", + "mode": "train_collection_source_gpt", + "model": "gpt-6.1-sol", + "reasoning_effort": "high", + "trials": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8 + ], + "proposal_workers": 2, + "seed": null, + "seed_control_available": false, + "proposal_format": "full_source_teacher", + "max_new_tokens": 3072, + "max_context_tokens": 8192, + "timeout_seconds": 240 + }, + "physical": { + "workers": 2, + "cpus_per_job": 2, + "generation_timeout_seconds": 240, + "evaluator_timeout_seconds": 720 + }, + "budget": { + "proposals_per_initial_state": 8, + "configurations_per_candidate": 9, + "effective_example_pipeline_pilot_target": 1000, + "initial_batch_initial_states": 3 + }, + "deduplication": { + "method": "exact_ast_dump", + "include_attributes": false, + "numeric_normalization": false, + "preserve_literals_identifiers_docstrings": true, + "unparseable_source": "Exact text identity only; real executor and gold required for any negative", + "duplicate_attempt_status": "semantic_duplicate_before_physics", + "all_generation_costs_retained": true + }, + "transport": { + "remote_endpoint": "http://127.0.0.1:8115", + "local_listen": "127.0.0.1:8115", + "mechanism": "SSH reverse forwarding to local authenticated GPT CLI broker; credentials remain on original host", + "service_script": "scripts/corpus_gpt_teacher_service.py", + "command_source": "command() uses the same native-capability disable flags as the existing isolated policy adapter" + }, + "isolation": { + "fresh_ephemeral_session_per_trial": true, + "sandbox": "read-only", + "native_tools": false, + "web_search": false, + "apps_plugins_mcp_memory": false, + "project_instructions": false, + "working_directory": "opaque random UUID, never trial-index text", + "shared_prompt_within_state": "byte-identical source_proposal_prompt(request)" + }, + "costs": "Keep every exact CLI argv/request/events/stderr/proposal/exit/wall and available public usage; no provider checkpoint, seed, hidden reasoning or billable price is inferred", + "output_budget_scope": "Pinned Qwen tokenizer counts complete returned JSON + EOS; excess outputs are retained but not applied, with no truncation", + "source_program_counting": "Same three initial AST programs as Qwen v2, not three new lineages or independent source programs; report unique terminal ASTs and useful initial states separately from DPO pairs", + "old_development_outcomes_admitted": false, + "new_baseline9_per_state_and_new_teacher_proposals_required": true, + "formal_collection_launched": false +} diff --git a/benchmarks/code_behind_layout/configs/development/lineages.json b/benchmarks/code_behind_layout/configs/development/lineages.json new file mode 100644 index 00000000..25387dbe --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/lineages.json @@ -0,0 +1,72 @@ +{ + "status": "DEVELOPMENT_INVENTORY_NOT_FROZEN_SPLITS", + "source_commit": "7426852e238ee3bc656e3263212a51d4beb735dd", + "validated_independent_lineage_count": null, + "four_independent_OTAs_established": false, + "eight_validated_independent_lineages_established": false, + "complete_OTA_assemblies": [ + { + "id": "miller_two_stage", + "source": "src/glayout/cells/composite/opamp/opamp_twostage.py", + "same_ancestry_wrappers": [ + "src/glayout/cells/composite/opamp/opamp.py" + ], + "physical_status": "full_DRC_LVS_pass_full_RC_electrical_flow_active" + }, + { + "id": "fvf_super_class_ab", + "source": "src/glayout/cells/composite/fvf_based_ota/ota.py", + "circuit_specific_helpers": [ + "n_block.py", + "p_block.py", + "low_voltage_cmirror.py" + ], + "physical_status": "repaired_fixed_intended_LVS_and_full_DRC_positive_RC_complete_three_corner_OP_AC_transient_DC_development_only" + } + ], + "must_group_copies": [ + [ + "src/glayout/cells/composite/low_voltage_cmirror/low_voltage_cmirror.py", + "src/glayout/cells/composite/fvf_based_ota/low_voltage_cmirror.py" + ] + ], + "shared_elementary_libraries": [ + "current_mirror", + "diff_pair", + "flipped_voltage_follower", + "transmission_gate" + ], + "non_independence_rules": [ + "parameters_do_not_create_lineages", + "tracing_and_labels_do_not_create_lineages", + "same_source_checkout_copies_do_not_create_lineages", + "wrapper_around_same_complete_OTA_does_not_create_OTA_lineage", + "duplicate_low_voltage_mirror_files_are_one_ancestry" + ], + "needed_expansion": [ + "separately_implemented_folded_cascode_OTA", + "separately_implemented_telescopic_or_feedforward_OTA", + "actual_reference_bound_flows_for_component_families" + ], + "formal_or_training_use": false, + "scope": "Existing vendor ancestry plus separately authored research assembly candidates; no frozen split or formal qualification count", + "existing_vendor_complete_OTA_assembly_count": 2, + "additional_research_assembly_candidates": [ + "src/generators/five_t.py", + "src/generators/compact_miller.py" + ], + "additional_public_compiler_lineage": { + "revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "target": "glayout.sharing plus textbook_sharing.layout/assembly", + "declared_topologies": 18, + "independent_program_lineages": 1, + "source_role_candidate": "train_cropped_only" + }, + "component_domain_evidence": { + "mirror": "results/derived/mirror_domain_development.json", + "pair": "results/derived/pair_three_size_domain_development.json", + "transmission_gate": "results/derived/tg_three_size_domain_development.json", + "fvf_follower": "results/derived/follower_two_size_domain_development.json" + }, + "validation_candidate": "src/generators/validation_mirror.py; high-level assembly separate, disclosed general port access constraints shared" +} diff --git a/benchmarks/code_behind_layout/configs/development/mim_plate_variant.json b/benchmarks/code_behind_layout/configs/development/mim_plate_variant.json new file mode 100644 index 00000000..92476df9 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/mim_plate_variant.json @@ -0,0 +1,7 @@ +{ + "scope": "development_plate_assignment_hypothesis_not_formal", + "base_commit": "ac3cbc7745c495d8eef5013f1fda2eafa1b432f8", + "source_commit": "d22f39cbbf716302e7ef65c8723099fd215383f9", + "source_path": "/srv/code-behind-layout/vendor/glayout-mim-plate-development", + "reference_unchanged": true +} diff --git a/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/domain.json b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/domain.json new file mode 100644 index 00000000..c608d55f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/domain.json @@ -0,0 +1,1875 @@ +{ + "status": "DRAFT_NEW_TRAIN_SOURCE_NINE_POINT_IDEAL_QUALIFICATION", + "lineage_id": "research_train_ratio_current_source_array_v1", + "circuit_id": "TRAIN_RATIO_CS01", + "split": "train", + "configurations": [ + { + "configuration_id": "ratio_cs_k2_r1", + "domain_role": "development", + "parameters": { + "K": 2, + "R": 1, + "top_cell": "ratio_cs_k2_r1", + "sizing": { + "MREF": { + "w": 1.0, + "l": 0.6, + "nf": 2 + }, + "MOUT1": { + "w": 1.0, + "l": 0.6, + "nf": 2 + }, + "MOUT2": { + "w": 1.0, + "l": 0.6, + "nf": 2 + } + } + }, + "reference_file": "references/ratio_cs_k2_r1.spice", + "contract": { + "task_id": "train_ratio_current_source_array_v1", + "configuration_id": "ratio_cs_k2_r1", + "reference_id": "ratio_cs_k2_r1_independent_perfinger", + "status": "DRAFT_UNMEASURED_PRIOR_SPECIFICATION", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "ports": [ + "VSS", + "IREF", + "IOUT1", + "IOUT2" + ], + "nominal_operating_point": { + "reference_supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_clamps_V": [ + 0.9, + 0.9 + ], + "expected_output_currents_A": [ + 5e-06, + 5e-06 + ], + "DC_output_sweep_V": [ + 0, + 1.8, + 0.1 + ], + "AC_output_excitation_V": 1, + "transient_output_levels_V": [ + 0.875, + 0.925 + ], + "transient_period_s": 2e-06, + "other_output_during_single_port_analysis_V": 0.9 + }, + "specifications": [ + { + "name": "branch1_nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch1_sampled_compliance_max_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch1_output_resistance_ohm", + "unit": "ohm", + "min": 300000.0 + }, + { + "name": "branch2_nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch2_sampled_compliance_max_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch2_output_resistance_ohm", + "unit": "ohm", + "min": 300000.0 + }, + { + "name": "max_settled_relative_current_error_vs_DC", + "unit": "1", + "max": 0.001 + } + ], + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 5, + "expected_rows": 1 + }, + "dc1": { + "kind": "dc", + "columns": 6, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + }, + "ac1": { + "kind": "ac", + "columns": 5, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran1": { + "kind": "transient", + "columns": 7, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc2": { + "kind": "dc", + "columns": 6, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + }, + "ac2": { + "kind": "ac", + "columns": 5, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran2": { + "kind": "transient", + "columns": 7, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + }, + "sampled_compliance_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "output_resistance_difference_interval_V": [ + 0.8, + 1.0 + ], + "settling_definition": "Both branch currents during each single-output step are compared with that same port DC sweep, using linear interpolation between declared0.1V samples; error normalized by each branch target current.", + "power_definition": "DUT has noVDDpin. Report diode-input port work plus each output-clamp port work; report external1.8V/5uA reference-source work separately.", + "specification_rationale": "5% current transfer/regulation over the declared sampled application band; Iout*ro>=1.5V for either current ratio;0.1% settled current error relative to corresponding DC controls. Thresholds fixed before any ideal or physical measurement.", + "objective": { + "id": "ratio_cs_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "numerical_controls": { + "integration_method": "trap", + "reltol": 1e-06, + "abstol": 1e-14, + "vntol": 1e-08, + "chgtol": 1e-16 + }, + "scope": "DRAFT_NEW_TRAIN_LINEAGE_QUALIFICATION_NOT_FORMAL_DATA" + } + }, + { + "configuration_id": "ratio_cs_k2_r2", + "domain_role": "development", + "parameters": { + "K": 2, + "R": 2, + "top_cell": "ratio_cs_k2_r2", + "sizing": { + "MREF": { + "w": 1.0, + "l": 0.6, + "nf": 2 + }, + "MOUT1": { + "w": 1.0, + "l": 0.6, + "nf": 2 + }, + "MOUT2": { + "w": 2.0, + "l": 0.6, + "nf": 4 + } + } + }, + "reference_file": "references/ratio_cs_k2_r2.spice", + "contract": { + "task_id": "train_ratio_current_source_array_v1", + "configuration_id": "ratio_cs_k2_r2", + "reference_id": "ratio_cs_k2_r2_independent_perfinger", + "status": "DRAFT_UNMEASURED_PRIOR_SPECIFICATION", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "ports": [ + "VSS", + "IREF", + "IOUT1", + "IOUT2" + ], + "nominal_operating_point": { + "reference_supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_clamps_V": [ + 0.9, + 0.9 + ], + "expected_output_currents_A": [ + 5e-06, + 1e-05 + ], + "DC_output_sweep_V": [ + 0, + 1.8, + 0.1 + ], + "AC_output_excitation_V": 1, + "transient_output_levels_V": [ + 0.875, + 0.925 + ], + "transient_period_s": 2e-06, + "other_output_during_single_port_analysis_V": 0.9 + }, + "specifications": [ + { + "name": "branch1_nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch1_sampled_compliance_max_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch1_output_resistance_ohm", + "unit": "ohm", + "min": 300000.0 + }, + { + "name": "branch2_nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch2_sampled_compliance_max_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch2_output_resistance_ohm", + "unit": "ohm", + "min": 150000.0 + }, + { + "name": "max_settled_relative_current_error_vs_DC", + "unit": "1", + "max": 0.001 + } + ], + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 5, + "expected_rows": 1 + }, + "dc1": { + "kind": "dc", + "columns": 6, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + }, + "ac1": { + "kind": "ac", + "columns": 5, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran1": { + "kind": "transient", + "columns": 7, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc2": { + "kind": "dc", + "columns": 6, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + }, + "ac2": { + "kind": "ac", + "columns": 5, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran2": { + "kind": "transient", + "columns": 7, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + }, + "sampled_compliance_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "output_resistance_difference_interval_V": [ + 0.8, + 1.0 + ], + "settling_definition": "Both branch currents during each single-output step are compared with that same port DC sweep, using linear interpolation between declared0.1V samples; error normalized by each branch target current.", + "power_definition": "DUT has noVDDpin. Report diode-input port work plus each output-clamp port work; report external1.8V/5uA reference-source work separately.", + "specification_rationale": "5% current transfer/regulation over the declared sampled application band; Iout*ro>=1.5V for either current ratio;0.1% settled current error relative to corresponding DC controls. Thresholds fixed before any ideal or physical measurement.", + "objective": { + "id": "ratio_cs_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "numerical_controls": { + "integration_method": "trap", + "reltol": 1e-06, + "abstol": 1e-14, + "vntol": 1e-08, + "chgtol": 1e-16 + }, + "scope": "DRAFT_NEW_TRAIN_LINEAGE_QUALIFICATION_NOT_FORMAL_DATA" + } + }, + { + "configuration_id": "ratio_cs_k2_r4", + "domain_role": "development", + "parameters": { + "K": 2, + "R": 4, + "top_cell": "ratio_cs_k2_r4", + "sizing": { + "MREF": { + "w": 1.0, + "l": 0.6, + "nf": 2 + }, + "MOUT1": { + "w": 1.0, + "l": 0.6, + "nf": 2 + }, + "MOUT2": { + "w": 4.0, + "l": 0.6, + "nf": 8 + } + } + }, + "reference_file": "references/ratio_cs_k2_r4.spice", + "contract": { + "task_id": "train_ratio_current_source_array_v1", + "configuration_id": "ratio_cs_k2_r4", + "reference_id": "ratio_cs_k2_r4_independent_perfinger", + "status": "DRAFT_UNMEASURED_PRIOR_SPECIFICATION", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "ports": [ + "VSS", + "IREF", + "IOUT1", + "IOUT2" + ], + "nominal_operating_point": { + "reference_supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_clamps_V": [ + 0.9, + 0.9 + ], + "expected_output_currents_A": [ + 5e-06, + 2e-05 + ], + "DC_output_sweep_V": [ + 0, + 1.8, + 0.1 + ], + "AC_output_excitation_V": 1, + "transient_output_levels_V": [ + 0.875, + 0.925 + ], + "transient_period_s": 2e-06, + "other_output_during_single_port_analysis_V": 0.9 + }, + "specifications": [ + { + "name": "branch1_nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch1_sampled_compliance_max_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch1_output_resistance_ohm", + "unit": "ohm", + "min": 300000.0 + }, + { + "name": "branch2_nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch2_sampled_compliance_max_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch2_output_resistance_ohm", + "unit": "ohm", + "min": 75000.0 + }, + { + "name": "max_settled_relative_current_error_vs_DC", + "unit": "1", + "max": 0.001 + } + ], + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 5, + "expected_rows": 1 + }, + "dc1": { + "kind": "dc", + "columns": 6, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + }, + "ac1": { + "kind": "ac", + "columns": 5, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran1": { + "kind": "transient", + "columns": 7, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc2": { + "kind": "dc", + "columns": 6, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + }, + "ac2": { + "kind": "ac", + "columns": 5, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran2": { + "kind": "transient", + "columns": 7, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + }, + "sampled_compliance_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "output_resistance_difference_interval_V": [ + 0.8, + 1.0 + ], + "settling_definition": "Both branch currents during each single-output step are compared with that same port DC sweep, using linear interpolation between declared0.1V samples; error normalized by each branch target current.", + "power_definition": "DUT has noVDDpin. Report diode-input port work plus each output-clamp port work; report external1.8V/5uA reference-source work separately.", + "specification_rationale": "5% current transfer/regulation over the declared sampled application band; Iout*ro>=1.5V for either current ratio;0.1% settled current error relative to corresponding DC controls. Thresholds fixed before any ideal or physical measurement.", + "objective": { + "id": "ratio_cs_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "numerical_controls": { + "integration_method": "trap", + "reltol": 1e-06, + "abstol": 1e-14, + "vntol": 1e-08, + "chgtol": 1e-16 + }, + "scope": "DRAFT_NEW_TRAIN_LINEAGE_QUALIFICATION_NOT_FORMAL_DATA" + } + }, + { + "configuration_id": "ratio_cs_k4_r1", + "domain_role": "development", + "parameters": { + "K": 4, + "R": 1, + "top_cell": "ratio_cs_k4_r1", + "sizing": { + "MREF": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "MOUT1": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "MOUT2": { + "w": 2.0, + "l": 0.6, + "nf": 4 + } + } + }, + "reference_file": "references/ratio_cs_k4_r1.spice", + "contract": { + "task_id": "train_ratio_current_source_array_v1", + "configuration_id": "ratio_cs_k4_r1", + "reference_id": "ratio_cs_k4_r1_independent_perfinger", + "status": "DRAFT_UNMEASURED_PRIOR_SPECIFICATION", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "ports": [ + "VSS", + "IREF", + "IOUT1", + "IOUT2" + ], + "nominal_operating_point": { + "reference_supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_clamps_V": [ + 0.9, + 0.9 + ], + "expected_output_currents_A": [ + 5e-06, + 5e-06 + ], + "DC_output_sweep_V": [ + 0, + 1.8, + 0.1 + ], + "AC_output_excitation_V": 1, + "transient_output_levels_V": [ + 0.875, + 0.925 + ], + "transient_period_s": 2e-06, + "other_output_during_single_port_analysis_V": 0.9 + }, + "specifications": [ + { + "name": "branch1_nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch1_sampled_compliance_max_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch1_output_resistance_ohm", + "unit": "ohm", + "min": 300000.0 + }, + { + "name": "branch2_nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch2_sampled_compliance_max_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch2_output_resistance_ohm", + "unit": "ohm", + "min": 300000.0 + }, + { + "name": "max_settled_relative_current_error_vs_DC", + "unit": "1", + "max": 0.001 + } + ], + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 5, + "expected_rows": 1 + }, + "dc1": { + "kind": "dc", + "columns": 6, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + }, + "ac1": { + "kind": "ac", + "columns": 5, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran1": { + "kind": "transient", + "columns": 7, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc2": { + "kind": "dc", + "columns": 6, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + }, + "ac2": { + "kind": "ac", + "columns": 5, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran2": { + "kind": "transient", + "columns": 7, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + }, + "sampled_compliance_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "output_resistance_difference_interval_V": [ + 0.8, + 1.0 + ], + "settling_definition": "Both branch currents during each single-output step are compared with that same port DC sweep, using linear interpolation between declared0.1V samples; error normalized by each branch target current.", + "power_definition": "DUT has noVDDpin. Report diode-input port work plus each output-clamp port work; report external1.8V/5uA reference-source work separately.", + "specification_rationale": "5% current transfer/regulation over the declared sampled application band; Iout*ro>=1.5V for either current ratio;0.1% settled current error relative to corresponding DC controls. Thresholds fixed before any ideal or physical measurement.", + "objective": { + "id": "ratio_cs_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "numerical_controls": { + "integration_method": "trap", + "reltol": 1e-06, + "abstol": 1e-14, + "vntol": 1e-08, + "chgtol": 1e-16 + }, + "scope": "DRAFT_NEW_TRAIN_LINEAGE_QUALIFICATION_NOT_FORMAL_DATA" + } + }, + { + "configuration_id": "ratio_cs_k4_r2", + "domain_role": "anchor", + "parameters": { + "K": 4, + "R": 2, + "top_cell": "ratio_cs_k4_r2", + "sizing": { + "MREF": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "MOUT1": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "MOUT2": { + "w": 4.0, + "l": 0.6, + "nf": 8 + } + } + }, + "reference_file": "references/ratio_cs_k4_r2.spice", + "contract": { + "task_id": "train_ratio_current_source_array_v1", + "configuration_id": "ratio_cs_k4_r2", + "reference_id": "ratio_cs_k4_r2_independent_perfinger", + "status": "DRAFT_UNMEASURED_PRIOR_SPECIFICATION", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "ports": [ + "VSS", + "IREF", + "IOUT1", + "IOUT2" + ], + "nominal_operating_point": { + "reference_supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_clamps_V": [ + 0.9, + 0.9 + ], + "expected_output_currents_A": [ + 5e-06, + 1e-05 + ], + "DC_output_sweep_V": [ + 0, + 1.8, + 0.1 + ], + "AC_output_excitation_V": 1, + "transient_output_levels_V": [ + 0.875, + 0.925 + ], + "transient_period_s": 2e-06, + "other_output_during_single_port_analysis_V": 0.9 + }, + "specifications": [ + { + "name": "branch1_nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch1_sampled_compliance_max_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch1_output_resistance_ohm", + "unit": "ohm", + "min": 300000.0 + }, + { + "name": "branch2_nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch2_sampled_compliance_max_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch2_output_resistance_ohm", + "unit": "ohm", + "min": 150000.0 + }, + { + "name": "max_settled_relative_current_error_vs_DC", + "unit": "1", + "max": 0.001 + } + ], + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 5, + "expected_rows": 1 + }, + "dc1": { + "kind": "dc", + "columns": 6, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + }, + "ac1": { + "kind": "ac", + "columns": 5, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran1": { + "kind": "transient", + "columns": 7, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc2": { + "kind": "dc", + "columns": 6, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + }, + "ac2": { + "kind": "ac", + "columns": 5, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran2": { + "kind": "transient", + "columns": 7, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + }, + "sampled_compliance_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "output_resistance_difference_interval_V": [ + 0.8, + 1.0 + ], + "settling_definition": "Both branch currents during each single-output step are compared with that same port DC sweep, using linear interpolation between declared0.1V samples; error normalized by each branch target current.", + "power_definition": "DUT has noVDDpin. Report diode-input port work plus each output-clamp port work; report external1.8V/5uA reference-source work separately.", + "specification_rationale": "5% current transfer/regulation over the declared sampled application band; Iout*ro>=1.5V for either current ratio;0.1% settled current error relative to corresponding DC controls. Thresholds fixed before any ideal or physical measurement.", + "objective": { + "id": "ratio_cs_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "numerical_controls": { + "integration_method": "trap", + "reltol": 1e-06, + "abstol": 1e-14, + "vntol": 1e-08, + "chgtol": 1e-16 + }, + "scope": "DRAFT_NEW_TRAIN_LINEAGE_QUALIFICATION_NOT_FORMAL_DATA" + } + }, + { + "configuration_id": "ratio_cs_k4_r4", + "domain_role": "development", + "parameters": { + "K": 4, + "R": 4, + "top_cell": "ratio_cs_k4_r4", + "sizing": { + "MREF": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "MOUT1": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "MOUT2": { + "w": 8.0, + "l": 0.6, + "nf": 16 + } + } + }, + "reference_file": "references/ratio_cs_k4_r4.spice", + "contract": { + "task_id": "train_ratio_current_source_array_v1", + "configuration_id": "ratio_cs_k4_r4", + "reference_id": "ratio_cs_k4_r4_independent_perfinger", + "status": "DRAFT_UNMEASURED_PRIOR_SPECIFICATION", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "ports": [ + "VSS", + "IREF", + "IOUT1", + "IOUT2" + ], + "nominal_operating_point": { + "reference_supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_clamps_V": [ + 0.9, + 0.9 + ], + "expected_output_currents_A": [ + 5e-06, + 2e-05 + ], + "DC_output_sweep_V": [ + 0, + 1.8, + 0.1 + ], + "AC_output_excitation_V": 1, + "transient_output_levels_V": [ + 0.875, + 0.925 + ], + "transient_period_s": 2e-06, + "other_output_during_single_port_analysis_V": 0.9 + }, + "specifications": [ + { + "name": "branch1_nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch1_sampled_compliance_max_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch1_output_resistance_ohm", + "unit": "ohm", + "min": 300000.0 + }, + { + "name": "branch2_nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch2_sampled_compliance_max_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch2_output_resistance_ohm", + "unit": "ohm", + "min": 75000.0 + }, + { + "name": "max_settled_relative_current_error_vs_DC", + "unit": "1", + "max": 0.001 + } + ], + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 5, + "expected_rows": 1 + }, + "dc1": { + "kind": "dc", + "columns": 6, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + }, + "ac1": { + "kind": "ac", + "columns": 5, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran1": { + "kind": "transient", + "columns": 7, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc2": { + "kind": "dc", + "columns": 6, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + }, + "ac2": { + "kind": "ac", + "columns": 5, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran2": { + "kind": "transient", + "columns": 7, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + }, + "sampled_compliance_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "output_resistance_difference_interval_V": [ + 0.8, + 1.0 + ], + "settling_definition": "Both branch currents during each single-output step are compared with that same port DC sweep, using linear interpolation between declared0.1V samples; error normalized by each branch target current.", + "power_definition": "DUT has noVDDpin. Report diode-input port work plus each output-clamp port work; report external1.8V/5uA reference-source work separately.", + "specification_rationale": "5% current transfer/regulation over the declared sampled application band; Iout*ro>=1.5V for either current ratio;0.1% settled current error relative to corresponding DC controls. Thresholds fixed before any ideal or physical measurement.", + "objective": { + "id": "ratio_cs_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "numerical_controls": { + "integration_method": "trap", + "reltol": 1e-06, + "abstol": 1e-14, + "vntol": 1e-08, + "chgtol": 1e-16 + }, + "scope": "DRAFT_NEW_TRAIN_LINEAGE_QUALIFICATION_NOT_FORMAL_DATA" + } + }, + { + "configuration_id": "ratio_cs_k8_r1", + "domain_role": "development", + "parameters": { + "K": 8, + "R": 1, + "top_cell": "ratio_cs_k8_r1", + "sizing": { + "MREF": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "MOUT1": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "MOUT2": { + "w": 4.0, + "l": 0.6, + "nf": 8 + } + } + }, + "reference_file": "references/ratio_cs_k8_r1.spice", + "contract": { + "task_id": "train_ratio_current_source_array_v1", + "configuration_id": "ratio_cs_k8_r1", + "reference_id": "ratio_cs_k8_r1_independent_perfinger", + "status": "DRAFT_UNMEASURED_PRIOR_SPECIFICATION", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "ports": [ + "VSS", + "IREF", + "IOUT1", + "IOUT2" + ], + "nominal_operating_point": { + "reference_supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_clamps_V": [ + 0.9, + 0.9 + ], + "expected_output_currents_A": [ + 5e-06, + 5e-06 + ], + "DC_output_sweep_V": [ + 0, + 1.8, + 0.1 + ], + "AC_output_excitation_V": 1, + "transient_output_levels_V": [ + 0.875, + 0.925 + ], + "transient_period_s": 2e-06, + "other_output_during_single_port_analysis_V": 0.9 + }, + "specifications": [ + { + "name": "branch1_nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch1_sampled_compliance_max_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch1_output_resistance_ohm", + "unit": "ohm", + "min": 300000.0 + }, + { + "name": "branch2_nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch2_sampled_compliance_max_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch2_output_resistance_ohm", + "unit": "ohm", + "min": 300000.0 + }, + { + "name": "max_settled_relative_current_error_vs_DC", + "unit": "1", + "max": 0.001 + } + ], + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 5, + "expected_rows": 1 + }, + "dc1": { + "kind": "dc", + "columns": 6, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + }, + "ac1": { + "kind": "ac", + "columns": 5, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran1": { + "kind": "transient", + "columns": 7, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc2": { + "kind": "dc", + "columns": 6, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + }, + "ac2": { + "kind": "ac", + "columns": 5, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran2": { + "kind": "transient", + "columns": 7, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + }, + "sampled_compliance_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "output_resistance_difference_interval_V": [ + 0.8, + 1.0 + ], + "settling_definition": "Both branch currents during each single-output step are compared with that same port DC sweep, using linear interpolation between declared0.1V samples; error normalized by each branch target current.", + "power_definition": "DUT has noVDDpin. Report diode-input port work plus each output-clamp port work; report external1.8V/5uA reference-source work separately.", + "specification_rationale": "5% current transfer/regulation over the declared sampled application band; Iout*ro>=1.5V for either current ratio;0.1% settled current error relative to corresponding DC controls. Thresholds fixed before any ideal or physical measurement.", + "objective": { + "id": "ratio_cs_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "numerical_controls": { + "integration_method": "trap", + "reltol": 1e-06, + "abstol": 1e-14, + "vntol": 1e-08, + "chgtol": 1e-16 + }, + "scope": "DRAFT_NEW_TRAIN_LINEAGE_QUALIFICATION_NOT_FORMAL_DATA" + } + }, + { + "configuration_id": "ratio_cs_k8_r2", + "domain_role": "development", + "parameters": { + "K": 8, + "R": 2, + "top_cell": "ratio_cs_k8_r2", + "sizing": { + "MREF": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "MOUT1": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "MOUT2": { + "w": 8.0, + "l": 0.6, + "nf": 16 + } + } + }, + "reference_file": "references/ratio_cs_k8_r2.spice", + "contract": { + "task_id": "train_ratio_current_source_array_v1", + "configuration_id": "ratio_cs_k8_r2", + "reference_id": "ratio_cs_k8_r2_independent_perfinger", + "status": "DRAFT_UNMEASURED_PRIOR_SPECIFICATION", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "ports": [ + "VSS", + "IREF", + "IOUT1", + "IOUT2" + ], + "nominal_operating_point": { + "reference_supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_clamps_V": [ + 0.9, + 0.9 + ], + "expected_output_currents_A": [ + 5e-06, + 1e-05 + ], + "DC_output_sweep_V": [ + 0, + 1.8, + 0.1 + ], + "AC_output_excitation_V": 1, + "transient_output_levels_V": [ + 0.875, + 0.925 + ], + "transient_period_s": 2e-06, + "other_output_during_single_port_analysis_V": 0.9 + }, + "specifications": [ + { + "name": "branch1_nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch1_sampled_compliance_max_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch1_output_resistance_ohm", + "unit": "ohm", + "min": 300000.0 + }, + { + "name": "branch2_nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch2_sampled_compliance_max_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch2_output_resistance_ohm", + "unit": "ohm", + "min": 150000.0 + }, + { + "name": "max_settled_relative_current_error_vs_DC", + "unit": "1", + "max": 0.001 + } + ], + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 5, + "expected_rows": 1 + }, + "dc1": { + "kind": "dc", + "columns": 6, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + }, + "ac1": { + "kind": "ac", + "columns": 5, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran1": { + "kind": "transient", + "columns": 7, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc2": { + "kind": "dc", + "columns": 6, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + }, + "ac2": { + "kind": "ac", + "columns": 5, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran2": { + "kind": "transient", + "columns": 7, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + }, + "sampled_compliance_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "output_resistance_difference_interval_V": [ + 0.8, + 1.0 + ], + "settling_definition": "Both branch currents during each single-output step are compared with that same port DC sweep, using linear interpolation between declared0.1V samples; error normalized by each branch target current.", + "power_definition": "DUT has noVDDpin. Report diode-input port work plus each output-clamp port work; report external1.8V/5uA reference-source work separately.", + "specification_rationale": "5% current transfer/regulation over the declared sampled application band; Iout*ro>=1.5V for either current ratio;0.1% settled current error relative to corresponding DC controls. Thresholds fixed before any ideal or physical measurement.", + "objective": { + "id": "ratio_cs_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "numerical_controls": { + "integration_method": "trap", + "reltol": 1e-06, + "abstol": 1e-14, + "vntol": 1e-08, + "chgtol": 1e-16 + }, + "scope": "DRAFT_NEW_TRAIN_LINEAGE_QUALIFICATION_NOT_FORMAL_DATA" + } + }, + { + "configuration_id": "ratio_cs_k8_r4", + "domain_role": "development", + "parameters": { + "K": 8, + "R": 4, + "top_cell": "ratio_cs_k8_r4", + "sizing": { + "MREF": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "MOUT1": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "MOUT2": { + "w": 16.0, + "l": 0.6, + "nf": 32 + } + } + }, + "reference_file": "references/ratio_cs_k8_r4.spice", + "contract": { + "task_id": "train_ratio_current_source_array_v1", + "configuration_id": "ratio_cs_k8_r4", + "reference_id": "ratio_cs_k8_r4_independent_perfinger", + "status": "DRAFT_UNMEASURED_PRIOR_SPECIFICATION", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "ports": [ + "VSS", + "IREF", + "IOUT1", + "IOUT2" + ], + "nominal_operating_point": { + "reference_supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_clamps_V": [ + 0.9, + 0.9 + ], + "expected_output_currents_A": [ + 5e-06, + 2e-05 + ], + "DC_output_sweep_V": [ + 0, + 1.8, + 0.1 + ], + "AC_output_excitation_V": 1, + "transient_output_levels_V": [ + 0.875, + 0.925 + ], + "transient_period_s": 2e-06, + "other_output_during_single_port_analysis_V": 0.9 + }, + "specifications": [ + { + "name": "branch1_nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch1_sampled_compliance_max_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch1_output_resistance_ohm", + "unit": "ohm", + "min": 300000.0 + }, + { + "name": "branch2_nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch2_sampled_compliance_max_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "branch2_output_resistance_ohm", + "unit": "ohm", + "min": 75000.0 + }, + { + "name": "max_settled_relative_current_error_vs_DC", + "unit": "1", + "max": 0.001 + } + ], + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 5, + "expected_rows": 1 + }, + "dc1": { + "kind": "dc", + "columns": 6, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + }, + "ac1": { + "kind": "ac", + "columns": 5, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran1": { + "kind": "transient", + "columns": 7, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc2": { + "kind": "dc", + "columns": 6, + "start": 0, + "end": 1.8, + "points": 19, + "scale": "linear" + }, + "ac2": { + "kind": "ac", + "columns": 5, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran2": { + "kind": "transient", + "columns": 7, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + }, + "sampled_compliance_grid_V": [ + 0.7, + 0.8, + 0.9, + 1.0 + ], + "output_resistance_difference_interval_V": [ + 0.8, + 1.0 + ], + "settling_definition": "Both branch currents during each single-output step are compared with that same port DC sweep, using linear interpolation between declared0.1V samples; error normalized by each branch target current.", + "power_definition": "DUT has noVDDpin. Report diode-input port work plus each output-clamp port work; report external1.8V/5uA reference-source work separately.", + "specification_rationale": "5% current transfer/regulation over the declared sampled application band; Iout*ro>=1.5V for either current ratio;0.1% settled current error relative to corresponding DC controls. Thresholds fixed before any ideal or physical measurement.", + "objective": { + "id": "ratio_cs_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "numerical_controls": { + "integration_method": "trap", + "reltol": 1e-06, + "abstol": 1e-14, + "vntol": 1e-08, + "chgtol": 1e-16 + }, + "scope": "DRAFT_NEW_TRAIN_LINEAGE_QUALIFICATION_NOT_FORMAL_DATA" + } + } + ], + "whole_grid_definition": { + "K": [ + 2, + 4, + 8 + ], + "R": [ + 1, + 2, + 4 + ], + "points": 9, + "no_post_result_filtering": true + }, + "reference_binding": "Each readonly literal per-finger N is independently generated from its own declared K/R/sizing and fixed transistor graph; layout source cannot redefine it.", + "counts": { + "ideal_qualified_points": 0, + "physical_qualified_points": 0, + "model_calls": 0, + "formal_training_examples": 0, + "qualified_independent_source_lineages_added": 0 + } +} diff --git a/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/lineage_declaration.json b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/lineage_declaration.json new file mode 100644 index 00000000..52c95cdd --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/lineage_declaration.json @@ -0,0 +1,56 @@ +{ + "status": "DRAFT_TRAIN_ONLY_ASSIGNMENT_PENDING_INDEPENDENT_QUALIFICATION", + "lineage_id": "research_train_ratio_current_source_array_v1", + "split": "train", + "circuit_id": "TRAIN_RATIO_CS01", + "topology_families": [ + "diode_biased_two_output_ratio_current_source_array" + ], + "parent_lineages": [], + "qualified_independent_source_lineages_added": 0, + "editable_source_files": [ + "src/train_generators/ratio_source.py" + ], + "source_package_files": [ + "src/__init__.py", + "src/train_generators/__init__.py", + "src/train_generators/ratio_source.py" + ], + "trusted_reference_and_bench_files": [ + "src/train_generators/ratio_source_intent.py", + "src/train_generators/ratio_source_bench.py" + ], + "shared_frozen_dependencies": [ + "gdsfactory7.7 geometry/component API", + "glayout.primitives.fet.nmos", + "glayout.primitives.via_gen.via_stack", + "glayout.sky130 mappedPDK", + "src/generators/terminal_access.py" + ], + "shared_access_disclosure": "Only terminal escape, rectangle/wire/via/pin/flatten helpers reused. That library has no circuit graph, placement or net route policy. Source/body/gate/output placement and H bias tree are newly authored here.", + "excluded_dependencies": [ + "all evaluation/validation circuit assemblies", + "glayout.cells", + "glayout.blocks", + "glayout.sharing compiler", + "textbook_sharing" + ], + "authorship": "New high-level assembly written for this train-only proposal, without reading or calling any evaluation assembly for this task. Shared common terminal-access source was read and is disclosed.", + "holdout_statement": "No Miller or FVF OTA graph/helper/data. A current-source graph is not a new topology holdout; source independence still needs actual import/ancestry/geometry qualification.", + "global_registry_modified": false, + "frozen_source_assignments_modified": false, + "required_before_formal_collection": [ + "Nine-point ideal qualification with full failures retained", + "Actual anchor and full nine-point full-ruleDRC/independentN LVS/deviceintent/positivefullRC/postlayoutcorner qualification", + "Prospective global source-assignment extension preserving every prior train/validation/test source assignment", + "New frozen source/trusted evaluator/contracts/labels/initialstates/context preflight before fresh model proposals" + ], + "formal_training_examples": 0, + "model_calls": 0, + "physical_runs": 0, + "frozen_common_source_files": [ + "src/generators/__init__.py", + "src/generators/terminal_access.py" + ], + "source_cli": "python src/train_generators/ratio_source.py --configuration parameters.json --output candidate.gds; configuration is the declared point.parameters object." +} diff --git a/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k2_r1.json b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k2_r1.json new file mode 100644 index 00000000..96330f73 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k2_r1.json @@ -0,0 +1,22 @@ +{ + "K": 2, + "R": 1, + "top_cell": "ratio_cs_k2_r1", + "sizing": { + "MREF": { + "w": 1.0, + "l": 0.6, + "nf": 2 + }, + "MOUT1": { + "w": 1.0, + "l": 0.6, + "nf": 2 + }, + "MOUT2": { + "w": 1.0, + "l": 0.6, + "nf": 2 + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k2_r2.json b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k2_r2.json new file mode 100644 index 00000000..a2ecdcc2 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k2_r2.json @@ -0,0 +1,22 @@ +{ + "K": 2, + "R": 2, + "top_cell": "ratio_cs_k2_r2", + "sizing": { + "MREF": { + "w": 1.0, + "l": 0.6, + "nf": 2 + }, + "MOUT1": { + "w": 1.0, + "l": 0.6, + "nf": 2 + }, + "MOUT2": { + "w": 2.0, + "l": 0.6, + "nf": 4 + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k2_r4.json b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k2_r4.json new file mode 100644 index 00000000..44eb74ac --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k2_r4.json @@ -0,0 +1,22 @@ +{ + "K": 2, + "R": 4, + "top_cell": "ratio_cs_k2_r4", + "sizing": { + "MREF": { + "w": 1.0, + "l": 0.6, + "nf": 2 + }, + "MOUT1": { + "w": 1.0, + "l": 0.6, + "nf": 2 + }, + "MOUT2": { + "w": 4.0, + "l": 0.6, + "nf": 8 + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k4_r1.json b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k4_r1.json new file mode 100644 index 00000000..a8f14a6f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k4_r1.json @@ -0,0 +1,22 @@ +{ + "K": 4, + "R": 1, + "top_cell": "ratio_cs_k4_r1", + "sizing": { + "MREF": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "MOUT1": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "MOUT2": { + "w": 2.0, + "l": 0.6, + "nf": 4 + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k4_r2.json b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k4_r2.json new file mode 100644 index 00000000..696833dd --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k4_r2.json @@ -0,0 +1,22 @@ +{ + "K": 4, + "R": 2, + "top_cell": "ratio_cs_k4_r2", + "sizing": { + "MREF": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "MOUT1": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "MOUT2": { + "w": 4.0, + "l": 0.6, + "nf": 8 + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k4_r4.json b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k4_r4.json new file mode 100644 index 00000000..99b567d1 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k4_r4.json @@ -0,0 +1,22 @@ +{ + "K": 4, + "R": 4, + "top_cell": "ratio_cs_k4_r4", + "sizing": { + "MREF": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "MOUT1": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "MOUT2": { + "w": 8.0, + "l": 0.6, + "nf": 16 + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k8_r1.json b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k8_r1.json new file mode 100644 index 00000000..b95d5c33 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k8_r1.json @@ -0,0 +1,22 @@ +{ + "K": 8, + "R": 1, + "top_cell": "ratio_cs_k8_r1", + "sizing": { + "MREF": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "MOUT1": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "MOUT2": { + "w": 4.0, + "l": 0.6, + "nf": 8 + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k8_r2.json b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k8_r2.json new file mode 100644 index 00000000..66897570 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k8_r2.json @@ -0,0 +1,22 @@ +{ + "K": 8, + "R": 2, + "top_cell": "ratio_cs_k8_r2", + "sizing": { + "MREF": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "MOUT1": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "MOUT2": { + "w": 8.0, + "l": 0.6, + "nf": 16 + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k8_r4.json b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k8_r4.json new file mode 100644 index 00000000..12bf47b5 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/parameters/ratio_cs_k8_r4.json @@ -0,0 +1,22 @@ +{ + "K": 8, + "R": 4, + "top_cell": "ratio_cs_k8_r4", + "sizing": { + "MREF": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "MOUT1": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "MOUT2": { + "w": 16.0, + "l": 0.6, + "nf": 32 + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k2_r1.spice b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k2_r1.spice new file mode 100644 index 00000000..50a506c2 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k2_r1.spice @@ -0,0 +1,8 @@ +.subckt ratio_cs_k2_r1 VSS IREF IOUT1 IOUT2 +XMREF_f0 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f1 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f0 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f1 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f0 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f1 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends ratio_cs_k2_r1 diff --git a/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k2_r2.spice b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k2_r2.spice new file mode 100644 index 00000000..cc4d2076 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k2_r2.spice @@ -0,0 +1,10 @@ +.subckt ratio_cs_k2_r2 VSS IREF IOUT1 IOUT2 +XMREF_f0 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f1 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f0 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f1 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f0 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f1 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f2 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f3 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends ratio_cs_k2_r2 diff --git a/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k2_r4.spice b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k2_r4.spice new file mode 100644 index 00000000..34de5665 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k2_r4.spice @@ -0,0 +1,14 @@ +.subckt ratio_cs_k2_r4 VSS IREF IOUT1 IOUT2 +XMREF_f0 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f1 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f0 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f1 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f0 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f1 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f2 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f3 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f4 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f5 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f6 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f7 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends ratio_cs_k2_r4 diff --git a/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k4_r1.spice b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k4_r1.spice new file mode 100644 index 00000000..3b9072ff --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k4_r1.spice @@ -0,0 +1,14 @@ +.subckt ratio_cs_k4_r1 VSS IREF IOUT1 IOUT2 +XMREF_f0 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f1 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f2 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f3 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f0 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f1 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f2 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f3 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f0 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f1 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f2 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f3 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends ratio_cs_k4_r1 diff --git a/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k4_r2.spice b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k4_r2.spice new file mode 100644 index 00000000..be69026c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k4_r2.spice @@ -0,0 +1,18 @@ +.subckt ratio_cs_k4_r2 VSS IREF IOUT1 IOUT2 +XMREF_f0 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f1 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f2 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f3 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f0 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f1 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f2 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f3 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f0 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f1 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f2 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f3 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f4 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f5 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f6 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f7 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends ratio_cs_k4_r2 diff --git a/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k4_r4.spice b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k4_r4.spice new file mode 100644 index 00000000..bda15ff5 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k4_r4.spice @@ -0,0 +1,26 @@ +.subckt ratio_cs_k4_r4 VSS IREF IOUT1 IOUT2 +XMREF_f0 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f1 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f2 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f3 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f0 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f1 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f2 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f3 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f0 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f1 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f2 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f3 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f4 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f5 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f6 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f7 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f8 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f9 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f10 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f11 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f12 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f13 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f14 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f15 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends ratio_cs_k4_r4 diff --git a/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k8_r1.spice b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k8_r1.spice new file mode 100644 index 00000000..3c34f4ae --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k8_r1.spice @@ -0,0 +1,26 @@ +.subckt ratio_cs_k8_r1 VSS IREF IOUT1 IOUT2 +XMREF_f0 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f1 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f2 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f3 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f4 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f5 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f6 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f7 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f0 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f1 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f2 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f3 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f4 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f5 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f6 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f7 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f0 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f1 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f2 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f3 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f4 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f5 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f6 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f7 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends ratio_cs_k8_r1 diff --git a/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k8_r2.spice b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k8_r2.spice new file mode 100644 index 00000000..7c973212 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k8_r2.spice @@ -0,0 +1,34 @@ +.subckt ratio_cs_k8_r2 VSS IREF IOUT1 IOUT2 +XMREF_f0 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f1 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f2 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f3 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f4 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f5 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f6 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f7 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f0 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f1 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f2 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f3 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f4 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f5 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f6 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f7 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f0 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f1 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f2 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f3 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f4 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f5 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f6 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f7 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f8 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f9 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f10 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f11 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f12 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f13 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f14 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f15 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends ratio_cs_k8_r2 diff --git a/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k8_r4.spice b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k8_r4.spice new file mode 100644 index 00000000..5fbc5cb5 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/ratio_source_array_v1/references/ratio_cs_k8_r4.spice @@ -0,0 +1,50 @@ +.subckt ratio_cs_k8_r4 VSS IREF IOUT1 IOUT2 +XMREF_f0 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f1 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f2 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f3 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f4 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f5 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f6 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMREF_f7 IREF IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f0 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f1 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f2 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f3 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f4 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f5 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f6 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT1_f7 IOUT1 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f0 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f1 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f2 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f3 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f4 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f5 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f6 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f7 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f8 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f9 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f10 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f11 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f12 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f13 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f14 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f15 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f16 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f17 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f18 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f19 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f20 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f21 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f22 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f23 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f24 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f25 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f26 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f27 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f28 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f29 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f30 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XMOUT2_f31 IOUT2 IREF VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends ratio_cs_k8_r4 diff --git a/benchmarks/code_behind_layout/configs/development/task_source_surfaces.json b/benchmarks/code_behind_layout/configs/development/task_source_surfaces.json new file mode 100644 index 00000000..c1bf423f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/task_source_surfaces.json @@ -0,0 +1,213 @@ +{ + "status": "DEVELOPMENT_REAL_SOURCE_EDIT_SURFACES_NOT_FROZEN_TASKS", + "formal_tasks_established": 0, + "registry_modified": false, + "source_group_proposal": "docs/source_group_partition.md", + "qualified_eight_lineages_established": false, + "validation_source_group_established": false, + "targets": [ + { + "source_implementation": "mirror", + "topology": "current_mirror", + "source_path": "src/glayout/cells/elementary/current_mirror/current_mirror.py", + "proposed_role": "E1_E2_E3_eval", + "editing_surfaces": [ + { + "metric_to_characterize": "relative_current_error", + "admission": "requires_actual_legal_configuration_domain_and_frozen_contract", + "formal_task_id": null + }, + { + "metric_to_characterize": "dc_output_resistance", + "admission": "requires_actual_legal_configuration_domain_and_frozen_contract", + "formal_task_id": null + }, + { + "metric_to_characterize": "compliance_voltage", + "admission": "requires_actual_legal_configuration_domain_and_frozen_contract", + "formal_task_id": null + } + ] + }, + { + "source_implementation": "pair", + "topology": "differential_pair", + "source_path": "src/glayout/cells/elementary/diff_pair/diff_pair.py", + "proposed_role": "E1_E2_E3_eval", + "editing_surfaces": [ + { + "metric_to_characterize": "transconductance", + "admission": "requires_actual_legal_configuration_domain_and_frozen_contract", + "formal_task_id": null + }, + { + "metric_to_characterize": "differential_branch_balance", + "admission": "requires_actual_legal_configuration_domain_and_frozen_contract", + "formal_task_id": null + }, + { + "metric_to_characterize": "loaded_differential_bandwidth", + "admission": "requires_actual_legal_configuration_domain_and_frozen_contract", + "formal_task_id": null + } + ] + }, + { + "source_implementation": "fvf", + "topology": "local_feedback_follower", + "source_path": "src/glayout/cells/elementary/FVF/fvf.py", + "proposed_role": "E1_E2_E3_eval", + "editing_surfaces": [ + { + "metric_to_characterize": "dc_transfer_gain_and_declared_level_shift", + "admission": "requires_actual_legal_configuration_domain_and_frozen_contract", + "formal_task_id": null + }, + { + "metric_to_characterize": "output_resistance", + "admission": "requires_actual_legal_configuration_domain_and_frozen_contract", + "formal_task_id": null + }, + { + "metric_to_characterize": "follower_bandwidth", + "admission": "requires_actual_legal_configuration_domain_and_frozen_contract", + "formal_task_id": null + } + ] + }, + { + "source_implementation": "tg", + "topology": "transmission_gate", + "source_path": "src/glayout/cells/elementary/transmission_gate/transmission_gate.py", + "proposed_role": "E1_E2_E3_eval", + "editing_surfaces": [ + { + "metric_to_characterize": "on_resistance", + "admission": "requires_actual_legal_configuration_domain_and_frozen_contract", + "formal_task_id": null + }, + { + "metric_to_characterize": "off_leakage", + "admission": "requires_actual_legal_configuration_domain_and_frozen_contract", + "formal_task_id": null + }, + { + "metric_to_characterize": "loaded_signal_tracking_error", + "admission": "requires_actual_legal_configuration_domain_and_frozen_contract", + "formal_task_id": null + } + ] + }, + { + "source_implementation": "miller", + "topology": "miller_ota", + "source_path": "src/glayout/cells/composite/opamp/opamp_twostage.py", + "proposed_role": "E1_E2_E3_eval", + "editing_surfaces": [ + { + "metric_to_characterize": "phase_margin", + "admission": "requires_actual_legal_configuration_domain_and_frozen_contract", + "formal_task_id": null + }, + { + "metric_to_characterize": "unity_gain_frequency", + "admission": "requires_actual_legal_configuration_domain_and_frozen_contract", + "formal_task_id": null + }, + { + "metric_to_characterize": "settling_error", + "admission": "requires_actual_legal_configuration_domain_and_frozen_contract", + "formal_task_id": null + } + ] + }, + { + "source_implementation": "fvf_ota", + "topology": "fvf_class_ab_ota", + "source_path": "src/glayout/cells/composite/fvf_based_ota/ota.py", + "proposed_role": "E1_E2_E3_eval", + "editing_surfaces": [ + { + "metric_to_characterize": "phase_margin", + "admission": "requires_actual_legal_configuration_domain_and_frozen_contract", + "formal_task_id": null + }, + { + "metric_to_characterize": "unity_gain_frequency", + "admission": "requires_actual_legal_configuration_domain_and_frozen_contract", + "formal_task_id": null + }, + { + "metric_to_characterize": "tracking_error", + "admission": "requires_actual_legal_configuration_domain_and_frozen_contract", + "formal_task_id": null + } + ] + }, + { + "source_implementation": "row_5t", + "topology": "five_transistor_ota", + "source_path": "src/generators/five_t.py", + "proposed_role": "E1_E2_E3_eval", + "editing_surfaces": [ + { + "metric_to_characterize": "gain", + "admission": "requires_actual_legal_configuration_domain_and_frozen_contract", + "formal_task_id": null + }, + { + "metric_to_characterize": "unity_gain_frequency", + "admission": "requires_actual_legal_configuration_domain_and_frozen_contract", + "formal_task_id": null + }, + { + "metric_to_characterize": "settling_error", + "admission": "requires_actual_legal_configuration_domain_and_frozen_contract", + "formal_task_id": null + } + ] + }, + { + "source_implementation": "block_miller", + "topology": "miller_ota", + "source_path": "src/generators/compact_miller.py", + "proposed_role": "E1_E2_E3_eval", + "editing_surfaces": [ + { + "metric_to_characterize": "phase_margin", + "admission": "requires_actual_legal_configuration_domain_and_frozen_contract", + "formal_task_id": null + }, + { + "metric_to_characterize": "unity_gain_frequency", + "admission": "requires_actual_legal_configuration_domain_and_frozen_contract", + "formal_task_id": null + }, + { + "metric_to_characterize": "settling_error", + "admission": "requires_actual_legal_configuration_domain_and_frozen_contract", + "formal_task_id": null + } + ] + } + ], + "real_source_implementation_candidates": 8, + "proposed_editing_surfaces": 24, + "missing_before_task_admission": [ + "per_target_legal_parameters_and_reference_binding", + "actual_electrical_metric_and_limit_contracts", + "source_similarity_and_dependency_group_assignment", + "anchor_and_8_development_16_hidden_legal_configurations", + "independent_candidate_interface_and_budget_admission" + ], + "validation_candidate_source_path": "src/generators/validation_mirror.py", + "validation_candidate_physical_run": "phase0_20261018T234605309409Z_validation_mirror", + "validation_candidate_status": "root reports real full DRC/LVS/positive RC/three-corner OP/DC complete; final source-group assignment remains draft", + "shared_helper_policy": "High-level circuit assemblies separate; PDK, MOS, via and disclosed general terminal-access constraints shared and frozen. Source-dependency clusters retained.", + "component_development_evidence": { + "mirror": "results/derived/mirror_domain_development.json", + "pair": "results/derived/pair_three_size_domain_development.json", + "tg": "results/derived/tg_three_size_domain_development.json", + "fvf": "results/derived/follower_two_size_domain_development.json" + } +} diff --git a/benchmarks/code_behind_layout/configs/development/telescopic_ota_design.json b/benchmarks/code_behind_layout/configs/development/telescopic_ota_design.json new file mode 100644 index 00000000..0c781369 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/telescopic_ota_design.json @@ -0,0 +1,76 @@ +{ + "status": "DRAFT_LOCAL_PREPARATION_NO_MEASUREMENTS", + "source_identity": "research_telescopic_cascode_mirror_ota_v1", + "layout_source": "src/generators/telescopic_ota.py", + "independent_reference": "src/generators/telescopic_ota_reference.py", + "topology": "NMOS differential pair, two NMOS cascodes, cascoded PMOS mirror load, NMOS tail plus explicit diode-connected bias reference", + "functional_device_groups": 10, + "signal_core_transistors": 9, + "default_per_finger_device_count": 32, + "application": { + "supply_V": 1.8, + "common_mode_V": 1.0, + "bias_reference_current_A": 1e-05, + "load_F": 2e-12, + "temperature_C": 27 + }, + "four_predeclared_bias_controls": [ + { + "id": "b00", + "VBN_V": 1.25, + "VBP_V": 0.45 + }, + { + "id": "b01", + "VBN_V": 1.25, + "VBP_V": 0.6 + }, + { + "id": "b10", + "VBN_V": 1.4, + "VBP_V": 0.45 + }, + { + "id": "b11", + "VBN_V": 1.4, + "VBP_V": 0.6 + } + ], + "corners": [ + "tt", + "ss", + "ff" + ], + "fixed_OP_AC_requirements": { + "gain_at_10Hz_dB_min": 30, + "ugb_Hz_min": 1000000, + "phase_margin_deg_min": 60, + "phase_margin_deg_max": 180, + "output_OP_acceptance_min_V": 0.7, + "output_OP_acceptance_max_V": 1.2, + "total_VDD_and_cascode_bias_power_W_max": 0.0005, + "minimum_absolute_channel_voltage_V": 0.05, + "minimum_abs_Vds_over_abs_Vdsat": 1.0 + }, + "OP_interpretation": "The AC fixture closes external negative feedback at DC through an inductor and opens it at AC. The declared0.7..1.2V window accepts a headroom-valid operating point; it is not a claim of intrinsic CMFB, precision tracking, or continuous usable swing across that entire interval. Each actual MOS must additionally pass the explicit channel-voltage and saturation checks.", + "power_accounting": "Total DC power is P_VDD+P_VBN+P_VBP, from actual source currents. IREF is connected from VDD into IBIAS; its entire VDD*10u reference branch is already included in P_VDD. Report (VDD-Vbias)*10u for the ideal current-source dissipation and Vbias*10u for its reference MOS as components, without adding them again. Input stimulus driver power is outside the quiescent circuit budget. VBN/VBP are ideal external voltage-bias ports. Their actual source output power is included, while the implementation overhead of an on-chip bias generator is outside this fixture; no zero-overhead bias-generator claim is made.", + "electrical_basis": "The two cascode stacks increase output resistance; the output load supplies the dominant pole. Upper PMOS gates sense the lower left collector across the entire reference stack, allowing external VBP to set cascode-source headroom without fixing the mirror input transistor's drain to its gate. VBN covers nominal lower-stack headroom; VBP covers upper-stack headroom. These are design hypotheses, not observed operation or a stability guarantee.", + "source_ancestry": { + "new_high_level_assembly": true, + "existing_OTA_or_circuit_assembly_imported": false, + "five_t_source_copied_or_parameterized": false, + "netlist_to_layout_compiler_used": false, + "shared_dependencies": [ + "glayout MOS", + "glayout via", + "SKY130 PDK", + "src/generators/terminal_access.py" + ], + "independence_limit": "High-level topology and assembly logic are new; basic primitive/access constraints are shared. This is not a claim of zero source dependency overlap." + }, + "selection_rule": "Measure all four fixed controls at all three corners once. If any passes every declared OP/AC requirement, the first in the declared order is the prospective physical-control bias. Do not search further if none passes. A passing ideal OP/AC control does not establish DRC, LVS, positive RC, transient/DC correctness or S2.", + "new_GDS_DRC_LVS_PEX_SPICE_calls": 0, + "old_legacy_domains_or_results_modified": false, + "formal_trials": 0, + "training_examples": 0 +} diff --git a/benchmarks/code_behind_layout/configs/development/telescopic_ota_fullflow.json b/benchmarks/code_behind_layout/configs/development/telescopic_ota_fullflow.json new file mode 100644 index 00000000..8c1641c9 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/telescopic_ota_fullflow.json @@ -0,0 +1,55 @@ +{ + "status": "PROSPECTIVE_DRAFT_NO_MEASUREMENTS", + "source_identity": "research_telescopic_cascode_mirror_ota_v1", + "prerequisite": "A true all-three-corner positive control among the fixed local_v4 twelve ideal OP/AC calls; select the first declared passing bias only after all twelve calls finish", + "application": { + "supply_V": 1.8, + "common_mode_V": 1.0, + "bias_reference_current_A": 0.00001, + "load_F": 2e-12, + "temperature_C": 27 + }, + "corners": ["tt", "ss", "ff"], + "numerics": {"solver": "KLU", "reltol": 1e-6, "abstol": 1e-14, "vntol": 1e-8, "chgtol": 1e-16}, + "per_analysis_wall_limit_s": 180, + "serial_analyses": true, + "physical_gates": ["full_rule_DRC", "independent_reference_LVS", "exact_per_finger_device_and_terminal_graph", "positive_full_RC"], + "fixed_requirements": { + "gain_at_10Hz_dB_min": 30, + "ugb_Hz_min": 1000000, + "phase_margin_deg_min": 60, + "phase_margin_deg_max": 180, + "nominal_output_OP_acceptance_min_V": 0.7, + "nominal_output_OP_acceptance_max_V": 1.2, + "total_VDD_and_cascode_bias_power_W_max": 0.0005, + "minimum_absolute_channel_voltage_V": 0.05, + "minimum_abs_Vds_over_abs_Vdsat": 1.0, + "dc_incremental_gain_min": 0.9, + "dc_incremental_gain_max": 1.1, + "transient_incremental_gain_min": 0.9, + "transient_incremental_gain_max": 1.1, + "transient_final_plateau_relative_error_max": 0.02 + }, + "transient": { + "feedback": "wire_alias_VN_equals_VOUT", + "stimulus": "VIN vp 0 pulse(0.99 1.01 1u 10n 10n 4u 8u)", + "analysis": "tran 5n 16u", + "high_plateau_window_s": [0.000004, 0.0000049], + "low_plateau_window_s": [0.000008, 0.0000089], + "settling_check_windows_s": [[0.000003, 0.0000049], [0.000007, 0.0000089]], + "relative_error_definition": "The maximum absolute output deviation from its corresponding final-plateau mean, divided by the absolute measured high-minus-low plateau difference; no absolute DC tracking precision is implied", + "incremental_gain_definition": "(mean(output in high plateau)-mean(output in low plateau))/0.02V" + }, + "dc": { + "feedback": "wire_alias_VN_equals_VOUT", + "analysis": "dc VIN 0.9 1.1 0.05", + "expected_axis_V": [0.9, 0.95, 1.0, 1.05, 1.1], + "incremental_gain_definition": "Every adjacent output difference divided by the corresponding 0.05V input difference; all five output samples must be finite and inside the original 0.7..1.2V headroom window", + "interpretation": "Five sampled closed-loop transfer points, not proof of continuous rail-to-rail swing" + }, + "power_accounting": "Use actual VDD/VBN/VBP source currents. The VDD-to-IBIAS reference branch is already included in VDD power. Ideal external bias generator implementation overhead is outside this declared fixture and remains disclosed.", + "completeness": "Every requested OP/AC/Tran/DC table and ngspice log must pass the exact declared analysis coverage. Timeout, partial trace, missing per-finger binding, or software exceptions are unknown, not a candidate-negative label.", + "new_measurements": 0, + "formal_measurements": 0, + "old_domains_modified": false +} diff --git a/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_12_12.spice b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_12_12.spice new file mode 100644 index 00000000..b7274d17 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_12_12.spice @@ -0,0 +1,50 @@ +.subckt train_pair_nf_c02 VSS IIN1 IOUT1 +XM1_f0 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f4 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f5 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f6 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f7 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f8 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f9 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f10 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f11 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f4 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f5 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f6 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f7 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f8 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f9 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f10 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f11 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f0 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f1 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f2 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f3 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f4 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f5 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f6 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f7 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f8 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f9 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f10 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f11 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f0 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f1 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f2 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f3 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f4 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f5 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f6 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f7 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f8 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f9 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f10 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f11 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends train_pair_nf_c02 diff --git a/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_12_4.spice b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_12_4.spice new file mode 100644 index 00000000..0bebc25b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_12_4.spice @@ -0,0 +1,34 @@ +.subckt train_pair_nf_c02 VSS IIN1 IOUT1 +XM1_f0 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f4 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f5 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f6 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f7 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f8 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f9 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f10 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f11 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f0 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f1 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f2 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f3 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f4 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f5 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f6 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f7 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f8 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f9 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f10 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f11 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f0 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f1 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f2 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f3 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends train_pair_nf_c02 diff --git a/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_12_8.spice b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_12_8.spice new file mode 100644 index 00000000..a4b04565 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_12_8.spice @@ -0,0 +1,42 @@ +.subckt train_pair_nf_c02 VSS IIN1 IOUT1 +XM1_f0 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f4 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f5 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f6 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f7 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f8 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f9 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f10 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f11 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f4 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f5 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f6 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f7 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f0 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f1 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f2 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f3 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f4 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f5 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f6 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f7 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f8 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f9 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f10 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f11 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f0 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f1 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f2 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f3 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f4 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f5 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f6 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f7 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends train_pair_nf_c02 diff --git a/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_4_12.spice b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_4_12.spice new file mode 100644 index 00000000..75cb866d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_4_12.spice @@ -0,0 +1,34 @@ +.subckt train_pair_nf_c02 VSS IIN1 IOUT1 +XM1_f0 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f4 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f5 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f6 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f7 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f8 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f9 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f10 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f11 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f0 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f1 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f2 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f3 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f0 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f1 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f2 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f3 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f4 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f5 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f6 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f7 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f8 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f9 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f10 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f11 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends train_pair_nf_c02 diff --git a/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_4_4.spice b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_4_4.spice new file mode 100644 index 00000000..8a27a306 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_4_4.spice @@ -0,0 +1,18 @@ +.subckt train_pair_nf_c02 VSS IIN1 IOUT1 +XM1_f0 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f0 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f1 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f2 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f3 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f0 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f1 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f2 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f3 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends train_pair_nf_c02 diff --git a/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_4_8.spice b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_4_8.spice new file mode 100644 index 00000000..cfbb2ab2 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_4_8.spice @@ -0,0 +1,26 @@ +.subckt train_pair_nf_c02 VSS IIN1 IOUT1 +XM1_f0 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f4 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f5 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f6 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f7 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f0 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f1 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f2 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f3 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f0 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f1 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f2 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f3 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f4 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f5 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f6 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f7 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends train_pair_nf_c02 diff --git a/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_8_12.spice b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_8_12.spice new file mode 100644 index 00000000..028f5c91 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_8_12.spice @@ -0,0 +1,42 @@ +.subckt train_pair_nf_c02 VSS IIN1 IOUT1 +XM1_f0 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f4 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f5 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f6 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f7 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f4 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f5 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f6 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f7 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f8 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f9 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f10 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f11 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f0 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f1 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f2 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f3 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f4 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f5 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f6 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f7 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f0 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f1 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f2 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f3 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f4 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f5 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f6 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f7 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f8 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f9 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f10 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f11 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends train_pair_nf_c02 diff --git a/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_8_4.spice b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_8_4.spice new file mode 100644 index 00000000..9695f3b1 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_8_4.spice @@ -0,0 +1,26 @@ +.subckt train_pair_nf_c02 VSS IIN1 IOUT1 +XM1_f0 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f4 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f5 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f6 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f7 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f0 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f1 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f2 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f3 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f4 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f5 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f6 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f7 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f0 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f1 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f2 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f3 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends train_pair_nf_c02 diff --git a/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_8_8.spice b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_8_8.spice new file mode 100644 index 00000000..8a029d14 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c02/references/c02_matched_nf_8_8.spice @@ -0,0 +1,34 @@ +.subckt train_pair_nf_c02 VSS IIN1 IOUT1 +XM1_f0 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f4 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f5 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f6 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f7 IIN1 IIN1 net6 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f1 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f2 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f3 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f4 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f5 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f6 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f7 net6 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f0 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f1 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f2 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f3 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f4 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f5 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f6 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM3_f7 IOUT1 IIN1 net12 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f0 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f1 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f2 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f3 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f4 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f5 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f6 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM4_f7 net12 net6 VSS VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +.ends train_pair_nf_c02 diff --git a/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_12_12.spice b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_12_12.spice new file mode 100644 index 00000000..9686c828 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_12_12.spice @@ -0,0 +1,50 @@ +.subckt train_pair_nf_c07 VDD VSS VIN1 VIN2 VOUT1 VOUT2 VB1 IB1 +XM1_f0 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f8 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f9 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f10 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f11 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f8 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f9 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f10 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f11 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f8 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f9 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f10 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f11 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f0 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f1 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f2 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f3 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f4 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f5 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f6 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f7 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f8 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f9 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f10 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f11 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends train_pair_nf_c07 diff --git a/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_12_4.spice b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_12_4.spice new file mode 100644 index 00000000..99e377cc --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_12_4.spice @@ -0,0 +1,34 @@ +.subckt train_pair_nf_c07 VDD VSS VIN1 VIN2 VOUT1 VOUT2 VB1 IB1 +XM1_f0 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f8 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f9 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f10 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f11 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f8 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f9 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f10 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f11 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f0 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f1 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f2 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f3 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends train_pair_nf_c07 diff --git a/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_12_8.spice b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_12_8.spice new file mode 100644 index 00000000..e7f7a0ba --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_12_8.spice @@ -0,0 +1,42 @@ +.subckt train_pair_nf_c07 VDD VSS VIN1 VIN2 VOUT1 VOUT2 VB1 IB1 +XM1_f0 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f8 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f9 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f10 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f11 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f8 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f9 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f10 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f11 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f0 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f1 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f2 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f3 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f4 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f5 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f6 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f7 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends train_pair_nf_c07 diff --git a/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_4_12.spice b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_4_12.spice new file mode 100644 index 00000000..a0501a0d --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_4_12.spice @@ -0,0 +1,34 @@ +.subckt train_pair_nf_c07 VDD VSS VIN1 VIN2 VOUT1 VOUT2 VB1 IB1 +XM1_f0 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f8 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f9 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f10 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f11 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f0 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f1 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f2 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f3 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f4 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f5 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f6 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f7 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f8 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f9 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f10 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f11 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends train_pair_nf_c07 diff --git a/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_4_4.spice b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_4_4.spice new file mode 100644 index 00000000..c72b0740 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_4_4.spice @@ -0,0 +1,18 @@ +.subckt train_pair_nf_c07 VDD VSS VIN1 VIN2 VOUT1 VOUT2 VB1 IB1 +XM1_f0 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f0 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f1 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f2 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f3 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends train_pair_nf_c07 diff --git a/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_4_8.spice b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_4_8.spice new file mode 100644 index 00000000..bade4876 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_4_8.spice @@ -0,0 +1,26 @@ +.subckt train_pair_nf_c07 VDD VSS VIN1 VIN2 VOUT1 VOUT2 VB1 IB1 +XM1_f0 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f0 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f1 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f2 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f3 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f4 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f5 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f6 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f7 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends train_pair_nf_c07 diff --git a/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_8_12.spice b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_8_12.spice new file mode 100644 index 00000000..2d7446db --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_8_12.spice @@ -0,0 +1,42 @@ +.subckt train_pair_nf_c07 VDD VSS VIN1 VIN2 VOUT1 VOUT2 VB1 IB1 +XM1_f0 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f8 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f9 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f10 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f11 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f0 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f1 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f2 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f3 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f4 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f5 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f6 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f7 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f8 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f9 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f10 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f11 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends train_pair_nf_c07 diff --git a/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_8_4.spice b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_8_4.spice new file mode 100644 index 00000000..28953789 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_8_4.spice @@ -0,0 +1,26 @@ +.subckt train_pair_nf_c07 VDD VSS VIN1 VIN2 VOUT1 VOUT2 VB1 IB1 +XM1_f0 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f0 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f1 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f2 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f3 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends train_pair_nf_c07 diff --git a/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_8_8.spice b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_8_8.spice new file mode 100644 index 00000000..49bdf1d3 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/c07/references/c07_matched_nf_8_8.spice @@ -0,0 +1,34 @@ +.subckt train_pair_nf_c07 VDD VSS VIN1 VIN2 VOUT1 VOUT2 VB1 IB1 +XM1_f0 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VIN1 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT2 VIN2 IB1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM3_f0 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f1 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f2 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f3 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f4 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f5 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f6 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM3_f7 VOUT1 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f0 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f1 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f2 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f3 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f4 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f5 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f6 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM4_f7 VOUT2 VB1 VDD VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends train_pair_nf_c07 diff --git a/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/domains.json b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/domains.json new file mode 100644 index 00000000..6aaa164f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_matched_pair_nf_v1/domains.json @@ -0,0 +1,4123 @@ +{ + "status": "DRAFT_TRAIN_ONLY_IDEAL_QUALIFICATION", + "domains": [ + { + "circuit_id": "C02", + "parent_lineage": "textbook_universal_compiler_cropped", + "independent_source_lineages_added": 0, + "matched_pairs": [ + [ + "M1", + "M3" + ], + [ + "M2", + "M4" + ] + ], + "levels": [ + 4, + 8, + 12 + ], + "configurations": [ + { + "configuration_id": "c02_matched_nf_4_4", + "role": "development", + "parameters": { + "circuit": { + "circuit_id": "C02", + "name": "cascode_current_mirror", + "ports": [ + "VSS", + "IIN1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IIN1", + "IIN1", + "net6", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "net6", + "net6", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "IOUT1", + "IIN1", + "net12", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "nfet", + "nets": [ + "net12", + "net6", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 672, + "files": [ + "Dataset/672/672.cir", + "Dataset/672/Port672.txt", + "Dataset/672/Pagenumber672.txt", + "Dataset/672/Book672.png", + "Dataset/672/Cadence672.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "129", + "device_name_map": { + "M1": "M3", + "M2": "M2", + "M3": "M1", + "M4": "M0" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/672/Book672.png", + "observation": "Johns p.129 scan: Q1/Q2 bottom pair, Q3/Q4 cascode pair, Q3 and Q1 diode-connected, Iin source on top; cascode mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M2": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M3": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M4": { + "w": 2.0, + "l": 0.6, + "nf": 4 + } + }, + "top_cell": "train_pair_nf_c02" + }, + "contract": { + "task_id": "c02_matched_pair_nf_v1", + "configuration_id": "c02_matched_nf_4_4", + "reference_id": "c02_matched_nf_4_4_literal_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_TRAIN_DOMAIN_IDEAL_QUALIFICATION_ONLY", + "objective": { + "id": "c02_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance_ohm", + "unit": "ohm", + "min": 300000 + }, + { + "name": "max_current_relative_error_1p3_to_1p7V", + "unit": "1", + "max": 0.05 + } + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.05, + "output_resistance_ohm_min": 300000, + "max_current_relative_error_1p3_to_1p7V": 0.05 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_V": 1.5, + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "output_transient_levels_V": [ + 1.475, + 1.525 + ], + "current_compliance_application_region_V": [ + 1.3, + 1.7 + ], + "load_definition": "Output voltage source sweeps the cascode compliance region; output-port current is measured. Bias is the two diode-connected reference devices in the immutable DUT, with a5uA external source from1.8V. No0.9V mirror clamp or voltage-gain claim." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + }, + "numerical_controls": { + "integration_method": "trap", + "independent_transient_inputs": false, + "tight_tolerances_unchanged": true + }, + "power_definition": "Three-port DUT has no VDD pin. Report input-port and output-port dissipation, and external1.8V reference-source supply work separately." + }, + "reference_file": "c02/references/c02_matched_nf_4_4.spice" + }, + { + "configuration_id": "c02_matched_nf_4_8", + "role": "development", + "parameters": { + "circuit": { + "circuit_id": "C02", + "name": "cascode_current_mirror", + "ports": [ + "VSS", + "IIN1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IIN1", + "IIN1", + "net6", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "net6", + "net6", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "IOUT1", + "IIN1", + "net12", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "nfet", + "nets": [ + "net12", + "net6", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 672, + "files": [ + "Dataset/672/672.cir", + "Dataset/672/Port672.txt", + "Dataset/672/Pagenumber672.txt", + "Dataset/672/Book672.png", + "Dataset/672/Cadence672.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "129", + "device_name_map": { + "M1": "M3", + "M2": "M2", + "M3": "M1", + "M4": "M0" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/672/Book672.png", + "observation": "Johns p.129 scan: Q1/Q2 bottom pair, Q3/Q4 cascode pair, Q3 and Q1 diode-connected, Iin source on top; cascode mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "M3": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M4": { + "w": 4.0, + "l": 0.6, + "nf": 8 + } + }, + "top_cell": "train_pair_nf_c02" + }, + "contract": { + "task_id": "c02_matched_pair_nf_v1", + "configuration_id": "c02_matched_nf_4_8", + "reference_id": "c02_matched_nf_4_8_literal_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_TRAIN_DOMAIN_IDEAL_QUALIFICATION_ONLY", + "objective": { + "id": "c02_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance_ohm", + "unit": "ohm", + "min": 300000 + }, + { + "name": "max_current_relative_error_1p3_to_1p7V", + "unit": "1", + "max": 0.05 + } + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.05, + "output_resistance_ohm_min": 300000, + "max_current_relative_error_1p3_to_1p7V": 0.05 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_V": 1.5, + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "output_transient_levels_V": [ + 1.475, + 1.525 + ], + "current_compliance_application_region_V": [ + 1.3, + 1.7 + ], + "load_definition": "Output voltage source sweeps the cascode compliance region; output-port current is measured. Bias is the two diode-connected reference devices in the immutable DUT, with a5uA external source from1.8V. No0.9V mirror clamp or voltage-gain claim." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + }, + "numerical_controls": { + "integration_method": "trap", + "independent_transient_inputs": false, + "tight_tolerances_unchanged": true + }, + "power_definition": "Three-port DUT has no VDD pin. Report input-port and output-port dissipation, and external1.8V reference-source supply work separately." + }, + "reference_file": "c02/references/c02_matched_nf_4_8.spice" + }, + { + "configuration_id": "c02_matched_nf_4_12", + "role": "development", + "parameters": { + "circuit": { + "circuit_id": "C02", + "name": "cascode_current_mirror", + "ports": [ + "VSS", + "IIN1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IIN1", + "IIN1", + "net6", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "net6", + "net6", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "IOUT1", + "IIN1", + "net12", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "nfet", + "nets": [ + "net12", + "net6", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 672, + "files": [ + "Dataset/672/672.cir", + "Dataset/672/Port672.txt", + "Dataset/672/Pagenumber672.txt", + "Dataset/672/Book672.png", + "Dataset/672/Cadence672.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "129", + "device_name_map": { + "M1": "M3", + "M2": "M2", + "M3": "M1", + "M4": "M0" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/672/Book672.png", + "observation": "Johns p.129 scan: Q1/Q2 bottom pair, Q3/Q4 cascode pair, Q3 and Q1 diode-connected, Iin source on top; cascode mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M2": { + "w": 6.0, + "l": 0.6, + "nf": 12 + }, + "M3": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M4": { + "w": 6.0, + "l": 0.6, + "nf": 12 + } + }, + "top_cell": "train_pair_nf_c02" + }, + "contract": { + "task_id": "c02_matched_pair_nf_v1", + "configuration_id": "c02_matched_nf_4_12", + "reference_id": "c02_matched_nf_4_12_literal_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_TRAIN_DOMAIN_IDEAL_QUALIFICATION_ONLY", + "objective": { + "id": "c02_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance_ohm", + "unit": "ohm", + "min": 300000 + }, + { + "name": "max_current_relative_error_1p3_to_1p7V", + "unit": "1", + "max": 0.05 + } + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.05, + "output_resistance_ohm_min": 300000, + "max_current_relative_error_1p3_to_1p7V": 0.05 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_V": 1.5, + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "output_transient_levels_V": [ + 1.475, + 1.525 + ], + "current_compliance_application_region_V": [ + 1.3, + 1.7 + ], + "load_definition": "Output voltage source sweeps the cascode compliance region; output-port current is measured. Bias is the two diode-connected reference devices in the immutable DUT, with a5uA external source from1.8V. No0.9V mirror clamp or voltage-gain claim." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + }, + "numerical_controls": { + "integration_method": "trap", + "independent_transient_inputs": false, + "tight_tolerances_unchanged": true + }, + "power_definition": "Three-port DUT has no VDD pin. Report input-port and output-port dissipation, and external1.8V reference-source supply work separately." + }, + "reference_file": "c02/references/c02_matched_nf_4_12.spice" + }, + { + "configuration_id": "c02_matched_nf_8_4", + "role": "development", + "parameters": { + "circuit": { + "circuit_id": "C02", + "name": "cascode_current_mirror", + "ports": [ + "VSS", + "IIN1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IIN1", + "IIN1", + "net6", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "net6", + "net6", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "IOUT1", + "IIN1", + "net12", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "nfet", + "nets": [ + "net12", + "net6", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 672, + "files": [ + "Dataset/672/672.cir", + "Dataset/672/Port672.txt", + "Dataset/672/Pagenumber672.txt", + "Dataset/672/Book672.png", + "Dataset/672/Cadence672.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "129", + "device_name_map": { + "M1": "M3", + "M2": "M2", + "M3": "M1", + "M4": "M0" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/672/Book672.png", + "observation": "Johns p.129 scan: Q1/Q2 bottom pair, Q3/Q4 cascode pair, Q3 and Q1 diode-connected, Iin source on top; cascode mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "M2": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M3": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "M4": { + "w": 2.0, + "l": 0.6, + "nf": 4 + } + }, + "top_cell": "train_pair_nf_c02" + }, + "contract": { + "task_id": "c02_matched_pair_nf_v1", + "configuration_id": "c02_matched_nf_8_4", + "reference_id": "c02_matched_nf_8_4_literal_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_TRAIN_DOMAIN_IDEAL_QUALIFICATION_ONLY", + "objective": { + "id": "c02_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance_ohm", + "unit": "ohm", + "min": 300000 + }, + { + "name": "max_current_relative_error_1p3_to_1p7V", + "unit": "1", + "max": 0.05 + } + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.05, + "output_resistance_ohm_min": 300000, + "max_current_relative_error_1p3_to_1p7V": 0.05 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_V": 1.5, + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "output_transient_levels_V": [ + 1.475, + 1.525 + ], + "current_compliance_application_region_V": [ + 1.3, + 1.7 + ], + "load_definition": "Output voltage source sweeps the cascode compliance region; output-port current is measured. Bias is the two diode-connected reference devices in the immutable DUT, with a5uA external source from1.8V. No0.9V mirror clamp or voltage-gain claim." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + }, + "numerical_controls": { + "integration_method": "trap", + "independent_transient_inputs": false, + "tight_tolerances_unchanged": true + }, + "power_definition": "Three-port DUT has no VDD pin. Report input-port and output-port dissipation, and external1.8V reference-source supply work separately." + }, + "reference_file": "c02/references/c02_matched_nf_8_4.spice" + }, + { + "configuration_id": "c02_matched_nf_8_8", + "role": "anchor", + "parameters": { + "circuit": { + "circuit_id": "C02", + "name": "cascode_current_mirror", + "ports": [ + "VSS", + "IIN1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IIN1", + "IIN1", + "net6", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "net6", + "net6", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "IOUT1", + "IIN1", + "net12", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "nfet", + "nets": [ + "net12", + "net6", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 672, + "files": [ + "Dataset/672/672.cir", + "Dataset/672/Port672.txt", + "Dataset/672/Pagenumber672.txt", + "Dataset/672/Book672.png", + "Dataset/672/Cadence672.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "129", + "device_name_map": { + "M1": "M3", + "M2": "M2", + "M3": "M1", + "M4": "M0" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/672/Book672.png", + "observation": "Johns p.129 scan: Q1/Q2 bottom pair, Q3/Q4 cascode pair, Q3 and Q1 diode-connected, Iin source on top; cascode mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "M3": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "M4": { + "w": 4.0, + "l": 0.6, + "nf": 8 + } + }, + "top_cell": "train_pair_nf_c02" + }, + "contract": { + "task_id": "c02_matched_pair_nf_v1", + "configuration_id": "c02_matched_nf_8_8", + "reference_id": "c02_matched_nf_8_8_literal_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_TRAIN_DOMAIN_IDEAL_QUALIFICATION_ONLY", + "objective": { + "id": "c02_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance_ohm", + "unit": "ohm", + "min": 300000 + }, + { + "name": "max_current_relative_error_1p3_to_1p7V", + "unit": "1", + "max": 0.05 + } + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.05, + "output_resistance_ohm_min": 300000, + "max_current_relative_error_1p3_to_1p7V": 0.05 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_V": 1.5, + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "output_transient_levels_V": [ + 1.475, + 1.525 + ], + "current_compliance_application_region_V": [ + 1.3, + 1.7 + ], + "load_definition": "Output voltage source sweeps the cascode compliance region; output-port current is measured. Bias is the two diode-connected reference devices in the immutable DUT, with a5uA external source from1.8V. No0.9V mirror clamp or voltage-gain claim." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + }, + "numerical_controls": { + "integration_method": "trap", + "independent_transient_inputs": false, + "tight_tolerances_unchanged": true + }, + "power_definition": "Three-port DUT has no VDD pin. Report input-port and output-port dissipation, and external1.8V reference-source supply work separately." + }, + "reference_file": "c02/references/c02_matched_nf_8_8.spice" + }, + { + "configuration_id": "c02_matched_nf_8_12", + "role": "development", + "parameters": { + "circuit": { + "circuit_id": "C02", + "name": "cascode_current_mirror", + "ports": [ + "VSS", + "IIN1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IIN1", + "IIN1", + "net6", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "net6", + "net6", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "IOUT1", + "IIN1", + "net12", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "nfet", + "nets": [ + "net12", + "net6", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 672, + "files": [ + "Dataset/672/672.cir", + "Dataset/672/Port672.txt", + "Dataset/672/Pagenumber672.txt", + "Dataset/672/Book672.png", + "Dataset/672/Cadence672.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "129", + "device_name_map": { + "M1": "M3", + "M2": "M2", + "M3": "M1", + "M4": "M0" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/672/Book672.png", + "observation": "Johns p.129 scan: Q1/Q2 bottom pair, Q3/Q4 cascode pair, Q3 and Q1 diode-connected, Iin source on top; cascode mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "M2": { + "w": 6.0, + "l": 0.6, + "nf": 12 + }, + "M3": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "M4": { + "w": 6.0, + "l": 0.6, + "nf": 12 + } + }, + "top_cell": "train_pair_nf_c02" + }, + "contract": { + "task_id": "c02_matched_pair_nf_v1", + "configuration_id": "c02_matched_nf_8_12", + "reference_id": "c02_matched_nf_8_12_literal_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_TRAIN_DOMAIN_IDEAL_QUALIFICATION_ONLY", + "objective": { + "id": "c02_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance_ohm", + "unit": "ohm", + "min": 300000 + }, + { + "name": "max_current_relative_error_1p3_to_1p7V", + "unit": "1", + "max": 0.05 + } + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.05, + "output_resistance_ohm_min": 300000, + "max_current_relative_error_1p3_to_1p7V": 0.05 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_V": 1.5, + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "output_transient_levels_V": [ + 1.475, + 1.525 + ], + "current_compliance_application_region_V": [ + 1.3, + 1.7 + ], + "load_definition": "Output voltage source sweeps the cascode compliance region; output-port current is measured. Bias is the two diode-connected reference devices in the immutable DUT, with a5uA external source from1.8V. No0.9V mirror clamp or voltage-gain claim." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + }, + "numerical_controls": { + "integration_method": "trap", + "independent_transient_inputs": false, + "tight_tolerances_unchanged": true + }, + "power_definition": "Three-port DUT has no VDD pin. Report input-port and output-port dissipation, and external1.8V reference-source supply work separately." + }, + "reference_file": "c02/references/c02_matched_nf_8_12.spice" + }, + { + "configuration_id": "c02_matched_nf_12_4", + "role": "development", + "parameters": { + "circuit": { + "circuit_id": "C02", + "name": "cascode_current_mirror", + "ports": [ + "VSS", + "IIN1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IIN1", + "IIN1", + "net6", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "net6", + "net6", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "IOUT1", + "IIN1", + "net12", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "nfet", + "nets": [ + "net12", + "net6", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 672, + "files": [ + "Dataset/672/672.cir", + "Dataset/672/Port672.txt", + "Dataset/672/Pagenumber672.txt", + "Dataset/672/Book672.png", + "Dataset/672/Cadence672.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "129", + "device_name_map": { + "M1": "M3", + "M2": "M2", + "M3": "M1", + "M4": "M0" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/672/Book672.png", + "observation": "Johns p.129 scan: Q1/Q2 bottom pair, Q3/Q4 cascode pair, Q3 and Q1 diode-connected, Iin source on top; cascode mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 6.0, + "l": 0.6, + "nf": 12 + }, + "M2": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M3": { + "w": 6.0, + "l": 0.6, + "nf": 12 + }, + "M4": { + "w": 2.0, + "l": 0.6, + "nf": 4 + } + }, + "top_cell": "train_pair_nf_c02" + }, + "contract": { + "task_id": "c02_matched_pair_nf_v1", + "configuration_id": "c02_matched_nf_12_4", + "reference_id": "c02_matched_nf_12_4_literal_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_TRAIN_DOMAIN_IDEAL_QUALIFICATION_ONLY", + "objective": { + "id": "c02_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance_ohm", + "unit": "ohm", + "min": 300000 + }, + { + "name": "max_current_relative_error_1p3_to_1p7V", + "unit": "1", + "max": 0.05 + } + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.05, + "output_resistance_ohm_min": 300000, + "max_current_relative_error_1p3_to_1p7V": 0.05 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_V": 1.5, + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "output_transient_levels_V": [ + 1.475, + 1.525 + ], + "current_compliance_application_region_V": [ + 1.3, + 1.7 + ], + "load_definition": "Output voltage source sweeps the cascode compliance region; output-port current is measured. Bias is the two diode-connected reference devices in the immutable DUT, with a5uA external source from1.8V. No0.9V mirror clamp or voltage-gain claim." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + }, + "numerical_controls": { + "integration_method": "trap", + "independent_transient_inputs": false, + "tight_tolerances_unchanged": true + }, + "power_definition": "Three-port DUT has no VDD pin. Report input-port and output-port dissipation, and external1.8V reference-source supply work separately." + }, + "reference_file": "c02/references/c02_matched_nf_12_4.spice" + }, + { + "configuration_id": "c02_matched_nf_12_8", + "role": "development", + "parameters": { + "circuit": { + "circuit_id": "C02", + "name": "cascode_current_mirror", + "ports": [ + "VSS", + "IIN1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IIN1", + "IIN1", + "net6", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "net6", + "net6", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "IOUT1", + "IIN1", + "net12", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "nfet", + "nets": [ + "net12", + "net6", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 672, + "files": [ + "Dataset/672/672.cir", + "Dataset/672/Port672.txt", + "Dataset/672/Pagenumber672.txt", + "Dataset/672/Book672.png", + "Dataset/672/Cadence672.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "129", + "device_name_map": { + "M1": "M3", + "M2": "M2", + "M3": "M1", + "M4": "M0" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/672/Book672.png", + "observation": "Johns p.129 scan: Q1/Q2 bottom pair, Q3/Q4 cascode pair, Q3 and Q1 diode-connected, Iin source on top; cascode mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 6.0, + "l": 0.6, + "nf": 12 + }, + "M2": { + "w": 4.0, + "l": 0.6, + "nf": 8 + }, + "M3": { + "w": 6.0, + "l": 0.6, + "nf": 12 + }, + "M4": { + "w": 4.0, + "l": 0.6, + "nf": 8 + } + }, + "top_cell": "train_pair_nf_c02" + }, + "contract": { + "task_id": "c02_matched_pair_nf_v1", + "configuration_id": "c02_matched_nf_12_8", + "reference_id": "c02_matched_nf_12_8_literal_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_TRAIN_DOMAIN_IDEAL_QUALIFICATION_ONLY", + "objective": { + "id": "c02_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance_ohm", + "unit": "ohm", + "min": 300000 + }, + { + "name": "max_current_relative_error_1p3_to_1p7V", + "unit": "1", + "max": 0.05 + } + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.05, + "output_resistance_ohm_min": 300000, + "max_current_relative_error_1p3_to_1p7V": 0.05 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_V": 1.5, + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "output_transient_levels_V": [ + 1.475, + 1.525 + ], + "current_compliance_application_region_V": [ + 1.3, + 1.7 + ], + "load_definition": "Output voltage source sweeps the cascode compliance region; output-port current is measured. Bias is the two diode-connected reference devices in the immutable DUT, with a5uA external source from1.8V. No0.9V mirror clamp or voltage-gain claim." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + }, + "numerical_controls": { + "integration_method": "trap", + "independent_transient_inputs": false, + "tight_tolerances_unchanged": true + }, + "power_definition": "Three-port DUT has no VDD pin. Report input-port and output-port dissipation, and external1.8V reference-source supply work separately." + }, + "reference_file": "c02/references/c02_matched_nf_12_8.spice" + }, + { + "configuration_id": "c02_matched_nf_12_12", + "role": "development", + "parameters": { + "circuit": { + "circuit_id": "C02", + "name": "cascode_current_mirror", + "ports": [ + "VSS", + "IIN1", + "IOUT1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "IIN1", + "IIN1", + "net6", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "net6", + "net6", + "VSS", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "nfet", + "nets": [ + "IOUT1", + "IIN1", + "net12", + "VSS" + ], + "params": {} + }, + { + "name": "M4", + "kind": "nfet", + "nets": [ + "net12", + "net6", + "VSS", + "VSS" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 672, + "files": [ + "Dataset/672/672.cir", + "Dataset/672/Port672.txt", + "Dataset/672/Pagenumber672.txt", + "Dataset/672/Book672.png", + "Dataset/672/Cadence672.png" + ], + "book": "T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd ed., Wiley, 2012", + "book_key": "johns", + "page_ref": "129", + "device_name_map": { + "M1": "M3", + "M2": "M2", + "M3": "M1", + "M4": "M0" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/672/Book672.png", + "observation": "Johns p.129 scan: Q1/Q2 bottom pair, Q3/Q4 cascode pair, Q3 and Q1 diode-connected, Iin source on top; cascode mirror" + }, + "modifications": [], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 6.0, + "l": 0.6, + "nf": 12 + }, + "M2": { + "w": 6.0, + "l": 0.6, + "nf": 12 + }, + "M3": { + "w": 6.0, + "l": 0.6, + "nf": 12 + }, + "M4": { + "w": 6.0, + "l": 0.6, + "nf": 12 + } + }, + "top_cell": "train_pair_nf_c02" + }, + "contract": { + "task_id": "c02_matched_pair_nf_v1", + "configuration_id": "c02_matched_nf_12_12", + "reference_id": "c02_matched_nf_12_12_literal_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_TRAIN_DOMAIN_IDEAL_QUALIFICATION_ONLY", + "objective": { + "id": "c02_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "nominal_current_relative_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance_ohm", + "unit": "ohm", + "min": 300000 + }, + { + "name": "max_current_relative_error_1p3_to_1p7V", + "unit": "1", + "max": 0.05 + } + ], + "prospective_application_constraints": { + "nominal_current_relative_error_max": 0.05, + "output_resistance_ohm_min": 300000, + "max_current_relative_error_1p3_to_1p7V": 0.05 + }, + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "reference_current_A": 5e-06, + "output_V": 1.5, + "output_DC_sweep_V": [ + 0, + 1.8, + 0.05 + ], + "output_transient_levels_V": [ + 1.475, + 1.525 + ], + "current_compliance_application_region_V": [ + 1.3, + 1.7 + ], + "load_definition": "Output voltage source sweeps the cascode compliance region; output-port current is measured. Bias is the two diode-connected reference devices in the immutable DUT, with a5uA external source from1.8V. No0.9V mirror clamp or voltage-gain claim." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0, + "end": 1.8, + "points": 37, + "scale": "linear" + } + }, + "numerical_controls": { + "integration_method": "trap", + "independent_transient_inputs": false, + "tight_tolerances_unchanged": true + }, + "power_definition": "Three-port DUT has no VDD pin. Report input-port and output-port dissipation, and external1.8V reference-source supply work separately." + }, + "reference_file": "c02/references/c02_matched_nf_12_12.spice" + } + ], + "whole_grid_preserved": true, + "width_semantics": "w is total width; w/nf=.5um for every finger; matching partners always share nf and dimensions.", + "specifications_bias_load_corners_numerical_controls": "Copied unchanged from the actual frozen train family. No post-layout outcome used to select these points.", + "qualification_status": "NOT_RUN", + "formal_training_rows": 0, + "parent_frozen_registry": "runtime/train_collections/c02_action_v1/registry.json" + }, + { + "circuit_id": "C07", + "parent_lineage": "textbook_universal_compiler_cropped", + "independent_source_lineages_added": 0, + "matched_pairs": [ + [ + "M1", + "M2" + ], + [ + "M3", + "M4" + ] + ], + "levels": [ + 4, + 8, + 12 + ], + "configurations": [ + { + "configuration_id": "c07_matched_nf_4_4", + "role": "development", + "parameters": { + "circuit": { + "circuit_id": "C07", + "name": "diff_pair_current_source_loads", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VIN2", + "VOUT1", + "VOUT2", + "VB1", + "IB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN1", + "IB1", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VOUT2", + "VIN2", + "IB1", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "pfet", + "nets": [ + "VOUT1", + "VB1", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M4", + "kind": "pfet", + "nets": [ + "VOUT2", + "VB1", + "VDD", + "VDD" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 192, + "files": [ + "Dataset/192/192.cir", + "Dataset/192/Port192.txt", + "Dataset/192/Pagenumber192.txt", + "Dataset/192/Book192.png", + "Dataset/192/Cadence192.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "260", + "device_name_map": { + "M1": "M0", + "M2": "M1", + "M3": "M2", + "M4": "M3" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/192/Book192.png", + "observation": "Razavi p.260 scan: M1/M2 pair with ideal tail current source symbol, M3/M4 PMOS current sources (Vb)" + }, + "modifications": [ + "tail node IB1 is a port: the tail current source is an ideal (disclosed) testbench source" + ], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M3": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M4": { + "w": 2.0, + "l": 0.3, + "nf": 4 + } + }, + "top_cell": "train_pair_nf_c07" + }, + "contract": { + "task_id": "c07_matched_pair_nf_v1", + "configuration_id": "c07_matched_nf_4_4", + "reference_id": "c07_matched_nf_4_4_literal_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_TRAIN_DOMAIN_IDEAL_QUALIFICATION_ONLY", + "objective": { + "id": "c07_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "differential_transconductance_S", + "unit": "S", + "min": 0.0001 + }, + { + "name": "differential_current_span_A", + "unit": "A", + "min": 2e-05 + }, + { + "name": "settled_current_error_vs_DC_A", + "unit": "A", + "max": 1e-09 + }, + { + "name": "main_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_common_mode_V": 0.9, + "clamped_outputs_V": [ + 0.9, + 0.9 + ], + "ideal_tail_sink_A": 4e-05, + "external_PMOS_replica_current_A": 2e-05, + "differential_AC_input_V": 1, + "differential_transient_levels_V": [ + -0.01, + 0.01 + ], + "differential_DC_sweep_V": [ + -0.1, + 0.1, + 0.005 + ], + "load_definition": "Each output has an ideal 0.9V clamp. Measure differential output-current transconductance, systematic offset and current steering, not free-output voltage gain or mismatch yield." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 6, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + } + }, + "numerical_controls": { + "integration_method": "trap", + "independent_transient_inputs": true, + "tight_tolerances_unchanged": true + }, + "power_definition": "Main VDD supply power only; separate diode-reference and output-clamp port work are reported separately." + }, + "reference_file": "c07/references/c07_matched_nf_4_4.spice" + }, + { + "configuration_id": "c07_matched_nf_4_8", + "role": "development", + "parameters": { + "circuit": { + "circuit_id": "C07", + "name": "diff_pair_current_source_loads", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VIN2", + "VOUT1", + "VOUT2", + "VB1", + "IB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN1", + "IB1", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VOUT2", + "VIN2", + "IB1", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "pfet", + "nets": [ + "VOUT1", + "VB1", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M4", + "kind": "pfet", + "nets": [ + "VOUT2", + "VB1", + "VDD", + "VDD" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 192, + "files": [ + "Dataset/192/192.cir", + "Dataset/192/Port192.txt", + "Dataset/192/Pagenumber192.txt", + "Dataset/192/Book192.png", + "Dataset/192/Cadence192.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "260", + "device_name_map": { + "M1": "M0", + "M2": "M1", + "M3": "M2", + "M4": "M3" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/192/Book192.png", + "observation": "Razavi p.260 scan: M1/M2 pair with ideal tail current source symbol, M3/M4 PMOS current sources (Vb)" + }, + "modifications": [ + "tail node IB1 is a port: the tail current source is an ideal (disclosed) testbench source" + ], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M3": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M4": { + "w": 4.0, + "l": 0.3, + "nf": 8 + } + }, + "top_cell": "train_pair_nf_c07" + }, + "contract": { + "task_id": "c07_matched_pair_nf_v1", + "configuration_id": "c07_matched_nf_4_8", + "reference_id": "c07_matched_nf_4_8_literal_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_TRAIN_DOMAIN_IDEAL_QUALIFICATION_ONLY", + "objective": { + "id": "c07_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "differential_transconductance_S", + "unit": "S", + "min": 0.0001 + }, + { + "name": "differential_current_span_A", + "unit": "A", + "min": 2e-05 + }, + { + "name": "settled_current_error_vs_DC_A", + "unit": "A", + "max": 1e-09 + }, + { + "name": "main_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_common_mode_V": 0.9, + "clamped_outputs_V": [ + 0.9, + 0.9 + ], + "ideal_tail_sink_A": 4e-05, + "external_PMOS_replica_current_A": 2e-05, + "differential_AC_input_V": 1, + "differential_transient_levels_V": [ + -0.01, + 0.01 + ], + "differential_DC_sweep_V": [ + -0.1, + 0.1, + 0.005 + ], + "load_definition": "Each output has an ideal 0.9V clamp. Measure differential output-current transconductance, systematic offset and current steering, not free-output voltage gain or mismatch yield." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 6, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + } + }, + "numerical_controls": { + "integration_method": "trap", + "independent_transient_inputs": true, + "tight_tolerances_unchanged": true + }, + "power_definition": "Main VDD supply power only; separate diode-reference and output-clamp port work are reported separately." + }, + "reference_file": "c07/references/c07_matched_nf_4_8.spice" + }, + { + "configuration_id": "c07_matched_nf_4_12", + "role": "development", + "parameters": { + "circuit": { + "circuit_id": "C07", + "name": "diff_pair_current_source_loads", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VIN2", + "VOUT1", + "VOUT2", + "VB1", + "IB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN1", + "IB1", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VOUT2", + "VIN2", + "IB1", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "pfet", + "nets": [ + "VOUT1", + "VB1", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M4", + "kind": "pfet", + "nets": [ + "VOUT2", + "VB1", + "VDD", + "VDD" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 192, + "files": [ + "Dataset/192/192.cir", + "Dataset/192/Port192.txt", + "Dataset/192/Pagenumber192.txt", + "Dataset/192/Book192.png", + "Dataset/192/Cadence192.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "260", + "device_name_map": { + "M1": "M0", + "M2": "M1", + "M3": "M2", + "M4": "M3" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/192/Book192.png", + "observation": "Razavi p.260 scan: M1/M2 pair with ideal tail current source symbol, M3/M4 PMOS current sources (Vb)" + }, + "modifications": [ + "tail node IB1 is a port: the tail current source is an ideal (disclosed) testbench source" + ], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M3": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M4": { + "w": 6.0, + "l": 0.3, + "nf": 12 + } + }, + "top_cell": "train_pair_nf_c07" + }, + "contract": { + "task_id": "c07_matched_pair_nf_v1", + "configuration_id": "c07_matched_nf_4_12", + "reference_id": "c07_matched_nf_4_12_literal_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_TRAIN_DOMAIN_IDEAL_QUALIFICATION_ONLY", + "objective": { + "id": "c07_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "differential_transconductance_S", + "unit": "S", + "min": 0.0001 + }, + { + "name": "differential_current_span_A", + "unit": "A", + "min": 2e-05 + }, + { + "name": "settled_current_error_vs_DC_A", + "unit": "A", + "max": 1e-09 + }, + { + "name": "main_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_common_mode_V": 0.9, + "clamped_outputs_V": [ + 0.9, + 0.9 + ], + "ideal_tail_sink_A": 4e-05, + "external_PMOS_replica_current_A": 2e-05, + "differential_AC_input_V": 1, + "differential_transient_levels_V": [ + -0.01, + 0.01 + ], + "differential_DC_sweep_V": [ + -0.1, + 0.1, + 0.005 + ], + "load_definition": "Each output has an ideal 0.9V clamp. Measure differential output-current transconductance, systematic offset and current steering, not free-output voltage gain or mismatch yield." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 6, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + } + }, + "numerical_controls": { + "integration_method": "trap", + "independent_transient_inputs": true, + "tight_tolerances_unchanged": true + }, + "power_definition": "Main VDD supply power only; separate diode-reference and output-clamp port work are reported separately." + }, + "reference_file": "c07/references/c07_matched_nf_4_12.spice" + }, + { + "configuration_id": "c07_matched_nf_8_4", + "role": "development", + "parameters": { + "circuit": { + "circuit_id": "C07", + "name": "diff_pair_current_source_loads", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VIN2", + "VOUT1", + "VOUT2", + "VB1", + "IB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN1", + "IB1", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VOUT2", + "VIN2", + "IB1", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "pfet", + "nets": [ + "VOUT1", + "VB1", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M4", + "kind": "pfet", + "nets": [ + "VOUT2", + "VB1", + "VDD", + "VDD" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 192, + "files": [ + "Dataset/192/192.cir", + "Dataset/192/Port192.txt", + "Dataset/192/Pagenumber192.txt", + "Dataset/192/Book192.png", + "Dataset/192/Cadence192.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "260", + "device_name_map": { + "M1": "M0", + "M2": "M1", + "M3": "M2", + "M4": "M3" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/192/Book192.png", + "observation": "Razavi p.260 scan: M1/M2 pair with ideal tail current source symbol, M3/M4 PMOS current sources (Vb)" + }, + "modifications": [ + "tail node IB1 is a port: the tail current source is an ideal (disclosed) testbench source" + ], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M3": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M4": { + "w": 2.0, + "l": 0.3, + "nf": 4 + } + }, + "top_cell": "train_pair_nf_c07" + }, + "contract": { + "task_id": "c07_matched_pair_nf_v1", + "configuration_id": "c07_matched_nf_8_4", + "reference_id": "c07_matched_nf_8_4_literal_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_TRAIN_DOMAIN_IDEAL_QUALIFICATION_ONLY", + "objective": { + "id": "c07_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "differential_transconductance_S", + "unit": "S", + "min": 0.0001 + }, + { + "name": "differential_current_span_A", + "unit": "A", + "min": 2e-05 + }, + { + "name": "settled_current_error_vs_DC_A", + "unit": "A", + "max": 1e-09 + }, + { + "name": "main_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_common_mode_V": 0.9, + "clamped_outputs_V": [ + 0.9, + 0.9 + ], + "ideal_tail_sink_A": 4e-05, + "external_PMOS_replica_current_A": 2e-05, + "differential_AC_input_V": 1, + "differential_transient_levels_V": [ + -0.01, + 0.01 + ], + "differential_DC_sweep_V": [ + -0.1, + 0.1, + 0.005 + ], + "load_definition": "Each output has an ideal 0.9V clamp. Measure differential output-current transconductance, systematic offset and current steering, not free-output voltage gain or mismatch yield." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 6, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + } + }, + "numerical_controls": { + "integration_method": "trap", + "independent_transient_inputs": true, + "tight_tolerances_unchanged": true + }, + "power_definition": "Main VDD supply power only; separate diode-reference and output-clamp port work are reported separately." + }, + "reference_file": "c07/references/c07_matched_nf_8_4.spice" + }, + { + "configuration_id": "c07_matched_nf_8_8", + "role": "anchor", + "parameters": { + "circuit": { + "circuit_id": "C07", + "name": "diff_pair_current_source_loads", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VIN2", + "VOUT1", + "VOUT2", + "VB1", + "IB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN1", + "IB1", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VOUT2", + "VIN2", + "IB1", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "pfet", + "nets": [ + "VOUT1", + "VB1", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M4", + "kind": "pfet", + "nets": [ + "VOUT2", + "VB1", + "VDD", + "VDD" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 192, + "files": [ + "Dataset/192/192.cir", + "Dataset/192/Port192.txt", + "Dataset/192/Pagenumber192.txt", + "Dataset/192/Book192.png", + "Dataset/192/Cadence192.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "260", + "device_name_map": { + "M1": "M0", + "M2": "M1", + "M3": "M2", + "M4": "M3" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/192/Book192.png", + "observation": "Razavi p.260 scan: M1/M2 pair with ideal tail current source symbol, M3/M4 PMOS current sources (Vb)" + }, + "modifications": [ + "tail node IB1 is a port: the tail current source is an ideal (disclosed) testbench source" + ], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M3": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M4": { + "w": 4.0, + "l": 0.3, + "nf": 8 + } + }, + "top_cell": "train_pair_nf_c07" + }, + "contract": { + "task_id": "c07_matched_pair_nf_v1", + "configuration_id": "c07_matched_nf_8_8", + "reference_id": "c07_matched_nf_8_8_literal_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_TRAIN_DOMAIN_IDEAL_QUALIFICATION_ONLY", + "objective": { + "id": "c07_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "differential_transconductance_S", + "unit": "S", + "min": 0.0001 + }, + { + "name": "differential_current_span_A", + "unit": "A", + "min": 2e-05 + }, + { + "name": "settled_current_error_vs_DC_A", + "unit": "A", + "max": 1e-09 + }, + { + "name": "main_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_common_mode_V": 0.9, + "clamped_outputs_V": [ + 0.9, + 0.9 + ], + "ideal_tail_sink_A": 4e-05, + "external_PMOS_replica_current_A": 2e-05, + "differential_AC_input_V": 1, + "differential_transient_levels_V": [ + -0.01, + 0.01 + ], + "differential_DC_sweep_V": [ + -0.1, + 0.1, + 0.005 + ], + "load_definition": "Each output has an ideal 0.9V clamp. Measure differential output-current transconductance, systematic offset and current steering, not free-output voltage gain or mismatch yield." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 6, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + } + }, + "numerical_controls": { + "integration_method": "trap", + "independent_transient_inputs": true, + "tight_tolerances_unchanged": true + }, + "power_definition": "Main VDD supply power only; separate diode-reference and output-clamp port work are reported separately." + }, + "reference_file": "c07/references/c07_matched_nf_8_8.spice" + }, + { + "configuration_id": "c07_matched_nf_8_12", + "role": "development", + "parameters": { + "circuit": { + "circuit_id": "C07", + "name": "diff_pair_current_source_loads", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VIN2", + "VOUT1", + "VOUT2", + "VB1", + "IB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN1", + "IB1", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VOUT2", + "VIN2", + "IB1", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "pfet", + "nets": [ + "VOUT1", + "VB1", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M4", + "kind": "pfet", + "nets": [ + "VOUT2", + "VB1", + "VDD", + "VDD" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 192, + "files": [ + "Dataset/192/192.cir", + "Dataset/192/Port192.txt", + "Dataset/192/Pagenumber192.txt", + "Dataset/192/Book192.png", + "Dataset/192/Cadence192.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "260", + "device_name_map": { + "M1": "M0", + "M2": "M1", + "M3": "M2", + "M4": "M3" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/192/Book192.png", + "observation": "Razavi p.260 scan: M1/M2 pair with ideal tail current source symbol, M3/M4 PMOS current sources (Vb)" + }, + "modifications": [ + "tail node IB1 is a port: the tail current source is an ideal (disclosed) testbench source" + ], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M2": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M3": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M4": { + "w": 6.0, + "l": 0.3, + "nf": 12 + } + }, + "top_cell": "train_pair_nf_c07" + }, + "contract": { + "task_id": "c07_matched_pair_nf_v1", + "configuration_id": "c07_matched_nf_8_12", + "reference_id": "c07_matched_nf_8_12_literal_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_TRAIN_DOMAIN_IDEAL_QUALIFICATION_ONLY", + "objective": { + "id": "c07_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "differential_transconductance_S", + "unit": "S", + "min": 0.0001 + }, + { + "name": "differential_current_span_A", + "unit": "A", + "min": 2e-05 + }, + { + "name": "settled_current_error_vs_DC_A", + "unit": "A", + "max": 1e-09 + }, + { + "name": "main_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_common_mode_V": 0.9, + "clamped_outputs_V": [ + 0.9, + 0.9 + ], + "ideal_tail_sink_A": 4e-05, + "external_PMOS_replica_current_A": 2e-05, + "differential_AC_input_V": 1, + "differential_transient_levels_V": [ + -0.01, + 0.01 + ], + "differential_DC_sweep_V": [ + -0.1, + 0.1, + 0.005 + ], + "load_definition": "Each output has an ideal 0.9V clamp. Measure differential output-current transconductance, systematic offset and current steering, not free-output voltage gain or mismatch yield." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 6, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + } + }, + "numerical_controls": { + "integration_method": "trap", + "independent_transient_inputs": true, + "tight_tolerances_unchanged": true + }, + "power_definition": "Main VDD supply power only; separate diode-reference and output-clamp port work are reported separately." + }, + "reference_file": "c07/references/c07_matched_nf_8_12.spice" + }, + { + "configuration_id": "c07_matched_nf_12_4", + "role": "development", + "parameters": { + "circuit": { + "circuit_id": "C07", + "name": "diff_pair_current_source_loads", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VIN2", + "VOUT1", + "VOUT2", + "VB1", + "IB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN1", + "IB1", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VOUT2", + "VIN2", + "IB1", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "pfet", + "nets": [ + "VOUT1", + "VB1", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M4", + "kind": "pfet", + "nets": [ + "VOUT2", + "VB1", + "VDD", + "VDD" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 192, + "files": [ + "Dataset/192/192.cir", + "Dataset/192/Port192.txt", + "Dataset/192/Pagenumber192.txt", + "Dataset/192/Book192.png", + "Dataset/192/Cadence192.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "260", + "device_name_map": { + "M1": "M0", + "M2": "M1", + "M3": "M2", + "M4": "M3" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/192/Book192.png", + "observation": "Razavi p.260 scan: M1/M2 pair with ideal tail current source symbol, M3/M4 PMOS current sources (Vb)" + }, + "modifications": [ + "tail node IB1 is a port: the tail current source is an ideal (disclosed) testbench source" + ], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M3": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M4": { + "w": 2.0, + "l": 0.3, + "nf": 4 + } + }, + "top_cell": "train_pair_nf_c07" + }, + "contract": { + "task_id": "c07_matched_pair_nf_v1", + "configuration_id": "c07_matched_nf_12_4", + "reference_id": "c07_matched_nf_12_4_literal_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_TRAIN_DOMAIN_IDEAL_QUALIFICATION_ONLY", + "objective": { + "id": "c07_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "differential_transconductance_S", + "unit": "S", + "min": 0.0001 + }, + { + "name": "differential_current_span_A", + "unit": "A", + "min": 2e-05 + }, + { + "name": "settled_current_error_vs_DC_A", + "unit": "A", + "max": 1e-09 + }, + { + "name": "main_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_common_mode_V": 0.9, + "clamped_outputs_V": [ + 0.9, + 0.9 + ], + "ideal_tail_sink_A": 4e-05, + "external_PMOS_replica_current_A": 2e-05, + "differential_AC_input_V": 1, + "differential_transient_levels_V": [ + -0.01, + 0.01 + ], + "differential_DC_sweep_V": [ + -0.1, + 0.1, + 0.005 + ], + "load_definition": "Each output has an ideal 0.9V clamp. Measure differential output-current transconductance, systematic offset and current steering, not free-output voltage gain or mismatch yield." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 6, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + } + }, + "numerical_controls": { + "integration_method": "trap", + "independent_transient_inputs": true, + "tight_tolerances_unchanged": true + }, + "power_definition": "Main VDD supply power only; separate diode-reference and output-clamp port work are reported separately." + }, + "reference_file": "c07/references/c07_matched_nf_12_4.spice" + }, + { + "configuration_id": "c07_matched_nf_12_8", + "role": "development", + "parameters": { + "circuit": { + "circuit_id": "C07", + "name": "diff_pair_current_source_loads", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VIN2", + "VOUT1", + "VOUT2", + "VB1", + "IB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN1", + "IB1", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VOUT2", + "VIN2", + "IB1", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "pfet", + "nets": [ + "VOUT1", + "VB1", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M4", + "kind": "pfet", + "nets": [ + "VOUT2", + "VB1", + "VDD", + "VDD" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 192, + "files": [ + "Dataset/192/192.cir", + "Dataset/192/Port192.txt", + "Dataset/192/Pagenumber192.txt", + "Dataset/192/Book192.png", + "Dataset/192/Cadence192.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "260", + "device_name_map": { + "M1": "M0", + "M2": "M1", + "M3": "M2", + "M4": "M3" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/192/Book192.png", + "observation": "Razavi p.260 scan: M1/M2 pair with ideal tail current source symbol, M3/M4 PMOS current sources (Vb)" + }, + "modifications": [ + "tail node IB1 is a port: the tail current source is an ideal (disclosed) testbench source" + ], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M3": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M4": { + "w": 4.0, + "l": 0.3, + "nf": 8 + } + }, + "top_cell": "train_pair_nf_c07" + }, + "contract": { + "task_id": "c07_matched_pair_nf_v1", + "configuration_id": "c07_matched_nf_12_8", + "reference_id": "c07_matched_nf_12_8_literal_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_TRAIN_DOMAIN_IDEAL_QUALIFICATION_ONLY", + "objective": { + "id": "c07_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "differential_transconductance_S", + "unit": "S", + "min": 0.0001 + }, + { + "name": "differential_current_span_A", + "unit": "A", + "min": 2e-05 + }, + { + "name": "settled_current_error_vs_DC_A", + "unit": "A", + "max": 1e-09 + }, + { + "name": "main_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_common_mode_V": 0.9, + "clamped_outputs_V": [ + 0.9, + 0.9 + ], + "ideal_tail_sink_A": 4e-05, + "external_PMOS_replica_current_A": 2e-05, + "differential_AC_input_V": 1, + "differential_transient_levels_V": [ + -0.01, + 0.01 + ], + "differential_DC_sweep_V": [ + -0.1, + 0.1, + 0.005 + ], + "load_definition": "Each output has an ideal 0.9V clamp. Measure differential output-current transconductance, systematic offset and current steering, not free-output voltage gain or mismatch yield." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 6, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + } + }, + "numerical_controls": { + "integration_method": "trap", + "independent_transient_inputs": true, + "tight_tolerances_unchanged": true + }, + "power_definition": "Main VDD supply power only; separate diode-reference and output-clamp port work are reported separately." + }, + "reference_file": "c07/references/c07_matched_nf_12_8.spice" + }, + { + "configuration_id": "c07_matched_nf_12_12", + "role": "development", + "parameters": { + "circuit": { + "circuit_id": "C07", + "name": "diff_pair_current_source_loads", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VIN2", + "VOUT1", + "VOUT2", + "VB1", + "IB1" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "VOUT1", + "VIN1", + "IB1", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "nfet", + "nets": [ + "VOUT2", + "VIN2", + "IB1", + "VSS" + ], + "params": {} + }, + { + "name": "M3", + "kind": "pfet", + "nets": [ + "VOUT1", + "VB1", + "VDD", + "VDD" + ], + "params": {} + }, + { + "name": "M4", + "kind": "pfet", + "nets": [ + "VOUT2", + "VB1", + "VDD", + "VDD" + ], + "params": {} + } + ], + "source": { + "dataset": "AnalogGenie", + "dataset_url": "https://github.com/xz-group/AnalogGenie", + "dataset_sha": "efc25358939c6bedd247f28d3df61066964f3a90", + "dataset_license": "MIT (code and dataset repository)", + "analoggenie_id": 192, + "files": [ + "Dataset/192/192.cir", + "Dataset/192/Port192.txt", + "Dataset/192/Pagenumber192.txt", + "Dataset/192/Book192.png", + "Dataset/192/Cadence192.png" + ], + "book": "B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017", + "book_key": "razavi", + "page_ref": "260", + "device_name_map": { + "M1": "M0", + "M2": "M1", + "M3": "M2", + "M4": "M3" + }, + "source_verification_level": "netlist_matched_isomorphic+image_checked", + "image_review": { + "file": "Dataset/192/Book192.png", + "observation": "Razavi p.260 scan: M1/M2 pair with ideal tail current source symbol, M3/M4 PMOS current sources (Vb)" + }, + "modifications": [ + "tail node IB1 is a port: the tail current source is an ideal (disclosed) testbench source" + ], + "textbook_image_note": "Book.png (textbook scan) and Cadence.png (schematic capture) ship inside the public AnalogGenie repository; for entries marked 'image_checked' the scan was compared with the netlist when the benchmark was built. The scans are not redistributed here." + }, + "notes": [] + }, + "sizing": { + "M1": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M3": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M4": { + "w": 6.0, + "l": 0.3, + "nf": 12 + } + }, + "top_cell": "train_pair_nf_c07" + }, + "contract": { + "task_id": "c07_matched_pair_nf_v1", + "configuration_id": "c07_matched_nf_12_12", + "reference_id": "c07_matched_nf_12_12_literal_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_TRAIN_DOMAIN_IDEAL_QUALIFICATION_ONLY", + "objective": { + "id": "c07_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [ + { + "name": "differential_transconductance_S", + "unit": "S", + "min": 0.0001 + }, + { + "name": "differential_current_span_A", + "unit": "A", + "min": 2e-05 + }, + { + "name": "settled_current_error_vs_DC_A", + "unit": "A", + "max": 1e-09 + }, + { + "name": "main_supply_power_W", + "unit": "W", + "max": 0.0001 + } + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "input_common_mode_V": 0.9, + "clamped_outputs_V": [ + 0.9, + 0.9 + ], + "ideal_tail_sink_A": 4e-05, + "external_PMOS_replica_current_A": 2e-05, + "differential_AC_input_V": 1, + "differential_transient_levels_V": [ + -0.01, + 0.01 + ], + "differential_DC_sweep_V": [ + -0.1, + 0.1, + 0.005 + ], + "load_definition": "Each output has an ideal 0.9V clamp. Measure differential output-current transconductance, systematic offset and current steering, not free-output voltage gain or mismatch yield." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 6, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + } + }, + "numerical_controls": { + "integration_method": "trap", + "independent_transient_inputs": true, + "tight_tolerances_unchanged": true + }, + "power_definition": "Main VDD supply power only; separate diode-reference and output-clamp port work are reported separately." + }, + "reference_file": "c07/references/c07_matched_nf_12_12.spice" + } + ], + "whole_grid_preserved": true, + "width_semantics": "w is total width; w/nf=.5um for every finger; matching partners always share nf and dimensions.", + "specifications_bias_load_corners_numerical_controls": "Copied unchanged from the actual frozen train family. No post-layout outcome used to select these points.", + "qualification_status": "NOT_RUN", + "formal_training_rows": 0, + "parent_frozen_registry": "runtime/train_collections/c07_action_v1/registry.json" + } + ], + "new_model_calls": 0, + "new_simulations": 0, + "old_domain_or_frozen_collection_changed": false +} diff --git a/benchmarks/code_behind_layout/configs/development/train_source_pack.json b/benchmarks/code_behind_layout/configs/development/train_source_pack.json new file mode 100644 index 00000000..b9e73ea1 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_source_pack.json @@ -0,0 +1,103 @@ +{ + "status": "DEVELOPMENT_SOURCE_SCOPE_NOT_FROZEN", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "actual_pack_remote": "/srv/code-behind-layout/runs/phase0/phase0_20261018T234220871091Z_fvf_textbook_cropped_source_smoke/source_pack", + "crop_evidence_run": "phase0_20261018T234220871091Z_fvf_textbook_cropped_source_smoke", + "editable_paths": [ + "textbook_sharing/layout.py" + ], + "editable_module_bytes": 5937, + "frozen_library_files": [ + "LICENSE", + "glayout/__init__.py", + "glayout/backend/__init__.py", + "glayout/backend/_gdsfactory.py", + "glayout/backend/_gdstk.py", + "glayout/pdk/__init__.py", + "glayout/pdk/gf180_mapped/__init__.py", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x02p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x04p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x08p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x16p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_05p00x05p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_10p00x10p00.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_05p00x00p42.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_05p00x05p00.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_10p00x00p42.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_10p00x10p00.gds", + "glayout/pdk/gf180_mapped/gf180_grules.py", + "glayout/pdk/gf180_mapped/gf180_mapped.py", + "glayout/pdk/gf180_mapped/gf180mcu.drc", + "glayout/pdk/gf180_mapped/gf180mcu_drc.lydrc", + "glayout/pdk/gf180_mapped/gf180mcu_drc_wrapper.drc", + "glayout/pdk/gf180_mapped/gf180mcu_osu_sc_9T.spice", + "glayout/pdk/ihp130_mapped/__init__.py", + "glayout/pdk/ihp130_mapped/ihp130_drc.lydrc", + "glayout/pdk/ihp130_mapped/ihp130_grules.py", + "glayout/pdk/ihp130_mapped/ihp130_mapped.py", + "glayout/pdk/mappedpdk.py", + "glayout/pdk/sky130_mapped/__init__.py", + "glayout/pdk/sky130_mapped/sky130.lydrc", + "glayout/pdk/sky130_mapped/sky130_add_npc.py", + "glayout/pdk/sky130_mapped/sky130_fd_sc_hd.spice", + "glayout/pdk/sky130_mapped/sky130_grules.py", + "glayout/pdk/sky130_mapped/sky130_mapped.py", + "glayout/placement/__init__.py", + "glayout/placement/common_centroid_ab_ba.py", + "glayout/placement/four_transistor_interdigitized.py", + "glayout/placement/two_transistor_interdigitized.py", + "glayout/placement/two_transistor_place.py", + "glayout/primitives/__init__.py", + "glayout/primitives/bjt.py", + "glayout/primitives/fet.py", + "glayout/primitives/guardring.py", + "glayout/primitives/mimcap.py", + "glayout/primitives/resistor.py", + "glayout/primitives/via_gen.py", + "glayout/routing/L_route.py", + "glayout/routing/__init__.py", + "glayout/routing/c_route.py", + "glayout/routing/smart_route.py", + "glayout/routing/straight_route.py", + "glayout/sharing/README.md", + "glayout/sharing/__init__.py", + "glayout/sharing/enumeration.py", + "glayout/sharing/evidence.py", + "glayout/sharing/group.py", + "glayout/sharing/rules.py", + "glayout/sharing/spec.py", + "glayout/spice/__init__.py", + "glayout/spice/netlist.py", + "glayout/util/__init__.py", + "glayout/util/comp_utils.py", + "glayout/util/component_array_create.py", + "glayout/util/geometry.py", + "glayout/util/pattern.py", + "glayout/util/port_utils.py", + "glayout/util/print_rules.py", + "glayout/util/routing.py", + "glayout/util/snap_to_grid.py", + "textbook_sharing/__init__.py", + "textbook_sharing/assembly/__init__.py", + "textbook_sharing/assembly/adapters.py", + "textbook_sharing/assembly/engine.py", + "textbook_sharing/assembly/passives.py", + "textbook_sharing/assembly/pincell.py", + "textbook_sharing/netlist.py" + ], + "initial_descriptor": "C08_only_in_source_crop_smoke_replaced_by_individually_exported_C01_C05_C08_inputs_in_yield_pilot", + "excluded": [ + "glayout/cells", + "glayout/blocks", + "textbook_sharing/circuits.py", + "nominal.py", + "cases.py", + "old_results", + "public_search_and_evaluator", + "C11_Miller", + "C18_classAB" + ], + "formal_train_examples": 0, + "formal_admission": false, + "larger_modules_need_explicit_refactoring_or_longer_context_before_editing": "assembly/engine.py36621B and sharing/group.py24174B remain complete frozen libraries, never silently truncated" +} diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/train_tg01_family/circuit_input.json new file mode 100644 index 00000000..7e839316 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_family/circuit_input.json @@ -0,0 +1,45 @@ +{ + "circuit_id": "TRAIN_TG01", + "name": "authored_complementary_transmission_gate", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VOUT1", + "VC1", + "VC2" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "VOUT1", + "VC1", + "VIN1", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "pfet", + "nets": [ + "VOUT1", + "VC2", + "VIN1", + "VDD" + ], + "params": {} + } + ], + "source": { + "kind": "new_authored_task_descriptor", + "author_role": "research_engineering", + "not_an_existing_public_C04": "Public C04 is a common-source amplifier; no TG exists among the public18 descriptors.", + "graph": "Parallel NMOS/PMOS channels; complementary external controls, separate well/body rails." + }, + "notes": [ + "Circuit input to the same public universal compiler, not an independent generator lineage." + ] +} diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_family/configurations.json b/benchmarks/code_behind_layout/configs/development/train_tg01_family/configurations.json new file mode 100644 index 00000000..8269c9fb --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_family/configurations.json @@ -0,0 +1,190 @@ +{ + "scope": "development_only_train_component_qualification", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "TRAIN_TG01", + "circuit_input_file": "configs/development/train_tg01_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 0.3, + "nf": 8 + } + } + }, + "reference_file": "configs/development/train_tg01_family/references/anchor.spice", + "contract_file": "configs/development/train_tg01_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.0, + "l": 0.3, + "nf": 2 + }, + "M2": { + "w": 2.0, + "l": 0.3, + "nf": 4 + } + } + }, + "reference_file": "configs/development/train_tg01_family/references/dev_nf_half.spice", + "contract_file": "configs/development/train_tg01_family/contracts/dev_nf_half.json" + }, + { + "configuration_id": "dev_nf_3quarters", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 1.5, + "l": 0.3, + "nf": 3 + }, + "M2": { + "w": 3.0, + "l": 0.3, + "nf": 6 + } + } + }, + "reference_file": "configs/development/train_tg01_family/references/dev_nf_3quarters.spice", + "contract_file": "configs/development/train_tg01_family/contracts/dev_nf_3quarters.json" + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.3, + "nf": 6 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 12 + } + } + }, + "reference_file": "configs/development/train_tg01_family/references/dev_nf_1half.spice", + "contract_file": "configs/development/train_tg01_family/contracts/dev_nf_1half.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M2": { + "w": 8.0, + "l": 0.3, + "nf": 16 + } + } + }, + "reference_file": "configs/development/train_tg01_family/references/dev_nf_double.spice", + "contract_file": "configs/development/train_tg01_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len045", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.45, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 0.45, + "nf": 8 + } + } + }, + "reference_file": "configs/development/train_tg01_family/references/dev_len045.spice", + "contract_file": "configs/development/train_tg01_family/contracts/dev_len045.json" + }, + { + "configuration_id": "dev_len060", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 2.0, + "l": 0.6, + "nf": 4 + }, + "M2": { + "w": 4.0, + "l": 0.6, + "nf": 8 + } + } + }, + "reference_file": "configs/development/train_tg01_family/references/dev_len060.spice", + "contract_file": "configs/development/train_tg01_family/contracts/dev_len060.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 3.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 6.0, + "l": 0.3, + "nf": 8 + } + } + }, + "reference_file": "configs/development/train_tg01_family/references/dev_unit075.spice", + "contract_file": "configs/development/train_tg01_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_unit100", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.3, + "nf": 4 + }, + "M2": { + "w": 8.0, + "l": 0.3, + "nf": 8 + } + } + }, + "reference_file": "configs/development/train_tg01_family/references/dev_unit100.spice", + "contract_file": "configs/development/train_tg01_family/contracts/dev_unit100.json" + } + ], + "ancestry": "One cropped public universal compiler source lineage; new descriptors and geometry configurations are not new source implementations." +} diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/anchor.json new file mode 100644 index 00000000..85dbcb15 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/anchor.json @@ -0,0 +1,96 @@ +{ + "task_id": "development_train_domain_train_tg01", + "configuration_id": "anchor", + "reference_id": "train_tg01_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "train_tg01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "on_controls_V": [ + 1.8, + 0 + ], + "off_controls_V": [ + 0, + 1.8 + ], + "nominal_input_V": 0.9, + "on_load_R_ohm": 100000, + "on_load_C_F": 1e-12, + "input_DC_sweep_V": [ + 0.1, + 1.7, + 0.1 + ], + "input_transient_levels_V": [ + 0.2, + 1.6 + ], + "off_output_clamp_V": 0.9, + "load_definition": "Enabled signal transfer uses100kOhm||1pF; disabled leakage uses only an ideal0.9V output clamp, without the load resistor. Controls are static, so no switching-charge-injection claim.", + "power_definition": "Signal-source work, external resistor dissipation, main well-supply work and channel conduction loss are separate quantities." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + }, + "off": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/dev_len045.json b/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/dev_len045.json new file mode 100644 index 00000000..a1268d97 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/dev_len045.json @@ -0,0 +1,96 @@ +{ + "task_id": "development_train_domain_train_tg01", + "configuration_id": "dev_len045", + "reference_id": "train_tg01_dev_len045_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "train_tg01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "on_controls_V": [ + 1.8, + 0 + ], + "off_controls_V": [ + 0, + 1.8 + ], + "nominal_input_V": 0.9, + "on_load_R_ohm": 100000, + "on_load_C_F": 1e-12, + "input_DC_sweep_V": [ + 0.1, + 1.7, + 0.1 + ], + "input_transient_levels_V": [ + 0.2, + 1.6 + ], + "off_output_clamp_V": 0.9, + "load_definition": "Enabled signal transfer uses100kOhm||1pF; disabled leakage uses only an ideal0.9V output clamp, without the load resistor. Controls are static, so no switching-charge-injection claim.", + "power_definition": "Signal-source work, external resistor dissipation, main well-supply work and channel conduction loss are separate quantities." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + }, + "off": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/dev_len060.json b/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/dev_len060.json new file mode 100644 index 00000000..d0b9944f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/dev_len060.json @@ -0,0 +1,96 @@ +{ + "task_id": "development_train_domain_train_tg01", + "configuration_id": "dev_len060", + "reference_id": "train_tg01_dev_len060_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "train_tg01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "on_controls_V": [ + 1.8, + 0 + ], + "off_controls_V": [ + 0, + 1.8 + ], + "nominal_input_V": 0.9, + "on_load_R_ohm": 100000, + "on_load_C_F": 1e-12, + "input_DC_sweep_V": [ + 0.1, + 1.7, + 0.1 + ], + "input_transient_levels_V": [ + 0.2, + 1.6 + ], + "off_output_clamp_V": 0.9, + "load_definition": "Enabled signal transfer uses100kOhm||1pF; disabled leakage uses only an ideal0.9V output clamp, without the load resistor. Controls are static, so no switching-charge-injection claim.", + "power_definition": "Signal-source work, external resistor dissipation, main well-supply work and channel conduction loss are separate quantities." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + }, + "off": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/dev_nf_1half.json b/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/dev_nf_1half.json new file mode 100644 index 00000000..0e079601 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/dev_nf_1half.json @@ -0,0 +1,96 @@ +{ + "task_id": "development_train_domain_train_tg01", + "configuration_id": "dev_nf_1half", + "reference_id": "train_tg01_dev_nf_1half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "train_tg01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "on_controls_V": [ + 1.8, + 0 + ], + "off_controls_V": [ + 0, + 1.8 + ], + "nominal_input_V": 0.9, + "on_load_R_ohm": 100000, + "on_load_C_F": 1e-12, + "input_DC_sweep_V": [ + 0.1, + 1.7, + 0.1 + ], + "input_transient_levels_V": [ + 0.2, + 1.6 + ], + "off_output_clamp_V": 0.9, + "load_definition": "Enabled signal transfer uses100kOhm||1pF; disabled leakage uses only an ideal0.9V output clamp, without the load resistor. Controls are static, so no switching-charge-injection claim.", + "power_definition": "Signal-source work, external resistor dissipation, main well-supply work and channel conduction loss are separate quantities." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + }, + "off": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/dev_nf_3quarters.json b/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/dev_nf_3quarters.json new file mode 100644 index 00000000..78eef906 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/dev_nf_3quarters.json @@ -0,0 +1,96 @@ +{ + "task_id": "development_train_domain_train_tg01", + "configuration_id": "dev_nf_3quarters", + "reference_id": "train_tg01_dev_nf_3quarters_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "train_tg01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "on_controls_V": [ + 1.8, + 0 + ], + "off_controls_V": [ + 0, + 1.8 + ], + "nominal_input_V": 0.9, + "on_load_R_ohm": 100000, + "on_load_C_F": 1e-12, + "input_DC_sweep_V": [ + 0.1, + 1.7, + 0.1 + ], + "input_transient_levels_V": [ + 0.2, + 1.6 + ], + "off_output_clamp_V": 0.9, + "load_definition": "Enabled signal transfer uses100kOhm||1pF; disabled leakage uses only an ideal0.9V output clamp, without the load resistor. Controls are static, so no switching-charge-injection claim.", + "power_definition": "Signal-source work, external resistor dissipation, main well-supply work and channel conduction loss are separate quantities." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + }, + "off": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..2f6561b9 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/dev_nf_double.json @@ -0,0 +1,96 @@ +{ + "task_id": "development_train_domain_train_tg01", + "configuration_id": "dev_nf_double", + "reference_id": "train_tg01_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "train_tg01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "on_controls_V": [ + 1.8, + 0 + ], + "off_controls_V": [ + 0, + 1.8 + ], + "nominal_input_V": 0.9, + "on_load_R_ohm": 100000, + "on_load_C_F": 1e-12, + "input_DC_sweep_V": [ + 0.1, + 1.7, + 0.1 + ], + "input_transient_levels_V": [ + 0.2, + 1.6 + ], + "off_output_clamp_V": 0.9, + "load_definition": "Enabled signal transfer uses100kOhm||1pF; disabled leakage uses only an ideal0.9V output clamp, without the load resistor. Controls are static, so no switching-charge-injection claim.", + "power_definition": "Signal-source work, external resistor dissipation, main well-supply work and channel conduction loss are separate quantities." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + }, + "off": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/dev_nf_half.json b/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/dev_nf_half.json new file mode 100644 index 00000000..1dddb791 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/dev_nf_half.json @@ -0,0 +1,96 @@ +{ + "task_id": "development_train_domain_train_tg01", + "configuration_id": "dev_nf_half", + "reference_id": "train_tg01_dev_nf_half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "train_tg01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "on_controls_V": [ + 1.8, + 0 + ], + "off_controls_V": [ + 0, + 1.8 + ], + "nominal_input_V": 0.9, + "on_load_R_ohm": 100000, + "on_load_C_F": 1e-12, + "input_DC_sweep_V": [ + 0.1, + 1.7, + 0.1 + ], + "input_transient_levels_V": [ + 0.2, + 1.6 + ], + "off_output_clamp_V": 0.9, + "load_definition": "Enabled signal transfer uses100kOhm||1pF; disabled leakage uses only an ideal0.9V output clamp, without the load resistor. Controls are static, so no switching-charge-injection claim.", + "power_definition": "Signal-source work, external resistor dissipation, main well-supply work and channel conduction loss are separate quantities." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + }, + "off": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/dev_unit075.json new file mode 100644 index 00000000..52f43847 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/dev_unit075.json @@ -0,0 +1,96 @@ +{ + "task_id": "development_train_domain_train_tg01", + "configuration_id": "dev_unit075", + "reference_id": "train_tg01_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "train_tg01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "on_controls_V": [ + 1.8, + 0 + ], + "off_controls_V": [ + 0, + 1.8 + ], + "nominal_input_V": 0.9, + "on_load_R_ohm": 100000, + "on_load_C_F": 1e-12, + "input_DC_sweep_V": [ + 0.1, + 1.7, + 0.1 + ], + "input_transient_levels_V": [ + 0.2, + 1.6 + ], + "off_output_clamp_V": 0.9, + "load_definition": "Enabled signal transfer uses100kOhm||1pF; disabled leakage uses only an ideal0.9V output clamp, without the load resistor. Controls are static, so no switching-charge-injection claim.", + "power_definition": "Signal-source work, external resistor dissipation, main well-supply work and channel conduction loss are separate quantities." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + }, + "off": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/dev_unit100.json b/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/dev_unit100.json new file mode 100644 index 00000000..6d6def0b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_family/contracts/dev_unit100.json @@ -0,0 +1,96 @@ +{ + "task_id": "development_train_domain_train_tg01", + "configuration_id": "dev_unit100", + "reference_id": "train_tg01_dev_unit100_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "train_tg01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "on_controls_V": [ + 1.8, + 0 + ], + "off_controls_V": [ + 0, + 1.8 + ], + "nominal_input_V": 0.9, + "on_load_R_ohm": 100000, + "on_load_C_F": 1e-12, + "input_DC_sweep_V": [ + 0.1, + 1.7, + 0.1 + ], + "input_transient_levels_V": [ + 0.2, + 1.6 + ], + "off_output_clamp_V": 0.9, + "load_definition": "Enabled signal transfer uses100kOhm||1pF; disabled leakage uses only an ideal0.9V output clamp, without the load resistor. Controls are static, so no switching-charge-injection claim.", + "power_definition": "Signal-source work, external resistor dissipation, main well-supply work and channel conduction loss are separate quantities." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + }, + "off": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + } + } +} diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/anchor.spice new file mode 100644 index 00000000..fed8a471 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/anchor.spice @@ -0,0 +1,14 @@ +.subckt corpus_train_tg01 VDD VSS VIN1 VOUT1 VC1 VC2 +XM1_f0 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_train_tg01 diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_len045.spice b/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_len045.spice new file mode 100644 index 00000000..9348db0e --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_len045.spice @@ -0,0 +1,14 @@ +.subckt corpus_train_tg01 VDD VSS VIN1 VOUT1 VC1 VC2 +XM1_f0 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f1 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f2 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f3 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f0 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f1 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f2 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f3 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f4 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f5 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f6 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f7 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +.ends corpus_train_tg01 diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_len060.spice b/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_len060.spice new file mode 100644 index 00000000..85ba1002 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_len060.spice @@ -0,0 +1,14 @@ +.subckt corpus_train_tg01 VDD VSS VIN1 VOUT1 VC1 VC2 +XM1_f0 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f1 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f2 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f3 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f4 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f5 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f6 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f7 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +.ends corpus_train_tg01 diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_nf_1half.spice b/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_nf_1half.spice new file mode 100644 index 00000000..15dbf2eb --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_nf_1half.spice @@ -0,0 +1,20 @@ +.subckt corpus_train_tg01 VDD VSS VIN1 VOUT1 VC1 VC2 +XM1_f0 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f8 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f9 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f10 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f11 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_train_tg01 diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_nf_3quarters.spice b/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_nf_3quarters.spice new file mode 100644 index 00000000..7e47b622 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_nf_3quarters.spice @@ -0,0 +1,11 @@ +.subckt corpus_train_tg01 VDD VSS VIN1 VOUT1 VC1 VC2 +XM1_f0 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_train_tg01 diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_nf_double.spice new file mode 100644 index 00000000..43feee06 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_nf_double.spice @@ -0,0 +1,26 @@ +.subckt corpus_train_tg01 VDD VSS VIN1 VOUT1 VC1 VC2 +XM1_f0 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f8 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f9 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f10 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f11 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f12 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f13 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f14 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f15 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_train_tg01 diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_nf_half.spice b/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_nf_half.spice new file mode 100644 index 00000000..20b4ebf9 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_nf_half.spice @@ -0,0 +1,8 @@ +.subckt corpus_train_tg01 VDD VSS VIN1 VOUT1 VC1 VC2 +XM1_f0 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_train_tg01 diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_unit075.spice new file mode 100644 index 00000000..01c28829 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_unit075.spice @@ -0,0 +1,14 @@ +.subckt corpus_train_tg01 VDD VSS VIN1 VOUT1 VC1 VC2 +XM1_f0 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f1 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f2 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f3 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f0 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f1 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f2 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f3 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f4 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f5 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f6 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f7 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +.ends corpus_train_tg01 diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_unit100.spice b/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_unit100.spice new file mode 100644 index 00000000..146deaaf --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_family/references/dev_unit100.spice @@ -0,0 +1,14 @@ +.subckt corpus_train_tg01 VDD VSS VIN1 VOUT1 VC1 VC2 +XM1_f0 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f1 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f2 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f3 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f0 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f1 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f2 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f3 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f4 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f5 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f6 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f7 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +.ends corpus_train_tg01 diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/circuit_input.json b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/circuit_input.json new file mode 100644 index 00000000..7e839316 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/circuit_input.json @@ -0,0 +1,45 @@ +{ + "circuit_id": "TRAIN_TG01", + "name": "authored_complementary_transmission_gate", + "ports": [ + "VDD", + "VSS", + "VIN1", + "VOUT1", + "VC1", + "VC2" + ], + "devices": [ + { + "name": "M1", + "kind": "nfet", + "nets": [ + "VOUT1", + "VC1", + "VIN1", + "VSS" + ], + "params": {} + }, + { + "name": "M2", + "kind": "pfet", + "nets": [ + "VOUT1", + "VC2", + "VIN1", + "VDD" + ], + "params": {} + } + ], + "source": { + "kind": "new_authored_task_descriptor", + "author_role": "research_engineering", + "not_an_existing_public_C04": "Public C04 is a common-source amplifier; no TG exists among the public18 descriptors.", + "graph": "Parallel NMOS/PMOS channels; complementary external controls, separate well/body rails." + }, + "notes": [ + "Circuit input to the same public universal compiler, not an independent generator lineage." + ] +} diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/configurations.json b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/configurations.json new file mode 100644 index 00000000..99eb1ce1 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/configurations.json @@ -0,0 +1,198 @@ +{ + "scope": "development_only_train_component_qualification", + "source_revision": "1f90e33913208e572744b7c5a144a7da8c073235", + "parent_lineage": "textbook_universal_compiler_cropped", + "circuit_id": "TRAIN_TG01", + "circuit_input_file": "configs/development/train_tg01_strength4_family/circuit_input.json", + "configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "sizing": { + "M1": { + "w": 8.0, + "l": 0.3, + "nf": 16 + }, + "M2": { + "w": 16.0, + "l": 0.3, + "nf": 32 + } + } + }, + "reference_file": "configs/development/train_tg01_strength4_family/references/anchor.spice", + "contract_file": "configs/development/train_tg01_strength4_family/contracts/anchor.json" + }, + { + "configuration_id": "dev_nf_half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 4.0, + "l": 0.3, + "nf": 8 + }, + "M2": { + "w": 8.0, + "l": 0.3, + "nf": 16 + } + } + }, + "reference_file": "configs/development/train_tg01_strength4_family/references/dev_nf_half.spice", + "contract_file": "configs/development/train_tg01_strength4_family/contracts/dev_nf_half.json" + }, + { + "configuration_id": "dev_nf_3quarters", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 6.0, + "l": 0.3, + "nf": 12 + }, + "M2": { + "w": 12.0, + "l": 0.3, + "nf": 24 + } + } + }, + "reference_file": "configs/development/train_tg01_strength4_family/references/dev_nf_3quarters.spice", + "contract_file": "configs/development/train_tg01_strength4_family/contracts/dev_nf_3quarters.json" + }, + { + "configuration_id": "dev_nf_1half", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 12.0, + "l": 0.3, + "nf": 24 + }, + "M2": { + "w": 24.0, + "l": 0.3, + "nf": 48 + } + } + }, + "reference_file": "configs/development/train_tg01_strength4_family/references/dev_nf_1half.spice", + "contract_file": "configs/development/train_tg01_strength4_family/contracts/dev_nf_1half.json" + }, + { + "configuration_id": "dev_nf_double", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 16.0, + "l": 0.3, + "nf": 32 + }, + "M2": { + "w": 32.0, + "l": 0.3, + "nf": 64 + } + } + }, + "reference_file": "configs/development/train_tg01_strength4_family/references/dev_nf_double.spice", + "contract_file": "configs/development/train_tg01_strength4_family/contracts/dev_nf_double.json" + }, + { + "configuration_id": "dev_len045", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 8.0, + "l": 0.45, + "nf": 16 + }, + "M2": { + "w": 16.0, + "l": 0.45, + "nf": 32 + } + } + }, + "reference_file": "configs/development/train_tg01_strength4_family/references/dev_len045.spice", + "contract_file": "configs/development/train_tg01_strength4_family/contracts/dev_len045.json" + }, + { + "configuration_id": "dev_len060", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 8.0, + "l": 0.6, + "nf": 16 + }, + "M2": { + "w": 16.0, + "l": 0.6, + "nf": 32 + } + } + }, + "reference_file": "configs/development/train_tg01_strength4_family/references/dev_len060.spice", + "contract_file": "configs/development/train_tg01_strength4_family/contracts/dev_len060.json" + }, + { + "configuration_id": "dev_unit075", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 12.0, + "l": 0.3, + "nf": 16 + }, + "M2": { + "w": 24.0, + "l": 0.3, + "nf": 32 + } + } + }, + "reference_file": "configs/development/train_tg01_strength4_family/references/dev_unit075.spice", + "contract_file": "configs/development/train_tg01_strength4_family/contracts/dev_unit075.json" + }, + { + "configuration_id": "dev_unit100", + "role": "development", + "parameters": { + "sizing": { + "M1": { + "w": 16.0, + "l": 0.3, + "nf": 16 + }, + "M2": { + "w": 32.0, + "l": 0.3, + "nf": 32 + } + } + }, + "reference_file": "configs/development/train_tg01_strength4_family/references/dev_unit100.spice", + "contract_file": "configs/development/train_tg01_strength4_family/contracts/dev_unit100.json" + } + ], + "ancestry": "One cropped public universal compiler source lineage; new descriptors and geometry configurations are not new source implementations.", + "development_domain_id": "TRAIN_TG01_strength4", + "sizing_change": { + "parent_table": "configs/development/train_tg01_family/configurations.json", + "width_and_fingers_multiplier": 4, + "channel_length_unchanged": true, + "external_load_and_all_specs_unchanged": true, + "reason": "Original real schematic and postlayout SS loaded gain about0.345/0.348 failed the declared0.5 core gate. This new engineering sizing is not training data or an edited source candidate." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/anchor.json b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/anchor.json new file mode 100644 index 00000000..058c9b74 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/anchor.json @@ -0,0 +1,103 @@ +{ + "task_id": "development_train_domain_train_tg01_strength4", + "configuration_id": "anchor", + "reference_id": "train_tg01_strength4_anchor_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "train_tg01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "on_controls_V": [ + 1.8, + 0 + ], + "off_controls_V": [ + 0, + 1.8 + ], + "nominal_input_V": 0.9, + "on_load_R_ohm": 100000, + "on_load_C_F": 1e-12, + "input_DC_sweep_V": [ + 0.1, + 1.7, + 0.1 + ], + "input_transient_levels_V": [ + 0.2, + 1.6 + ], + "off_output_clamp_V": 0.9, + "load_definition": "Enabled signal transfer uses100kOhm||1pF; disabled leakage uses only an ideal0.9V output clamp, without the load resistor. Controls are static, so no switching-charge-injection claim.", + "power_definition": "Signal-source work, external resistor dissipation, main well-supply work and channel conduction loss are separate quantities." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + }, + "off": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + } + }, + "sizing_origin": { + "parent_table": "configs/development/train_tg01_family/configurations.json", + "width_and_fingers_multiplier": 4, + "channel_length_unchanged": true, + "external_load_and_all_specs_unchanged": true, + "reason": "Original real schematic and postlayout SS loaded gain about0.345/0.348 failed the declared0.5 core gate. This new engineering sizing is not training data or an edited source candidate." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/dev_len045.json b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/dev_len045.json new file mode 100644 index 00000000..34a5c352 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/dev_len045.json @@ -0,0 +1,103 @@ +{ + "task_id": "development_train_domain_train_tg01_strength4", + "configuration_id": "dev_len045", + "reference_id": "train_tg01_strength4_dev_len045_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "train_tg01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "on_controls_V": [ + 1.8, + 0 + ], + "off_controls_V": [ + 0, + 1.8 + ], + "nominal_input_V": 0.9, + "on_load_R_ohm": 100000, + "on_load_C_F": 1e-12, + "input_DC_sweep_V": [ + 0.1, + 1.7, + 0.1 + ], + "input_transient_levels_V": [ + 0.2, + 1.6 + ], + "off_output_clamp_V": 0.9, + "load_definition": "Enabled signal transfer uses100kOhm||1pF; disabled leakage uses only an ideal0.9V output clamp, without the load resistor. Controls are static, so no switching-charge-injection claim.", + "power_definition": "Signal-source work, external resistor dissipation, main well-supply work and channel conduction loss are separate quantities." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + }, + "off": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + } + }, + "sizing_origin": { + "parent_table": "configs/development/train_tg01_family/configurations.json", + "width_and_fingers_multiplier": 4, + "channel_length_unchanged": true, + "external_load_and_all_specs_unchanged": true, + "reason": "Original real schematic and postlayout SS loaded gain about0.345/0.348 failed the declared0.5 core gate. This new engineering sizing is not training data or an edited source candidate." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/dev_len060.json b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/dev_len060.json new file mode 100644 index 00000000..26f99eeb --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/dev_len060.json @@ -0,0 +1,103 @@ +{ + "task_id": "development_train_domain_train_tg01_strength4", + "configuration_id": "dev_len060", + "reference_id": "train_tg01_strength4_dev_len060_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "train_tg01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "on_controls_V": [ + 1.8, + 0 + ], + "off_controls_V": [ + 0, + 1.8 + ], + "nominal_input_V": 0.9, + "on_load_R_ohm": 100000, + "on_load_C_F": 1e-12, + "input_DC_sweep_V": [ + 0.1, + 1.7, + 0.1 + ], + "input_transient_levels_V": [ + 0.2, + 1.6 + ], + "off_output_clamp_V": 0.9, + "load_definition": "Enabled signal transfer uses100kOhm||1pF; disabled leakage uses only an ideal0.9V output clamp, without the load resistor. Controls are static, so no switching-charge-injection claim.", + "power_definition": "Signal-source work, external resistor dissipation, main well-supply work and channel conduction loss are separate quantities." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + }, + "off": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + } + }, + "sizing_origin": { + "parent_table": "configs/development/train_tg01_family/configurations.json", + "width_and_fingers_multiplier": 4, + "channel_length_unchanged": true, + "external_load_and_all_specs_unchanged": true, + "reason": "Original real schematic and postlayout SS loaded gain about0.345/0.348 failed the declared0.5 core gate. This new engineering sizing is not training data or an edited source candidate." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/dev_nf_1half.json b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/dev_nf_1half.json new file mode 100644 index 00000000..f7774965 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/dev_nf_1half.json @@ -0,0 +1,103 @@ +{ + "task_id": "development_train_domain_train_tg01_strength4", + "configuration_id": "dev_nf_1half", + "reference_id": "train_tg01_strength4_dev_nf_1half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "train_tg01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "on_controls_V": [ + 1.8, + 0 + ], + "off_controls_V": [ + 0, + 1.8 + ], + "nominal_input_V": 0.9, + "on_load_R_ohm": 100000, + "on_load_C_F": 1e-12, + "input_DC_sweep_V": [ + 0.1, + 1.7, + 0.1 + ], + "input_transient_levels_V": [ + 0.2, + 1.6 + ], + "off_output_clamp_V": 0.9, + "load_definition": "Enabled signal transfer uses100kOhm||1pF; disabled leakage uses only an ideal0.9V output clamp, without the load resistor. Controls are static, so no switching-charge-injection claim.", + "power_definition": "Signal-source work, external resistor dissipation, main well-supply work and channel conduction loss are separate quantities." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + }, + "off": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + } + }, + "sizing_origin": { + "parent_table": "configs/development/train_tg01_family/configurations.json", + "width_and_fingers_multiplier": 4, + "channel_length_unchanged": true, + "external_load_and_all_specs_unchanged": true, + "reason": "Original real schematic and postlayout SS loaded gain about0.345/0.348 failed the declared0.5 core gate. This new engineering sizing is not training data or an edited source candidate." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/dev_nf_3quarters.json b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/dev_nf_3quarters.json new file mode 100644 index 00000000..6246f524 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/dev_nf_3quarters.json @@ -0,0 +1,103 @@ +{ + "task_id": "development_train_domain_train_tg01_strength4", + "configuration_id": "dev_nf_3quarters", + "reference_id": "train_tg01_strength4_dev_nf_3quarters_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "train_tg01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "on_controls_V": [ + 1.8, + 0 + ], + "off_controls_V": [ + 0, + 1.8 + ], + "nominal_input_V": 0.9, + "on_load_R_ohm": 100000, + "on_load_C_F": 1e-12, + "input_DC_sweep_V": [ + 0.1, + 1.7, + 0.1 + ], + "input_transient_levels_V": [ + 0.2, + 1.6 + ], + "off_output_clamp_V": 0.9, + "load_definition": "Enabled signal transfer uses100kOhm||1pF; disabled leakage uses only an ideal0.9V output clamp, without the load resistor. Controls are static, so no switching-charge-injection claim.", + "power_definition": "Signal-source work, external resistor dissipation, main well-supply work and channel conduction loss are separate quantities." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + }, + "off": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + } + }, + "sizing_origin": { + "parent_table": "configs/development/train_tg01_family/configurations.json", + "width_and_fingers_multiplier": 4, + "channel_length_unchanged": true, + "external_load_and_all_specs_unchanged": true, + "reason": "Original real schematic and postlayout SS loaded gain about0.345/0.348 failed the declared0.5 core gate. This new engineering sizing is not training data or an edited source candidate." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/dev_nf_double.json b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/dev_nf_double.json new file mode 100644 index 00000000..911d7ccb --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/dev_nf_double.json @@ -0,0 +1,103 @@ +{ + "task_id": "development_train_domain_train_tg01_strength4", + "configuration_id": "dev_nf_double", + "reference_id": "train_tg01_strength4_dev_nf_double_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "train_tg01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "on_controls_V": [ + 1.8, + 0 + ], + "off_controls_V": [ + 0, + 1.8 + ], + "nominal_input_V": 0.9, + "on_load_R_ohm": 100000, + "on_load_C_F": 1e-12, + "input_DC_sweep_V": [ + 0.1, + 1.7, + 0.1 + ], + "input_transient_levels_V": [ + 0.2, + 1.6 + ], + "off_output_clamp_V": 0.9, + "load_definition": "Enabled signal transfer uses100kOhm||1pF; disabled leakage uses only an ideal0.9V output clamp, without the load resistor. Controls are static, so no switching-charge-injection claim.", + "power_definition": "Signal-source work, external resistor dissipation, main well-supply work and channel conduction loss are separate quantities." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + }, + "off": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + } + }, + "sizing_origin": { + "parent_table": "configs/development/train_tg01_family/configurations.json", + "width_and_fingers_multiplier": 4, + "channel_length_unchanged": true, + "external_load_and_all_specs_unchanged": true, + "reason": "Original real schematic and postlayout SS loaded gain about0.345/0.348 failed the declared0.5 core gate. This new engineering sizing is not training data or an edited source candidate." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/dev_nf_half.json b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/dev_nf_half.json new file mode 100644 index 00000000..fd21778f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/dev_nf_half.json @@ -0,0 +1,103 @@ +{ + "task_id": "development_train_domain_train_tg01_strength4", + "configuration_id": "dev_nf_half", + "reference_id": "train_tg01_strength4_dev_nf_half_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "train_tg01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "on_controls_V": [ + 1.8, + 0 + ], + "off_controls_V": [ + 0, + 1.8 + ], + "nominal_input_V": 0.9, + "on_load_R_ohm": 100000, + "on_load_C_F": 1e-12, + "input_DC_sweep_V": [ + 0.1, + 1.7, + 0.1 + ], + "input_transient_levels_V": [ + 0.2, + 1.6 + ], + "off_output_clamp_V": 0.9, + "load_definition": "Enabled signal transfer uses100kOhm||1pF; disabled leakage uses only an ideal0.9V output clamp, without the load resistor. Controls are static, so no switching-charge-injection claim.", + "power_definition": "Signal-source work, external resistor dissipation, main well-supply work and channel conduction loss are separate quantities." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + }, + "off": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + } + }, + "sizing_origin": { + "parent_table": "configs/development/train_tg01_family/configurations.json", + "width_and_fingers_multiplier": 4, + "channel_length_unchanged": true, + "external_load_and_all_specs_unchanged": true, + "reason": "Original real schematic and postlayout SS loaded gain about0.345/0.348 failed the declared0.5 core gate. This new engineering sizing is not training data or an edited source candidate." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/dev_unit075.json b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/dev_unit075.json new file mode 100644 index 00000000..e157a78e --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/dev_unit075.json @@ -0,0 +1,103 @@ +{ + "task_id": "development_train_domain_train_tg01_strength4", + "configuration_id": "dev_unit075", + "reference_id": "train_tg01_strength4_dev_unit075_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "train_tg01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "on_controls_V": [ + 1.8, + 0 + ], + "off_controls_V": [ + 0, + 1.8 + ], + "nominal_input_V": 0.9, + "on_load_R_ohm": 100000, + "on_load_C_F": 1e-12, + "input_DC_sweep_V": [ + 0.1, + 1.7, + 0.1 + ], + "input_transient_levels_V": [ + 0.2, + 1.6 + ], + "off_output_clamp_V": 0.9, + "load_definition": "Enabled signal transfer uses100kOhm||1pF; disabled leakage uses only an ideal0.9V output clamp, without the load resistor. Controls are static, so no switching-charge-injection claim.", + "power_definition": "Signal-source work, external resistor dissipation, main well-supply work and channel conduction loss are separate quantities." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + }, + "off": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + } + }, + "sizing_origin": { + "parent_table": "configs/development/train_tg01_family/configurations.json", + "width_and_fingers_multiplier": 4, + "channel_length_unchanged": true, + "external_load_and_all_specs_unchanged": true, + "reason": "Original real schematic and postlayout SS loaded gain about0.345/0.348 failed the declared0.5 core gate. This new engineering sizing is not training data or an edited source candidate." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/dev_unit100.json b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/dev_unit100.json new file mode 100644 index 00000000..391da475 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/contracts/dev_unit100.json @@ -0,0 +1,103 @@ +{ + "task_id": "development_train_domain_train_tg01_strength4", + "configuration_id": "dev_unit100", + "reference_id": "train_tg01_strength4_dev_unit100_perfinger", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "scope": "DRAFT_DEVELOPMENT_QUALIFICATION_NOT_FORMAL", + "objective": { + "id": "train_tg01_area_min", + "metric": "area", + "unit": "um2", + "direction": "min", + "corner_aggregation": "worst" + }, + "specifications": [], + "pending_before_freeze": [ + "Actual independent anchor and all nine geometry qualification required before selecting prospective electrical floors." + ], + "nominal_operating_point": { + "supply_V": 1.8, + "temperature_C": 27, + "on_controls_V": [ + 1.8, + 0 + ], + "off_controls_V": [ + 0, + 1.8 + ], + "nominal_input_V": 0.9, + "on_load_R_ohm": 100000, + "on_load_C_F": 1e-12, + "input_DC_sweep_V": [ + 0.1, + 1.7, + 0.1 + ], + "input_transient_levels_V": [ + 0.2, + 1.6 + ], + "off_output_clamp_V": 0.9, + "load_definition": "Enabled signal transfer uses100kOhm||1pF; disabled leakage uses only an ideal0.9V output clamp, without the load resistor. Controls are static, so no switching-charge-injection claim.", + "power_definition": "Signal-source work, external resistor dissipation, main well-supply work and channel conduction loss are separate quantities." + }, + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 161, + "scale": "log" + }, + "tran": { + "kind": "transient", + "columns": 3, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + }, + "dc": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + }, + "off": { + "kind": "dc", + "columns": 3, + "start": 0.1, + "end": 1.7, + "points": 17, + "scale": "linear" + } + }, + "sizing_origin": { + "parent_table": "configs/development/train_tg01_family/configurations.json", + "width_and_fingers_multiplier": 4, + "channel_length_unchanged": true, + "external_load_and_all_specs_unchanged": true, + "reason": "Original real schematic and postlayout SS loaded gain about0.345/0.348 failed the declared0.5 core gate. This new engineering sizing is not training data or an edited source candidate." + } +} diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/anchor.spice b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/anchor.spice new file mode 100644 index 00000000..470e61cb --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/anchor.spice @@ -0,0 +1,50 @@ +.subckt corpus_train_tg01 VDD VSS VIN1 VOUT1 VC1 VC2 +XM1_f0 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f8 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f9 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f10 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f11 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f12 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f13 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f14 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f15 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f8 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f9 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f10 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f11 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f12 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f13 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f14 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f15 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f16 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f17 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f18 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f19 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f20 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f21 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f22 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f23 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f24 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f25 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f26 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f27 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f28 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f29 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f30 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f31 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_train_tg01 diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/dev_len045.spice b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/dev_len045.spice new file mode 100644 index 00000000..06bf1757 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/dev_len045.spice @@ -0,0 +1,50 @@ +.subckt corpus_train_tg01 VDD VSS VIN1 VOUT1 VC1 VC2 +XM1_f0 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f1 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f2 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f3 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f4 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f5 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f6 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f7 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f8 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f9 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f10 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f11 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f12 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f13 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f14 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM1_f15 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.45 +XM2_f0 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f1 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f2 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f3 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f4 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f5 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f6 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f7 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f8 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f9 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f10 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f11 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f12 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f13 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f14 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f15 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f16 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f17 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f18 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f19 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f20 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f21 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f22 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f23 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f24 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f25 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f26 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f27 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f28 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f29 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f30 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +XM2_f31 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.45 +.ends corpus_train_tg01 diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/dev_len060.spice b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/dev_len060.spice new file mode 100644 index 00000000..52bb30f9 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/dev_len060.spice @@ -0,0 +1,50 @@ +.subckt corpus_train_tg01 VDD VSS VIN1 VOUT1 VC1 VC2 +XM1_f0 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f1 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f2 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f3 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f4 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f5 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f6 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f7 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f8 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f9 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f10 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f11 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f12 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f13 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f14 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM1_f15 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.6 +XM2_f0 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f1 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f2 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f3 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f4 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f5 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f6 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f7 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f8 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f9 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f10 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f11 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f12 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f13 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f14 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f15 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f16 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f17 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f18 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f19 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f20 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f21 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f22 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f23 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f24 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f25 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f26 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f27 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f28 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f29 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f30 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +XM2_f31 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.6 +.ends corpus_train_tg01 diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/dev_nf_1half.spice b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/dev_nf_1half.spice new file mode 100644 index 00000000..9cbbd1fb --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/dev_nf_1half.spice @@ -0,0 +1,74 @@ +.subckt corpus_train_tg01 VDD VSS VIN1 VOUT1 VC1 VC2 +XM1_f0 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f8 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f9 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f10 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f11 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f12 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f13 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f14 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f15 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f16 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f17 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f18 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f19 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f20 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f21 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f22 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f23 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f8 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f9 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f10 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f11 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f12 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f13 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f14 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f15 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f16 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f17 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f18 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f19 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f20 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f21 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f22 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f23 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f24 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f25 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f26 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f27 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f28 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f29 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f30 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f31 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f32 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f33 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f34 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f35 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f36 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f37 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f38 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f39 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f40 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f41 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f42 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f43 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f44 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f45 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f46 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f47 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_train_tg01 diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/dev_nf_3quarters.spice b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/dev_nf_3quarters.spice new file mode 100644 index 00000000..723e2819 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/dev_nf_3quarters.spice @@ -0,0 +1,38 @@ +.subckt corpus_train_tg01 VDD VSS VIN1 VOUT1 VC1 VC2 +XM1_f0 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f8 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f9 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f10 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f11 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f8 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f9 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f10 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f11 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f12 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f13 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f14 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f15 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f16 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f17 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f18 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f19 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f20 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f21 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f22 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f23 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_train_tg01 diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/dev_nf_double.spice b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/dev_nf_double.spice new file mode 100644 index 00000000..3bf68622 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/dev_nf_double.spice @@ -0,0 +1,98 @@ +.subckt corpus_train_tg01 VDD VSS VIN1 VOUT1 VC1 VC2 +XM1_f0 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f8 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f9 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f10 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f11 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f12 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f13 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f14 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f15 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f16 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f17 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f18 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f19 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f20 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f21 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f22 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f23 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f24 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f25 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f26 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f27 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f28 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f29 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f30 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f31 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f8 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f9 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f10 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f11 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f12 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f13 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f14 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f15 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f16 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f17 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f18 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f19 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f20 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f21 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f22 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f23 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f24 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f25 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f26 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f27 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f28 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f29 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f30 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f31 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f32 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f33 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f34 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f35 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f36 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f37 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f38 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f39 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f40 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f41 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f42 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f43 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f44 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f45 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f46 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f47 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f48 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f49 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f50 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f51 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f52 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f53 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f54 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f55 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f56 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f57 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f58 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f59 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f60 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f61 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f62 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f63 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_train_tg01 diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/dev_nf_half.spice b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/dev_nf_half.spice new file mode 100644 index 00000000..43feee06 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/dev_nf_half.spice @@ -0,0 +1,26 @@ +.subckt corpus_train_tg01 VDD VSS VIN1 VOUT1 VC1 VC2 +XM1_f0 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f1 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f2 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f3 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f4 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f5 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f6 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM1_f7 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.5 l=0.3 +XM2_f0 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f1 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f2 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f3 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f4 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f5 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f6 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f7 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f8 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f9 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f10 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f11 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f12 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f13 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f14 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +XM2_f15 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.5 l=0.3 +.ends corpus_train_tg01 diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/dev_unit075.spice b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/dev_unit075.spice new file mode 100644 index 00000000..c6fc8b7c --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/dev_unit075.spice @@ -0,0 +1,50 @@ +.subckt corpus_train_tg01 VDD VSS VIN1 VOUT1 VC1 VC2 +XM1_f0 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f1 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f2 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f3 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f4 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f5 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f6 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f7 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f8 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f9 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f10 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f11 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f12 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f13 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f14 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM1_f15 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=0.75 l=0.3 +XM2_f0 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f1 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f2 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f3 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f4 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f5 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f6 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f7 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f8 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f9 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f10 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f11 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f12 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f13 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f14 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f15 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f16 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f17 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f18 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f19 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f20 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f21 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f22 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f23 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f24 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f25 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f26 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f27 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f28 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f29 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f30 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +XM2_f31 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=0.75 l=0.3 +.ends corpus_train_tg01 diff --git a/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/dev_unit100.spice b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/dev_unit100.spice new file mode 100644 index 00000000..1e78da34 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/train_tg01_strength4_family/references/dev_unit100.spice @@ -0,0 +1,50 @@ +.subckt corpus_train_tg01 VDD VSS VIN1 VOUT1 VC1 VC2 +XM1_f0 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f1 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f2 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f3 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f4 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f5 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f6 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f7 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f8 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f9 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f10 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f11 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f12 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f13 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f14 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM1_f15 VOUT1 VC1 VIN1 VSS sky130_fd_pr__nfet_01v8 w=1 l=0.3 +XM2_f0 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f1 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f2 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f3 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f4 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f5 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f6 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f7 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f8 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f9 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f10 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f11 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f12 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f13 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f14 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f15 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f16 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f17 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f18 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f19 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f20 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f21 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f22 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f23 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f24 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f25 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f26 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f27 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f28 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f29 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f30 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +XM2_f31 VOUT1 VC2 VIN1 VDD sky130_fd_pr__pfet_01v8 w=1 l=0.3 +.ends corpus_train_tg01 diff --git a/benchmarks/code_behind_layout/configs/development/validation_interface_v2.json b/benchmarks/code_behind_layout/configs/development/validation_interface_v2.json new file mode 100644 index 00000000..7038492a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/validation_interface_v2.json @@ -0,0 +1,25 @@ +{ + "interface_id": "validation_named_top_v2", + "status": "FROZEN_DEVELOPMENT_INTERFACE", + "frozen_at_utc": "2026-10-19T02:05:10.289329+00:00", + "scope": "Prospective development validation composition gateway; main benchmark remains DRAFT", + "contract_target": "validation_mirror", + "selection": "Exactly one cell with the contract name; complete resolvable referenced hierarchy; full recursive bounding box", + "unreferenced_cells": "Permitted; excluded from target DRC/LVS/PEX", + "GDS_input_rewrite": false, + "default_unnamed_DRC_call": "Original sole-top requirement unchanged", + "feedback": "Structured interface_error; missing or unresolved target is unknown/interface, never a physical candidate failure", + "snapshot_files": [ + "src/physical_drc.py", + "scripts/validation_task_evaluator.py", + "scripts/validation_budget_pilot.py", + "scripts/named_top_smoke.py", + "results/derived/named_top_calibration.json" + ], + "physical_smoke": "phase0_20261019T020356543075Z_named_top_smoke", + "sealed_prior_batch": "20261019T015810313920Z", + "prior_batch_regraded_or_rerun": false, + "formal_trials": 0, + "training_examples": 0, + "frozen_generic_library_remote": "runs/development/validation_bundles/20261019T015648213799Z" +} diff --git a/benchmarks/code_behind_layout/configs/development/validation_shared_budget_v3.json b/benchmarks/code_behind_layout/configs/development/validation_shared_budget_v3.json new file mode 100644 index 00000000..544d051e --- /dev/null +++ b/benchmarks/code_behind_layout/configs/development/validation_shared_budget_v3.json @@ -0,0 +1,19 @@ +{ + "interface_id": "validation_shared_budget_v3", + "status": "FROZEN_DEVELOPMENT_INTERFACE", + "frozen_at_utc": "2026-10-19T02:14:32.487258+00:00", + "scope": "Prospective validation only; main benchmark DRAFT", + "input_output_contract": "Exact ordinary serving decision_prompt, single-user chat;8192 total with1024 full output reserve; exact returned output plusEOS\u22641024 shared Qwen-tokenizer tokens. No source/history truncation. Overlong provider output rejected before action; all raw output/public usage retained.", + "target_geometry_interface": "validation_named_top_v2 unchanged", + "generic_library": "runs/development/validation_bundles/20261019T015648213799Z", + "budgets": { + "decisions": 10, + "physical_evaluations": 3, + "wall_seconds": 1200, + "simultaneous_physical_pipelines": 1 + }, + "prior_evidence": "results/derived/gpt_shared_budget_calibration.json", + "prior_batch_regraded_or_rerun": false, + "formal_trials": 0, + "training_examples": 0 +} diff --git a/benchmarks/code_behind_layout/configs/experiments/e2_four_source_prospective_v3.json b/benchmarks/code_behind_layout/configs/experiments/e2_four_source_prospective_v3.json new file mode 100644 index 00000000..e65d0a4f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/experiments/e2_four_source_prospective_v3.json @@ -0,0 +1,10587 @@ +{ + "status": "PROSPECTIVE_DRAFT_NOT_FROZEN_NO_FORMAL_LABELS", + "formal_execution_allowed": false, + "scope": "FourthindependentOTA replaces nooldmeasurement; newformal4source\u00d73N\u00d764maskdistinctpoolplan", + "source_families": [ + "five_t", + "compact_miller", + "fvf", + "telescopic" + ], + "independent_high_level_assembly_programs": 4, + "independence_limit": "MOS/via/PDK andprimitiveaccess constraints shared; disclosefullsourceclosure andmergedsensitivity. Filecount orwidthvariants are notnewlineages.", + "source_assignment": "Allfourhighleveltargets areevaluation-only. Newtelescopicsource/N/results mustnotentertraining orpromotioncalibration. Sharedprimitive/access code isdeclaredseparately.", + "existing_three_source_inputs": "runtime/e2_execution_preparation/20261019T0344Z_serial_costs/execution_manifest.json", + "existing_three_source_fields_adopted_without_electrical_changes": [ + "source_dir", + "source_paths", + "layout_target", + "source_snapshot", + "point", + "full_trusted", + "top_cell", + "candidate_stream" + ], + "source_qualifications": { + "five_t": { + "sizing_ids": [ + "s0", + "s1", + "s2" + ], + "control_source": "OriginalexactthreeNsandqualifiedsource/benchbinding from0344executionmanifest", + "default_and_s0_s2_physical_control_status": "ActualS2complete; rootmust rereadrawsource/N/contract beforefreeze" + }, + "compact_miller": { + "sizing_ids": [ + "s0", + "s1", + "s2" + ], + "control_source": "OriginalexactthreeNsandqualifiedsource/benchbinding from0344executionmanifest", + "default_and_s0_s2_physical_control_status": "ActualS2complete; rootmust rereadrawsource/N/contract beforefreeze" + }, + "fvf": { + "sizing_ids": [ + "s0", + "s1", + "s2" + ], + "control_source": "OriginalexactthreeNsandqualifiedsource/benchbinding from0344executionmanifest", + "default_and_s0_s2_physical_control_status": "ActualS2complete; rootmust rereadrawsource/N/contract beforefreeze" + }, + "telescopic": { + "sizing_ids": [ + "s0", + "s1", + "s2" + ], + "independent_sizings": [ + { + "sizing_id": "s0", + "sizing": { + "input_width": 2.7, + "input_length": 1.0, + "input_fingers": 2, + "ncas_width": 3.0, + "ncas_length": 0.5, + "ncas_fingers": 2, + "mirror_width": 3.0, + "mirror_length": 1.0, + "mirror_fingers": 4, + "pcas_width": 3.0, + "pcas_length": 0.5, + "pcas_fingers": 4, + "tail_width": 3.0, + "tail_length": 1.0, + "tail_fingers": 4 + }, + "independent_N_rule": "src.generators.telescopic_ota_reference.schematic(sizing)", + "intent_fingers": 32 + }, + { + "sizing_id": "s1", + "sizing": { + "input_width": 3.0, + "input_length": 1.0, + "input_fingers": 2, + "ncas_width": 3.0, + "ncas_length": 0.5, + "ncas_fingers": 2, + "mirror_width": 3.0, + "mirror_length": 1.0, + "mirror_fingers": 4, + "pcas_width": 3.0, + "pcas_length": 0.5, + "pcas_fingers": 4, + "tail_width": 3.0, + "tail_length": 1.0, + "tail_fingers": 4 + }, + "independent_N_rule": "src.generators.telescopic_ota_reference.schematic(sizing)", + "intent_fingers": 32 + }, + { + "sizing_id": "s2", + "sizing": { + "input_width": 3.3, + "input_length": 1.0, + "input_fingers": 2, + "ncas_width": 3.0, + "ncas_length": 0.5, + "ncas_fingers": 2, + "mirror_width": 3.0, + "mirror_length": 1.0, + "mirror_fingers": 4, + "pcas_width": 3.0, + "pcas_length": 0.5, + "pcas_fingers": 4, + "tail_width": 3.0, + "tail_length": 1.0, + "tail_fingers": 4 + }, + "independent_N_rule": "src.generators.telescopic_ota_reference.schematic(sizing)", + "intent_fingers": 32 + } + ], + "control_source": "runtime/telescopic_sizing_qualification_20261019/prepared_v1", + "default_actual_control": "phase0_20261019T051625997960Z_telescopic_ota_fullflow", + "default_status": "ActualcompleteS2;6additionalideal+2fullnondefaultcontrols prepared, notyetobservedreturned" + } + }, + "prospective_pools": [ + { + "pool_id": "five_t_s0", + "source_family": "five_t", + "sizing_id": "s0", + "required_mask_distinct_candidates": 64, + "maximum_generation_attempts": 256, + "online_selected": true + }, + { + "pool_id": "five_t_s1", + "source_family": "five_t", + "sizing_id": "s1", + "required_mask_distinct_candidates": 64, + "maximum_generation_attempts": 256, + "online_selected": false + }, + { + "pool_id": "five_t_s2", + "source_family": "five_t", + "sizing_id": "s2", + "required_mask_distinct_candidates": 64, + "maximum_generation_attempts": 256, + "online_selected": true + }, + { + "pool_id": "compact_miller_s0", + "source_family": "compact_miller", + "sizing_id": "s0", + "required_mask_distinct_candidates": 64, + "maximum_generation_attempts": 256, + "online_selected": true + }, + { + "pool_id": "compact_miller_s1", + "source_family": "compact_miller", + "sizing_id": "s1", + "required_mask_distinct_candidates": 64, + "maximum_generation_attempts": 256, + "online_selected": false + }, + { + "pool_id": "compact_miller_s2", + "source_family": "compact_miller", + "sizing_id": "s2", + "required_mask_distinct_candidates": 64, + "maximum_generation_attempts": 256, + "online_selected": true + }, + { + "pool_id": "fvf_s0", + "source_family": "fvf", + "sizing_id": "s0", + "required_mask_distinct_candidates": 64, + "maximum_generation_attempts": 256, + "online_selected": true + }, + { + "pool_id": "fvf_s1", + "source_family": "fvf", + "sizing_id": "s1", + "required_mask_distinct_candidates": 64, + "maximum_generation_attempts": 256, + "online_selected": false + }, + { + "pool_id": "fvf_s2", + "source_family": "fvf", + "sizing_id": "s2", + "required_mask_distinct_candidates": 64, + "maximum_generation_attempts": 256, + "online_selected": true + }, + { + "pool_id": "telescopic_s0", + "source_family": "telescopic", + "sizing_id": "s0", + "required_mask_distinct_candidates": 64, + "maximum_generation_attempts": 256, + "online_selected": false + }, + { + "pool_id": "telescopic_s1", + "source_family": "telescopic", + "sizing_id": "s1", + "required_mask_distinct_candidates": 64, + "maximum_generation_attempts": 256, + "online_selected": false + }, + { + "pool_id": "telescopic_s2", + "source_family": "telescopic", + "sizing_id": "s2", + "required_mask_distinct_candidates": 64, + "maximum_generation_attempts": 256, + "online_selected": false + } + ], + "offline_full_oracle_candidates": 768, + "six_online_pool_ids": [ + "five_t_s0", + "five_t_s2", + "compact_miller_s0", + "compact_miller_s2", + "fvf_s0", + "fvf_s2" + ], + "six_online_choice": "Retainpreviouslydeclaredsix5T/compact/FVFs0+s2tasks; do notchangebasedonnewtelescopicoutcomes. Four-sourcecoverageisprovidedbythe12offlinepools.", + "candidate_streams": { + "five_t": [ + { + "stream_index": 0, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 1, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 2, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 3, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 4, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 5, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 6, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 7, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 8, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 9, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 10, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 11, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 12, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 13, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 14, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 15, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 16, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 17, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 18, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 19, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 20, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 21, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 22, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 23, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 24, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 25, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 26, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 27, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 28, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 29, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 30, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 31, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 32, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 33, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 34, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 35, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 36, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 37, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 38, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 39, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 40, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 41, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 42, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 43, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 44, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 45, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 46, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 47, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 48, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 49, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 50, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 51, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 52, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 53, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 54, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 55, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 56, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 57, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 58, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 59, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 60, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 61, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 62, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 3 + }, + "initial_prefix64": true + }, + { + "stream_index": 63, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 64, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 65, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 66, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 67, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 68, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 69, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 70, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 71, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 72, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 73, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 74, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 75, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 76, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 77, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 78, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 79, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 80, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 81, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 82, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 83, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 84, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 85, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 86, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 87, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 88, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 89, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 90, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 91, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 92, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 93, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 94, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 95, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 96, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 97, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 98, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 99, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 100, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 101, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 102, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 103, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 104, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 105, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 106, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 107, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 108, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 109, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 110, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 111, + "controls": { + "channel_gap_um": 22, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 112, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 113, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 114, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 115, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 116, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 117, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 118, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 119, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 120, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 121, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 122, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 123, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 124, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 125, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 126, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 127, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 128, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 129, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 130, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 131, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 132, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 133, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 134, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 135, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 136, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 137, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 138, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 139, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 140, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 141, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 142, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 143, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 144, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 145, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 146, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 147, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 148, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 149, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 150, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 151, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 152, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 153, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 154, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 155, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 156, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 157, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 158, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 159, + "controls": { + "channel_gap_um": 24, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 160, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 161, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 162, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 163, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 164, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 165, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 166, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 167, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 168, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 169, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 170, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 171, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 172, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 173, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 174, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 175, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 176, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 177, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 178, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 179, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 180, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 181, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 182, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 183, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 184, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 185, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 186, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 187, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 188, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 189, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 190, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 191, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 192, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 193, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 194, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 195, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 196, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 197, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 198, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 199, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 200, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 201, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 202, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 203, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 204, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 205, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 206, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 207, + "controls": { + "channel_gap_um": 28, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 208, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 209, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 210, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 211, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 212, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 213, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 214, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 215, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 216, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 217, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 218, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 219, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.68, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 220, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 221, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 222, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 223, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 224, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 225, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 226, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 227, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 228, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 229, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 230, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 231, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.76, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 232, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 233, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 234, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 235, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 236, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 237, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 238, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 239, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 240, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 241, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 242, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 243, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.84, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 244, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 245, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 0.8, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 246, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 247, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 1.4, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 248, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 249, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 250, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 251, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 1, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + }, + { + "stream_index": 252, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 3 + }, + "initial_prefix64": false + }, + { + "stream_index": 253, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 254, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.25 + }, + "initial_prefix64": false + }, + { + "stream_index": 255, + "controls": { + "channel_gap_um": 30, + "drop_width_um": 0.92, + "trunk_width_um": 1.2, + "bus_pitch_um": 3.75 + }, + "initial_prefix64": false + } + ], + "compact_miller": [ + { + "stream_index": 0, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 1, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 2, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 3, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 4, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 5, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 6, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 7, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 8, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 9, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 10, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 11, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 12, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 13, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 14, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 15, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 16, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 17, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 18, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 19, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 20, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 21, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 22, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 23, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 24, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 25, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 26, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 27, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 28, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 29, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 30, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 31, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 32, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 33, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 34, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 35, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 36, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 37, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 38, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 39, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 40, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 41, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 42, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 43, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 44, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 45, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 46, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 47, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 48, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 49, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 50, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 51, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 52, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 53, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 54, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 55, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 56, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 57, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 58, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 59, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 60, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 61, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 62, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": true + }, + { + "stream_index": 63, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": true + }, + { + "stream_index": 64, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 65, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 66, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 67, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 68, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 69, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 70, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 71, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 72, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 73, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 74, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 75, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 76, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 77, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 78, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 79, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 80, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 81, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 82, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 83, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 84, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 85, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 86, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 87, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 88, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 89, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 90, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 91, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 92, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 93, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 94, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 95, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 96, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 97, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 98, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 99, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 100, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 101, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 102, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 103, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 104, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 105, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 106, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 107, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 108, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 109, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 110, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 111, + "controls": { + "spine_width_um": 0.6, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 112, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 113, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 114, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 115, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 116, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 117, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 118, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 119, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 120, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 121, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 122, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 123, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 124, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 125, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 126, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 127, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 128, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 129, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 130, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 131, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 132, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 133, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 134, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 135, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 136, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 137, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 138, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 139, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 140, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 141, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 142, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 143, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 144, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 145, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 146, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 147, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 148, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 149, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 150, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 151, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 152, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 153, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 154, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 155, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 156, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 157, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 158, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 159, + "controls": { + "spine_width_um": 0.7, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 160, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 161, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 162, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 163, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 164, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 165, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 166, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 167, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 168, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 169, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 170, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 171, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 172, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 173, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 174, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 175, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 176, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 177, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 178, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 179, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 180, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 181, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 182, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 183, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 184, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 185, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 186, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 187, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 188, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 189, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 190, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 191, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 192, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 193, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 194, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 195, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 196, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 197, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 198, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 199, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 200, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 201, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 202, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 203, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 204, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 205, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 206, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 207, + "controls": { + "spine_width_um": 0.8, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 208, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 209, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 210, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 211, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 212, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 213, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 214, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 215, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 216, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 217, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 218, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 219, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.88, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 220, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 221, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 222, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 223, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 224, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 225, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 226, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 227, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 228, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 229, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 230, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 231, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 0.96, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 232, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 233, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 234, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 235, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 236, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 237, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 238, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 239, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 240, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 241, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 242, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 243, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.04, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 244, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 245, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 130, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 246, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 247, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 146, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 248, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 249, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 250, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 251, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 134, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + }, + { + "stream_index": 252, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 4 + }, + "initial_prefix64": false + }, + { + "stream_index": 253, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 8 + }, + "initial_prefix64": false + }, + { + "stream_index": 254, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 5 + }, + "initial_prefix64": false + }, + { + "stream_index": 255, + "controls": { + "spine_width_um": 0.9, + "bus_width_um": 1.12, + "capacitor_center_x_um": 142, + "output_landing_clearance_um": 7 + }, + "initial_prefix64": false + } + ], + "fvf": [ + { + "stream_index": 0, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 1, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 2, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 3, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 4, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 5, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 6, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 7, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 8, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 9, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 10, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 11, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 12, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 13, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 14, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 15, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 16, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 17, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 18, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 19, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 20, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 21, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 22, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 23, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 24, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 25, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 26, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 27, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 28, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 29, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 30, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 31, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 32, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 33, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 34, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 35, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 36, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 37, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 38, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 39, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 40, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 41, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 42, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 43, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 44, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 45, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 46, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 47, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 48, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 49, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 50, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 51, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 52, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 53, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 54, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 55, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 56, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 57, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 58, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 59, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 60, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 61, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 62, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": true + }, + { + "stream_index": 63, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": true + }, + { + "stream_index": 64, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 65, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 66, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 67, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 68, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 69, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 70, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 71, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 72, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 73, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 74, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 75, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 76, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 77, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 78, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 79, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 80, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 81, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 82, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 83, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 84, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 85, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 86, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 87, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 88, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 89, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 90, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 91, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 92, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 93, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 94, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 95, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 96, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 97, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 98, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 99, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 100, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 101, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 102, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 103, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 104, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 105, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 106, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 107, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 108, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 109, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 110, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 111, + "controls": { + "pblock_gap_um": 8, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 112, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 113, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 114, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 115, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 116, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 117, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 118, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 119, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 120, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 121, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 122, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 123, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 124, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 125, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 126, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 127, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 128, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 129, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 130, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 131, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 132, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 133, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 134, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 135, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 136, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 137, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 138, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 139, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 140, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 141, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 142, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 143, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 144, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 145, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 146, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 147, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 148, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 149, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 150, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 151, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 152, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 153, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 154, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 155, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 156, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 157, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 158, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 159, + "controls": { + "pblock_gap_um": 9, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 160, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 161, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 162, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 163, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 164, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 165, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 166, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 167, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 168, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 169, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 170, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 171, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 172, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 173, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 174, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 175, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 176, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 177, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 178, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 179, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 180, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 181, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 182, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 183, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 184, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 185, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 186, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 187, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 188, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 189, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 190, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 191, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 192, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 193, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 194, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 195, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 196, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 197, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 198, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 199, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 200, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 201, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 202, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 203, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 204, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 205, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 206, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 207, + "controls": { + "pblock_gap_um": 11, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 208, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 209, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 210, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 211, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 212, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 213, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 214, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 215, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 216, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 217, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 218, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 219, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 8.8, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 220, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 221, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 222, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 223, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 224, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 225, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 226, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 227, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 228, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 229, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 230, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 231, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 9.6, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 232, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 233, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 234, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 235, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 236, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 237, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 238, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 239, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 240, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 241, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 242, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 243, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 10.4, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 244, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 245, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.6, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 246, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 247, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.9, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 248, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 249, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 250, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 251, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.7, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + }, + { + "stream_index": 252, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 0.9 + }, + "initial_prefix64": false + }, + { + "stream_index": 253, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.2 + }, + "initial_prefix64": false + }, + { + "stream_index": 254, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1 + }, + "initial_prefix64": false + }, + { + "stream_index": 255, + "controls": { + "pblock_gap_um": 12, + "bias_route_extension_um": 11.2, + "source_tie_width_um": 0.8, + "lcmfb_route_width_um": 1.1 + }, + "initial_prefix64": false + } + ], + "telescopic": [ + { + "stream_index": 0, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 80.0, + "join_width": 0.8, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 1, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 80.0, + "join_width": 0.8, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 2, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 80.0, + "join_width": 1.0, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 3, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 80.0, + "join_width": 1.0, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 4, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 90.0, + "join_width": 0.8, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 5, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 90.0, + "join_width": 0.8, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 6, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 90.0, + "join_width": 1.0, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 7, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 90.0, + "join_width": 1.0, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 8, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 100.0, + "join_width": 0.8, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 9, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 100.0, + "join_width": 0.8, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 10, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 100.0, + "join_width": 1.0, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 11, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 100.0, + "join_width": 1.0, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 12, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 110.0, + "join_width": 0.8, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 13, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 110.0, + "join_width": 0.8, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 14, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 110.0, + "join_width": 1.0, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 15, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 110.0, + "join_width": 1.0, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 16, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 80.0, + "join_width": 0.8, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 17, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 80.0, + "join_width": 0.8, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 18, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 80.0, + "join_width": 1.0, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 19, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 80.0, + "join_width": 1.0, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 20, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 90.0, + "join_width": 0.8, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 21, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 90.0, + "join_width": 0.8, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 22, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 90.0, + "join_width": 1.0, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 23, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 90.0, + "join_width": 1.0, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 24, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 100.0, + "join_width": 0.8, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 25, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 100.0, + "join_width": 0.8, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 26, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 100.0, + "join_width": 1.0, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 27, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 100.0, + "join_width": 1.0, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 28, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 110.0, + "join_width": 0.8, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 29, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 110.0, + "join_width": 0.8, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 30, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 110.0, + "join_width": 1.0, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 31, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 110.0, + "join_width": 1.0, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 32, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 80.0, + "join_width": 0.8, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 33, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 80.0, + "join_width": 0.8, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 34, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 80.0, + "join_width": 1.0, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 35, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 80.0, + "join_width": 1.0, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 36, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 90.0, + "join_width": 0.8, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 37, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 90.0, + "join_width": 0.8, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 38, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 90.0, + "join_width": 1.0, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 39, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 90.0, + "join_width": 1.0, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 40, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 100.0, + "join_width": 0.8, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 41, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 100.0, + "join_width": 0.8, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 42, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 100.0, + "join_width": 1.0, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 43, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 100.0, + "join_width": 1.0, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 44, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 110.0, + "join_width": 0.8, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 45, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 110.0, + "join_width": 0.8, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 46, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 110.0, + "join_width": 1.0, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 47, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 110.0, + "join_width": 1.0, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 48, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 80.0, + "join_width": 0.8, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 49, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 80.0, + "join_width": 0.8, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 50, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 80.0, + "join_width": 1.0, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 51, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 80.0, + "join_width": 1.0, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 52, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 90.0, + "join_width": 0.8, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 53, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 90.0, + "join_width": 0.8, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 54, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 90.0, + "join_width": 1.0, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 55, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 90.0, + "join_width": 1.0, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 56, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 100.0, + "join_width": 0.8, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 57, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 100.0, + "join_width": 0.8, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 58, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 100.0, + "join_width": 1.0, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 59, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 100.0, + "join_width": 1.0, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 60, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 110.0, + "join_width": 0.8, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 61, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 110.0, + "join_width": 0.8, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 62, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 110.0, + "join_width": 1.0, + "track_stagger": 24.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 63, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 110.0, + "join_width": 1.0, + "track_stagger": 28.0 + }, + "initial_prefix64": true + }, + { + "stream_index": 64, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 80.0, + "join_width": 0.8, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 65, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 80.0, + "join_width": 0.8, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 66, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 80.0, + "join_width": 1.0, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 67, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 80.0, + "join_width": 1.0, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 68, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 80.0, + "join_width": 1.2, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 69, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 80.0, + "join_width": 1.2, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 70, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 80.0, + "join_width": 1.2, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 71, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 80.0, + "join_width": 1.2, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 72, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 80.0, + "join_width": 1.4, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 73, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 80.0, + "join_width": 1.4, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 74, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 80.0, + "join_width": 1.4, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 75, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 80.0, + "join_width": 1.4, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 76, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 90.0, + "join_width": 0.8, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 77, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 90.0, + "join_width": 0.8, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 78, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 90.0, + "join_width": 1.0, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 79, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 90.0, + "join_width": 1.0, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 80, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 90.0, + "join_width": 1.2, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 81, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 90.0, + "join_width": 1.2, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 82, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 90.0, + "join_width": 1.2, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 83, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 90.0, + "join_width": 1.2, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 84, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 90.0, + "join_width": 1.4, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 85, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 90.0, + "join_width": 1.4, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 86, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 90.0, + "join_width": 1.4, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 87, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 90.0, + "join_width": 1.4, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 88, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 100.0, + "join_width": 0.8, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 89, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 100.0, + "join_width": 0.8, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 90, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 100.0, + "join_width": 1.0, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 91, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 100.0, + "join_width": 1.0, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 92, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 100.0, + "join_width": 1.2, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 93, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 100.0, + "join_width": 1.2, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 94, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 100.0, + "join_width": 1.2, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 95, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 100.0, + "join_width": 1.2, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 96, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 100.0, + "join_width": 1.4, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 97, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 100.0, + "join_width": 1.4, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 98, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 100.0, + "join_width": 1.4, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 99, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 100.0, + "join_width": 1.4, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 100, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 110.0, + "join_width": 0.8, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 101, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 110.0, + "join_width": 0.8, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 102, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 110.0, + "join_width": 1.0, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 103, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 110.0, + "join_width": 1.0, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 104, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 110.0, + "join_width": 1.2, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 105, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 110.0, + "join_width": 1.2, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 106, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 110.0, + "join_width": 1.2, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 107, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 110.0, + "join_width": 1.2, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 108, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 110.0, + "join_width": 1.4, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 109, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 110.0, + "join_width": 1.4, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 110, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 110.0, + "join_width": 1.4, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 111, + "controls": { + "branch_gap": 110.0, + "stack_pitch": 110.0, + "join_width": 1.4, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 112, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 80.0, + "join_width": 0.8, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 113, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 80.0, + "join_width": 0.8, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 114, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 80.0, + "join_width": 1.0, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 115, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 80.0, + "join_width": 1.0, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 116, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 80.0, + "join_width": 1.2, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 117, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 80.0, + "join_width": 1.2, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 118, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 80.0, + "join_width": 1.2, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 119, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 80.0, + "join_width": 1.2, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 120, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 80.0, + "join_width": 1.4, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 121, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 80.0, + "join_width": 1.4, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 122, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 80.0, + "join_width": 1.4, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 123, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 80.0, + "join_width": 1.4, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 124, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 90.0, + "join_width": 0.8, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 125, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 90.0, + "join_width": 0.8, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 126, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 90.0, + "join_width": 1.0, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 127, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 90.0, + "join_width": 1.0, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 128, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 90.0, + "join_width": 1.2, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 129, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 90.0, + "join_width": 1.2, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 130, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 90.0, + "join_width": 1.2, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 131, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 90.0, + "join_width": 1.2, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 132, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 90.0, + "join_width": 1.4, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 133, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 90.0, + "join_width": 1.4, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 134, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 90.0, + "join_width": 1.4, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 135, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 90.0, + "join_width": 1.4, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 136, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 100.0, + "join_width": 0.8, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 137, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 100.0, + "join_width": 0.8, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 138, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 100.0, + "join_width": 1.0, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 139, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 100.0, + "join_width": 1.0, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 140, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 100.0, + "join_width": 1.2, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 141, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 100.0, + "join_width": 1.2, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 142, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 100.0, + "join_width": 1.2, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 143, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 100.0, + "join_width": 1.2, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 144, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 100.0, + "join_width": 1.4, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 145, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 100.0, + "join_width": 1.4, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 146, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 100.0, + "join_width": 1.4, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 147, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 100.0, + "join_width": 1.4, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 148, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 110.0, + "join_width": 0.8, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 149, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 110.0, + "join_width": 0.8, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 150, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 110.0, + "join_width": 1.0, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 151, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 110.0, + "join_width": 1.0, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 152, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 110.0, + "join_width": 1.2, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 153, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 110.0, + "join_width": 1.2, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 154, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 110.0, + "join_width": 1.2, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 155, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 110.0, + "join_width": 1.2, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 156, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 110.0, + "join_width": 1.4, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 157, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 110.0, + "join_width": 1.4, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 158, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 110.0, + "join_width": 1.4, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 159, + "controls": { + "branch_gap": 125.0, + "stack_pitch": 110.0, + "join_width": 1.4, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 160, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 80.0, + "join_width": 0.8, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 161, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 80.0, + "join_width": 0.8, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 162, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 80.0, + "join_width": 1.0, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 163, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 80.0, + "join_width": 1.0, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 164, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 80.0, + "join_width": 1.2, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 165, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 80.0, + "join_width": 1.2, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 166, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 80.0, + "join_width": 1.2, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 167, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 80.0, + "join_width": 1.2, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 168, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 80.0, + "join_width": 1.4, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 169, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 80.0, + "join_width": 1.4, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 170, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 80.0, + "join_width": 1.4, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 171, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 80.0, + "join_width": 1.4, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 172, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 90.0, + "join_width": 0.8, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 173, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 90.0, + "join_width": 0.8, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 174, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 90.0, + "join_width": 1.0, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 175, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 90.0, + "join_width": 1.0, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 176, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 90.0, + "join_width": 1.2, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 177, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 90.0, + "join_width": 1.2, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 178, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 90.0, + "join_width": 1.2, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 179, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 90.0, + "join_width": 1.2, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 180, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 90.0, + "join_width": 1.4, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 181, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 90.0, + "join_width": 1.4, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 182, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 90.0, + "join_width": 1.4, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 183, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 90.0, + "join_width": 1.4, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 184, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 100.0, + "join_width": 0.8, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 185, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 100.0, + "join_width": 0.8, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 186, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 100.0, + "join_width": 1.0, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 187, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 100.0, + "join_width": 1.0, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 188, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 100.0, + "join_width": 1.2, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 189, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 100.0, + "join_width": 1.2, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 190, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 100.0, + "join_width": 1.2, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 191, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 100.0, + "join_width": 1.2, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 192, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 100.0, + "join_width": 1.4, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 193, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 100.0, + "join_width": 1.4, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 194, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 100.0, + "join_width": 1.4, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 195, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 100.0, + "join_width": 1.4, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 196, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 110.0, + "join_width": 0.8, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 197, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 110.0, + "join_width": 0.8, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 198, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 110.0, + "join_width": 1.0, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 199, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 110.0, + "join_width": 1.0, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 200, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 110.0, + "join_width": 1.2, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 201, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 110.0, + "join_width": 1.2, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 202, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 110.0, + "join_width": 1.2, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 203, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 110.0, + "join_width": 1.2, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 204, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 110.0, + "join_width": 1.4, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 205, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 110.0, + "join_width": 1.4, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 206, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 110.0, + "join_width": 1.4, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 207, + "controls": { + "branch_gap": 140.0, + "stack_pitch": 110.0, + "join_width": 1.4, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 208, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 80.0, + "join_width": 0.8, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 209, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 80.0, + "join_width": 0.8, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 210, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 80.0, + "join_width": 1.0, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 211, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 80.0, + "join_width": 1.0, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 212, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 80.0, + "join_width": 1.2, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 213, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 80.0, + "join_width": 1.2, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 214, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 80.0, + "join_width": 1.2, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 215, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 80.0, + "join_width": 1.2, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 216, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 80.0, + "join_width": 1.4, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 217, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 80.0, + "join_width": 1.4, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 218, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 80.0, + "join_width": 1.4, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 219, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 80.0, + "join_width": 1.4, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 220, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 90.0, + "join_width": 0.8, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 221, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 90.0, + "join_width": 0.8, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 222, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 90.0, + "join_width": 1.0, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 223, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 90.0, + "join_width": 1.0, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 224, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 90.0, + "join_width": 1.2, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 225, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 90.0, + "join_width": 1.2, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 226, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 90.0, + "join_width": 1.2, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 227, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 90.0, + "join_width": 1.2, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 228, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 90.0, + "join_width": 1.4, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 229, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 90.0, + "join_width": 1.4, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 230, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 90.0, + "join_width": 1.4, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 231, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 90.0, + "join_width": 1.4, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 232, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 100.0, + "join_width": 0.8, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 233, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 100.0, + "join_width": 0.8, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 234, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 100.0, + "join_width": 1.0, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 235, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 100.0, + "join_width": 1.0, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 236, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 100.0, + "join_width": 1.2, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 237, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 100.0, + "join_width": 1.2, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 238, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 100.0, + "join_width": 1.2, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 239, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 100.0, + "join_width": 1.2, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 240, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 100.0, + "join_width": 1.4, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 241, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 100.0, + "join_width": 1.4, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 242, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 100.0, + "join_width": 1.4, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 243, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 100.0, + "join_width": 1.4, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 244, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 110.0, + "join_width": 0.8, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 245, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 110.0, + "join_width": 0.8, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 246, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 110.0, + "join_width": 1.0, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 247, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 110.0, + "join_width": 1.0, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 248, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 110.0, + "join_width": 1.2, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 249, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 110.0, + "join_width": 1.2, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 250, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 110.0, + "join_width": 1.2, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 251, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 110.0, + "join_width": 1.2, + "track_stagger": 36.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 252, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 110.0, + "join_width": 1.4, + "track_stagger": 24.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 253, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 110.0, + "join_width": 1.4, + "track_stagger": 28.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 254, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 110.0, + "join_width": 1.4, + "track_stagger": 32.0 + }, + "initial_prefix64": false + }, + { + "stream_index": 255, + "controls": { + "branch_gap": 155.0, + "stack_pitch": 110.0, + "join_width": 1.4, + "track_stagger": 36.0 + }, + "initial_prefix64": false + } + ] + }, + "stream_selection": "First64successfullygenerated exactmask-distinct GDS notmatching anysamesource/sizingknown developmentmask; everyfailure/duplicate charged. This selection seesgeometryonly. A laterDRC/LVS/PEX/electricalfailure isneverreplaced byanotherstreammember. Stopat256 evenifunder64.", + "telescopic_development_disclosure": "Theoriginal64controlstream isunchanged asfirstprefix. Addtheremaining192of4^4byjoin_width1.2/1.4andstagger32/36 asprospectivereserves. This isdeclaredafterdefaultdevelopmentS2butbeforeanynondefaultorformalpoollayoutoutcomes. Theknownc00defaultmask andnewnondefaultcontrolmasksareexcludedbyexactgeometry, soatleastonenewreserveattemptmaybeneeded; baselinegeometryisnotrelabelledformal.", + "geometry_equivalence": "Existing src/e2_mask_geometry.py physicalfilled-layer Boolean-union/XOR withnormalizedtranslation andfixedSKY130annotationexclusions; labels/names/repartitioningneverdistinct. RetainacceptedGDSwhilepoolactive.", + "objective": { + "metric": "ugb", + "unit": "Hz", + "direction": "maximize", + "aggregation": "minimumovertt/ss/ff onlyafterallfrozenphysical/electricalconstraintscompleteandpassed" + }, + "finite_pool_no_feasible_or_unknown": "regret=null ifnofeasibleoracle ororacleincomplete; separatelyreportcompletedinfeasible,physicalfailure,unknown/censoredandNOT_RUN. Do notlower60degorotherlimits.", + "retained_legacy": "Old.5p/15p/4newNdiagnostic/16poolfailures andallcost remainoriginaldevelopmentcensored evidence. Theyarenotoneofthefournewformalpoolfamilies andarenotagentfailurelabels.", + "methods": { + "full_oracle": { + "pools": 12, + "full_budget_per_pool": 64, + "full_attempts_max": 768 + }, + "fixed_area": { + "pools": [ + "five_t_s0", + "five_t_s2", + "compact_miller_s0", + "compact_miller_s2", + "fvf_s0", + "fvf_s2" + ], + "full_budget_per_pool": 16, + "ranking": "actualL0bboxarea; noUGBprediction" + }, + "adaptive_geometry": { + "pools": [ + "five_t_s0", + "five_t_s2", + "compact_miller_s0", + "compact_miller_s2", + "fvf_s0", + "fvf_s2" + ], + "full_budget_per_pool": 16, + "ranking": "existingfixed2querybatcharea/wireheuristic; nofit" + }, + "fixed_rc_product": { + "pools": [ + "five_t_s0", + "five_t_s2", + "compact_miller_s0", + "compact_miller_s2", + "fvf_s0", + "fvf_s2" + ], + "full_budget_per_pool": 16, + "ranking": "Rsum*Csum afteractualfullRC; PEXfidelity/cost, notcheapL1" + }, + "f3_calibrated": { + "pools": [ + "five_t_s0", + "five_t_s2", + "compact_miller_s0", + "compact_miller_s2", + "fvf_s0", + "fvf_s2" + ], + "full_budget_per_pool": 16, + "actual_PEX_invocations_max_per_pool": 64, + "actual_TT_nominal_invocations_max_per_pool": 64, + "artifact": "runs/development/promotion_calibration_20261019T0353Z_nine_validation.json", + "fit_or_support_change_using_eval": false, + "force_full": "Unhealthy/incomplete/OODnominal; unsupportedpointsremainunverifiedwhen16fullbudgetends. PredictionsneverS2. ExistingOTAdefaults areOOD;zerosavingsplusoverheadisvalidnegative." + } + }, + "strategy_isolation": "Eachonlineexecution newlyregeneratesitsstreamandacquiresitsownGDS/PEX/nominal/fullmeasurements. Neverprovideofflineoraclelabelstoapromotionmethod; allmethodcode/calibration/stream/artifacts sealedbeforeanyformaloracledispatch.", + "minimal_implementation_reuse": { + "unchanged_core": [ + "scripts/e2_execution.py::Pool", + "scripts/e2_stage_prepare.py", + "scripts/e2_cached_evaluator.py", + "scripts/e2_nominal_bench.py", + "src/e2_mask_geometry.py", + "scripts/archive_e2_run.py" + ], + "new_telescopic_trusted_bundle": "Separateprotectedadapter copiedfromthefrozencommonphysicalprefix, withindependentteleN andtheliteralqualifiedbenchfunctions; do noteditE1LIVE orF3actualcontrolsnapshothelpers.", + "new_telescopic_measurement_adapter": "Source-specific fullshim mustreturnexisting normalizedcorner/analysis/metric schema. NominalmustactuallyrunoriginalTTOPandACas2separateSPICEcalls, noTran/DC/SS/FF; advertise2callsandactualcost, neverhardcode1.", + "new_dispatcher": "VersionedE2wrapperverifiesreadonlymanifest/sourceimplementation/calibrationbinding thenusesexistingPool;telescopic-specificPool.executeoverrideonlythederivednominalcapsulemodule/SPICEcount, notsharedhelpers. Frozennewtemplatealiasesownshim asota_frozen_bench.py soexistingfullcached physicalcorecanbereused unchanged.", + "freeze": "Onlyafterall12actualNcontrolsandrealteleisolatedgeometry\u2192positiveRC\u2192nominal\u2192fulltransportcontrol; freezeimmutablecompleteNs/bench/source/256patches/PDKexclusions/calibration/methodbudgets/qualifiedknownmasklist andappendtest-onlyregistryidentities. Recheckglobalregistryimmediatelybeforeappend; rootserializesfreezes.", + "guard": "Beforeeachnewpool verifyfrozenimplementationbytes andimmutableinputs. Neverauto-repeatanunresolvedreservedidentity. Each2CPU/8GiBcontainer usesactualbusy+2<=24/RAMused<=190GiB/diskfree>=4GiB." + }, + "required_actual_pre_freeze_controls": [ + "Newtelescopics0/s2sixideal+twofullpositives", + "Newtelescopicisolatedgeometry/PEX-only/actualTT2callnominal/fulltransport smoke withsameGDS/RC, originalbenchandTTtrace/UGBagreement; currentlynotimplemented/dispatched", + "Existingthree-sourceactualqualificationrawreinspectionandpinnedcontract/sourceclosure", + "Source-specificadapter/12poolmaterializationandall256patchcompilepreflight", + "Readonlytrain/validationcalibrationfreeze withoutrefit/supportwidening; all4methodsandfulloracleartifactssealed", + "Storagecapacityandrollingcompression smokealreadyimplemented; keepallrawandactualcost/nohiddenexport" + ], + "stage_costs": "ActualwaitedcontainerCPU/wall+perSPICEchildcost+hostpatch/mask/archiveCPU+queuewait; noallocatedCPUestimates ordoublecountcomponentCPU. Chargefailure/duplicate/timeoutandalllowfidelityacquisition.", + "formal_measurements_reused_from_development": 0, + "new_physical_calls_during_local_preparation": 0 +} diff --git a/benchmarks/code_behind_layout/configs/experiments/e2_telescopic_draft.json b/benchmarks/code_behind_layout/configs/experiments/e2_telescopic_draft.json new file mode 100644 index 00000000..b21660e3 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/experiments/e2_telescopic_draft.json @@ -0,0 +1,749 @@ +{ + "status": "DRAFT_CONDITIONAL_ON_FIRST_DECLARED_PHYSICAL_POSITIVE_CONTROL", + "scope": "Prospective fourth feasible independent E2 source proposal; no formal labels collected", + "new_source_identity": "independent_telescopic_mirror_ota", + "source": "src/generators/telescopic_ota.py", + "independent_reference": "src/generators/telescopic_ota_reference.py", + "baseline_ideal_control": "phase0_20261019T045154472544Z_telescopic_ota_characterization", + "first_predeclared_bias": "b00", + "bias_V": { + "VBN": 1.25, + "VBP": 0.45 + }, + "application": { + "VDD_V": 1.8, + "common_mode_V": 1.0, + "IREF_A": 1e-05, + "load_F": 2e-12, + "temperature_C": 27 + }, + "electrical_contract": "configs/development/telescopic_ota_fullflow.json", + "frozen_fixed_N_per_pool": true, + "sizings": [ + { + "sizing_id": "s0", + "sizing": { + "input_width": 2.7, + "input_length": 1.0, + "input_fingers": 2, + "ncas_width": 3.0, + "ncas_length": 0.5, + "ncas_fingers": 2, + "mirror_width": 3.0, + "mirror_length": 1.0, + "mirror_fingers": 4, + "pcas_width": 3.0, + "pcas_length": 0.5, + "pcas_fingers": 4, + "tail_width": 3.0, + "tail_length": 1.0, + "tail_fingers": 4 + }, + "independent_N_rule": "src.generators.telescopic_ota_reference.schematic(sizing)", + "intent_fingers": 32 + }, + { + "sizing_id": "s1", + "sizing": { + "input_width": 3.0, + "input_length": 1.0, + "input_fingers": 2, + "ncas_width": 3.0, + "ncas_length": 0.5, + "ncas_fingers": 2, + "mirror_width": 3.0, + "mirror_length": 1.0, + "mirror_fingers": 4, + "pcas_width": 3.0, + "pcas_length": 0.5, + "pcas_fingers": 4, + "tail_width": 3.0, + "tail_length": 1.0, + "tail_fingers": 4 + }, + "independent_N_rule": "src.generators.telescopic_ota_reference.schematic(sizing)", + "intent_fingers": 32 + }, + { + "sizing_id": "s2", + "sizing": { + "input_width": 3.3, + "input_length": 1.0, + "input_fingers": 2, + "ncas_width": 3.0, + "ncas_length": 0.5, + "ncas_fingers": 2, + "mirror_width": 3.0, + "mirror_length": 1.0, + "mirror_fingers": 4, + "pcas_width": 3.0, + "pcas_length": 0.5, + "pcas_fingers": 4, + "tail_width": 3.0, + "tail_length": 1.0, + "tail_fingers": 4 + }, + "independent_N_rule": "src.generators.telescopic_ota_reference.schematic(sizing)", + "intent_fingers": 32 + } + ], + "additional_sizing_qualification_before_freeze": "Six exact idealOPAC corner calls at s0/s2, then two real nondefault source-to-GDS fullflow controls; not dispatched by this file", + "geometry_controls_only": [ + "branch_gap", + "stack_pitch", + "join_width", + "track_stagger" + ], + "candidate_stream": [ + { + "stream_index": 0, + "candidate_id": "c00", + "controls": { + "branch_gap": 110.0, + "stack_pitch": 80.0, + "join_width": 0.8, + "track_stagger": 24.0 + } + }, + { + "stream_index": 1, + "candidate_id": "c01", + "controls": { + "branch_gap": 110.0, + "stack_pitch": 80.0, + "join_width": 0.8, + "track_stagger": 28.0 + } + }, + { + "stream_index": 2, + "candidate_id": "c02", + "controls": { + "branch_gap": 110.0, + "stack_pitch": 80.0, + "join_width": 1.0, + "track_stagger": 24.0 + } + }, + { + "stream_index": 3, + "candidate_id": "c03", + "controls": { + "branch_gap": 110.0, + "stack_pitch": 80.0, + "join_width": 1.0, + "track_stagger": 28.0 + } + }, + { + "stream_index": 4, + "candidate_id": "c04", + "controls": { + "branch_gap": 110.0, + "stack_pitch": 90.0, + "join_width": 0.8, + "track_stagger": 24.0 + } + }, + { + "stream_index": 5, + "candidate_id": "c05", + "controls": { + "branch_gap": 110.0, + "stack_pitch": 90.0, + "join_width": 0.8, + "track_stagger": 28.0 + } + }, + { + "stream_index": 6, + "candidate_id": "c06", + "controls": { + "branch_gap": 110.0, + "stack_pitch": 90.0, + "join_width": 1.0, + "track_stagger": 24.0 + } + }, + { + "stream_index": 7, + "candidate_id": "c07", + "controls": { + "branch_gap": 110.0, + "stack_pitch": 90.0, + "join_width": 1.0, + "track_stagger": 28.0 + } + }, + { + "stream_index": 8, + "candidate_id": "c08", + "controls": { + "branch_gap": 110.0, + "stack_pitch": 100.0, + "join_width": 0.8, + "track_stagger": 24.0 + } + }, + { + "stream_index": 9, + "candidate_id": "c09", + "controls": { + "branch_gap": 110.0, + "stack_pitch": 100.0, + "join_width": 0.8, + "track_stagger": 28.0 + } + }, + { + "stream_index": 10, + "candidate_id": "c10", + "controls": { + "branch_gap": 110.0, + "stack_pitch": 100.0, + "join_width": 1.0, + "track_stagger": 24.0 + } + }, + { + "stream_index": 11, + "candidate_id": "c11", + "controls": { + "branch_gap": 110.0, + "stack_pitch": 100.0, + "join_width": 1.0, + "track_stagger": 28.0 + } + }, + { + "stream_index": 12, + "candidate_id": "c12", + "controls": { + "branch_gap": 110.0, + "stack_pitch": 110.0, + "join_width": 0.8, + "track_stagger": 24.0 + } + }, + { + "stream_index": 13, + "candidate_id": "c13", + "controls": { + "branch_gap": 110.0, + "stack_pitch": 110.0, + "join_width": 0.8, + "track_stagger": 28.0 + } + }, + { + "stream_index": 14, + "candidate_id": "c14", + "controls": { + "branch_gap": 110.0, + "stack_pitch": 110.0, + "join_width": 1.0, + "track_stagger": 24.0 + } + }, + { + "stream_index": 15, + "candidate_id": "c15", + "controls": { + "branch_gap": 110.0, + "stack_pitch": 110.0, + "join_width": 1.0, + "track_stagger": 28.0 + } + }, + { + "stream_index": 16, + "candidate_id": "c16", + "controls": { + "branch_gap": 125.0, + "stack_pitch": 80.0, + "join_width": 0.8, + "track_stagger": 24.0 + } + }, + { + "stream_index": 17, + "candidate_id": "c17", + "controls": { + "branch_gap": 125.0, + "stack_pitch": 80.0, + "join_width": 0.8, + "track_stagger": 28.0 + } + }, + { + "stream_index": 18, + "candidate_id": "c18", + "controls": { + "branch_gap": 125.0, + "stack_pitch": 80.0, + "join_width": 1.0, + "track_stagger": 24.0 + } + }, + { + "stream_index": 19, + "candidate_id": "c19", + "controls": { + "branch_gap": 125.0, + "stack_pitch": 80.0, + "join_width": 1.0, + "track_stagger": 28.0 + } + }, + { + "stream_index": 20, + "candidate_id": "c20", + "controls": { + "branch_gap": 125.0, + "stack_pitch": 90.0, + "join_width": 0.8, + "track_stagger": 24.0 + } + }, + { + "stream_index": 21, + "candidate_id": "c21", + "controls": { + "branch_gap": 125.0, + "stack_pitch": 90.0, + "join_width": 0.8, + "track_stagger": 28.0 + } + }, + { + "stream_index": 22, + "candidate_id": "c22", + "controls": { + "branch_gap": 125.0, + "stack_pitch": 90.0, + "join_width": 1.0, + "track_stagger": 24.0 + } + }, + { + "stream_index": 23, + "candidate_id": "c23", + "controls": { + "branch_gap": 125.0, + "stack_pitch": 90.0, + "join_width": 1.0, + "track_stagger": 28.0 + } + }, + { + "stream_index": 24, + "candidate_id": "c24", + "controls": { + "branch_gap": 125.0, + "stack_pitch": 100.0, + "join_width": 0.8, + "track_stagger": 24.0 + } + }, + { + "stream_index": 25, + "candidate_id": "c25", + "controls": { + "branch_gap": 125.0, + "stack_pitch": 100.0, + "join_width": 0.8, + "track_stagger": 28.0 + } + }, + { + "stream_index": 26, + "candidate_id": "c26", + "controls": { + "branch_gap": 125.0, + "stack_pitch": 100.0, + "join_width": 1.0, + "track_stagger": 24.0 + } + }, + { + "stream_index": 27, + "candidate_id": "c27", + "controls": { + "branch_gap": 125.0, + "stack_pitch": 100.0, + "join_width": 1.0, + "track_stagger": 28.0 + } + }, + { + "stream_index": 28, + "candidate_id": "c28", + "controls": { + "branch_gap": 125.0, + "stack_pitch": 110.0, + "join_width": 0.8, + "track_stagger": 24.0 + } + }, + { + "stream_index": 29, + "candidate_id": "c29", + "controls": { + "branch_gap": 125.0, + "stack_pitch": 110.0, + "join_width": 0.8, + "track_stagger": 28.0 + } + }, + { + "stream_index": 30, + "candidate_id": "c30", + "controls": { + "branch_gap": 125.0, + "stack_pitch": 110.0, + "join_width": 1.0, + "track_stagger": 24.0 + } + }, + { + "stream_index": 31, + "candidate_id": "c31", + "controls": { + "branch_gap": 125.0, + "stack_pitch": 110.0, + "join_width": 1.0, + "track_stagger": 28.0 + } + }, + { + "stream_index": 32, + "candidate_id": "c32", + "controls": { + "branch_gap": 140.0, + "stack_pitch": 80.0, + "join_width": 0.8, + "track_stagger": 24.0 + } + }, + { + "stream_index": 33, + "candidate_id": "c33", + "controls": { + "branch_gap": 140.0, + "stack_pitch": 80.0, + "join_width": 0.8, + "track_stagger": 28.0 + } + }, + { + "stream_index": 34, + "candidate_id": "c34", + "controls": { + "branch_gap": 140.0, + "stack_pitch": 80.0, + "join_width": 1.0, + "track_stagger": 24.0 + } + }, + { + "stream_index": 35, + "candidate_id": "c35", + "controls": { + "branch_gap": 140.0, + "stack_pitch": 80.0, + "join_width": 1.0, + "track_stagger": 28.0 + } + }, + { + "stream_index": 36, + "candidate_id": "c36", + "controls": { + "branch_gap": 140.0, + "stack_pitch": 90.0, + "join_width": 0.8, + "track_stagger": 24.0 + } + }, + { + "stream_index": 37, + "candidate_id": "c37", + "controls": { + "branch_gap": 140.0, + "stack_pitch": 90.0, + "join_width": 0.8, + "track_stagger": 28.0 + } + }, + { + "stream_index": 38, + "candidate_id": "c38", + "controls": { + "branch_gap": 140.0, + "stack_pitch": 90.0, + "join_width": 1.0, + "track_stagger": 24.0 + } + }, + { + "stream_index": 39, + "candidate_id": "c39", + "controls": { + "branch_gap": 140.0, + "stack_pitch": 90.0, + "join_width": 1.0, + "track_stagger": 28.0 + } + }, + { + "stream_index": 40, + "candidate_id": "c40", + "controls": { + "branch_gap": 140.0, + "stack_pitch": 100.0, + "join_width": 0.8, + "track_stagger": 24.0 + } + }, + { + "stream_index": 41, + "candidate_id": "c41", + "controls": { + "branch_gap": 140.0, + "stack_pitch": 100.0, + "join_width": 0.8, + "track_stagger": 28.0 + } + }, + { + "stream_index": 42, + "candidate_id": "c42", + "controls": { + "branch_gap": 140.0, + "stack_pitch": 100.0, + "join_width": 1.0, + "track_stagger": 24.0 + } + }, + { + "stream_index": 43, + "candidate_id": "c43", + "controls": { + "branch_gap": 140.0, + "stack_pitch": 100.0, + "join_width": 1.0, + "track_stagger": 28.0 + } + }, + { + "stream_index": 44, + "candidate_id": "c44", + "controls": { + "branch_gap": 140.0, + "stack_pitch": 110.0, + "join_width": 0.8, + "track_stagger": 24.0 + } + }, + { + "stream_index": 45, + "candidate_id": "c45", + "controls": { + "branch_gap": 140.0, + "stack_pitch": 110.0, + "join_width": 0.8, + "track_stagger": 28.0 + } + }, + { + "stream_index": 46, + "candidate_id": "c46", + "controls": { + "branch_gap": 140.0, + "stack_pitch": 110.0, + "join_width": 1.0, + "track_stagger": 24.0 + } + }, + { + "stream_index": 47, + "candidate_id": "c47", + "controls": { + "branch_gap": 140.0, + "stack_pitch": 110.0, + "join_width": 1.0, + "track_stagger": 28.0 + } + }, + { + "stream_index": 48, + "candidate_id": "c48", + "controls": { + "branch_gap": 155.0, + "stack_pitch": 80.0, + "join_width": 0.8, + "track_stagger": 24.0 + } + }, + { + "stream_index": 49, + "candidate_id": "c49", + "controls": { + "branch_gap": 155.0, + "stack_pitch": 80.0, + "join_width": 0.8, + "track_stagger": 28.0 + } + }, + { + "stream_index": 50, + "candidate_id": "c50", + "controls": { + "branch_gap": 155.0, + "stack_pitch": 80.0, + "join_width": 1.0, + "track_stagger": 24.0 + } + }, + { + "stream_index": 51, + "candidate_id": "c51", + "controls": { + "branch_gap": 155.0, + "stack_pitch": 80.0, + "join_width": 1.0, + "track_stagger": 28.0 + } + }, + { + "stream_index": 52, + "candidate_id": "c52", + "controls": { + "branch_gap": 155.0, + "stack_pitch": 90.0, + "join_width": 0.8, + "track_stagger": 24.0 + } + }, + { + "stream_index": 53, + "candidate_id": "c53", + "controls": { + "branch_gap": 155.0, + "stack_pitch": 90.0, + "join_width": 0.8, + "track_stagger": 28.0 + } + }, + { + "stream_index": 54, + "candidate_id": "c54", + "controls": { + "branch_gap": 155.0, + "stack_pitch": 90.0, + "join_width": 1.0, + "track_stagger": 24.0 + } + }, + { + "stream_index": 55, + "candidate_id": "c55", + "controls": { + "branch_gap": 155.0, + "stack_pitch": 90.0, + "join_width": 1.0, + "track_stagger": 28.0 + } + }, + { + "stream_index": 56, + "candidate_id": "c56", + "controls": { + "branch_gap": 155.0, + "stack_pitch": 100.0, + "join_width": 0.8, + "track_stagger": 24.0 + } + }, + { + "stream_index": 57, + "candidate_id": "c57", + "controls": { + "branch_gap": 155.0, + "stack_pitch": 100.0, + "join_width": 0.8, + "track_stagger": 28.0 + } + }, + { + "stream_index": 58, + "candidate_id": "c58", + "controls": { + "branch_gap": 155.0, + "stack_pitch": 100.0, + "join_width": 1.0, + "track_stagger": 24.0 + } + }, + { + "stream_index": 59, + "candidate_id": "c59", + "controls": { + "branch_gap": 155.0, + "stack_pitch": 100.0, + "join_width": 1.0, + "track_stagger": 28.0 + } + }, + { + "stream_index": 60, + "candidate_id": "c60", + "controls": { + "branch_gap": 155.0, + "stack_pitch": 110.0, + "join_width": 0.8, + "track_stagger": 24.0 + } + }, + { + "stream_index": 61, + "candidate_id": "c61", + "controls": { + "branch_gap": 155.0, + "stack_pitch": 110.0, + "join_width": 0.8, + "track_stagger": 28.0 + } + }, + { + "stream_index": 62, + "candidate_id": "c62", + "controls": { + "branch_gap": 155.0, + "stack_pitch": 110.0, + "join_width": 1.0, + "track_stagger": 24.0 + } + }, + { + "stream_index": 63, + "candidate_id": "c63", + "controls": { + "branch_gap": 155.0, + "stack_pitch": 110.0, + "join_width": 1.0, + "track_stagger": 28.0 + } + } + ], + "distinctness_requirement": "64 unique filled masks using all-layer Boolean-union/XOR after common translation normalization; names/labels do not establish distinctness", + "generation_attempt_cap_per_sizing": 256, + "duplicates_and_failures": "Retain original stream, dispatch, cost and geometry duplicate dispositions; no retrospective label or silent replacement", + "formal_labels_or_policy_trials": 0, + "physical_control_required": "Original first-declared b00 exact source N and new contract must complete fullruleDRC/independentLVS/exactdevicegraph/positivefullRC/all3cornerOPACTranDC; failure stays unadmitted", + "source_ancestry": "Independent explicit two-column four-tier cascode-mirror assembly. Shared MOS/via/PDK/terminal_access constraints disclosed; no existing OTA target assembly import/copy or universal circuit compiler. Full source-dependency/merged-cluster sensitivity retained.", + "development_selection_disclosure": "Range written after ideal12 predeclared bias controls, before returned physical fullflow; no telescopic layout outcome used. Existing 5T/compact/FVF development experience informed choosing noncrowding spacing and legal metal widths. This is prospective development-informed E2 design, not a blind validation claim.", + "legacy_disposition": "All old legacy pools, N, spec failures and cost remain unchanged and censored where no feasible oracle; this new source never replaces their labels or denominator", + "execution_adapter_status": "Pending independent source-specific frozen trusted adapter; existing E1/F3 measurement snapshots are not modified", + "formal_execution_allowed": false +} diff --git a/benchmarks/code_behind_layout/configs/experiments/e3_instance_arrivals_draft.json b/benchmarks/code_behind_layout/configs/experiments/e3_instance_arrivals_draft.json new file mode 100644 index 00000000..1704660a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/experiments/e3_instance_arrivals_draft.json @@ -0,0 +1,27 @@ +[ + "anchor", + "hidden_14", + "hidden_07", + "dev_02", + "hidden_13", + "hidden_05", + "hidden_06", + "hidden_15", + "hidden_16", + "dev_08", + "dev_05", + "hidden_09", + "hidden_04", + "hidden_12", + "dev_03", + "dev_06", + "dev_01", + "hidden_01", + "hidden_02", + "hidden_10", + "hidden_08", + "dev_07", + "dev_04", + "hidden_03", + "hidden_11" +] diff --git a/benchmarks/code_behind_layout/configs/experiments/e3_matched_draft.json b/benchmarks/code_behind_layout/configs/experiments/e3_matched_draft.json new file mode 100644 index 00000000..093f03ea --- /dev/null +++ b/benchmarks/code_behind_layout/configs/experiments/e3_matched_draft.json @@ -0,0 +1,178 @@ +{ + "status": "DRAFT_E3_RUNNER", + "formal_dispatch": false, + "preparation": "runtime/task_preparation/e3_expanded_P_20261019T035505371049Z", + "task_ids": [ + "draft_E3_mirror_edit01", + "draft_E3_mirror_edit02", + "draft_E3_mirror_edit03", + "draft_E3_cascode_mirror_edit01", + "draft_E3_cascode_mirror_edit02", + "draft_E3_cascode_mirror_edit03", + "draft_E3_source_follower_edit01", + "draft_E3_source_follower_edit02", + "draft_E3_source_follower_edit03", + "draft_E3_stacked_switch_edit01", + "draft_E3_stacked_switch_edit02", + "draft_E3_stacked_switch_edit03", + "draft_E3_common_source_stage_edit01", + "draft_E3_common_source_stage_edit02", + "draft_E3_common_source_stage_edit03", + "draft_E3_resistive_diff_edit01", + "draft_E3_resistive_diff_edit02", + "draft_E3_resistive_diff_edit03", + "draft_E3_five_t_edit01", + "draft_E3_five_t_edit02", + "draft_E3_five_t_edit03", + "draft_E3_compact_miller_edit01", + "draft_E3_compact_miller_edit02", + "draft_E3_compact_miller_edit03" + ], + "methods": [ + "A", + "R", + "B", + "C" + ], + "trials": 5, + "selection_seeds": [ + 41, + 73, + 109, + 167, + 223 + ], + "model_config": "configs/models/gpt_e3_16k.draft.json", + "risk_model": "results/derived/e3_visible_risk_rule_status_predicate_v1.json", + "risk_weights": { + "failure_probability": 0, + "uncertainty": 1, + "changed_call_coverage": 0, + "low_margin": 1 + }, + "weight_status": "PREDECLARED_EQUAL_WEIGHT_TRANSPARENT_RULE_NOT_VALIDATION_TUNED", + "fidelity_policy": "F0_actual_full_each_selected_configuration", + "budget_status": "ACTUAL_96PACKET_AND_EIGHT_REAL_FEEDBACK_STRESS_FIT_16K_PENDING_GPU_AND_POLICY_CONTROL", + "budget": { + "wall_seconds": 14400, + "decisions": 24, + "patches": 8, + "full_evaluations": 8, + "maximum_context_tokens": 16384, + "maximum_output_tokens": 1024 + }, + "parameter_baseline": { + "configuration_selector": "C", + "strategies": [ + "random", + "gpt_feedback" + ], + "interface": "prospective_expanded_layout_grid_v1" + }, + "freeze_blockers": [ + "24 actually qualified editing states and at least12 genuine natural or clean-poor shortfalls", + "Actual near-full12k H100 SFT/DPO/checkpoint restore and consistent serving", + "Complete source plus actual feedback history calibration and real gateway control", + "Prospectively frozen transparent-rule artifact and explicitly disclosed unavailable probabilistic variant", + "All24 exact initial parameter-render byte bindings", + "Immutable original-program baseline plan; actual hidden vectors after global sealing release", + "E3 own registry, implementation, analysis and dispatch freeze" + ], + "parameter_task_ids": [ + "draft_E3_mirror_edit02", + "draft_E3_cascode_mirror_edit02", + "draft_E3_source_follower_edit02", + "draft_E3_stacked_switch_edit02", + "draft_E3_common_source_stage_edit02", + "draft_E3_resistive_diff_edit02", + "draft_E3_five_t_edit02", + "draft_E3_compact_miller_edit02" + ], + "instance_task_ids": [ + "draft_E3_mirror_edit02", + "draft_E3_cascode_mirror_edit02", + "draft_E3_source_follower_edit02", + "draft_E3_stacked_switch_edit02", + "draft_E3_common_source_stage_edit02", + "draft_E3_resistive_diff_edit02", + "draft_E3_five_t_edit02", + "draft_E3_compact_miller_edit02" + ], + "instance_trials": 1, + "dispatch_order_seed": 20261019, + "e4_methods_manifest": "runtime/protocol_freezes/E4_primary/manifest.json", + "global_release_parts": [ + "gpt", + "parameter", + "local", + "signals", + "fidelity" + ], + "global_release_requires_fidelity_freeze": true, + "fidelity_manifest": "runtime/protocol_freezes/E3_F3_primary/manifest.json", + "e4_evaluation": { + "variants": [ + "T0", + "T1", + "T2", + "T3", + "T4" + ], + "matched_evaluation_seed_slots": [ + 41, + 73, + 109 + ], + "inference_trials": 3, + "T0_actual_model_count": 1, + "T0_independent_training_seeds": 0 + }, + "instance_baseline": { + "algorithm": "independent_arrivals_with_verified_library_exact_cache_v1", + "warm_start": "nearest_previous_verified_configuration_then_latest", + "cache": "exact_source_configuration_reference_PDK_deck_tools_fidelity", + "arrival_order": "configs/experiments/e3_instance_arrivals_draft.json", + "deployment_verification_maximum_physical_calls": 1, + "budget": { + "wall_seconds": 14400, + "decisions": 24, + "patches": 8, + "full_evaluations": 8, + "maximum_context_tokens": 16384, + "maximum_output_tokens": 1024 + }, + "budget_scope": "Same per-arrival search limits as one shared-code episode; every arrival, cache, verification and library cost is charged separately for cumulative cost comparison." + }, + "signal_task_ids": [ + "draft_E3_mirror_edit02", + "draft_E3_cascode_mirror_edit02", + "draft_E3_source_follower_edit02", + "draft_E3_stacked_switch_edit02", + "draft_E3_common_source_stage_edit02", + "draft_E3_resistive_diff_edit02", + "draft_E3_five_t_edit02", + "draft_E3_compact_miller_edit02" + ], + "selector_ablation_weights": { + "without_distance": { + "failure_probability": 0, + "uncertainty": 0, + "changed_call_coverage": 0, + "low_margin": 1 + }, + "without_margin": { + "failure_probability": 0, + "uncertainty": 1, + "changed_call_coverage": 0, + "low_margin": 0 + } + }, + "unavailable_signal_ablation": { + "changed_call_coverage": "No validated current impact map; weight0 in main, so a duplicate run would not identify an effect", + "failure_probability": "No qualified mixed-label family vectors; transparent-rule fallback has weight0" + }, + "fidelity_task_ids": [ + "draft_E3_five_t_edit02", + "draft_E3_compact_miller_edit02" + ] +} diff --git a/benchmarks/code_behind_layout/configs/experiments/frozen/E1_20261019T0410Z.json b/benchmarks/code_behind_layout/configs/experiments/frozen/E1_20261019T0410Z.json new file mode 100644 index 00000000..3da02b92 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/experiments/frozen/E1_20261019T0410Z.json @@ -0,0 +1,330 @@ +{ + "status": "FROZEN_E1", + "formal_dispatch": true, + "phase": "formal_E1", + "packet_root": "/srv/code-behind-layout/runtime/protocol_freezes/E1_20261019T0410Z/packets", + "task_catalog": "/srv/code-behind-layout/runtime/protocol_freezes/E1_20261019T0410Z/packets/public/catalog.json", + "task_ids": [ + "draft_E1_mirror_s01", + "draft_E1_mirror_s02", + "draft_E1_mirror_s03", + "draft_E1_cascode_mirror_s01", + "draft_E1_cascode_mirror_s02", + "draft_E1_cascode_mirror_s03", + "draft_E1_source_follower_s01", + "draft_E1_source_follower_s02", + "draft_E1_source_follower_s03", + "draft_E1_stacked_switch_s01", + "draft_E1_stacked_switch_s02", + "draft_E1_stacked_switch_s03", + "draft_E1_common_source_stage_s01", + "draft_E1_common_source_stage_s02", + "draft_E1_common_source_stage_s03", + "draft_E1_resistive_diff_s01", + "draft_E1_resistive_diff_s02", + "draft_E1_resistive_diff_s03", + "draft_E1_five_t_s01", + "draft_E1_five_t_s02", + "draft_E1_five_t_s03", + "draft_E1_compact_miller_s01", + "draft_E1_compact_miller_s02", + "draft_E1_compact_miller_s03" + ], + "methods": [ + "G0", + "G1", + "G2" + ], + "trials": 5, + "model_config": "/srv/code-behind-layout/runtime/protocol_freezes/E1_20261019T0410Z/model_config.json", + "visible_history_policy": "current_source_and_feedback_v1", + "budget": { + "wall_seconds": 1200, + "decisions": 10, + "physical_evaluations": 3, + "maximum_context_tokens": 8192, + "maximum_output_tokens": 1024 + }, + "runtime": { + "EDA": "runtime/GLdev", + "magic": "runtime/magic-8.3.685", + "candidate_CPUs": 2, + "simultaneous_point_workers_per_episode": 1 + }, + "trusted_bench_bindings": "Built independently per task by scripts/e1_matched_runner.py; no target assembly enters the trusted evaluator.", + "post_freeze": { + "visible": "Fill current-source anchor plus eight development points without policy feedback; separately charge post_freeze_diagnostic.", + "hidden": "Evaluate sixteen points once after source sealing; all raw hidden results stay on trusted backend.", + "incomplete": "Stop affected episode on unknown/infrastructure, retain observed denominators and label no missing outcomes." + }, + "grouping": { + "target_logics": 8, + "primary_groups": 8, + "merged_sensitivity_groups": 7, + "strata": { + "reuse": 12, + "composition": 12 + }, + "shared_domains": "Three sized tasks per target rotate roles of the same25 points, explicitly linked in private/shared_domain_relationships.json. Fresh isolated trials receive only their own fixed nine visible points." + }, + "freeze_blockers": [], + "freeze_id": "E1_20261019T0410Z", + "backend_manifest_path": "/srv/code-behind-layout/runtime/protocol_freezes/E1_20261019T0410Z/manifest.json", + "frozen_at_utc": "2026-10-19T04:29:16.570135+00:00", + "tasks": [ + { + "task_id": "draft_E1_mirror_s01", + "target": "mirror", + "stratum": "reuse", + "source_group": "vendor_glayout_connected", + "merged_source_group": "vendor_glayout_connected", + "parent_lineage": "glayout_mirror", + "shared_domain_id": "mirror_narrow_v3_shared25_mirror" + }, + { + "task_id": "draft_E1_mirror_s02", + "target": "mirror", + "stratum": "composition", + "source_group": "vendor_glayout_connected", + "merged_source_group": "vendor_glayout_connected", + "parent_lineage": "glayout_mirror", + "shared_domain_id": "mirror_narrow_v3_shared25_mirror" + }, + { + "task_id": "draft_E1_mirror_s03", + "target": "mirror", + "stratum": "reuse", + "source_group": "vendor_glayout_connected", + "merged_source_group": "vendor_glayout_connected", + "parent_lineage": "glayout_mirror", + "shared_domain_id": "mirror_narrow_v3_shared25_mirror" + }, + { + "task_id": "draft_E1_cascode_mirror_s01", + "target": "cascode_mirror", + "stratum": "composition", + "source_group": "research_cascode_mirror", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_cascode_mirror", + "shared_domain_id": "exact_grid_v2_shared25_cascode_mirror" + }, + { + "task_id": "draft_E1_cascode_mirror_s02", + "target": "cascode_mirror", + "stratum": "reuse", + "source_group": "research_cascode_mirror", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_cascode_mirror", + "shared_domain_id": "exact_grid_v2_shared25_cascode_mirror" + }, + { + "task_id": "draft_E1_cascode_mirror_s03", + "target": "cascode_mirror", + "stratum": "composition", + "source_group": "research_cascode_mirror", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_cascode_mirror", + "shared_domain_id": "exact_grid_v2_shared25_cascode_mirror" + }, + { + "task_id": "draft_E1_source_follower_s01", + "target": "source_follower", + "stratum": "reuse", + "source_group": "research_source_follower", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_source_follower", + "shared_domain_id": "exact_grid_v2_shared25_source_follower" + }, + { + "task_id": "draft_E1_source_follower_s02", + "target": "source_follower", + "stratum": "composition", + "source_group": "research_source_follower", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_source_follower", + "shared_domain_id": "exact_grid_v2_shared25_source_follower" + }, + { + "task_id": "draft_E1_source_follower_s03", + "target": "source_follower", + "stratum": "reuse", + "source_group": "research_source_follower", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_source_follower", + "shared_domain_id": "exact_grid_v2_shared25_source_follower" + }, + { + "task_id": "draft_E1_stacked_switch_s01", + "target": "stacked_switch", + "stratum": "composition", + "source_group": "research_stacked_switch", + "merged_source_group": "research_stacked_switch", + "parent_lineage": "research_stacked_switch", + "shared_domain_id": "exact_grid_v2_shared25_stacked_switch" + }, + { + "task_id": "draft_E1_stacked_switch_s02", + "target": "stacked_switch", + "stratum": "reuse", + "source_group": "research_stacked_switch", + "merged_source_group": "research_stacked_switch", + "parent_lineage": "research_stacked_switch", + "shared_domain_id": "exact_grid_v2_shared25_stacked_switch" + }, + { + "task_id": "draft_E1_stacked_switch_s03", + "target": "stacked_switch", + "stratum": "composition", + "source_group": "research_stacked_switch", + "merged_source_group": "research_stacked_switch", + "parent_lineage": "research_stacked_switch", + "shared_domain_id": "exact_grid_v2_shared25_stacked_switch" + }, + { + "task_id": "draft_E1_common_source_stage_s01", + "target": "common_source_stage", + "stratum": "reuse", + "source_group": "research_common_source_stage", + "merged_source_group": "research_common_source_stage", + "parent_lineage": "research_common_source_stage", + "shared_domain_id": "exact_grid_v2_shared25_common_source_stage" + }, + { + "task_id": "draft_E1_common_source_stage_s02", + "target": "common_source_stage", + "stratum": "composition", + "source_group": "research_common_source_stage", + "merged_source_group": "research_common_source_stage", + "parent_lineage": "research_common_source_stage", + "shared_domain_id": "exact_grid_v2_shared25_common_source_stage" + }, + { + "task_id": "draft_E1_common_source_stage_s03", + "target": "common_source_stage", + "stratum": "reuse", + "source_group": "research_common_source_stage", + "merged_source_group": "research_common_source_stage", + "parent_lineage": "research_common_source_stage", + "shared_domain_id": "exact_grid_v2_shared25_common_source_stage" + }, + { + "task_id": "draft_E1_resistive_diff_s01", + "target": "resistive_diff", + "stratum": "composition", + "source_group": "research_resistive_diff", + "merged_source_group": "research_resistive_diff", + "parent_lineage": "research_resistive_diff", + "shared_domain_id": "exact_grid_v2_shared25_resistive_diff" + }, + { + "task_id": "draft_E1_resistive_diff_s02", + "target": "resistive_diff", + "stratum": "reuse", + "source_group": "research_resistive_diff", + "merged_source_group": "research_resistive_diff", + "parent_lineage": "research_resistive_diff", + "shared_domain_id": "exact_grid_v2_shared25_resistive_diff" + }, + { + "task_id": "draft_E1_resistive_diff_s03", + "target": "resistive_diff", + "stratum": "composition", + "source_group": "research_resistive_diff", + "merged_source_group": "research_resistive_diff", + "parent_lineage": "research_resistive_diff", + "shared_domain_id": "exact_grid_v2_shared25_resistive_diff" + }, + { + "task_id": "draft_E1_five_t_s01", + "target": "five_t", + "stratum": "reuse", + "source_group": "research_five_t", + "merged_source_group": "research_five_t", + "parent_lineage": "research_five_t", + "shared_domain_id": "exact_grid_v2_shared25_five_t" + }, + { + "task_id": "draft_E1_five_t_s02", + "target": "five_t", + "stratum": "composition", + "source_group": "research_five_t", + "merged_source_group": "research_five_t", + "parent_lineage": "research_five_t", + "shared_domain_id": "exact_grid_v2_shared25_five_t" + }, + { + "task_id": "draft_E1_five_t_s03", + "target": "five_t", + "stratum": "reuse", + "source_group": "research_five_t", + "merged_source_group": "research_five_t", + "parent_lineage": "research_five_t", + "shared_domain_id": "exact_grid_v2_shared25_five_t" + }, + { + "task_id": "draft_E1_compact_miller_s01", + "target": "compact_miller", + "stratum": "composition", + "source_group": "research_compact_miller", + "merged_source_group": "research_compact_miller", + "parent_lineage": "research_compact_miller", + "shared_domain_id": "exact_grid_v2_shared25_compact_miller" + }, + { + "task_id": "draft_E1_compact_miller_s02", + "target": "compact_miller", + "stratum": "reuse", + "source_group": "research_compact_miller", + "merged_source_group": "research_compact_miller", + "parent_lineage": "research_compact_miller", + "shared_domain_id": "exact_grid_v2_shared25_compact_miller" + }, + { + "task_id": "draft_E1_compact_miller_s03", + "target": "compact_miller", + "stratum": "composition", + "source_group": "research_compact_miller", + "merged_source_group": "research_compact_miller", + "parent_lineage": "research_compact_miller", + "shared_domain_id": "exact_grid_v2_shared25_compact_miller" + } + ], + "source_revision": "ece66e62e0512c8aa4180461fb323af0aa4e4978", + "implementation_sha256": { + "src/candidate_executor.py": "2aa700405ed2c52869c3c6a6a039ab2afe8ca02372cb2fe5432c04fb1c5c66e6", + "src/domain_runner.py": "e9ef34b451b1b0cdbe6e6275e69ebd3448c209a4718b4d7375355628f44d0ddf", + "src/model_adapter.py": "fa737a01c9b23dbf4ed0b4d1d6ba391637c0c769af56252ac6bcdbe4f0a71338", + "src/local_model_adapter.py": "24e99a3ad5d6dc0a46db7441683fcbfb36507f59f8efeee537b09dbd1be8e283", + "src/policy_state.py": "c8803e428d5da62aa6ad886c2cae650fb1fa27fb26d011fdc238a513543751a4", + "src/e1_packets.py": "03562f228f77e81577ec6a03c8ca405044ec80d4a7f7cb8492e486ed27aaa6fc", + "src/e1_benchmarks.py": "22e89b29bd2319fd8a6c9cf5ac9d690699b52e3432456c5d37bc5300b862dcc4", + "src/report_parsers.py": "4ad6a2124e2a573a40910aa13a3ee61cd00e6eb8dd4fba218e1d129cbea994f8", + "src/measurement.py": "1e9736325e094e023f7f5be1fba4a2328ca61a16ea1667e3f88496e6bf64f18f", + "src/spice_validation.py": "76b3b34fa9013f5165fd5af66b71101c2835786b2d86df2289f9641a4dd2d628", + "src/device_intent.py": "895976ed93024bc30aee2d7afef75eb895261a61742c9ab9a777c7ae68f2de3d", + "src/e1_analysis.py": "7765dafd874b3db242f0bd4b6004b0d7e00526a3c3d5edf64485a4015881b901", + "scripts/e1_matched_runner.py": "1658264fc4be12520231f27f0a5d15bfc185000833a7dfc14953eb81b42f8856", + "scripts/materialize_e1_packets.py": "51064bb1614ad32dfe20bd51eed3a066fce7c626ac8bc648ff726ae56260ea2a", + "scripts/e1_pcell_prepare.py": "b3bd32774eae9a79257a7cedb3d2f9d718c93023ff95268bc1434a42f5162daa", + "scripts/run_eda_probe.py": "1f5229c918cc7b563f1f6c03c733bb46eb06f60d0cc246aa2a70c510bd65f5f1", + "scripts/analyze_e1.py": "adbf72f0d475190647a6b38cc3961682452f7fdc5c682931150565cc95fd450a", + "scripts/run_e1_suite.py": "7f7fd2a35b75459553f1a64f62ad5f855bb15fea3c5ff3c993c230d9fc13881a", + "scripts/archive_e1_episode.py": "02a7d42e02df3b7cfeb86b1b0113c91e5bbeb1d2d550cd41b6d52ea79dcea540" + }, + "frozen_registry": "/srv/code-behind-layout/runtime/protocol_freezes/E1_20261019T0410Z/registry.json", + "qualification": { + "mechanical": "/srv/code-behind-layout/runtime/protocol_freezes/E1_20261019T0410Z/mechanical_controls.json", + "schematic": "/srv/code-behind-layout/runtime/protocol_freezes/E1_20261019T0410Z/circuit_feasibility.json" + }, + "dispatch_order_seed": 20261018, + "GPT_sampling_seed": "unavailable; fresh independent trial identifiers only", + "primary_contrasts": [ + "G1-G0", + "G2-G1" + ], + "analysis": { + "stratify_by": "reuse/composition", + "cluster_bootstrap_replicates": 2000, + "bootstrap_seed": 20261018 + } +} diff --git a/benchmarks/code_behind_layout/configs/experiments/frozen/E1_20261019T0449Z_permission_fix.json b/benchmarks/code_behind_layout/configs/experiments/frozen/E1_20261019T0449Z_permission_fix.json new file mode 100644 index 00000000..284ef667 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/experiments/frozen/E1_20261019T0449Z_permission_fix.json @@ -0,0 +1,364 @@ +{ + "status": "FROZEN_E1", + "formal_dispatch": true, + "phase": "formal_E1", + "packet_root": "/srv/code-behind-layout/runtime/protocol_freezes/E1_20261019T0449Z_permission_fix/packets", + "task_catalog": "/srv/code-behind-layout/runtime/protocol_freezes/E1_20261019T0449Z_permission_fix/packets/public/catalog.json", + "task_ids": [ + "draft_E1_mirror_s01", + "draft_E1_mirror_s02", + "draft_E1_mirror_s03", + "draft_E1_cascode_mirror_s01", + "draft_E1_cascode_mirror_s02", + "draft_E1_cascode_mirror_s03", + "draft_E1_source_follower_s01", + "draft_E1_source_follower_s02", + "draft_E1_source_follower_s03", + "draft_E1_stacked_switch_s01", + "draft_E1_stacked_switch_s02", + "draft_E1_stacked_switch_s03", + "draft_E1_common_source_stage_s01", + "draft_E1_common_source_stage_s02", + "draft_E1_common_source_stage_s03", + "draft_E1_resistive_diff_s01", + "draft_E1_resistive_diff_s02", + "draft_E1_resistive_diff_s03", + "draft_E1_five_t_s01", + "draft_E1_five_t_s02", + "draft_E1_five_t_s03", + "draft_E1_compact_miller_s01", + "draft_E1_compact_miller_s02", + "draft_E1_compact_miller_s03" + ], + "methods": [ + "G0", + "G1", + "G2" + ], + "trials": 5, + "model_config": "/srv/code-behind-layout/runtime/protocol_freezes/E1_20261019T0449Z_permission_fix/model_config.json", + "visible_history_policy": "current_source_and_feedback_v1", + "budget": { + "wall_seconds": 1200, + "decisions": 10, + "physical_evaluations": 3, + "maximum_context_tokens": 8192, + "maximum_output_tokens": 1024 + }, + "runtime": { + "EDA": "runtime/GLdev", + "magic": "runtime/magic-8.3.685", + "candidate_CPUs": 2, + "simultaneous_point_workers_per_episode": 1 + }, + "trusted_bench_bindings": "Built independently per task by scripts/e1_matched_runner.py; no target assembly enters the trusted evaluator.", + "post_freeze": { + "visible": "Fill current-source anchor plus eight development points without policy feedback; separately charge post_freeze_diagnostic.", + "hidden": "Evaluate sixteen points once after source sealing; all raw hidden results stay on trusted backend.", + "incomplete": "Stop affected episode on unknown/infrastructure, retain observed denominators and label no missing outcomes." + }, + "grouping": { + "target_logics": 8, + "primary_groups": 8, + "merged_sensitivity_groups": 7, + "strata": { + "reuse": 12, + "composition": 12 + }, + "shared_domains": "Three sized tasks per target rotate roles of the same25 points, explicitly linked in private/shared_domain_relationships.json. Fresh isolated trials receive only their own fixed nine visible points." + }, + "freeze_blockers": [], + "freeze_id": "E1_20261019T0449Z_permission_fix", + "backend_manifest_path": "/srv/code-behind-layout/runtime/protocol_freezes/E1_20261019T0449Z_permission_fix/manifest.json", + "frozen_at_utc": "2026-10-19T04:49:49.974155+00:00", + "tasks": [ + { + "task_id": "draft_E1_mirror_s01", + "target": "mirror", + "stratum": "reuse", + "source_group": "vendor_glayout_connected", + "merged_source_group": "vendor_glayout_connected", + "parent_lineage": "glayout_mirror", + "shared_domain_id": "mirror_narrow_v3_shared25_mirror" + }, + { + "task_id": "draft_E1_mirror_s02", + "target": "mirror", + "stratum": "composition", + "source_group": "vendor_glayout_connected", + "merged_source_group": "vendor_glayout_connected", + "parent_lineage": "glayout_mirror", + "shared_domain_id": "mirror_narrow_v3_shared25_mirror" + }, + { + "task_id": "draft_E1_mirror_s03", + "target": "mirror", + "stratum": "reuse", + "source_group": "vendor_glayout_connected", + "merged_source_group": "vendor_glayout_connected", + "parent_lineage": "glayout_mirror", + "shared_domain_id": "mirror_narrow_v3_shared25_mirror" + }, + { + "task_id": "draft_E1_cascode_mirror_s01", + "target": "cascode_mirror", + "stratum": "composition", + "source_group": "research_cascode_mirror", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_cascode_mirror", + "shared_domain_id": "exact_grid_v2_shared25_cascode_mirror" + }, + { + "task_id": "draft_E1_cascode_mirror_s02", + "target": "cascode_mirror", + "stratum": "reuse", + "source_group": "research_cascode_mirror", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_cascode_mirror", + "shared_domain_id": "exact_grid_v2_shared25_cascode_mirror" + }, + { + "task_id": "draft_E1_cascode_mirror_s03", + "target": "cascode_mirror", + "stratum": "composition", + "source_group": "research_cascode_mirror", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_cascode_mirror", + "shared_domain_id": "exact_grid_v2_shared25_cascode_mirror" + }, + { + "task_id": "draft_E1_source_follower_s01", + "target": "source_follower", + "stratum": "reuse", + "source_group": "research_source_follower", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_source_follower", + "shared_domain_id": "exact_grid_v2_shared25_source_follower" + }, + { + "task_id": "draft_E1_source_follower_s02", + "target": "source_follower", + "stratum": "composition", + "source_group": "research_source_follower", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_source_follower", + "shared_domain_id": "exact_grid_v2_shared25_source_follower" + }, + { + "task_id": "draft_E1_source_follower_s03", + "target": "source_follower", + "stratum": "reuse", + "source_group": "research_source_follower", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_source_follower", + "shared_domain_id": "exact_grid_v2_shared25_source_follower" + }, + { + "task_id": "draft_E1_stacked_switch_s01", + "target": "stacked_switch", + "stratum": "composition", + "source_group": "research_stacked_switch", + "merged_source_group": "research_stacked_switch", + "parent_lineage": "research_stacked_switch", + "shared_domain_id": "exact_grid_v2_shared25_stacked_switch" + }, + { + "task_id": "draft_E1_stacked_switch_s02", + "target": "stacked_switch", + "stratum": "reuse", + "source_group": "research_stacked_switch", + "merged_source_group": "research_stacked_switch", + "parent_lineage": "research_stacked_switch", + "shared_domain_id": "exact_grid_v2_shared25_stacked_switch" + }, + { + "task_id": "draft_E1_stacked_switch_s03", + "target": "stacked_switch", + "stratum": "composition", + "source_group": "research_stacked_switch", + "merged_source_group": "research_stacked_switch", + "parent_lineage": "research_stacked_switch", + "shared_domain_id": "exact_grid_v2_shared25_stacked_switch" + }, + { + "task_id": "draft_E1_common_source_stage_s01", + "target": "common_source_stage", + "stratum": "reuse", + "source_group": "research_common_source_stage", + "merged_source_group": "research_common_source_stage", + "parent_lineage": "research_common_source_stage", + "shared_domain_id": "exact_grid_v2_shared25_common_source_stage" + }, + { + "task_id": "draft_E1_common_source_stage_s02", + "target": "common_source_stage", + "stratum": "composition", + "source_group": "research_common_source_stage", + "merged_source_group": "research_common_source_stage", + "parent_lineage": "research_common_source_stage", + "shared_domain_id": "exact_grid_v2_shared25_common_source_stage" + }, + { + "task_id": "draft_E1_common_source_stage_s03", + "target": "common_source_stage", + "stratum": "reuse", + "source_group": "research_common_source_stage", + "merged_source_group": "research_common_source_stage", + "parent_lineage": "research_common_source_stage", + "shared_domain_id": "exact_grid_v2_shared25_common_source_stage" + }, + { + "task_id": "draft_E1_resistive_diff_s01", + "target": "resistive_diff", + "stratum": "composition", + "source_group": "research_resistive_diff", + "merged_source_group": "research_resistive_diff", + "parent_lineage": "research_resistive_diff", + "shared_domain_id": "exact_grid_v2_shared25_resistive_diff" + }, + { + "task_id": "draft_E1_resistive_diff_s02", + "target": "resistive_diff", + "stratum": "reuse", + "source_group": "research_resistive_diff", + "merged_source_group": "research_resistive_diff", + "parent_lineage": "research_resistive_diff", + "shared_domain_id": "exact_grid_v2_shared25_resistive_diff" + }, + { + "task_id": "draft_E1_resistive_diff_s03", + "target": "resistive_diff", + "stratum": "composition", + "source_group": "research_resistive_diff", + "merged_source_group": "research_resistive_diff", + "parent_lineage": "research_resistive_diff", + "shared_domain_id": "exact_grid_v2_shared25_resistive_diff" + }, + { + "task_id": "draft_E1_five_t_s01", + "target": "five_t", + "stratum": "reuse", + "source_group": "research_five_t", + "merged_source_group": "research_five_t", + "parent_lineage": "research_five_t", + "shared_domain_id": "exact_grid_v2_shared25_five_t" + }, + { + "task_id": "draft_E1_five_t_s02", + "target": "five_t", + "stratum": "composition", + "source_group": "research_five_t", + "merged_source_group": "research_five_t", + "parent_lineage": "research_five_t", + "shared_domain_id": "exact_grid_v2_shared25_five_t" + }, + { + "task_id": "draft_E1_five_t_s03", + "target": "five_t", + "stratum": "reuse", + "source_group": "research_five_t", + "merged_source_group": "research_five_t", + "parent_lineage": "research_five_t", + "shared_domain_id": "exact_grid_v2_shared25_five_t" + }, + { + "task_id": "draft_E1_compact_miller_s01", + "target": "compact_miller", + "stratum": "composition", + "source_group": "research_compact_miller", + "merged_source_group": "research_compact_miller", + "parent_lineage": "research_compact_miller", + "shared_domain_id": "exact_grid_v2_shared25_compact_miller" + }, + { + "task_id": "draft_E1_compact_miller_s02", + "target": "compact_miller", + "stratum": "reuse", + "source_group": "research_compact_miller", + "merged_source_group": "research_compact_miller", + "parent_lineage": "research_compact_miller", + "shared_domain_id": "exact_grid_v2_shared25_compact_miller" + }, + { + "task_id": "draft_E1_compact_miller_s03", + "target": "compact_miller", + "stratum": "composition", + "source_group": "research_compact_miller", + "merged_source_group": "research_compact_miller", + "parent_lineage": "research_compact_miller", + "shared_domain_id": "exact_grid_v2_shared25_compact_miller" + } + ], + "source_revision": "0b82cbd7f28a377e05a1a6116116944e5f99b497", + "implementation_sha256": { + "src/candidate_executor.py": "2aa700405ed2c52869c3c6a6a039ab2afe8ca02372cb2fe5432c04fb1c5c66e6", + "src/domain_runner.py": "e9ef34b451b1b0cdbe6e6275e69ebd3448c209a4718b4d7375355628f44d0ddf", + "src/model_adapter.py": "fa737a01c9b23dbf4ed0b4d1d6ba391637c0c769af56252ac6bcdbe4f0a71338", + "src/local_model_adapter.py": "24e99a3ad5d6dc0a46db7441683fcbfb36507f59f8efeee537b09dbd1be8e283", + "src/policy_state.py": "c8803e428d5da62aa6ad886c2cae650fb1fa27fb26d011fdc238a513543751a4", + "src/e1_packets.py": "03562f228f77e81577ec6a03c8ca405044ec80d4a7f7cb8492e486ed27aaa6fc", + "src/e1_benchmarks.py": "22e89b29bd2319fd8a6c9cf5ac9d690699b52e3432456c5d37bc5300b862dcc4", + "src/report_parsers.py": "4ad6a2124e2a573a40910aa13a3ee61cd00e6eb8dd4fba218e1d129cbea994f8", + "src/measurement.py": "1e9736325e094e023f7f5be1fba4a2328ca61a16ea1667e3f88496e6bf64f18f", + "src/spice_validation.py": "76b3b34fa9013f5165fd5af66b71101c2835786b2d86df2289f9641a4dd2d628", + "src/device_intent.py": "895976ed93024bc30aee2d7afef75eb895261a61742c9ab9a777c7ae68f2de3d", + "src/e1_analysis.py": "7765dafd874b3db242f0bd4b6004b0d7e00526a3c3d5edf64485a4015881b901", + "scripts/e1_matched_runner.py": "1658264fc4be12520231f27f0a5d15bfc185000833a7dfc14953eb81b42f8856", + "scripts/materialize_e1_packets.py": "e0a467cee0e70b18013eba3c02eb2af34be562a3869bf746ab4d0f07d0755349", + "scripts/e1_pcell_prepare.py": "b3bd32774eae9a79257a7cedb3d2f9d718c93023ff95268bc1434a42f5162daa", + "scripts/run_eda_probe.py": "1f5229c918cc7b563f1f6c03c733bb46eb06f60d0cc246aa2a70c510bd65f5f1", + "scripts/analyze_e1.py": "adbf72f0d475190647a6b38cc3961682452f7fdc5c682931150565cc95fd450a", + "scripts/run_e1_suite.py": "7f7fd2a35b75459553f1a64f62ad5f855bb15fea3c5ff3c993c230d9fc13881a", + "scripts/archive_e1_episode.py": "02a7d42e02df3b7cfeb86b1b0113c91e5bbeb1d2d550cd41b6d52ea79dcea540" + }, + "frozen_registry": "/srv/code-behind-layout/runtime/protocol_freezes/E1_20261019T0449Z_permission_fix/registry.json", + "qualification": { + "mechanical": "/srv/code-behind-layout/runtime/protocol_freezes/E1_20261019T0449Z_permission_fix/mechanical_controls.json", + "schematic": "/srv/code-behind-layout/runtime/protocol_freezes/E1_20261019T0449Z_permission_fix/circuit_feasibility.json" + }, + "dispatch_order_seed": 20261018, + "GPT_sampling_seed": "unavailable; fresh independent trial identifiers only", + "primary_contrasts": [ + "G1-G0", + "G2-G1" + ], + "analysis": { + "stratify_by": "reuse/composition", + "cluster_bootstrap_replicates": 2000, + "bootstrap_seed": 20261018 + }, + "protocol_amendment": { + "kind": "working_copy_directory_permission_only", + "prior_manifest": "runtime/protocol_freezes/E1_20261019T0410Z/manifest.json", + "prior_freeze_id": "E1_20261019T0410Z", + "scope": "Exactly one destination source.chmod(0o755) after copytree; no policy, information, budget or electrical change", + "original_planned_trials": 360, + "already_dispatched_trials": 3, + "remaining_undispatched_trials": 357, + "automatic_or_engineering_model_retries": 0, + "retained_prior_trials": [ + { + "task_id": "draft_E1_compact_miller_s03", + "method": "G2", + "trial_id": "5", + "episode_directory": "runs/formal/E1/20261019T043205046362Z_080d610c", + "post_freeze": "INCOMPLETE_UNKNOWN_CAPSULE_PERMISSION_FAILURE" + }, + { + "task_id": "draft_E1_compact_miller_s03", + "method": "G1", + "trial_id": "5", + "episode_directory": "runs/formal/E1/20261019T043211851907Z_712ecd32", + "post_freeze": "COMPLETE" + }, + { + "task_id": "draft_E1_compact_miller_s03", + "method": "G0", + "trial_id": "5", + "episode_directory": "runs/formal/E1/20261019T043218444555Z_3f96cf4e", + "post_freeze": "COMPLETE" + } + ], + "actual_working_copy_control": "/srv/code-behind-layout/runs/development/E1_permission_capsule_smoke/summary.json" + } +} diff --git a/benchmarks/code_behind_layout/configs/experiments/frozen/E1_scope_v2_16k.json b/benchmarks/code_behind_layout/configs/experiments/frozen/E1_scope_v2_16k.json new file mode 100644 index 00000000..26eccf58 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/experiments/frozen/E1_scope_v2_16k.json @@ -0,0 +1,351 @@ +{ + "status": "FROZEN_E1", + "formal_dispatch": true, + "phase": "formal_E1", + "packet_root": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/packets", + "task_catalog": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/packets/public/catalog.json", + "task_ids": [ + "draft_E1_mirror_s01", + "draft_E1_mirror_s02", + "draft_E1_mirror_s03", + "draft_E1_cascode_mirror_s01", + "draft_E1_cascode_mirror_s02", + "draft_E1_cascode_mirror_s03", + "draft_E1_source_follower_s01", + "draft_E1_source_follower_s02", + "draft_E1_source_follower_s03", + "draft_E1_stacked_switch_s01", + "draft_E1_stacked_switch_s02", + "draft_E1_stacked_switch_s03", + "draft_E1_common_source_stage_s01", + "draft_E1_common_source_stage_s02", + "draft_E1_common_source_stage_s03", + "draft_E1_resistive_diff_s01", + "draft_E1_resistive_diff_s02", + "draft_E1_resistive_diff_s03", + "draft_E1_five_t_s01", + "draft_E1_five_t_s02", + "draft_E1_five_t_s03", + "draft_E1_compact_miller_s01", + "draft_E1_compact_miller_s02", + "draft_E1_compact_miller_s03" + ], + "methods": [ + "G0", + "G1", + "G2" + ], + "trials": 5, + "model_config": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/model_config.json", + "visible_history_policy": "current_source_and_feedback_v1", + "budget": { + "wall_seconds": 1200, + "decisions": 10, + "physical_evaluations": 3, + "maximum_context_tokens": 16384, + "maximum_output_tokens": 1024 + }, + "runtime": { + "EDA": "runtime/GLdev", + "magic": "runtime/magic-8.3.685", + "candidate_CPUs": 2, + "simultaneous_point_workers_per_episode": 1 + }, + "trusted_bench_bindings": "Built independently per task by scripts/e1_matched_runner.py; no target assembly enters the trusted evaluator.", + "post_freeze": { + "visible": "Fill current-source anchor plus eight development points without policy feedback; separately charge post_freeze_diagnostic.", + "hidden": "Evaluate sixteen points once after source sealing; all raw hidden results stay on trusted backend.", + "incomplete": "Stop affected episode on unknown/infrastructure, retain observed denominators and label no missing outcomes." + }, + "grouping": { + "target_logics": 8, + "primary_groups": 8, + "merged_sensitivity_groups": 7, + "strata": { + "reuse": 12, + "composition": 12 + }, + "shared_domains": "Three sized tasks per target rotate roles of the same25 points, explicitly linked in private/shared_domain_relationships.json. Fresh isolated trials receive only their own fixed nine visible points." + }, + "freeze_blockers": [], + "backend_manifest_path": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/manifest.json", + "tasks": [ + { + "task_id": "draft_E1_mirror_s01", + "target": "mirror", + "stratum": "reuse", + "source_group": "vendor_glayout_connected", + "merged_source_group": "vendor_glayout_connected", + "parent_lineage": "glayout_mirror", + "shared_domain_id": "mirror_narrow_v3_shared25_mirror" + }, + { + "task_id": "draft_E1_mirror_s02", + "target": "mirror", + "stratum": "composition", + "source_group": "vendor_glayout_connected", + "merged_source_group": "vendor_glayout_connected", + "parent_lineage": "glayout_mirror", + "shared_domain_id": "mirror_narrow_v3_shared25_mirror" + }, + { + "task_id": "draft_E1_mirror_s03", + "target": "mirror", + "stratum": "reuse", + "source_group": "vendor_glayout_connected", + "merged_source_group": "vendor_glayout_connected", + "parent_lineage": "glayout_mirror", + "shared_domain_id": "mirror_narrow_v3_shared25_mirror" + }, + { + "task_id": "draft_E1_cascode_mirror_s01", + "target": "cascode_mirror", + "stratum": "composition", + "source_group": "research_cascode_mirror", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_cascode_mirror", + "shared_domain_id": "exact_grid_v2_shared25_cascode_mirror" + }, + { + "task_id": "draft_E1_cascode_mirror_s02", + "target": "cascode_mirror", + "stratum": "reuse", + "source_group": "research_cascode_mirror", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_cascode_mirror", + "shared_domain_id": "exact_grid_v2_shared25_cascode_mirror" + }, + { + "task_id": "draft_E1_cascode_mirror_s03", + "target": "cascode_mirror", + "stratum": "composition", + "source_group": "research_cascode_mirror", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_cascode_mirror", + "shared_domain_id": "exact_grid_v2_shared25_cascode_mirror" + }, + { + "task_id": "draft_E1_source_follower_s01", + "target": "source_follower", + "stratum": "reuse", + "source_group": "research_source_follower", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_source_follower", + "shared_domain_id": "exact_grid_v2_shared25_source_follower" + }, + { + "task_id": "draft_E1_source_follower_s02", + "target": "source_follower", + "stratum": "composition", + "source_group": "research_source_follower", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_source_follower", + "shared_domain_id": "exact_grid_v2_shared25_source_follower" + }, + { + "task_id": "draft_E1_source_follower_s03", + "target": "source_follower", + "stratum": "reuse", + "source_group": "research_source_follower", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_source_follower", + "shared_domain_id": "exact_grid_v2_shared25_source_follower" + }, + { + "task_id": "draft_E1_stacked_switch_s01", + "target": "stacked_switch", + "stratum": "composition", + "source_group": "research_stacked_switch", + "merged_source_group": "research_stacked_switch", + "parent_lineage": "research_stacked_switch", + "shared_domain_id": "exact_grid_v2_shared25_stacked_switch" + }, + { + "task_id": "draft_E1_stacked_switch_s02", + "target": "stacked_switch", + "stratum": "reuse", + "source_group": "research_stacked_switch", + "merged_source_group": "research_stacked_switch", + "parent_lineage": "research_stacked_switch", + "shared_domain_id": "exact_grid_v2_shared25_stacked_switch" + }, + { + "task_id": "draft_E1_stacked_switch_s03", + "target": "stacked_switch", + "stratum": "composition", + "source_group": "research_stacked_switch", + "merged_source_group": "research_stacked_switch", + "parent_lineage": "research_stacked_switch", + "shared_domain_id": "exact_grid_v2_shared25_stacked_switch" + }, + { + "task_id": "draft_E1_common_source_stage_s01", + "target": "common_source_stage", + "stratum": "reuse", + "source_group": "research_common_source_stage", + "merged_source_group": "research_common_source_stage", + "parent_lineage": "research_common_source_stage", + "shared_domain_id": "exact_grid_v2_shared25_common_source_stage" + }, + { + "task_id": "draft_E1_common_source_stage_s02", + "target": "common_source_stage", + "stratum": "composition", + "source_group": "research_common_source_stage", + "merged_source_group": "research_common_source_stage", + "parent_lineage": "research_common_source_stage", + "shared_domain_id": "exact_grid_v2_shared25_common_source_stage" + }, + { + "task_id": "draft_E1_common_source_stage_s03", + "target": "common_source_stage", + "stratum": "reuse", + "source_group": "research_common_source_stage", + "merged_source_group": "research_common_source_stage", + "parent_lineage": "research_common_source_stage", + "shared_domain_id": "exact_grid_v2_shared25_common_source_stage" + }, + { + "task_id": "draft_E1_resistive_diff_s01", + "target": "resistive_diff", + "stratum": "composition", + "source_group": "research_resistive_diff", + "merged_source_group": "research_resistive_diff", + "parent_lineage": "research_resistive_diff", + "shared_domain_id": "exact_grid_v2_shared25_resistive_diff" + }, + { + "task_id": "draft_E1_resistive_diff_s02", + "target": "resistive_diff", + "stratum": "reuse", + "source_group": "research_resistive_diff", + "merged_source_group": "research_resistive_diff", + "parent_lineage": "research_resistive_diff", + "shared_domain_id": "exact_grid_v2_shared25_resistive_diff" + }, + { + "task_id": "draft_E1_resistive_diff_s03", + "target": "resistive_diff", + "stratum": "composition", + "source_group": "research_resistive_diff", + "merged_source_group": "research_resistive_diff", + "parent_lineage": "research_resistive_diff", + "shared_domain_id": "exact_grid_v2_shared25_resistive_diff" + }, + { + "task_id": "draft_E1_five_t_s01", + "target": "five_t", + "stratum": "reuse", + "source_group": "research_five_t", + "merged_source_group": "research_five_t", + "parent_lineage": "research_five_t", + "shared_domain_id": "exact_grid_v2_shared25_five_t" + }, + { + "task_id": "draft_E1_five_t_s02", + "target": "five_t", + "stratum": "composition", + "source_group": "research_five_t", + "merged_source_group": "research_five_t", + "parent_lineage": "research_five_t", + "shared_domain_id": "exact_grid_v2_shared25_five_t" + }, + { + "task_id": "draft_E1_five_t_s03", + "target": "five_t", + "stratum": "reuse", + "source_group": "research_five_t", + "merged_source_group": "research_five_t", + "parent_lineage": "research_five_t", + "shared_domain_id": "exact_grid_v2_shared25_five_t" + }, + { + "task_id": "draft_E1_compact_miller_s01", + "target": "compact_miller", + "stratum": "composition", + "source_group": "research_compact_miller", + "merged_source_group": "research_compact_miller", + "parent_lineage": "research_compact_miller", + "shared_domain_id": "exact_grid_v2_shared25_compact_miller" + }, + { + "task_id": "draft_E1_compact_miller_s02", + "target": "compact_miller", + "stratum": "reuse", + "source_group": "research_compact_miller", + "merged_source_group": "research_compact_miller", + "parent_lineage": "research_compact_miller", + "shared_domain_id": "exact_grid_v2_shared25_compact_miller" + }, + { + "task_id": "draft_E1_compact_miller_s03", + "target": "compact_miller", + "stratum": "composition", + "source_group": "research_compact_miller", + "merged_source_group": "research_compact_miller", + "parent_lineage": "research_compact_miller", + "shared_domain_id": "exact_grid_v2_shared25_compact_miller" + } + ], + "frozen_registry": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/registry.json", + "qualification": { + "mechanical": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/mechanical_controls.json", + "schematic": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/circuit_feasibility.json", + "policy_interface": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/pilot_reinspection.json", + "capacity": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/token_history_preflight.json" + }, + "dispatch_order_seed": 20261018, + "GPT_sampling_seed": "unavailable; fresh independent trial identifiers only", + "primary_contrasts": [ + "G1-G0", + "G2-G1" + ], + "analysis": { + "stratify_by": "reuse/composition", + "cluster_bootstrap_replicates": 2000, + "bootstrap_seed": 20261018 + }, + "cohort_id": "scope_v2_16k", + "interface_version": "scope_v2_16k", + "prior_interface_manifest": "/srv/code-behind-layout/runtime/protocol_freezes/E1_20261019T0449Z_permission_fix/manifest.json", + "prior_interface_freeze_id": "E1_20261019T0449Z_permission_fix", + "prior_interface_role": "partial_interface_v1_preserve_all_records_and_NOT_RUN", + "scope_proposal": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/scope_proposal.json", + "formal_cohort_rule": "New fresh360 matched trial identities in a separate suite/index; no old trial carried or repeated into this cohort.", + "freeze_id": "E1_scope_v2_16k", + "frozen_at_utc": "2026-10-19T06:01:29.125746+00:00", + "source_revision": "63d33183e745016fddfa071f2e452d9d9008625a", + "implementation_sha256": { + "configs/development/e1_scope_candidate_error_classification.patch": "79b60889f619cbed59515d6aafed0ff45a356d52b989e594e785269601aad651", + "scripts/analyze_e1.py": "adbf72f0d475190647a6b38cc3961682452f7fdc5c682931150565cc95fd450a", + "scripts/analyze_e1_scope.py": "b37b765900bf5615e54b096651c96a12a31a39a48ff036a6b41f6171a4b7f806", + "scripts/archive_e1_episode.py": "02a7d42e02df3b7cfeb86b1b0113c91e5bbeb1d2d550cd41b6d52ea79dcea540", + "scripts/e1_matched_runner.py": "1658264fc4be12520231f27f0a5d15bfc185000833a7dfc14953eb81b42f8856", + "scripts/e1_pcell_prepare.py": "b3bd32774eae9a79257a7cedb3d2f9d718c93023ff95268bc1434a42f5162daa", + "scripts/e1_scope_history_preflight.py": "5e90ef579672e9f3d714f28c4a646d156fbe0c889cff78aa9189ca80ff195fce", + "scripts/e1_scope_pilot.py": "b5df52b54c6a3bd07e8d554c1156a35cbfcd46a07a4bf504c3454cabc48168e3", + "scripts/e1_scope_proposal_preflight.py": "bc55fd4e479cb26c69ed564e84930f3fad92769b2d593efd54844693864f843c", + "scripts/e1_scope_runner.py": "656b5008344be4e86dee2ca52c4df8457bef77a693b9aa872b7fd7f230f88179", + "scripts/freeze_e1.py": "d8258ad41c63e3dcf190ad37d680996c5db1aaeb22e5cdf708ef9b293f7079a6", + "scripts/freeze_e1_scope_cohort.py": "10954129bf38ddd410a7fe4fba5cd81974e9380d1d6c9fcbfc8a7a92442e15bf", + "scripts/materialize_e1_packets.py": "e0a467cee0e70b18013eba3c02eb2af34be562a3869bf746ab4d0f07d0755349", + "scripts/prepare_e1_scope_cohort.py": "7f561ee62d9904f9efbd5279fe3ec45a1d19903763dfbff4e1821ed1a55da7d8", + "scripts/run_e1_scope_suite.py": "19dcb366ef90adccf5c484dab636a56589701e8e2bd7338705dfdfbc03d01f5f", + "scripts/run_e1_suite.py": "7f7fd2a35b75459553f1a64f62ad5f855bb15fea3c5ff3c993c230d9fc13881a", + "scripts/run_eda_probe.py": "1f5229c918cc7b563f1f6c03c733bb46eb06f60d0cc246aa2a70c510bd65f5f1", + "src/candidate_executor.py": "2aa700405ed2c52869c3c6a6a039ab2afe8ca02372cb2fe5432c04fb1c5c66e6", + "src/device_intent.py": "895976ed93024bc30aee2d7afef75eb895261a61742c9ab9a777c7ae68f2de3d", + "src/domain_runner.py": "e9ef34b451b1b0cdbe6e6275e69ebd3448c209a4718b4d7375355628f44d0ddf", + "src/e1_analysis.py": "7765dafd874b3db242f0bd4b6004b0d7e00526a3c3d5edf64485a4015881b901", + "src/e1_benchmarks.py": "22e89b29bd2319fd8a6c9cf5ac9d690699b52e3432456c5d37bc5300b862dcc4", + "src/e1_packets.py": "03562f228f77e81577ec6a03c8ca405044ec80d4a7f7cb8492e486ed27aaa6fc", + "src/local_model_adapter.py": "24e99a3ad5d6dc0a46db7441683fcbfb36507f59f8efeee537b09dbd1be8e283", + "src/measurement.py": "1e9736325e094e023f7f5be1fba4a2328ca61a16ea1667e3f88496e6bf64f18f", + "src/model_adapter.py": "fa737a01c9b23dbf4ed0b4d1d6ba391637c0c769af56252ac6bcdbe4f0a71338", + "src/policy_state.py": "c8803e428d5da62aa6ad886c2cae650fb1fa27fb26d011fdc238a513543751a4", + "src/report_parsers.py": "4ad6a2124e2a573a40910aa13a3ee61cd00e6eb8dd4fba218e1d129cbea994f8", + "src/spice_validation.py": "76b3b34fa9013f5165fd5af66b71101c2835786b2d86df2289f9641a4dd2d628" + }, + "prior_partial_matrix": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/prior_partial_suite.json", + "cohort_analysis_rule": "Only this cohort-specific complete index enters its360 task-paired analysis. Old partial interface trials remain a separate matrix and research cost." +} diff --git a/benchmarks/code_behind_layout/configs/experiments/frozen/E1_scope_v2_16k_claude.json b/benchmarks/code_behind_layout/configs/experiments/frozen/E1_scope_v2_16k_claude.json new file mode 100644 index 00000000..b3ff1e5a --- /dev/null +++ b/benchmarks/code_behind_layout/configs/experiments/frozen/E1_scope_v2_16k_claude.json @@ -0,0 +1,461 @@ +{ + "status": "FROZEN_E1", + "formal_dispatch": true, + "phase": "formal_E1", + "packet_root": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/packets", + "task_catalog": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/packets/public/catalog.json", + "task_ids": [ + "draft_E1_mirror_s01", + "draft_E1_mirror_s02", + "draft_E1_mirror_s03", + "draft_E1_cascode_mirror_s01", + "draft_E1_cascode_mirror_s02", + "draft_E1_cascode_mirror_s03", + "draft_E1_source_follower_s01", + "draft_E1_source_follower_s02", + "draft_E1_source_follower_s03", + "draft_E1_stacked_switch_s01", + "draft_E1_stacked_switch_s02", + "draft_E1_stacked_switch_s03", + "draft_E1_common_source_stage_s01", + "draft_E1_common_source_stage_s02", + "draft_E1_common_source_stage_s03", + "draft_E1_resistive_diff_s01", + "draft_E1_resistive_diff_s02", + "draft_E1_resistive_diff_s03", + "draft_E1_five_t_s01", + "draft_E1_five_t_s02", + "draft_E1_five_t_s03", + "draft_E1_compact_miller_s01", + "draft_E1_compact_miller_s02", + "draft_E1_compact_miller_s03" + ], + "methods": [ + "G0", + "G1", + "G2" + ], + "trials": 2, + "model_config": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k_claude/model_config.json", + "visible_history_policy": "current_source_and_feedback_v1", + "budget": { + "wall_seconds": 1200, + "decisions": 10, + "physical_evaluations": 3, + "maximum_context_tokens": 16384, + "maximum_output_tokens": 1024 + }, + "runtime": { + "EDA": "runtime/GLdev", + "magic": "runtime/magic-8.3.685", + "candidate_CPUs": 2, + "simultaneous_point_workers_per_episode": 1 + }, + "trusted_bench_bindings": "Built independently per task by scripts/e1_matched_runner.py; no target assembly enters the trusted evaluator.", + "post_freeze": { + "visible": "Fill current-source anchor plus eight development points without policy feedback; separately charge post_freeze_diagnostic.", + "hidden": "Evaluate sixteen points once after source sealing; all raw hidden results stay on trusted backend.", + "incomplete": "Stop affected episode on unknown/infrastructure, retain observed denominators and label no missing outcomes." + }, + "grouping": { + "target_logics": 8, + "primary_groups": 8, + "merged_sensitivity_groups": 7, + "strata": { + "reuse": 12, + "composition": 12 + }, + "shared_domains": "Three sized tasks per target rotate roles of the same25 points, explicitly linked in private/shared_domain_relationships.json. Fresh isolated trials receive only their own fixed nine visible points." + }, + "freeze_blockers": [], + "backend_manifest_path": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k_claude/manifest.json", + "tasks": [ + { + "task_id": "draft_E1_mirror_s01", + "target": "mirror", + "stratum": "reuse", + "source_group": "vendor_glayout_connected", + "merged_source_group": "vendor_glayout_connected", + "parent_lineage": "glayout_mirror", + "shared_domain_id": "mirror_narrow_v3_shared25_mirror" + }, + { + "task_id": "draft_E1_mirror_s02", + "target": "mirror", + "stratum": "composition", + "source_group": "vendor_glayout_connected", + "merged_source_group": "vendor_glayout_connected", + "parent_lineage": "glayout_mirror", + "shared_domain_id": "mirror_narrow_v3_shared25_mirror" + }, + { + "task_id": "draft_E1_mirror_s03", + "target": "mirror", + "stratum": "reuse", + "source_group": "vendor_glayout_connected", + "merged_source_group": "vendor_glayout_connected", + "parent_lineage": "glayout_mirror", + "shared_domain_id": "mirror_narrow_v3_shared25_mirror" + }, + { + "task_id": "draft_E1_cascode_mirror_s01", + "target": "cascode_mirror", + "stratum": "composition", + "source_group": "research_cascode_mirror", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_cascode_mirror", + "shared_domain_id": "exact_grid_v2_shared25_cascode_mirror" + }, + { + "task_id": "draft_E1_cascode_mirror_s02", + "target": "cascode_mirror", + "stratum": "reuse", + "source_group": "research_cascode_mirror", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_cascode_mirror", + "shared_domain_id": "exact_grid_v2_shared25_cascode_mirror" + }, + { + "task_id": "draft_E1_cascode_mirror_s03", + "target": "cascode_mirror", + "stratum": "composition", + "source_group": "research_cascode_mirror", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_cascode_mirror", + "shared_domain_id": "exact_grid_v2_shared25_cascode_mirror" + }, + { + "task_id": "draft_E1_source_follower_s01", + "target": "source_follower", + "stratum": "reuse", + "source_group": "research_source_follower", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_source_follower", + "shared_domain_id": "exact_grid_v2_shared25_source_follower" + }, + { + "task_id": "draft_E1_source_follower_s02", + "target": "source_follower", + "stratum": "composition", + "source_group": "research_source_follower", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_source_follower", + "shared_domain_id": "exact_grid_v2_shared25_source_follower" + }, + { + "task_id": "draft_E1_source_follower_s03", + "target": "source_follower", + "stratum": "reuse", + "source_group": "research_source_follower", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_source_follower", + "shared_domain_id": "exact_grid_v2_shared25_source_follower" + }, + { + "task_id": "draft_E1_stacked_switch_s01", + "target": "stacked_switch", + "stratum": "composition", + "source_group": "research_stacked_switch", + "merged_source_group": "research_stacked_switch", + "parent_lineage": "research_stacked_switch", + "shared_domain_id": "exact_grid_v2_shared25_stacked_switch" + }, + { + "task_id": "draft_E1_stacked_switch_s02", + "target": "stacked_switch", + "stratum": "reuse", + "source_group": "research_stacked_switch", + "merged_source_group": "research_stacked_switch", + "parent_lineage": "research_stacked_switch", + "shared_domain_id": "exact_grid_v2_shared25_stacked_switch" + }, + { + "task_id": "draft_E1_stacked_switch_s03", + "target": "stacked_switch", + "stratum": "composition", + "source_group": "research_stacked_switch", + "merged_source_group": "research_stacked_switch", + "parent_lineage": "research_stacked_switch", + "shared_domain_id": "exact_grid_v2_shared25_stacked_switch" + }, + { + "task_id": "draft_E1_common_source_stage_s01", + "target": "common_source_stage", + "stratum": "reuse", + "source_group": "research_common_source_stage", + "merged_source_group": "research_common_source_stage", + "parent_lineage": "research_common_source_stage", + "shared_domain_id": "exact_grid_v2_shared25_common_source_stage" + }, + { + "task_id": "draft_E1_common_source_stage_s02", + "target": "common_source_stage", + "stratum": "composition", + "source_group": "research_common_source_stage", + "merged_source_group": "research_common_source_stage", + "parent_lineage": "research_common_source_stage", + "shared_domain_id": "exact_grid_v2_shared25_common_source_stage" + }, + { + "task_id": "draft_E1_common_source_stage_s03", + "target": "common_source_stage", + "stratum": "reuse", + "source_group": "research_common_source_stage", + "merged_source_group": "research_common_source_stage", + "parent_lineage": "research_common_source_stage", + "shared_domain_id": "exact_grid_v2_shared25_common_source_stage" + }, + { + "task_id": "draft_E1_resistive_diff_s01", + "target": "resistive_diff", + "stratum": "composition", + "source_group": "research_resistive_diff", + "merged_source_group": "research_resistive_diff", + "parent_lineage": "research_resistive_diff", + "shared_domain_id": "exact_grid_v2_shared25_resistive_diff" + }, + { + "task_id": "draft_E1_resistive_diff_s02", + "target": "resistive_diff", + "stratum": "reuse", + "source_group": "research_resistive_diff", + "merged_source_group": "research_resistive_diff", + "parent_lineage": "research_resistive_diff", + "shared_domain_id": "exact_grid_v2_shared25_resistive_diff" + }, + { + "task_id": "draft_E1_resistive_diff_s03", + "target": "resistive_diff", + "stratum": "composition", + "source_group": "research_resistive_diff", + "merged_source_group": "research_resistive_diff", + "parent_lineage": "research_resistive_diff", + "shared_domain_id": "exact_grid_v2_shared25_resistive_diff" + }, + { + "task_id": "draft_E1_five_t_s01", + "target": "five_t", + "stratum": "reuse", + "source_group": "research_five_t", + "merged_source_group": "research_five_t", + "parent_lineage": "research_five_t", + "shared_domain_id": "exact_grid_v2_shared25_five_t" + }, + { + "task_id": "draft_E1_five_t_s02", + "target": "five_t", + "stratum": "composition", + "source_group": "research_five_t", + "merged_source_group": "research_five_t", + "parent_lineage": "research_five_t", + "shared_domain_id": "exact_grid_v2_shared25_five_t" + }, + { + "task_id": "draft_E1_five_t_s03", + "target": "five_t", + "stratum": "reuse", + "source_group": "research_five_t", + "merged_source_group": "research_five_t", + "parent_lineage": "research_five_t", + "shared_domain_id": "exact_grid_v2_shared25_five_t" + }, + { + "task_id": "draft_E1_compact_miller_s01", + "target": "compact_miller", + "stratum": "composition", + "source_group": "research_compact_miller", + "merged_source_group": "research_compact_miller", + "parent_lineage": "research_compact_miller", + "shared_domain_id": "exact_grid_v2_shared25_compact_miller" + }, + { + "task_id": "draft_E1_compact_miller_s02", + "target": "compact_miller", + "stratum": "reuse", + "source_group": "research_compact_miller", + "merged_source_group": "research_compact_miller", + "parent_lineage": "research_compact_miller", + "shared_domain_id": "exact_grid_v2_shared25_compact_miller" + }, + { + "task_id": "draft_E1_compact_miller_s03", + "target": "compact_miller", + "stratum": "composition", + "source_group": "research_compact_miller", + "merged_source_group": "research_compact_miller", + "parent_lineage": "research_compact_miller", + "shared_domain_id": "exact_grid_v2_shared25_compact_miller" + } + ], + "frozen_registry": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/registry.json", + "qualification": { + "mechanical": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/mechanical_controls.json", + "schematic": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/circuit_feasibility.json", + "policy_interface": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/pilot_reinspection.json", + "capacity": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/token_history_preflight.json" + }, + "dispatch_order_seed": 20261018, + "GPT_sampling_seed": "unavailable; fresh independent trial identifiers only", + "primary_contrasts": [ + "G1-G0", + "G2-G1" + ], + "analysis": { + "stratify_by": "reuse/composition", + "cluster_bootstrap_replicates": 2000, + "bootstrap_seed": 20261018 + }, + "cohort_id": "scope_v2_16k", + "interface_version": "scope_v2_16k", + "prior_interface_manifest": "/srv/code-behind-layout/runtime/protocol_freezes/E1_20261019T0449Z_permission_fix/manifest.json", + "prior_interface_freeze_id": "E1_20261019T0449Z_permission_fix", + "prior_interface_role": "partial_interface_v1_preserve_all_records_and_NOT_RUN", + "scope_proposal": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/scope_proposal.json", + "formal_cohort_rule": "Fresh 144 matched trial identities in a separate suite/index; no parent trial is carried or repeated.", + "freeze_id": "E1_scope_v2_16k_claude", + "frozen_at_utc": "2026-10-20T01:53:25.734558+00:00", + "source_revision": "63d33183e745016fddfa071f2e452d9d9008625a", + "implementation_sha256": { + "configs/development/e1_scope_candidate_error_classification.patch": "79b60889f619cbed59515d6aafed0ff45a356d52b989e594e785269601aad651", + "scripts/analyze_e1.py": "adbf72f0d475190647a6b38cc3961682452f7fdc5c682931150565cc95fd450a", + "scripts/analyze_e1_scope.py": "b37b765900bf5615e54b096651c96a12a31a39a48ff036a6b41f6171a4b7f806", + "scripts/archive_e1_episode.py": "02a7d42e02df3b7cfeb86b1b0113c91e5bbeb1d2d550cd41b6d52ea79dcea540", + "scripts/e1_matched_runner.py": "1658264fc4be12520231f27f0a5d15bfc185000833a7dfc14953eb81b42f8856", + "scripts/e1_pcell_prepare.py": "b3bd32774eae9a79257a7cedb3d2f9d718c93023ff95268bc1434a42f5162daa", + "scripts/e1_scope_history_preflight.py": "5e90ef579672e9f3d714f28c4a646d156fbe0c889cff78aa9189ca80ff195fce", + "scripts/e1_scope_pilot.py": "b5df52b54c6a3bd07e8d554c1156a35cbfcd46a07a4bf504c3454cabc48168e3", + "scripts/e1_scope_proposal_preflight.py": "bc55fd4e479cb26c69ed564e84930f3fad92769b2d593efd54844693864f843c", + "scripts/e1_scope_runner.py": "656b5008344be4e86dee2ca52c4df8457bef77a693b9aa872b7fd7f230f88179", + "scripts/freeze_e1.py": "d8258ad41c63e3dcf190ad37d680996c5db1aaeb22e5cdf708ef9b293f7079a6", + "scripts/freeze_e1_scope_cohort.py": "10954129bf38ddd410a7fe4fba5cd81974e9380d1d6c9fcbfc8a7a92442e15bf", + "scripts/materialize_e1_packets.py": "e0a467cee0e70b18013eba3c02eb2af34be562a3869bf746ab4d0f07d0755349", + "scripts/prepare_e1_scope_cohort.py": "7f561ee62d9904f9efbd5279fe3ec45a1d19903763dfbff4e1821ed1a55da7d8", + "scripts/run_e1_scope_suite.py": "19dcb366ef90adccf5c484dab636a56589701e8e2bd7338705dfdfbc03d01f5f", + "scripts/run_e1_suite.py": "7f7fd2a35b75459553f1a64f62ad5f855bb15fea3c5ff3c993c230d9fc13881a", + "scripts/run_eda_probe.py": "1f5229c918cc7b563f1f6c03c733bb46eb06f60d0cc246aa2a70c510bd65f5f1", + "src/candidate_executor.py": "2aa700405ed2c52869c3c6a6a039ab2afe8ca02372cb2fe5432c04fb1c5c66e6", + "src/device_intent.py": "895976ed93024bc30aee2d7afef75eb895261a61742c9ab9a777c7ae68f2de3d", + "src/domain_runner.py": "e9ef34b451b1b0cdbe6e6275e69ebd3448c209a4718b4d7375355628f44d0ddf", + "src/e1_analysis.py": "7765dafd874b3db242f0bd4b6004b0d7e00526a3c3d5edf64485a4015881b901", + "src/e1_benchmarks.py": "22e89b29bd2319fd8a6c9cf5ac9d690699b52e3432456c5d37bc5300b862dcc4", + "src/e1_packets.py": "03562f228f77e81577ec6a03c8ca405044ec80d4a7f7cb8492e486ed27aaa6fc", + "src/local_model_adapter.py": "24e99a3ad5d6dc0a46db7441683fcbfb36507f59f8efeee537b09dbd1be8e283", + "src/measurement.py": "1e9736325e094e023f7f5be1fba4a2328ca61a16ea1667e3f88496e6bf64f18f", + "src/model_adapter.py": "fa737a01c9b23dbf4ed0b4d1d6ba391637c0c769af56252ac6bcdbe4f0a71338", + "src/policy_state.py": "c8803e428d5da62aa6ad886c2cae650fb1fa27fb26d011fdc238a513543751a4", + "src/report_parsers.py": "4ad6a2124e2a573a40910aa13a3ee61cd00e6eb8dd4fba218e1d129cbea994f8", + "src/spice_validation.py": "76b3b34fa9013f5165fd5af66b71101c2835786b2d86df2289f9641a4dd2d628", + "src/opus_cli_adapter.py": "05c80a37429921f2247dfc9522ed950bbea4fd480acfcb5349922465c774fc9a", + "scripts/opus_cohort/__init__.py": "640263ae5bf6af6b3d6bd1c68045204d276ea437fe507c92e9b09439ad9f9046", + "scripts/opus_cohort/common.py": "bc1d92112ec47bfcc427df703397a6d188f78f8dbde482245f0c277afcb49ad6", + "scripts/opus_cohort/e3_episode_opus.py": "cf6e6e56763f927c8c90a3d756387846e52da644c652135eb6656235b640ed48", + "scripts/opus_cohort/e3_parameter_episode_opus.py": "c773ab6c2ae162968f372710c1c055d97677a52f863664b9f5e63fefc0988a6b", + "scripts/opus_cohort/e1_scope_runner_opus.py": "06d3c6af41843f438aff5b5182c76ae88be9d73f589af6263abd76e3e5633b31", + "scripts/opus_cohort/run_e3_suite_opus.py": "4da23faf625d55b02d3eb379a4e241b2bf292b43c618e7360988ff647821723b", + "scripts/opus_cohort/run_e1_scope_suite_opus.py": "d6d806c4dee71349a3e09f27ed717aff3168702d8a0e5ba6c41dd7b735a5d167", + "scripts/opus_cohort/freeze_cohorts_opus.py": "f1b3a31bdc909118ea4be426ad31cc439c4c688cda19100d166d7a98848d4261", + "scripts/opus_cohort/pilot_opus_policy.py": "81b9c63b24880701c7882e85e6a18f246f826a0bcd28337ecadcf48b38c71be7" + }, + "prior_partial_matrix": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/prior_partial_suite.json", + "cohort_analysis_rule": "Only this cohort-specific complete index enters its task-paired analysis.", + "parent_freeze_id": "E1_scope_v2_16k", + "parent_manifest_path": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/manifest.json", + "parent_manifest_sha256": "005ab7fb495df68304b17c5027ecc94301460c2a2af91e49801c93d5f09853d5", + "policy_backend": "claude_cli", + "policy_model": "claude-opus-5-5", + "cohort_label": "E1-C", + "minimum_tier": { + "e3_trials": 3, + "e1_trials": 2, + "parameter_tasks": 4, + "signal_tasks": 4, + "local_tasks": 8, + "local_inference_trials": 1, + "local_seed_slots": [ + 41, + 73, + 109 + ] + }, + "protocol_amendment": "docs/protocol_amendments_20261019.md", + "cohort_rule": "Same tasks, anchors, visible and hidden configurations, references, benches, budgets, selection rules and gateway as the parent freeze; only the policy backend, the adapter implementation and the Minimum-tier matrix differ. Parent trials stay a separate matrix.", + "declared_episodes": 144, + "pilot_evidence": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k_claude/pilot_evidence", + "pilot_reinspection": { + "summary": "runtime/opus_cohort_pilots/E1/summary.json", + "jobs": [ + { + "method": "G0", + "invocations": [ + "/srv/code-behind-layout/runtime/opus_cohort_pilots/E1/policy/G0/decisions/3bf6ebe1-5193-49c6-81f0-8dcba67b29fd/decision_000/invocation.json", + "/srv/code-behind-layout/runtime/opus_cohort_pilots/E1/policy/G0/decisions/3bf6ebe1-5193-49c6-81f0-8dcba67b29fd/decision_001/invocation.json" + ], + "real_replies": [ + { + "path": "/srv/code-behind-layout/runtime/opus_cohort_pilots/E1/policy/G0/decisions/3bf6ebe1-5193-49c6-81f0-8dcba67b29fd/decision_000/invocation.json", + "status": "COMPLETED" + }, + { + "path": "/srv/code-behind-layout/runtime/opus_cohort_pilots/E1/policy/G0/decisions/3bf6ebe1-5193-49c6-81f0-8dcba67b29fd/decision_001/invocation.json", + "status": "COMPLETED" + } + ], + "episode_directory": "/srv/code-behind-layout/runs/development/E1_scope/20261020T014705041353Z_da894835", + "search_status": "SEARCH_FINISHED", + "actions_accepted": 2, + "hidden_calls": 0 + }, + { + "method": "G1", + "invocations": [ + "/srv/code-behind-layout/runtime/opus_cohort_pilots/E1/policy/G1/decisions/89f2cabc-8735-4dcb-9ab4-c1ed74fbd8eb/decision_000/invocation.json" + ], + "real_replies": [ + { + "path": "/srv/code-behind-layout/runtime/opus_cohort_pilots/E1/policy/G1/decisions/89f2cabc-8735-4dcb-9ab4-c1ed74fbd8eb/decision_000/invocation.json", + "status": "REJECTED_SHARED_OUTPUT_BUDGET" + } + ], + "episode_directory": "/srv/code-behind-layout/runs/development/E1_scope/20261020T014914183226Z_2c5e9fce", + "search_status": "MODEL_FAILED", + "actions_accepted": 0, + "hidden_calls": 0 + }, + { + "method": "G2", + "invocations": [ + "/srv/code-behind-layout/runtime/opus_cohort_pilots/E1/policy/G2/decisions/c981e355-1c24-4ef6-a63f-08e39e009b5c/decision_000/invocation.json", + "/srv/code-behind-layout/runtime/opus_cohort_pilots/E1/policy/G2/decisions/c981e355-1c24-4ef6-a63f-08e39e009b5c/decision_001/invocation.json" + ], + "real_replies": [ + { + "path": "/srv/code-behind-layout/runtime/opus_cohort_pilots/E1/policy/G2/decisions/c981e355-1c24-4ef6-a63f-08e39e009b5c/decision_000/invocation.json", + "status": "COMPLETED" + }, + { + "path": "/srv/code-behind-layout/runtime/opus_cohort_pilots/E1/policy/G2/decisions/c981e355-1c24-4ef6-a63f-08e39e009b5c/decision_001/invocation.json", + "status": "COMPLETED" + } + ], + "episode_directory": "/srv/code-behind-layout/runs/development/E1_scope/20261020T015152959079Z_893febcf", + "search_status": "SEARCH_FINISHED", + "actions_accepted": 2, + "hidden_calls": 0 + } + ], + "rule": "Bounded development interface control: at most two Claude decisions and one visible full evaluation per session, no hidden or post-freeze call, raw CLI envelopes retained." + }, + "pilot_runtime_differences": { + "files_changed_after_pilot": { + "scripts/opus_cohort/freeze_cohorts_opus.py": [ + "G0", + "G1", + "G2" + ] + }, + "allowed": [ + "scripts/opus_cohort/freeze_cohorts_opus.py" + ], + "reason": "The freeze tool itself was amended after the pilot (relaxed evidence rule, runtime-difference record); no runtime file changed." + } +} diff --git a/benchmarks/code_behind_layout/configs/experiments/frozen/E1_scope_v2_16k_claude_v2.json b/benchmarks/code_behind_layout/configs/experiments/frozen/E1_scope_v2_16k_claude_v2.json new file mode 100644 index 00000000..8fc578d1 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/experiments/frozen/E1_scope_v2_16k_claude_v2.json @@ -0,0 +1,472 @@ +{ + "status": "FROZEN_E1", + "formal_dispatch": true, + "phase": "formal_E1", + "packet_root": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/packets", + "task_catalog": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/packets/public/catalog.json", + "task_ids": [ + "draft_E1_mirror_s01", + "draft_E1_mirror_s02", + "draft_E1_mirror_s03", + "draft_E1_cascode_mirror_s01", + "draft_E1_cascode_mirror_s02", + "draft_E1_cascode_mirror_s03", + "draft_E1_source_follower_s01", + "draft_E1_source_follower_s02", + "draft_E1_source_follower_s03", + "draft_E1_stacked_switch_s01", + "draft_E1_stacked_switch_s02", + "draft_E1_stacked_switch_s03", + "draft_E1_common_source_stage_s01", + "draft_E1_common_source_stage_s02", + "draft_E1_common_source_stage_s03", + "draft_E1_resistive_diff_s01", + "draft_E1_resistive_diff_s02", + "draft_E1_resistive_diff_s03", + "draft_E1_five_t_s01", + "draft_E1_five_t_s02", + "draft_E1_five_t_s03", + "draft_E1_compact_miller_s01", + "draft_E1_compact_miller_s02", + "draft_E1_compact_miller_s03" + ], + "methods": [ + "G0", + "G1", + "G2" + ], + "trials": 2, + "model_config": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k_claude_v2/model_config.json", + "visible_history_policy": "current_source_and_feedback_v1", + "budget": { + "wall_seconds": 1200, + "decisions": 10, + "physical_evaluations": 3, + "maximum_context_tokens": 16384, + "maximum_output_tokens": 1024 + }, + "runtime": { + "EDA": "runtime/GLdev", + "magic": "runtime/magic-8.3.685", + "candidate_CPUs": 2, + "simultaneous_point_workers_per_episode": 1 + }, + "trusted_bench_bindings": "Built independently per task by scripts/e1_matched_runner.py; no target assembly enters the trusted evaluator.", + "post_freeze": { + "visible": "Fill current-source anchor plus eight development points without policy feedback; separately charge post_freeze_diagnostic.", + "hidden": "Evaluate sixteen points once after source sealing; all raw hidden results stay on trusted backend.", + "incomplete": "Stop affected episode on unknown/infrastructure, retain observed denominators and label no missing outcomes." + }, + "grouping": { + "target_logics": 8, + "primary_groups": 8, + "merged_sensitivity_groups": 7, + "strata": { + "reuse": 12, + "composition": 12 + }, + "shared_domains": "Three sized tasks per target rotate roles of the same25 points, explicitly linked in private/shared_domain_relationships.json. Fresh isolated trials receive only their own fixed nine visible points." + }, + "freeze_blockers": [], + "backend_manifest_path": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k_claude_v2/manifest.json", + "tasks": [ + { + "task_id": "draft_E1_mirror_s01", + "target": "mirror", + "stratum": "reuse", + "source_group": "vendor_glayout_connected", + "merged_source_group": "vendor_glayout_connected", + "parent_lineage": "glayout_mirror", + "shared_domain_id": "mirror_narrow_v3_shared25_mirror" + }, + { + "task_id": "draft_E1_mirror_s02", + "target": "mirror", + "stratum": "composition", + "source_group": "vendor_glayout_connected", + "merged_source_group": "vendor_glayout_connected", + "parent_lineage": "glayout_mirror", + "shared_domain_id": "mirror_narrow_v3_shared25_mirror" + }, + { + "task_id": "draft_E1_mirror_s03", + "target": "mirror", + "stratum": "reuse", + "source_group": "vendor_glayout_connected", + "merged_source_group": "vendor_glayout_connected", + "parent_lineage": "glayout_mirror", + "shared_domain_id": "mirror_narrow_v3_shared25_mirror" + }, + { + "task_id": "draft_E1_cascode_mirror_s01", + "target": "cascode_mirror", + "stratum": "composition", + "source_group": "research_cascode_mirror", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_cascode_mirror", + "shared_domain_id": "exact_grid_v2_shared25_cascode_mirror" + }, + { + "task_id": "draft_E1_cascode_mirror_s02", + "target": "cascode_mirror", + "stratum": "reuse", + "source_group": "research_cascode_mirror", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_cascode_mirror", + "shared_domain_id": "exact_grid_v2_shared25_cascode_mirror" + }, + { + "task_id": "draft_E1_cascode_mirror_s03", + "target": "cascode_mirror", + "stratum": "composition", + "source_group": "research_cascode_mirror", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_cascode_mirror", + "shared_domain_id": "exact_grid_v2_shared25_cascode_mirror" + }, + { + "task_id": "draft_E1_source_follower_s01", + "target": "source_follower", + "stratum": "reuse", + "source_group": "research_source_follower", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_source_follower", + "shared_domain_id": "exact_grid_v2_shared25_source_follower" + }, + { + "task_id": "draft_E1_source_follower_s02", + "target": "source_follower", + "stratum": "composition", + "source_group": "research_source_follower", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_source_follower", + "shared_domain_id": "exact_grid_v2_shared25_source_follower" + }, + { + "task_id": "draft_E1_source_follower_s03", + "target": "source_follower", + "stratum": "reuse", + "source_group": "research_source_follower", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_source_follower", + "shared_domain_id": "exact_grid_v2_shared25_source_follower" + }, + { + "task_id": "draft_E1_stacked_switch_s01", + "target": "stacked_switch", + "stratum": "composition", + "source_group": "research_stacked_switch", + "merged_source_group": "research_stacked_switch", + "parent_lineage": "research_stacked_switch", + "shared_domain_id": "exact_grid_v2_shared25_stacked_switch" + }, + { + "task_id": "draft_E1_stacked_switch_s02", + "target": "stacked_switch", + "stratum": "reuse", + "source_group": "research_stacked_switch", + "merged_source_group": "research_stacked_switch", + "parent_lineage": "research_stacked_switch", + "shared_domain_id": "exact_grid_v2_shared25_stacked_switch" + }, + { + "task_id": "draft_E1_stacked_switch_s03", + "target": "stacked_switch", + "stratum": "composition", + "source_group": "research_stacked_switch", + "merged_source_group": "research_stacked_switch", + "parent_lineage": "research_stacked_switch", + "shared_domain_id": "exact_grid_v2_shared25_stacked_switch" + }, + { + "task_id": "draft_E1_common_source_stage_s01", + "target": "common_source_stage", + "stratum": "reuse", + "source_group": "research_common_source_stage", + "merged_source_group": "research_common_source_stage", + "parent_lineage": "research_common_source_stage", + "shared_domain_id": "exact_grid_v2_shared25_common_source_stage" + }, + { + "task_id": "draft_E1_common_source_stage_s02", + "target": "common_source_stage", + "stratum": "composition", + "source_group": "research_common_source_stage", + "merged_source_group": "research_common_source_stage", + "parent_lineage": "research_common_source_stage", + "shared_domain_id": "exact_grid_v2_shared25_common_source_stage" + }, + { + "task_id": "draft_E1_common_source_stage_s03", + "target": "common_source_stage", + "stratum": "reuse", + "source_group": "research_common_source_stage", + "merged_source_group": "research_common_source_stage", + "parent_lineage": "research_common_source_stage", + "shared_domain_id": "exact_grid_v2_shared25_common_source_stage" + }, + { + "task_id": "draft_E1_resistive_diff_s01", + "target": "resistive_diff", + "stratum": "composition", + "source_group": "research_resistive_diff", + "merged_source_group": "research_resistive_diff", + "parent_lineage": "research_resistive_diff", + "shared_domain_id": "exact_grid_v2_shared25_resistive_diff" + }, + { + "task_id": "draft_E1_resistive_diff_s02", + "target": "resistive_diff", + "stratum": "reuse", + "source_group": "research_resistive_diff", + "merged_source_group": "research_resistive_diff", + "parent_lineage": "research_resistive_diff", + "shared_domain_id": "exact_grid_v2_shared25_resistive_diff" + }, + { + "task_id": "draft_E1_resistive_diff_s03", + "target": "resistive_diff", + "stratum": "composition", + "source_group": "research_resistive_diff", + "merged_source_group": "research_resistive_diff", + "parent_lineage": "research_resistive_diff", + "shared_domain_id": "exact_grid_v2_shared25_resistive_diff" + }, + { + "task_id": "draft_E1_five_t_s01", + "target": "five_t", + "stratum": "reuse", + "source_group": "research_five_t", + "merged_source_group": "research_five_t", + "parent_lineage": "research_five_t", + "shared_domain_id": "exact_grid_v2_shared25_five_t" + }, + { + "task_id": "draft_E1_five_t_s02", + "target": "five_t", + "stratum": "composition", + "source_group": "research_five_t", + "merged_source_group": "research_five_t", + "parent_lineage": "research_five_t", + "shared_domain_id": "exact_grid_v2_shared25_five_t" + }, + { + "task_id": "draft_E1_five_t_s03", + "target": "five_t", + "stratum": "reuse", + "source_group": "research_five_t", + "merged_source_group": "research_five_t", + "parent_lineage": "research_five_t", + "shared_domain_id": "exact_grid_v2_shared25_five_t" + }, + { + "task_id": "draft_E1_compact_miller_s01", + "target": "compact_miller", + "stratum": "composition", + "source_group": "research_compact_miller", + "merged_source_group": "research_compact_miller", + "parent_lineage": "research_compact_miller", + "shared_domain_id": "exact_grid_v2_shared25_compact_miller" + }, + { + "task_id": "draft_E1_compact_miller_s02", + "target": "compact_miller", + "stratum": "reuse", + "source_group": "research_compact_miller", + "merged_source_group": "research_compact_miller", + "parent_lineage": "research_compact_miller", + "shared_domain_id": "exact_grid_v2_shared25_compact_miller" + }, + { + "task_id": "draft_E1_compact_miller_s03", + "target": "compact_miller", + "stratum": "composition", + "source_group": "research_compact_miller", + "merged_source_group": "research_compact_miller", + "parent_lineage": "research_compact_miller", + "shared_domain_id": "exact_grid_v2_shared25_compact_miller" + } + ], + "frozen_registry": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/registry.json", + "qualification": { + "mechanical": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/mechanical_controls.json", + "schematic": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/circuit_feasibility.json", + "policy_interface": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/pilot_reinspection.json", + "capacity": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/token_history_preflight.json" + }, + "dispatch_order_seed": 20261018, + "GPT_sampling_seed": "unavailable; fresh independent trial identifiers only", + "primary_contrasts": [ + "G1-G0", + "G2-G1" + ], + "analysis": { + "stratify_by": "reuse/composition", + "cluster_bootstrap_replicates": 2000, + "bootstrap_seed": 20261018 + }, + "cohort_id": "scope_v2_16k", + "interface_version": "scope_v2_16k", + "prior_interface_manifest": "/srv/code-behind-layout/runtime/protocol_freezes/E1_20261019T0449Z_permission_fix/manifest.json", + "prior_interface_freeze_id": "E1_20261019T0449Z_permission_fix", + "prior_interface_role": "partial_interface_v1_preserve_all_records_and_NOT_RUN", + "scope_proposal": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/scope_proposal.json", + "formal_cohort_rule": "Fresh 144 matched trial identities in a separate suite/index; no parent or E1-C trial is carried or repeated.", + "freeze_id": "E1_scope_v2_16k_claude_v2", + "frozen_at_utc": "2026-10-20T02:38:53.381015+00:00", + "source_revision": "63d33183e745016fddfa071f2e452d9d9008625a", + "implementation_sha256": { + "configs/development/e1_scope_candidate_error_classification.patch": "79b60889f619cbed59515d6aafed0ff45a356d52b989e594e785269601aad651", + "scripts/analyze_e1.py": "adbf72f0d475190647a6b38cc3961682452f7fdc5c682931150565cc95fd450a", + "scripts/analyze_e1_scope.py": "b37b765900bf5615e54b096651c96a12a31a39a48ff036a6b41f6171a4b7f806", + "scripts/archive_e1_episode.py": "02a7d42e02df3b7cfeb86b1b0113c91e5bbeb1d2d550cd41b6d52ea79dcea540", + "scripts/e1_matched_runner.py": "1658264fc4be12520231f27f0a5d15bfc185000833a7dfc14953eb81b42f8856", + "scripts/e1_pcell_prepare.py": "b3bd32774eae9a79257a7cedb3d2f9d718c93023ff95268bc1434a42f5162daa", + "scripts/e1_scope_history_preflight.py": "5e90ef579672e9f3d714f28c4a646d156fbe0c889cff78aa9189ca80ff195fce", + "scripts/e1_scope_pilot.py": "b5df52b54c6a3bd07e8d554c1156a35cbfcd46a07a4bf504c3454cabc48168e3", + "scripts/e1_scope_proposal_preflight.py": "bc55fd4e479cb26c69ed564e84930f3fad92769b2d593efd54844693864f843c", + "scripts/e1_scope_runner.py": "656b5008344be4e86dee2ca52c4df8457bef77a693b9aa872b7fd7f230f88179", + "scripts/freeze_e1.py": "d8258ad41c63e3dcf190ad37d680996c5db1aaeb22e5cdf708ef9b293f7079a6", + "scripts/freeze_e1_scope_cohort.py": "10954129bf38ddd410a7fe4fba5cd81974e9380d1d6c9fcbfc8a7a92442e15bf", + "scripts/materialize_e1_packets.py": "e0a467cee0e70b18013eba3c02eb2af34be562a3869bf746ab4d0f07d0755349", + "scripts/prepare_e1_scope_cohort.py": "7f561ee62d9904f9efbd5279fe3ec45a1d19903763dfbff4e1821ed1a55da7d8", + "scripts/run_e1_scope_suite.py": "19dcb366ef90adccf5c484dab636a56589701e8e2bd7338705dfdfbc03d01f5f", + "scripts/run_e1_suite.py": "7f7fd2a35b75459553f1a64f62ad5f855bb15fea3c5ff3c993c230d9fc13881a", + "scripts/run_eda_probe.py": "1f5229c918cc7b563f1f6c03c733bb46eb06f60d0cc246aa2a70c510bd65f5f1", + "src/candidate_executor.py": "2aa700405ed2c52869c3c6a6a039ab2afe8ca02372cb2fe5432c04fb1c5c66e6", + "src/device_intent.py": "895976ed93024bc30aee2d7afef75eb895261a61742c9ab9a777c7ae68f2de3d", + "src/domain_runner.py": "e9ef34b451b1b0cdbe6e6275e69ebd3448c209a4718b4d7375355628f44d0ddf", + "src/e1_analysis.py": "7765dafd874b3db242f0bd4b6004b0d7e00526a3c3d5edf64485a4015881b901", + "src/e1_benchmarks.py": "22e89b29bd2319fd8a6c9cf5ac9d690699b52e3432456c5d37bc5300b862dcc4", + "src/e1_packets.py": "03562f228f77e81577ec6a03c8ca405044ec80d4a7f7cb8492e486ed27aaa6fc", + "src/local_model_adapter.py": "24e99a3ad5d6dc0a46db7441683fcbfb36507f59f8efeee537b09dbd1be8e283", + "src/measurement.py": "1e9736325e094e023f7f5be1fba4a2328ca61a16ea1667e3f88496e6bf64f18f", + "src/model_adapter.py": "fa737a01c9b23dbf4ed0b4d1d6ba391637c0c769af56252ac6bcdbe4f0a71338", + "src/policy_state.py": "c8803e428d5da62aa6ad886c2cae650fb1fa27fb26d011fdc238a513543751a4", + "src/report_parsers.py": "4ad6a2124e2a573a40910aa13a3ee61cd00e6eb8dd4fba218e1d129cbea994f8", + "src/spice_validation.py": "76b3b34fa9013f5165fd5af66b71101c2835786b2d86df2289f9641a4dd2d628", + "src/opus_cli_adapter.py": "05c80a37429921f2247dfc9522ed950bbea4fd480acfcb5349922465c774fc9a", + "scripts/opus_cohort/__init__.py": "640263ae5bf6af6b3d6bd1c68045204d276ea437fe507c92e9b09439ad9f9046", + "scripts/opus_cohort/common.py": "bc1d92112ec47bfcc427df703397a6d188f78f8dbde482245f0c277afcb49ad6", + "scripts/opus_cohort/e3_episode_opus.py": "cf6e6e56763f927c8c90a3d756387846e52da644c652135eb6656235b640ed48", + "scripts/opus_cohort/e3_parameter_episode_opus.py": "c773ab6c2ae162968f372710c1c055d97677a52f863664b9f5e63fefc0988a6b", + "scripts/opus_cohort/e1_scope_runner_opus.py": "06d3c6af41843f438aff5b5182c76ae88be9d73f589af6263abd76e3e5633b31", + "scripts/opus_cohort/run_e3_suite_opus.py": "4da23faf625d55b02d3eb379a4e241b2bf292b43c618e7360988ff647821723b", + "scripts/opus_cohort/run_e1_scope_suite_opus.py": "d6d806c4dee71349a3e09f27ed717aff3168702d8a0e5ba6c41dd7b735a5d167", + "scripts/opus_cohort/freeze_cohorts_opus.py": "f1b3a31bdc909118ea4be426ad31cc439c4c688cda19100d166d7a98848d4261", + "scripts/opus_cohort/pilot_opus_policy.py": "81b9c63b24880701c7882e85e6a18f246f826a0bcd28337ecadcf48b38c71be7", + "src/opus_cli_adapter_v2.py": "77a54cd60262fd14288fd5541e2f7518a504243d479426a883dde0705f4cabf9", + "scripts/opus_cohort/common_v2.py": "38f6dd71f4b7c7f49cbf5b8d2d270c9c400fb35afcae784844d4e2d0a540947f", + "scripts/opus_cohort/e1_scope_runner_opus_v2.py": "1690bf787e676317ac81083f08376971e26ac817fb6abe10ada331f169d873ac", + "scripts/opus_cohort/run_e1_scope_suite_opus_v2.py": "9e1f57583a0fdda263e518a1f94435090ea04edecf3cbf989b2f2ceef4a1f499", + "scripts/opus_cohort/pilot_opus_policy_v2.py": "99824d8935fd0506d083d671956762cbb7111177e861cdcbc92d2a6652bc099e", + "scripts/opus_cohort/freeze_cohorts_opus_v2.py": "af983eccf618f330b757472ca4296f5713aea4b6927a8888d30a6d72cc9e341a" + }, + "prior_partial_matrix": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/prior_partial_suite.json", + "cohort_analysis_rule": "Only this cohort-specific complete index enters its task-paired analysis; E1-C is reported alongside as the no-guidance condition.", + "parent_freeze_id": "E1_scope_v2_16k", + "parent_manifest_path": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k/manifest.json", + "parent_manifest_sha256": "005ab7fb495df68304b17c5027ecc94301460c2a2af91e49801c93d5f09853d5", + "predecessor_cohort": { + "freeze_id": "E1_scope_v2_16k_claude", + "manifest": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k_claude/manifest.json", + "role": "E1-C without format guidance; its recorded episodes stay a separate partial matrix (paused 2026-10-20 02:11 UTC)" + }, + "policy_backend": "claude_cli", + "policy_model": "claude-opus-5-5", + "cohort_label": "E1-C2", + "system_prompt_version": "format_guidance_v2", + "minimum_tier": { + "e3_trials": 3, + "e1_trials": 2, + "parameter_tasks": 4, + "signal_tasks": 4, + "local_tasks": 8, + "local_inference_trials": 1, + "local_seed_slots": [ + 41, + 73, + 109 + ] + }, + "protocol_amendment": "docs/protocol_amendments_20261019.md A6 (format guidance in the fixed system prompt)", + "declared_episodes": 144, + "format_guidance": "The fixed system prompt adds: one-sentence summary; the whole action within the 1,024-token shared budget; strict unified diff with exact hunk counts and three context lines before and after each change.", + "cohort_rule": "Same tasks, anchors, visible and hidden configurations, references, benches, budgets, selection rules and gateway as the parent freeze and as E1-C; only the policy prompt text differs (amendment A6).", + "pilot_evidence": "/srv/code-behind-layout/runtime/protocol_freezes/E1_scope_v2_16k_claude_v2/pilot_evidence", + "pilot_reinspection": { + "summary": "runtime/opus_cohort_pilots/E1v2/summary.json", + "jobs": [ + { + "method": "G0", + "invocations": [ + "/srv/code-behind-layout/runtime/opus_cohort_pilots/E1v2/policy/G0/decisions/3cdab8df-f937-4a34-b6e4-e3a3a5556c3b/decision_000/invocation.json", + "/srv/code-behind-layout/runtime/opus_cohort_pilots/E1v2/policy/G0/decisions/3cdab8df-f937-4a34-b6e4-e3a3a5556c3b/decision_001/invocation.json" + ], + "real_replies": [ + { + "path": "/srv/code-behind-layout/runtime/opus_cohort_pilots/E1v2/policy/G0/decisions/3cdab8df-f937-4a34-b6e4-e3a3a5556c3b/decision_000/invocation.json", + "status": "COMPLETED" + }, + { + "path": "/srv/code-behind-layout/runtime/opus_cohort_pilots/E1v2/policy/G0/decisions/3cdab8df-f937-4a34-b6e4-e3a3a5556c3b/decision_001/invocation.json", + "status": "COMPLETED" + } + ], + "episode_directory": "/srv/code-behind-layout/runs/development/E1_scope/20261020T023313775453Z_56f3143c", + "search_status": "SEARCH_FINISHED", + "actions_accepted": 2, + "hidden_calls": 0 + }, + { + "method": "G1", + "invocations": [ + "/srv/code-behind-layout/runtime/opus_cohort_pilots/E1v2/policy/G1/decisions/a1cef61d-6c50-490b-a52d-9cb8426a8ca3/decision_000/invocation.json", + "/srv/code-behind-layout/runtime/opus_cohort_pilots/E1v2/policy/G1/decisions/a1cef61d-6c50-490b-a52d-9cb8426a8ca3/decision_001/invocation.json" + ], + "real_replies": [ + { + "path": "/srv/code-behind-layout/runtime/opus_cohort_pilots/E1v2/policy/G1/decisions/a1cef61d-6c50-490b-a52d-9cb8426a8ca3/decision_000/invocation.json", + "status": "COMPLETED" + }, + { + "path": "/srv/code-behind-layout/runtime/opus_cohort_pilots/E1v2/policy/G1/decisions/a1cef61d-6c50-490b-a52d-9cb8426a8ca3/decision_001/invocation.json", + "status": "COMPLETED" + } + ], + "episode_directory": "/srv/code-behind-layout/runs/development/E1_scope/20261020T023458488136Z_52a27dfc", + "search_status": "SEARCH_FINISHED", + "actions_accepted": 2, + "hidden_calls": 0 + }, + { + "method": "G2", + "invocations": [ + "/srv/code-behind-layout/runtime/opus_cohort_pilots/E1v2/policy/G2/decisions/4ba99ad6-b59f-4213-9813-d88651f4b7bf/decision_000/invocation.json", + "/srv/code-behind-layout/runtime/opus_cohort_pilots/E1v2/policy/G2/decisions/4ba99ad6-b59f-4213-9813-d88651f4b7bf/decision_001/invocation.json" + ], + "real_replies": [ + { + "path": "/srv/code-behind-layout/runtime/opus_cohort_pilots/E1v2/policy/G2/decisions/4ba99ad6-b59f-4213-9813-d88651f4b7bf/decision_000/invocation.json", + "status": "COMPLETED" + }, + { + "path": "/srv/code-behind-layout/runtime/opus_cohort_pilots/E1v2/policy/G2/decisions/4ba99ad6-b59f-4213-9813-d88651f4b7bf/decision_001/invocation.json", + "status": "COMPLETED" + } + ], + "episode_directory": "/srv/code-behind-layout/runs/development/E1_scope/20261020T023813592563Z_624fe6c2", + "search_status": "SEARCH_FINISHED", + "actions_accepted": 2, + "hidden_calls": 0 + } + ], + "rule": "Bounded development interface control: at most two Claude decisions and one visible full evaluation per session, no hidden or post-freeze call, raw CLI envelopes retained." + }, + "pilot_runtime_differences": { + "files_changed_after_pilot": {}, + "allowed": [ + "scripts/opus_cohort/freeze_cohorts_opus_v2.py" + ] + } +} diff --git a/benchmarks/code_behind_layout/configs/experiments/frozen/E3_F3_primary.json b/benchmarks/code_behind_layout/configs/experiments/frozen/E3_F3_primary.json new file mode 100644 index 00000000..9e18f1b2 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/experiments/frozen/E3_F3_primary.json @@ -0,0 +1,508 @@ +{ + "status": "FROZEN_E3_FIDELITY_METHOD", + "formal_dispatch": true, + "preparation": "/srv/code-behind-layout/runtime/protocol_freezes/E3_primary_v2/packets", + "task_ids": [ + "draft_E3_five_t_edit02", + "draft_E3_compact_miller_edit02" + ], + "methods": [ + "C" + ], + "trials": 5, + "selection_seeds": [ + 41, + 73, + 109, + 167, + 223 + ], + "model_config": "/srv/code-behind-layout/runtime/protocol_freezes/E3_primary_v2/model_config.json", + "risk_model": "/srv/code-behind-layout/runtime/protocol_freezes/E3_primary_v2/risk_model.json", + "risk_weights": { + "failure_probability": 0, + "uncertainty": 1, + "changed_call_coverage": 0, + "low_margin": 1 + }, + "weight_status": "PREDECLARED_EQUAL_WEIGHT_TRANSPARENT_RULE_NOT_VALIDATION_TUNED", + "fidelity_policy": "F3_actual_nominal_promote_shared_PEX", + "budget_status": "ACTUAL_96PACKET_AND_EIGHT_REAL_FEEDBACK_STRESS_FIT_16K_PENDING_GPU_AND_POLICY_CONTROL", + "budget": { + "wall_seconds": 14400, + "decisions": 24, + "patches": 8, + "full_evaluations": 8, + "maximum_context_tokens": 16384, + "maximum_output_tokens": 1024 + }, + "parameter_baseline": { + "configuration_selector": "C", + "strategies": [ + "random", + "gpt_feedback" + ], + "interface": "prospective_expanded_layout_grid_v1" + }, + "freeze_blockers": [], + "parameter_task_ids": [ + "draft_E3_mirror_edit02", + "draft_E3_cascode_mirror_edit02", + "draft_E3_source_follower_edit02", + "draft_E3_stacked_switch_edit02", + "draft_E3_common_source_stage_edit02", + "draft_E3_resistive_diff_edit02", + "draft_E3_five_t_edit02", + "draft_E3_compact_miller_edit02" + ], + "instance_task_ids": [ + "draft_E3_mirror_edit02", + "draft_E3_cascode_mirror_edit02", + "draft_E3_source_follower_edit02", + "draft_E3_stacked_switch_edit02", + "draft_E3_common_source_stage_edit02", + "draft_E3_resistive_diff_edit02", + "draft_E3_five_t_edit02", + "draft_E3_compact_miller_edit02" + ], + "instance_trials": 1, + "dispatch_order_seed": 20261019, + "e4_methods_manifest": "runtime/protocol_freezes/E4_primary/manifest.json", + "global_release_parts": [ + "gpt", + "parameter", + "local", + "signals", + "fidelity" + ], + "global_release_requires_fidelity_freeze": true, + "fidelity_manifest": "runtime/protocol_freezes/E3_F3_primary/manifest.json", + "e4_evaluation": { + "variants": [ + "T0", + "T1", + "T2", + "T3", + "T4" + ], + "matched_evaluation_seed_slots": [ + 41, + 73, + 109 + ], + "inference_trials": 3, + "T0_actual_model_count": 1, + "T0_independent_training_seeds": 0 + }, + "instance_baseline": { + "algorithm": "independent_arrivals_with_verified_library_exact_cache_v1", + "warm_start": "nearest_previous_verified_configuration_then_latest", + "cache": "exact_source_configuration_reference_PDK_deck_tools_fidelity", + "arrival_order": "/srv/code-behind-layout/runtime/protocol_freezes/E3_primary_v2/instance_arrival_order.json", + "deployment_verification_maximum_physical_calls": 1, + "budget": { + "wall_seconds": 14400, + "decisions": 24, + "patches": 8, + "full_evaluations": 8, + "maximum_context_tokens": 16384, + "maximum_output_tokens": 1024 + }, + "budget_scope": "Same per-arrival search limits as one shared-code episode; every arrival, cache, verification and library cost is charged separately for cumulative cost comparison." + }, + "signal_task_ids": [ + "draft_E3_mirror_edit02", + "draft_E3_cascode_mirror_edit02", + "draft_E3_source_follower_edit02", + "draft_E3_stacked_switch_edit02", + "draft_E3_common_source_stage_edit02", + "draft_E3_resistive_diff_edit02", + "draft_E3_five_t_edit02", + "draft_E3_compact_miller_edit02" + ], + "selector_ablation_weights": { + "without_distance": { + "failure_probability": 0, + "uncertainty": 0, + "changed_call_coverage": 0, + "low_margin": 1 + }, + "without_margin": { + "failure_probability": 0, + "uncertainty": 1, + "changed_call_coverage": 0, + "low_margin": 0 + } + }, + "unavailable_signal_ablation": { + "changed_call_coverage": "No validated current impact map; weight0 in main, so a duplicate run would not identify an effect", + "failure_probability": "No qualified mixed-label family vectors; transparent-rule fallback has weight0" + }, + "fidelity_task_ids": [ + "draft_E3_five_t_edit02", + "draft_E3_compact_miller_edit02" + ], + "phase": "formal_E3", + "freeze_id": "E3_F3_primary", + "frozen_at_utc": "2026-10-19T05:42:44.686665+00:00", + "backend_manifest_path": "/srv/code-behind-layout/runtime/protocol_freezes/E3_F3_primary/manifest.json", + "source_revision": "58565680a3a4d52b83ac09d37888307404a47d53", + "implementation_sha256": { + "docs/e3_protocol.md": "01a83a5c1010c888f98016597b7f3d5692a0b864bdf552131c4e8ae3db9d4127", + "scripts/analyze_e1.py": "adbf72f0d475190647a6b38cc3961682452f7fdc5c682931150565cc95fd450a", + "scripts/archive_e1_episode.py": "02a7d42e02df3b7cfeb86b1b0113c91e5bbeb1d2d550cd41b6d52ea79dcea540", + "scripts/archive_e3_evidence.py": "b7688f12cf1269588edb9d74d95ba2cad5942949aa444008328ebe30a4627126", + "scripts/e1_matched_runner.py": "1658264fc4be12520231f27f0a5d15bfc185000833a7dfc14953eb81b42f8856", + "scripts/e1_pcell_prepare.py": "b3bd32774eae9a79257a7cedb3d2f9d718c93023ff95268bc1434a42f5162daa", + "scripts/e3_anchor_qualify.py": "b044766a322fbc0d3d81163a4e2b8321545d0a69d8602aeed234beeece209b53", + "scripts/e3_episode.py": "c6865e14f729bcb02d65840829895da97447de9f215697e5e24768c2a66b70fa", + "scripts/e3_gateway_control.py": "89396040abceec97ce2d0fc8c1275bcf820409fb6249d4653b5ea39688798143", + "scripts/e3_generation_qualify.py": "fd098c15060910133c4153986c9ef188a116be6232fec15f3e9febf955f6752c", + "scripts/e3_history_preflight.py": "b4e49d8ce4e78af0d5cec93d98d59336c7f1715e654f748b75fdc6bfc911a7cc", + "scripts/e3_instance_episode.py": "dc3ec817156dec42d1834f913d964558b8e423ffc3741fc9f9a2100fa9351447", + "scripts/e3_original_baseline.py": "178f7d8d86c21169821d472463e168834b69fd9cb2e75fbe70d49d5f9807ebf8", + "scripts/e3_parameter_binding_check.py": "6a40b5c098aed65e37ceb3d9b24570a8441f32593d7851d177ea5d4aeb4f4b6d", + "scripts/e3_parameter_episode.py": "32d919e68999721c16e794215fb72c09c987ba44197835e0f63ea3dd6823f40d", + "scripts/e3_physical_point.py": "dda0cf99e81626020ab3cc002a6f36111fb1858314e97553521100460e091eb0", + "scripts/e3_summarize_qualification.py": "41c18e23697e6dc4b8915c878968b2f736825b2ad03a79a6d206d3d8382a7caf", + "scripts/e3_task_prepare.py": "60062e9c5b743adcb0e95ae61f64a52239beb44dada0d5e8f595e86d4c5416d3", + "scripts/e3_trusted_objective.py": "76abbcff773fb27dc817ec8c541deea096d1bb4a59772e17399c85d2980ef812", + "scripts/freeze_e3.py": "662fb1828fd170a8907b65a47792871bd46de7598c582896226e05e0b3dc8ff1", + "scripts/materialize_e1_packets.py": "e0a467cee0e70b18013eba3c02eb2af34be562a3869bf746ab4d0f07d0755349", + "scripts/release_e3_hidden.py": "31bf926e6811707028075716254891eb6ef4aad3ed9a6adeb9fbe84c377b3f59", + "scripts/request_frozen_policy.py": "fc6595360a910f7fe398c4539fb26fe85f92f6055701c53efb75e144c8053e59", + "scripts/run_e1_suite.py": "7f7fd2a35b75459553f1a64f62ad5f855bb15fea3c5ff3c993c230d9fc13881a", + "scripts/run_e3_evaluation.py": "b7043794ca07a1ac461c888f81f1272963baa4a61fcc17278ecc0151ae6fc47e", + "scripts/run_e3_suite.py": "814c47923a664b2a3f39eeac6c2bded1b47489d942a3978cfe71f57fab89a0c9", + "scripts/run_eda_probe.py": "1f5229c918cc7b563f1f6c03c733bb46eb06f60d0cc246aa2a70c510bd65f5f1", + "src/candidate_executor.py": "2aa700405ed2c52869c3c6a6a039ab2afe8ca02372cb2fe5432c04fb1c5c66e6", + "src/device_intent.py": "895976ed93024bc30aee2d7afef75eb895261a61742c9ab9a777c7ae68f2de3d", + "src/domain_runner.py": "e9ef34b451b1b0cdbe6e6275e69ebd3448c209a4718b4d7375355628f44d0ddf", + "src/e1_analysis.py": "7765dafd874b3db242f0bd4b6004b0d7e00526a3c3d5edf64485a4015881b901", + "src/e1_benchmarks.py": "22e89b29bd2319fd8a6c9cf5ac9d690699b52e3432456c5d37bc5300b862dcc4", + "src/e1_packets.py": "03562f228f77e81577ec6a03c8ca405044ec80d4a7f7cb8492e486ed27aaa6fc", + "src/e3_analysis.py": "0576f220be4144015612182374e9b7348d7f75bfc18e0d1af113cde549a5a3ef", + "src/e3_dispatch.py": "6944c06f44825efd2aa0038639c8962e9343e4c36c6ffdb414517daabb764053", + "src/e3_episode_state.py": "05fa6f50b3b271c494f31bc9670c1ab1343b45699031ef4c1137ea2a820cad6f", + "src/e3_feedback.py": "42061fd32c96f07f3d7d1e88a6446a9d7f54908dda1e588d9a328ad1eccf1a8b", + "src/e3_parameters.py": "256bba3d482eee78ad883825b6e2ba2210e5d2fd5542c5d86f876f8a578bfcd2", + "src/e3_policy_models.py": "11b07b2b90118849185d3990524ca6d77ccc8e567d74ca188c5ae2022aafcefb", + "src/e3_regression.py": "428d079a752d5c55e586a788b512f1120fa7ac3ab6d4db9ad13d9430ed880eb2", + "src/e3_risk_model.py": "2131da5f253e63f51454c91c24f9d3a98073f3e06d40b5226bf0af9fa8b6d6ce", + "src/e3_task_prepare.py": "f44c34cfbd448947b5060287a7d6c8065613d94a5a963f89fd58b5563b785ad6", + "src/local_model_adapter.py": "24e99a3ad5d6dc0a46db7441683fcbfb36507f59f8efeee537b09dbd1be8e283", + "src/measurement.py": "1e9736325e094e023f7f5be1fba4a2328ca61a16ea1667e3f88496e6bf64f18f", + "src/model_adapter.py": "fa737a01c9b23dbf4ed0b4d1d6ba391637c0c769af56252ac6bcdbe4f0a71338", + "src/policy_state.py": "c8803e428d5da62aa6ad886c2cae650fb1fa27fb26d011fdc238a513543751a4", + "src/regression_selector.py": "54994e94b514e27f37289520e065c97d8c3bc0950cb01b624d876789c4b8aed4", + "src/report_parsers.py": "4ad6a2124e2a573a40910aa13a3ee61cd00e6eb8dd4fba218e1d129cbea994f8", + "src/spice_validation.py": "76b3b34fa9013f5165fd5af66b71101c2835786b2d86df2289f9641a4dd2d628", + "scripts/e3_fidelity_episode.py": "25da510db20be6190a7f30b590eb728447d76320d6f2e120a48405b6fccb5b94", + "scripts/freeze_e3_fidelity.py": "bb03145fd348ab5487f51a7dc0ea84f9e9c961e48c6b69cc22c086d0d3008f84", + "scripts/e3_fidelity_point.py": "7d4e0b84cb32ffa40b358299791f3725b68c5f949ce54f64f33d0ca7b31d9318", + "scripts/e3_nominal_objective.py": "49a0ca4a6afac161db22b6b8922388f6d1ffc2e87fb9173a7415e254db47bd9c", + "scripts/e2_stage_prepare.py": "51c9f4238e2a8404563beb0857e6c61a16fc5d038e0e0e29d03995a9ec41c999", + "scripts/e2_cached_evaluator.py": "cff820d748f5573482b11bf15e9ee25221737ef6198e2a921e34153b51c9fe68", + "scripts/e2_nominal_bench.py": "1ee40d942d13983112c32ad1318550ae1019c0d8ac7041833192d383c8890173", + "scripts/e2_spice_process_profile.py": "381643021aceb790367b7d1224d9e0a5537689631e2768116380fc9948aebcaa", + "scripts/e2_execution.py": "dfb7d8d25a2676b7f1f9936d1b11a6c2cf72e618694dd0779871d55824aa64cb", + "src/promotion_calibration.py": "94eff5d73ab848867fcf000d9d07260a29fd5de4af7c3947150070235eff57c3" + }, + "original_baseline_plan": "/srv/code-behind-layout/runtime/protocol_freezes/E3_primary_v2/original_baseline/plan.json", + "hidden_release_file": "/srv/code-behind-layout/runtime/evaluation_releases/E3_E3_primary_v2.json", + "hidden_evaluation": "Use the main global release only after this method artifact and all ten extra search sources are sealed and source-hash bound", + "frozen_registry": "/srv/code-behind-layout/runtime/protocol_freezes/E3_primary_v2/registry.json", + "E1_manifest": "/srv/code-behind-layout/runtime/protocol_freezes/E1_20261019T0449Z_permission_fix/manifest.json", + "tasks": [ + { + "task_id": "draft_E3_mirror_edit01", + "target": "mirror", + "source_group": "vendor_glayout_connected", + "merged_source_group": "vendor_glayout_connected", + "parent_lineage": "glayout_mirror" + }, + { + "task_id": "draft_E3_mirror_edit02", + "target": "mirror", + "source_group": "vendor_glayout_connected", + "merged_source_group": "vendor_glayout_connected", + "parent_lineage": "glayout_mirror" + }, + { + "task_id": "draft_E3_mirror_edit03", + "target": "mirror", + "source_group": "vendor_glayout_connected", + "merged_source_group": "vendor_glayout_connected", + "parent_lineage": "glayout_mirror" + }, + { + "task_id": "draft_E3_cascode_mirror_edit01", + "target": "cascode_mirror", + "source_group": "research_cascode_mirror", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_cascode_mirror" + }, + { + "task_id": "draft_E3_cascode_mirror_edit02", + "target": "cascode_mirror", + "source_group": "research_cascode_mirror", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_cascode_mirror" + }, + { + "task_id": "draft_E3_cascode_mirror_edit03", + "target": "cascode_mirror", + "source_group": "research_cascode_mirror", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_cascode_mirror" + }, + { + "task_id": "draft_E3_source_follower_edit01", + "target": "source_follower", + "source_group": "research_source_follower", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_source_follower" + }, + { + "task_id": "draft_E3_source_follower_edit02", + "target": "source_follower", + "source_group": "research_source_follower", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_source_follower" + }, + { + "task_id": "draft_E3_source_follower_edit03", + "target": "source_follower", + "source_group": "research_source_follower", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_source_follower" + }, + { + "task_id": "draft_E3_stacked_switch_edit01", + "target": "stacked_switch", + "source_group": "research_stacked_switch", + "merged_source_group": "research_stacked_switch", + "parent_lineage": "research_stacked_switch" + }, + { + "task_id": "draft_E3_stacked_switch_edit02", + "target": "stacked_switch", + "source_group": "research_stacked_switch", + "merged_source_group": "research_stacked_switch", + "parent_lineage": "research_stacked_switch" + }, + { + "task_id": "draft_E3_stacked_switch_edit03", + "target": "stacked_switch", + "source_group": "research_stacked_switch", + "merged_source_group": "research_stacked_switch", + "parent_lineage": "research_stacked_switch" + }, + { + "task_id": "draft_E3_common_source_stage_edit01", + "target": "common_source_stage", + "source_group": "research_common_source_stage", + "merged_source_group": "research_common_source_stage", + "parent_lineage": "research_common_source_stage" + }, + { + "task_id": "draft_E3_common_source_stage_edit02", + "target": "common_source_stage", + "source_group": "research_common_source_stage", + "merged_source_group": "research_common_source_stage", + "parent_lineage": "research_common_source_stage" + }, + { + "task_id": "draft_E3_common_source_stage_edit03", + "target": "common_source_stage", + "source_group": "research_common_source_stage", + "merged_source_group": "research_common_source_stage", + "parent_lineage": "research_common_source_stage" + }, + { + "task_id": "draft_E3_resistive_diff_edit01", + "target": "resistive_diff", + "source_group": "research_resistive_diff", + "merged_source_group": "research_resistive_diff", + "parent_lineage": "research_resistive_diff" + }, + { + "task_id": "draft_E3_resistive_diff_edit02", + "target": "resistive_diff", + "source_group": "research_resistive_diff", + "merged_source_group": "research_resistive_diff", + "parent_lineage": "research_resistive_diff" + }, + { + "task_id": "draft_E3_resistive_diff_edit03", + "target": "resistive_diff", + "source_group": "research_resistive_diff", + "merged_source_group": "research_resistive_diff", + "parent_lineage": "research_resistive_diff" + }, + { + "task_id": "draft_E3_five_t_edit01", + "target": "five_t", + "source_group": "research_five_t", + "merged_source_group": "research_five_t", + "parent_lineage": "research_five_t" + }, + { + "task_id": "draft_E3_five_t_edit02", + "target": "five_t", + "source_group": "research_five_t", + "merged_source_group": "research_five_t", + "parent_lineage": "research_five_t" + }, + { + "task_id": "draft_E3_five_t_edit03", + "target": "five_t", + "source_group": "research_five_t", + "merged_source_group": "research_five_t", + "parent_lineage": "research_five_t" + }, + { + "task_id": "draft_E3_compact_miller_edit01", + "target": "compact_miller", + "source_group": "research_compact_miller", + "merged_source_group": "research_compact_miller", + "parent_lineage": "research_compact_miller" + }, + { + "task_id": "draft_E3_compact_miller_edit02", + "target": "compact_miller", + "source_group": "research_compact_miller", + "merged_source_group": "research_compact_miller", + "parent_lineage": "research_compact_miller" + }, + { + "task_id": "draft_E3_compact_miller_edit03", + "target": "compact_miller", + "source_group": "research_compact_miller", + "merged_source_group": "research_compact_miller", + "parent_lineage": "research_compact_miller" + } + ], + "primary_source_groups": 8, + "merged_sensitivity_groups": 7, + "qualification": "/srv/code-behind-layout/runtime/protocol_freezes/E3_primary_v2/qualification", + "original_baseline_declared_points": 600, + "analysis": { + "primary_contrasts": [ + "C-R", + "C-B" + ], + "cluster_bootstrap_replicates": 2000, + "bootstrap_seed": 20261019, + "group_units": [ + 8, + 7 + ], + "baseline_regression": "Private original-pass denominator join" + }, + "GPT_sampling_seed": "Unavailable; five fresh trial identities, not claimed provider random seeds", + "fidelity_freeze_id": "E3_F3_primary", + "main_freeze_id": "E3_primary_v2", + "main_protocol_manifest": "/srv/code-behind-layout/runtime/protocol_freezes/E3_primary_v2/manifest.json", + "policy_variants": [ + "GPT" + ], + "search_plan": [ + { + "task_id": "draft_E3_five_t_edit02", + "method": "C", + "trial_id": "1", + "policy_variant": "GPT", + "selection_seed": 41, + "fidelity_policy": "F3_actual_nominal_promote_shared_PEX" + }, + { + "task_id": "draft_E3_five_t_edit02", + "method": "C", + "trial_id": "2", + "policy_variant": "GPT", + "selection_seed": 73, + "fidelity_policy": "F3_actual_nominal_promote_shared_PEX" + }, + { + "task_id": "draft_E3_five_t_edit02", + "method": "C", + "trial_id": "3", + "policy_variant": "GPT", + "selection_seed": 109, + "fidelity_policy": "F3_actual_nominal_promote_shared_PEX" + }, + { + "task_id": "draft_E3_five_t_edit02", + "method": "C", + "trial_id": "4", + "policy_variant": "GPT", + "selection_seed": 167, + "fidelity_policy": "F3_actual_nominal_promote_shared_PEX" + }, + { + "task_id": "draft_E3_five_t_edit02", + "method": "C", + "trial_id": "5", + "policy_variant": "GPT", + "selection_seed": 223, + "fidelity_policy": "F3_actual_nominal_promote_shared_PEX" + }, + { + "task_id": "draft_E3_compact_miller_edit02", + "method": "C", + "trial_id": "1", + "policy_variant": "GPT", + "selection_seed": 41, + "fidelity_policy": "F3_actual_nominal_promote_shared_PEX" + }, + { + "task_id": "draft_E3_compact_miller_edit02", + "method": "C", + "trial_id": "2", + "policy_variant": "GPT", + "selection_seed": 73, + "fidelity_policy": "F3_actual_nominal_promote_shared_PEX" + }, + { + "task_id": "draft_E3_compact_miller_edit02", + "method": "C", + "trial_id": "3", + "policy_variant": "GPT", + "selection_seed": 109, + "fidelity_policy": "F3_actual_nominal_promote_shared_PEX" + }, + { + "task_id": "draft_E3_compact_miller_edit02", + "method": "C", + "trial_id": "4", + "policy_variant": "GPT", + "selection_seed": 167, + "fidelity_policy": "F3_actual_nominal_promote_shared_PEX" + }, + { + "task_id": "draft_E3_compact_miller_edit02", + "method": "C", + "trial_id": "5", + "policy_variant": "GPT", + "selection_seed": 223, + "fidelity_policy": "F3_actual_nominal_promote_shared_PEX" + } + ], + "promotion_calibration": "/srv/code-behind-layout/runtime/protocol_freezes/E3_F3_primary/promotion_calibration.json", + "promotion_calibration_sha256": "0aabfb6c7bbb34a7e02d5c00312076646052cb51bb29b83d0bcc84015d5b4f59", + "fidelity_budget": { + "low_fidelity_calls": 32, + "counting": "Actual PEX acquisition=1; actual TT nominal invocation=1; combined total32, not64", + "actual_full_evaluator_invocations": 8, + "wall_and_decision_patch_context_budgets_match_main": true + }, + "actual_control_proofs": "/srv/code-behind-layout/runtime/protocol_freezes/E3_F3_primary/actual_control_proofs.json", + "F0_comparison": "Reuse the same main C task/trial searches; do not launch or relabel extra F0 trials", + "retained_verification": "Anchor and all previously observed passing/failing regressions force actual full; only new untested development points may be screened_deferred", + "screened_status": "No S2 prediction, no actual failure/counterexample, no observed pass; verified selection uses actual full only", + "post_freeze_physical_path": "Fresh original F0 source-to-GDS/full physical benchmark for every configuration; no search cache reuse", + "expected_efficiency_limitation": "Existing development OTA nominals are outside calibration support and force full. Zero full savings plus nominal overhead is an admissible negative result.", + "new_physical_calls_during_freeze": 0, + "new_model_calls_during_freeze": 0 +} diff --git a/benchmarks/code_behind_layout/configs/experiments/frozen/E3_primary_v2.json b/benchmarks/code_behind_layout/configs/experiments/frozen/E3_primary_v2.json new file mode 100644 index 00000000..cbcd3be6 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/experiments/frozen/E3_primary_v2.json @@ -0,0 +1,419 @@ +{ + "status": "FROZEN_E3", + "formal_dispatch": true, + "preparation": "/srv/code-behind-layout/runtime/protocol_freezes/E3_primary_v2/packets", + "task_ids": [ + "draft_E3_mirror_edit01", + "draft_E3_mirror_edit02", + "draft_E3_mirror_edit03", + "draft_E3_cascode_mirror_edit01", + "draft_E3_cascode_mirror_edit02", + "draft_E3_cascode_mirror_edit03", + "draft_E3_source_follower_edit01", + "draft_E3_source_follower_edit02", + "draft_E3_source_follower_edit03", + "draft_E3_stacked_switch_edit01", + "draft_E3_stacked_switch_edit02", + "draft_E3_stacked_switch_edit03", + "draft_E3_common_source_stage_edit01", + "draft_E3_common_source_stage_edit02", + "draft_E3_common_source_stage_edit03", + "draft_E3_resistive_diff_edit01", + "draft_E3_resistive_diff_edit02", + "draft_E3_resistive_diff_edit03", + "draft_E3_five_t_edit01", + "draft_E3_five_t_edit02", + "draft_E3_five_t_edit03", + "draft_E3_compact_miller_edit01", + "draft_E3_compact_miller_edit02", + "draft_E3_compact_miller_edit03" + ], + "methods": [ + "A", + "R", + "B", + "C" + ], + "trials": 5, + "selection_seeds": [ + 41, + 73, + 109, + 167, + 223 + ], + "model_config": "/srv/code-behind-layout/runtime/protocol_freezes/E3_primary_v2/model_config.json", + "risk_model": "/srv/code-behind-layout/runtime/protocol_freezes/E3_primary_v2/risk_model.json", + "risk_weights": { + "failure_probability": 0, + "uncertainty": 1, + "changed_call_coverage": 0, + "low_margin": 1 + }, + "weight_status": "PREDECLARED_EQUAL_WEIGHT_TRANSPARENT_RULE_NOT_VALIDATION_TUNED", + "fidelity_policy": "F0_actual_full_each_selected_configuration", + "budget_status": "ACTUAL_96PACKET_AND_EIGHT_REAL_FEEDBACK_STRESS_FIT_16K_PENDING_GPU_AND_POLICY_CONTROL", + "budget": { + "wall_seconds": 14400, + "decisions": 24, + "patches": 8, + "full_evaluations": 8, + "maximum_context_tokens": 16384, + "maximum_output_tokens": 1024 + }, + "parameter_baseline": { + "configuration_selector": "C", + "strategies": [ + "random", + "gpt_feedback" + ], + "interface": "prospective_expanded_layout_grid_v1" + }, + "freeze_blockers": [], + "parameter_task_ids": [ + "draft_E3_mirror_edit02", + "draft_E3_cascode_mirror_edit02", + "draft_E3_source_follower_edit02", + "draft_E3_stacked_switch_edit02", + "draft_E3_common_source_stage_edit02", + "draft_E3_resistive_diff_edit02", + "draft_E3_five_t_edit02", + "draft_E3_compact_miller_edit02" + ], + "instance_task_ids": [ + "draft_E3_mirror_edit02", + "draft_E3_cascode_mirror_edit02", + "draft_E3_source_follower_edit02", + "draft_E3_stacked_switch_edit02", + "draft_E3_common_source_stage_edit02", + "draft_E3_resistive_diff_edit02", + "draft_E3_five_t_edit02", + "draft_E3_compact_miller_edit02" + ], + "instance_trials": 1, + "dispatch_order_seed": 20261019, + "e4_methods_manifest": "runtime/protocol_freezes/E4_primary/manifest.json", + "global_release_parts": [ + "gpt", + "parameter", + "local", + "signals", + "fidelity" + ], + "global_release_requires_fidelity_freeze": true, + "fidelity_manifest": "runtime/protocol_freezes/E3_F3_primary/manifest.json", + "e4_evaluation": { + "variants": [ + "T0", + "T1", + "T2", + "T3", + "T4" + ], + "matched_evaluation_seed_slots": [ + 41, + 73, + 109 + ], + "inference_trials": 3, + "T0_actual_model_count": 1, + "T0_independent_training_seeds": 0 + }, + "instance_baseline": { + "algorithm": "independent_arrivals_with_verified_library_exact_cache_v1", + "warm_start": "nearest_previous_verified_configuration_then_latest", + "cache": "exact_source_configuration_reference_PDK_deck_tools_fidelity", + "arrival_order": "/srv/code-behind-layout/runtime/protocol_freezes/E3_primary_v2/instance_arrival_order.json", + "deployment_verification_maximum_physical_calls": 1, + "budget": { + "wall_seconds": 14400, + "decisions": 24, + "patches": 8, + "full_evaluations": 8, + "maximum_context_tokens": 16384, + "maximum_output_tokens": 1024 + }, + "budget_scope": "Same per-arrival search limits as one shared-code episode; every arrival, cache, verification and library cost is charged separately for cumulative cost comparison." + }, + "signal_task_ids": [ + "draft_E3_mirror_edit02", + "draft_E3_cascode_mirror_edit02", + "draft_E3_source_follower_edit02", + "draft_E3_stacked_switch_edit02", + "draft_E3_common_source_stage_edit02", + "draft_E3_resistive_diff_edit02", + "draft_E3_five_t_edit02", + "draft_E3_compact_miller_edit02" + ], + "selector_ablation_weights": { + "without_distance": { + "failure_probability": 0, + "uncertainty": 0, + "changed_call_coverage": 0, + "low_margin": 1 + }, + "without_margin": { + "failure_probability": 0, + "uncertainty": 1, + "changed_call_coverage": 0, + "low_margin": 0 + } + }, + "unavailable_signal_ablation": { + "changed_call_coverage": "No validated current impact map; weight0 in main, so a duplicate run would not identify an effect", + "failure_probability": "No qualified mixed-label family vectors; transparent-rule fallback has weight0" + }, + "fidelity_task_ids": [ + "draft_E3_five_t_edit02", + "draft_E3_compact_miller_edit02" + ], + "phase": "formal_E3", + "freeze_id": "E3_primary_v2", + "frozen_at_utc": "2026-10-19T05:41:24.782513+00:00", + "backend_manifest_path": "/srv/code-behind-layout/runtime/protocol_freezes/E3_primary_v2/manifest.json", + "source_revision": "58565680a3a4d52b83ac09d37888307404a47d53", + "implementation_sha256": { + "docs/e3_protocol.md": "01a83a5c1010c888f98016597b7f3d5692a0b864bdf552131c4e8ae3db9d4127", + "scripts/analyze_e1.py": "adbf72f0d475190647a6b38cc3961682452f7fdc5c682931150565cc95fd450a", + "scripts/archive_e1_episode.py": "02a7d42e02df3b7cfeb86b1b0113c91e5bbeb1d2d550cd41b6d52ea79dcea540", + "scripts/archive_e3_evidence.py": "b7688f12cf1269588edb9d74d95ba2cad5942949aa444008328ebe30a4627126", + "scripts/e1_matched_runner.py": "1658264fc4be12520231f27f0a5d15bfc185000833a7dfc14953eb81b42f8856", + "scripts/e1_pcell_prepare.py": "b3bd32774eae9a79257a7cedb3d2f9d718c93023ff95268bc1434a42f5162daa", + "scripts/e3_anchor_qualify.py": "b044766a322fbc0d3d81163a4e2b8321545d0a69d8602aeed234beeece209b53", + "scripts/e3_episode.py": "c6865e14f729bcb02d65840829895da97447de9f215697e5e24768c2a66b70fa", + "scripts/e3_gateway_control.py": "89396040abceec97ce2d0fc8c1275bcf820409fb6249d4653b5ea39688798143", + "scripts/e3_generation_qualify.py": "fd098c15060910133c4153986c9ef188a116be6232fec15f3e9febf955f6752c", + "scripts/e3_history_preflight.py": "b4e49d8ce4e78af0d5cec93d98d59336c7f1715e654f748b75fdc6bfc911a7cc", + "scripts/e3_instance_episode.py": "dc3ec817156dec42d1834f913d964558b8e423ffc3741fc9f9a2100fa9351447", + "scripts/e3_original_baseline.py": "178f7d8d86c21169821d472463e168834b69fd9cb2e75fbe70d49d5f9807ebf8", + "scripts/e3_parameter_binding_check.py": "6a40b5c098aed65e37ceb3d9b24570a8441f32593d7851d177ea5d4aeb4f4b6d", + "scripts/e3_parameter_episode.py": "32d919e68999721c16e794215fb72c09c987ba44197835e0f63ea3dd6823f40d", + "scripts/e3_physical_point.py": "dda0cf99e81626020ab3cc002a6f36111fb1858314e97553521100460e091eb0", + "scripts/e3_summarize_qualification.py": "41c18e23697e6dc4b8915c878968b2f736825b2ad03a79a6d206d3d8382a7caf", + "scripts/e3_task_prepare.py": "60062e9c5b743adcb0e95ae61f64a52239beb44dada0d5e8f595e86d4c5416d3", + "scripts/e3_trusted_objective.py": "76abbcff773fb27dc817ec8c541deea096d1bb4a59772e17399c85d2980ef812", + "scripts/freeze_e3.py": "662fb1828fd170a8907b65a47792871bd46de7598c582896226e05e0b3dc8ff1", + "scripts/materialize_e1_packets.py": "e0a467cee0e70b18013eba3c02eb2af34be562a3869bf746ab4d0f07d0755349", + "scripts/release_e3_hidden.py": "31bf926e6811707028075716254891eb6ef4aad3ed9a6adeb9fbe84c377b3f59", + "scripts/request_frozen_policy.py": "fc6595360a910f7fe398c4539fb26fe85f92f6055701c53efb75e144c8053e59", + "scripts/run_e1_suite.py": "7f7fd2a35b75459553f1a64f62ad5f855bb15fea3c5ff3c993c230d9fc13881a", + "scripts/run_e3_evaluation.py": "b7043794ca07a1ac461c888f81f1272963baa4a61fcc17278ecc0151ae6fc47e", + "scripts/run_e3_suite.py": "814c47923a664b2a3f39eeac6c2bded1b47489d942a3978cfe71f57fab89a0c9", + "scripts/run_eda_probe.py": "1f5229c918cc7b563f1f6c03c733bb46eb06f60d0cc246aa2a70c510bd65f5f1", + "src/candidate_executor.py": "2aa700405ed2c52869c3c6a6a039ab2afe8ca02372cb2fe5432c04fb1c5c66e6", + "src/device_intent.py": "895976ed93024bc30aee2d7afef75eb895261a61742c9ab9a777c7ae68f2de3d", + "src/domain_runner.py": "e9ef34b451b1b0cdbe6e6275e69ebd3448c209a4718b4d7375355628f44d0ddf", + "src/e1_analysis.py": "7765dafd874b3db242f0bd4b6004b0d7e00526a3c3d5edf64485a4015881b901", + "src/e1_benchmarks.py": "22e89b29bd2319fd8a6c9cf5ac9d690699b52e3432456c5d37bc5300b862dcc4", + "src/e1_packets.py": "03562f228f77e81577ec6a03c8ca405044ec80d4a7f7cb8492e486ed27aaa6fc", + "src/e3_analysis.py": "0576f220be4144015612182374e9b7348d7f75bfc18e0d1af113cde549a5a3ef", + "src/e3_dispatch.py": "6944c06f44825efd2aa0038639c8962e9343e4c36c6ffdb414517daabb764053", + "src/e3_episode_state.py": "05fa6f50b3b271c494f31bc9670c1ab1343b45699031ef4c1137ea2a820cad6f", + "src/e3_feedback.py": "42061fd32c96f07f3d7d1e88a6446a9d7f54908dda1e588d9a328ad1eccf1a8b", + "src/e3_parameters.py": "256bba3d482eee78ad883825b6e2ba2210e5d2fd5542c5d86f876f8a578bfcd2", + "src/e3_policy_models.py": "11b07b2b90118849185d3990524ca6d77ccc8e567d74ca188c5ae2022aafcefb", + "src/e3_regression.py": "428d079a752d5c55e586a788b512f1120fa7ac3ab6d4db9ad13d9430ed880eb2", + "src/e3_risk_model.py": "2131da5f253e63f51454c91c24f9d3a98073f3e06d40b5226bf0af9fa8b6d6ce", + "src/e3_task_prepare.py": "f44c34cfbd448947b5060287a7d6c8065613d94a5a963f89fd58b5563b785ad6", + "src/local_model_adapter.py": "24e99a3ad5d6dc0a46db7441683fcbfb36507f59f8efeee537b09dbd1be8e283", + "src/measurement.py": "1e9736325e094e023f7f5be1fba4a2328ca61a16ea1667e3f88496e6bf64f18f", + "src/model_adapter.py": "fa737a01c9b23dbf4ed0b4d1d6ba391637c0c769af56252ac6bcdbe4f0a71338", + "src/policy_state.py": "c8803e428d5da62aa6ad886c2cae650fb1fa27fb26d011fdc238a513543751a4", + "src/regression_selector.py": "54994e94b514e27f37289520e065c97d8c3bc0950cb01b624d876789c4b8aed4", + "src/report_parsers.py": "4ad6a2124e2a573a40910aa13a3ee61cd00e6eb8dd4fba218e1d129cbea994f8", + "src/spice_validation.py": "76b3b34fa9013f5165fd5af66b71101c2835786b2d86df2289f9641a4dd2d628" + }, + "original_baseline_plan": "/srv/code-behind-layout/runtime/protocol_freezes/E3_primary_v2/original_baseline/plan.json", + "hidden_release_file": "/srv/code-behind-layout/runtime/evaluation_releases/E3_E3_primary_v2.json", + "hidden_evaluation": "Deferred until all declared searches and all method/model artifacts are sealed; private oracle released once", + "frozen_registry": "/srv/code-behind-layout/runtime/protocol_freezes/E3_primary_v2/registry.json", + "E1_manifest": "/srv/code-behind-layout/runtime/protocol_freezes/E1_20261019T0449Z_permission_fix/manifest.json", + "tasks": [ + { + "task_id": "draft_E3_mirror_edit01", + "target": "mirror", + "source_group": "vendor_glayout_connected", + "merged_source_group": "vendor_glayout_connected", + "parent_lineage": "glayout_mirror" + }, + { + "task_id": "draft_E3_mirror_edit02", + "target": "mirror", + "source_group": "vendor_glayout_connected", + "merged_source_group": "vendor_glayout_connected", + "parent_lineage": "glayout_mirror" + }, + { + "task_id": "draft_E3_mirror_edit03", + "target": "mirror", + "source_group": "vendor_glayout_connected", + "merged_source_group": "vendor_glayout_connected", + "parent_lineage": "glayout_mirror" + }, + { + "task_id": "draft_E3_cascode_mirror_edit01", + "target": "cascode_mirror", + "source_group": "research_cascode_mirror", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_cascode_mirror" + }, + { + "task_id": "draft_E3_cascode_mirror_edit02", + "target": "cascode_mirror", + "source_group": "research_cascode_mirror", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_cascode_mirror" + }, + { + "task_id": "draft_E3_cascode_mirror_edit03", + "target": "cascode_mirror", + "source_group": "research_cascode_mirror", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_cascode_mirror" + }, + { + "task_id": "draft_E3_source_follower_edit01", + "target": "source_follower", + "source_group": "research_source_follower", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_source_follower" + }, + { + "task_id": "draft_E3_source_follower_edit02", + "target": "source_follower", + "source_group": "research_source_follower", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_source_follower" + }, + { + "task_id": "draft_E3_source_follower_edit03", + "target": "source_follower", + "source_group": "research_source_follower", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_source_follower" + }, + { + "task_id": "draft_E3_stacked_switch_edit01", + "target": "stacked_switch", + "source_group": "research_stacked_switch", + "merged_source_group": "research_stacked_switch", + "parent_lineage": "research_stacked_switch" + }, + { + "task_id": "draft_E3_stacked_switch_edit02", + "target": "stacked_switch", + "source_group": "research_stacked_switch", + "merged_source_group": "research_stacked_switch", + "parent_lineage": "research_stacked_switch" + }, + { + "task_id": "draft_E3_stacked_switch_edit03", + "target": "stacked_switch", + "source_group": "research_stacked_switch", + "merged_source_group": "research_stacked_switch", + "parent_lineage": "research_stacked_switch" + }, + { + "task_id": "draft_E3_common_source_stage_edit01", + "target": "common_source_stage", + "source_group": "research_common_source_stage", + "merged_source_group": "research_common_source_stage", + "parent_lineage": "research_common_source_stage" + }, + { + "task_id": "draft_E3_common_source_stage_edit02", + "target": "common_source_stage", + "source_group": "research_common_source_stage", + "merged_source_group": "research_common_source_stage", + "parent_lineage": "research_common_source_stage" + }, + { + "task_id": "draft_E3_common_source_stage_edit03", + "target": "common_source_stage", + "source_group": "research_common_source_stage", + "merged_source_group": "research_common_source_stage", + "parent_lineage": "research_common_source_stage" + }, + { + "task_id": "draft_E3_resistive_diff_edit01", + "target": "resistive_diff", + "source_group": "research_resistive_diff", + "merged_source_group": "research_resistive_diff", + "parent_lineage": "research_resistive_diff" + }, + { + "task_id": "draft_E3_resistive_diff_edit02", + "target": "resistive_diff", + "source_group": "research_resistive_diff", + "merged_source_group": "research_resistive_diff", + "parent_lineage": "research_resistive_diff" + }, + { + "task_id": "draft_E3_resistive_diff_edit03", + "target": "resistive_diff", + "source_group": "research_resistive_diff", + "merged_source_group": "research_resistive_diff", + "parent_lineage": "research_resistive_diff" + }, + { + "task_id": "draft_E3_five_t_edit01", + "target": "five_t", + "source_group": "research_five_t", + "merged_source_group": "research_five_t", + "parent_lineage": "research_five_t" + }, + { + "task_id": "draft_E3_five_t_edit02", + "target": "five_t", + "source_group": "research_five_t", + "merged_source_group": "research_five_t", + "parent_lineage": "research_five_t" + }, + { + "task_id": "draft_E3_five_t_edit03", + "target": "five_t", + "source_group": "research_five_t", + "merged_source_group": "research_five_t", + "parent_lineage": "research_five_t" + }, + { + "task_id": "draft_E3_compact_miller_edit01", + "target": "compact_miller", + "source_group": "research_compact_miller", + "merged_source_group": "research_compact_miller", + "parent_lineage": "research_compact_miller" + }, + { + "task_id": "draft_E3_compact_miller_edit02", + "target": "compact_miller", + "source_group": "research_compact_miller", + "merged_source_group": "research_compact_miller", + "parent_lineage": "research_compact_miller" + }, + { + "task_id": "draft_E3_compact_miller_edit03", + "target": "compact_miller", + "source_group": "research_compact_miller", + "merged_source_group": "research_compact_miller", + "parent_lineage": "research_compact_miller" + } + ], + "primary_source_groups": 8, + "merged_sensitivity_groups": 7, + "qualification": "/srv/code-behind-layout/runtime/protocol_freezes/E3_primary_v2/qualification", + "original_baseline_declared_points": 600, + "analysis": { + "primary_contrasts": [ + "C-R", + "C-B" + ], + "cluster_bootstrap_replicates": 2000, + "bootstrap_seed": 20261019, + "group_units": [ + 8, + 7 + ], + "baseline_regression": "Private original-pass denominator join" + }, + "GPT_sampling_seed": "Unavailable; five fresh trial identities, not claimed provider random seeds" +} diff --git a/benchmarks/code_behind_layout/configs/experiments/frozen/E3_primary_v2_claude.json b/benchmarks/code_behind_layout/configs/experiments/frozen/E3_primary_v2_claude.json new file mode 100644 index 00000000..64e97334 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/experiments/frozen/E3_primary_v2_claude.json @@ -0,0 +1,534 @@ +{ + "status": "FROZEN_E3", + "formal_dispatch": true, + "preparation": "/srv/code-behind-layout/runtime/protocol_freezes/E3_primary_v2/packets", + "task_ids": [ + "draft_E3_mirror_edit01", + "draft_E3_mirror_edit02", + "draft_E3_mirror_edit03", + "draft_E3_cascode_mirror_edit01", + "draft_E3_cascode_mirror_edit02", + "draft_E3_cascode_mirror_edit03", + "draft_E3_source_follower_edit01", + "draft_E3_source_follower_edit02", + "draft_E3_source_follower_edit03", + "draft_E3_stacked_switch_edit01", + "draft_E3_stacked_switch_edit02", + "draft_E3_stacked_switch_edit03", + "draft_E3_common_source_stage_edit01", + "draft_E3_common_source_stage_edit02", + "draft_E3_common_source_stage_edit03", + "draft_E3_resistive_diff_edit01", + "draft_E3_resistive_diff_edit02", + "draft_E3_resistive_diff_edit03", + "draft_E3_five_t_edit01", + "draft_E3_five_t_edit02", + "draft_E3_five_t_edit03", + "draft_E3_compact_miller_edit01", + "draft_E3_compact_miller_edit02", + "draft_E3_compact_miller_edit03" + ], + "methods": [ + "A", + "R", + "B", + "C" + ], + "trials": 3, + "selection_seeds": [ + 41, + 73, + 109, + 167, + 223 + ], + "model_config": "/srv/code-behind-layout/runtime/protocol_freezes/E3_primary_v2_claude/model_config.json", + "risk_model": "/srv/code-behind-layout/runtime/protocol_freezes/E3_primary_v2/risk_model.json", + "risk_weights": { + "failure_probability": 0, + "uncertainty": 1, + "changed_call_coverage": 0, + "low_margin": 1 + }, + "weight_status": "PREDECLARED_EQUAL_WEIGHT_TRANSPARENT_RULE_NOT_VALIDATION_TUNED", + "fidelity_policy": "F0_actual_full_each_selected_configuration", + "budget_status": "ACTUAL_96PACKET_AND_EIGHT_REAL_FEEDBACK_STRESS_FIT_16K_PENDING_GPU_AND_POLICY_CONTROL", + "budget": { + "wall_seconds": 14400, + "decisions": 24, + "patches": 8, + "full_evaluations": 8, + "maximum_context_tokens": 16384, + "maximum_output_tokens": 1024 + }, + "parameter_baseline": { + "configuration_selector": "C", + "strategies": [ + "random", + "gpt_feedback" + ], + "interface": "prospective_expanded_layout_grid_v1" + }, + "freeze_blockers": [], + "parameter_task_ids": [ + "draft_E3_mirror_edit02", + "draft_E3_cascode_mirror_edit02", + "draft_E3_source_follower_edit02", + "draft_E3_stacked_switch_edit02", + "draft_E3_common_source_stage_edit02", + "draft_E3_resistive_diff_edit02", + "draft_E3_five_t_edit02", + "draft_E3_compact_miller_edit02" + ], + "instance_task_ids": [ + "draft_E3_mirror_edit02", + "draft_E3_cascode_mirror_edit02", + "draft_E3_source_follower_edit02", + "draft_E3_stacked_switch_edit02", + "draft_E3_common_source_stage_edit02", + "draft_E3_resistive_diff_edit02", + "draft_E3_five_t_edit02", + "draft_E3_compact_miller_edit02" + ], + "instance_trials": 1, + "dispatch_order_seed": 20261019, + "e4_methods_manifest": "runtime/protocol_freezes/E4_primary/manifest.json", + "global_release_parts": [ + "gpt", + "parameter", + "signals", + "local" + ], + "global_release_requires_fidelity_freeze": false, + "fidelity_manifest": "runtime/protocol_freezes/E3_F3_primary/manifest.json", + "e4_evaluation": { + "variants": [ + "T0", + "T1", + "T2", + "T3", + "T4" + ], + "matched_evaluation_seed_slots": [ + 41, + 73, + 109 + ], + "inference_trials": 1, + "T0_actual_model_count": 1, + "T0_independent_training_seeds": 0 + }, + "instance_baseline": { + "algorithm": "independent_arrivals_with_verified_library_exact_cache_v1", + "warm_start": "nearest_previous_verified_configuration_then_latest", + "cache": "exact_source_configuration_reference_PDK_deck_tools_fidelity", + "arrival_order": "/srv/code-behind-layout/runtime/protocol_freezes/E3_primary_v2/instance_arrival_order.json", + "deployment_verification_maximum_physical_calls": 1, + "budget": { + "wall_seconds": 14400, + "decisions": 24, + "patches": 8, + "full_evaluations": 8, + "maximum_context_tokens": 16384, + "maximum_output_tokens": 1024 + }, + "budget_scope": "Same per-arrival search limits as one shared-code episode; every arrival, cache, verification and library cost is charged separately for cumulative cost comparison." + }, + "signal_task_ids": [ + "draft_E3_mirror_edit02", + "draft_E3_cascode_mirror_edit02", + "draft_E3_source_follower_edit02", + "draft_E3_stacked_switch_edit02", + "draft_E3_common_source_stage_edit02", + "draft_E3_resistive_diff_edit02", + "draft_E3_five_t_edit02", + "draft_E3_compact_miller_edit02" + ], + "selector_ablation_weights": { + "without_distance": { + "failure_probability": 0, + "uncertainty": 0, + "changed_call_coverage": 0, + "low_margin": 1 + }, + "without_margin": { + "failure_probability": 0, + "uncertainty": 1, + "changed_call_coverage": 0, + "low_margin": 0 + } + }, + "unavailable_signal_ablation": { + "changed_call_coverage": "No validated current impact map; weight0 in main, so a duplicate run would not identify an effect", + "failure_probability": "No qualified mixed-label family vectors; transparent-rule fallback has weight0" + }, + "fidelity_task_ids": [ + "draft_E3_five_t_edit02", + "draft_E3_compact_miller_edit02" + ], + "phase": "formal_E3", + "freeze_id": "E3_primary_v2_claude", + "frozen_at_utc": "2026-10-20T01:53:25.800485+00:00", + "backend_manifest_path": "/srv/code-behind-layout/runtime/protocol_freezes/E3_primary_v2_claude/manifest.json", + "source_revision": "58565680a3a4d52b83ac09d37888307404a47d53", + "implementation_sha256": { + "docs/e3_protocol.md": "01a83a5c1010c888f98016597b7f3d5692a0b864bdf552131c4e8ae3db9d4127", + "scripts/analyze_e1.py": "adbf72f0d475190647a6b38cc3961682452f7fdc5c682931150565cc95fd450a", + "scripts/archive_e1_episode.py": "02a7d42e02df3b7cfeb86b1b0113c91e5bbeb1d2d550cd41b6d52ea79dcea540", + "scripts/archive_e3_evidence.py": "b7688f12cf1269588edb9d74d95ba2cad5942949aa444008328ebe30a4627126", + "scripts/e1_matched_runner.py": "1658264fc4be12520231f27f0a5d15bfc185000833a7dfc14953eb81b42f8856", + "scripts/e1_pcell_prepare.py": "b3bd32774eae9a79257a7cedb3d2f9d718c93023ff95268bc1434a42f5162daa", + "scripts/e3_anchor_qualify.py": "b044766a322fbc0d3d81163a4e2b8321545d0a69d8602aeed234beeece209b53", + "scripts/e3_episode.py": "c6865e14f729bcb02d65840829895da97447de9f215697e5e24768c2a66b70fa", + "scripts/e3_gateway_control.py": "89396040abceec97ce2d0fc8c1275bcf820409fb6249d4653b5ea39688798143", + "scripts/e3_generation_qualify.py": "fd098c15060910133c4153986c9ef188a116be6232fec15f3e9febf955f6752c", + "scripts/e3_history_preflight.py": "b4e49d8ce4e78af0d5cec93d98d59336c7f1715e654f748b75fdc6bfc911a7cc", + "scripts/e3_instance_episode.py": "dc3ec817156dec42d1834f913d964558b8e423ffc3741fc9f9a2100fa9351447", + "scripts/e3_original_baseline.py": "178f7d8d86c21169821d472463e168834b69fd9cb2e75fbe70d49d5f9807ebf8", + "scripts/e3_parameter_binding_check.py": "6a40b5c098aed65e37ceb3d9b24570a8441f32593d7851d177ea5d4aeb4f4b6d", + "scripts/e3_parameter_episode.py": "32d919e68999721c16e794215fb72c09c987ba44197835e0f63ea3dd6823f40d", + "scripts/e3_physical_point.py": "dda0cf99e81626020ab3cc002a6f36111fb1858314e97553521100460e091eb0", + "scripts/e3_summarize_qualification.py": "41c18e23697e6dc4b8915c878968b2f736825b2ad03a79a6d206d3d8382a7caf", + "scripts/e3_task_prepare.py": "60062e9c5b743adcb0e95ae61f64a52239beb44dada0d5e8f595e86d4c5416d3", + "scripts/e3_trusted_objective.py": "76abbcff773fb27dc817ec8c541deea096d1bb4a59772e17399c85d2980ef812", + "scripts/freeze_e3.py": "662fb1828fd170a8907b65a47792871bd46de7598c582896226e05e0b3dc8ff1", + "scripts/materialize_e1_packets.py": "e0a467cee0e70b18013eba3c02eb2af34be562a3869bf746ab4d0f07d0755349", + "scripts/release_e3_hidden.py": "31bf926e6811707028075716254891eb6ef4aad3ed9a6adeb9fbe84c377b3f59", + "scripts/request_frozen_policy.py": "fc6595360a910f7fe398c4539fb26fe85f92f6055701c53efb75e144c8053e59", + "scripts/run_e1_suite.py": "7f7fd2a35b75459553f1a64f62ad5f855bb15fea3c5ff3c993c230d9fc13881a", + "scripts/run_e3_evaluation.py": "b7043794ca07a1ac461c888f81f1272963baa4a61fcc17278ecc0151ae6fc47e", + "scripts/run_e3_suite.py": "814c47923a664b2a3f39eeac6c2bded1b47489d942a3978cfe71f57fab89a0c9", + "scripts/run_eda_probe.py": "1f5229c918cc7b563f1f6c03c733bb46eb06f60d0cc246aa2a70c510bd65f5f1", + "src/candidate_executor.py": "2aa700405ed2c52869c3c6a6a039ab2afe8ca02372cb2fe5432c04fb1c5c66e6", + "src/device_intent.py": "895976ed93024bc30aee2d7afef75eb895261a61742c9ab9a777c7ae68f2de3d", + "src/domain_runner.py": "e9ef34b451b1b0cdbe6e6275e69ebd3448c209a4718b4d7375355628f44d0ddf", + "src/e1_analysis.py": "7765dafd874b3db242f0bd4b6004b0d7e00526a3c3d5edf64485a4015881b901", + "src/e1_benchmarks.py": "22e89b29bd2319fd8a6c9cf5ac9d690699b52e3432456c5d37bc5300b862dcc4", + "src/e1_packets.py": "03562f228f77e81577ec6a03c8ca405044ec80d4a7f7cb8492e486ed27aaa6fc", + "src/e3_analysis.py": "0576f220be4144015612182374e9b7348d7f75bfc18e0d1af113cde549a5a3ef", + "src/e3_dispatch.py": "6944c06f44825efd2aa0038639c8962e9343e4c36c6ffdb414517daabb764053", + "src/e3_episode_state.py": "05fa6f50b3b271c494f31bc9670c1ab1343b45699031ef4c1137ea2a820cad6f", + "src/e3_feedback.py": "42061fd32c96f07f3d7d1e88a6446a9d7f54908dda1e588d9a328ad1eccf1a8b", + "src/e3_parameters.py": "256bba3d482eee78ad883825b6e2ba2210e5d2fd5542c5d86f876f8a578bfcd2", + "src/e3_policy_models.py": "11b07b2b90118849185d3990524ca6d77ccc8e567d74ca188c5ae2022aafcefb", + "src/e3_regression.py": "428d079a752d5c55e586a788b512f1120fa7ac3ab6d4db9ad13d9430ed880eb2", + "src/e3_risk_model.py": "2131da5f253e63f51454c91c24f9d3a98073f3e06d40b5226bf0af9fa8b6d6ce", + "src/e3_task_prepare.py": "f44c34cfbd448947b5060287a7d6c8065613d94a5a963f89fd58b5563b785ad6", + "src/local_model_adapter.py": "24e99a3ad5d6dc0a46db7441683fcbfb36507f59f8efeee537b09dbd1be8e283", + "src/measurement.py": "1e9736325e094e023f7f5be1fba4a2328ca61a16ea1667e3f88496e6bf64f18f", + "src/model_adapter.py": "fa737a01c9b23dbf4ed0b4d1d6ba391637c0c769af56252ac6bcdbe4f0a71338", + "src/policy_state.py": "c8803e428d5da62aa6ad886c2cae650fb1fa27fb26d011fdc238a513543751a4", + "src/regression_selector.py": "54994e94b514e27f37289520e065c97d8c3bc0950cb01b624d876789c4b8aed4", + "src/report_parsers.py": "4ad6a2124e2a573a40910aa13a3ee61cd00e6eb8dd4fba218e1d129cbea994f8", + "src/spice_validation.py": "76b3b34fa9013f5165fd5af66b71101c2835786b2d86df2289f9641a4dd2d628", + "src/opus_cli_adapter.py": "05c80a37429921f2247dfc9522ed950bbea4fd480acfcb5349922465c774fc9a", + "scripts/opus_cohort/__init__.py": "640263ae5bf6af6b3d6bd1c68045204d276ea437fe507c92e9b09439ad9f9046", + "scripts/opus_cohort/common.py": "bc1d92112ec47bfcc427df703397a6d188f78f8dbde482245f0c277afcb49ad6", + "scripts/opus_cohort/e3_episode_opus.py": "cf6e6e56763f927c8c90a3d756387846e52da644c652135eb6656235b640ed48", + "scripts/opus_cohort/e3_parameter_episode_opus.py": "c773ab6c2ae162968f372710c1c055d97677a52f863664b9f5e63fefc0988a6b", + "scripts/opus_cohort/e1_scope_runner_opus.py": "06d3c6af41843f438aff5b5182c76ae88be9d73f589af6263abd76e3e5633b31", + "scripts/opus_cohort/run_e3_suite_opus.py": "4da23faf625d55b02d3eb379a4e241b2bf292b43c618e7360988ff647821723b", + "scripts/opus_cohort/run_e1_scope_suite_opus.py": "d6d806c4dee71349a3e09f27ed717aff3168702d8a0e5ba6c41dd7b735a5d167", + "scripts/opus_cohort/freeze_cohorts_opus.py": "f1b3a31bdc909118ea4be426ad31cc439c4c688cda19100d166d7a98848d4261", + "scripts/opus_cohort/pilot_opus_policy.py": "81b9c63b24880701c7882e85e6a18f246f826a0bcd28337ecadcf48b38c71be7" + }, + "original_baseline_plan": "/srv/code-behind-layout/runtime/protocol_freezes/E3_primary_v2/original_baseline/plan.json", + "hidden_release_file": "/srv/code-behind-layout/runtime/evaluation_releases/E3_E3_primary_v2_claude.json", + "hidden_evaluation": "Deferred per cohort (amendment A2): released once every declared E3-C search is sealed and the E4 training data, split registry and recipe are frozen.", + "frozen_registry": "/srv/code-behind-layout/runtime/protocol_freezes/E3_primary_v2/registry.json", + "E1_manifest": "/srv/code-behind-layout/runtime/protocol_freezes/E1_20261019T0449Z_permission_fix/manifest.json", + "tasks": [ + { + "task_id": "draft_E3_mirror_edit01", + "target": "mirror", + "source_group": "vendor_glayout_connected", + "merged_source_group": "vendor_glayout_connected", + "parent_lineage": "glayout_mirror" + }, + { + "task_id": "draft_E3_mirror_edit02", + "target": "mirror", + "source_group": "vendor_glayout_connected", + "merged_source_group": "vendor_glayout_connected", + "parent_lineage": "glayout_mirror" + }, + { + "task_id": "draft_E3_mirror_edit03", + "target": "mirror", + "source_group": "vendor_glayout_connected", + "merged_source_group": "vendor_glayout_connected", + "parent_lineage": "glayout_mirror" + }, + { + "task_id": "draft_E3_cascode_mirror_edit01", + "target": "cascode_mirror", + "source_group": "research_cascode_mirror", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_cascode_mirror" + }, + { + "task_id": "draft_E3_cascode_mirror_edit02", + "target": "cascode_mirror", + "source_group": "research_cascode_mirror", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_cascode_mirror" + }, + { + "task_id": "draft_E3_cascode_mirror_edit03", + "target": "cascode_mirror", + "source_group": "research_cascode_mirror", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_cascode_mirror" + }, + { + "task_id": "draft_E3_source_follower_edit01", + "target": "source_follower", + "source_group": "research_source_follower", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_source_follower" + }, + { + "task_id": "draft_E3_source_follower_edit02", + "target": "source_follower", + "source_group": "research_source_follower", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_source_follower" + }, + { + "task_id": "draft_E3_source_follower_edit03", + "target": "source_follower", + "source_group": "research_source_follower", + "merged_source_group": "research_bias_buffer_shared", + "parent_lineage": "research_source_follower" + }, + { + "task_id": "draft_E3_stacked_switch_edit01", + "target": "stacked_switch", + "source_group": "research_stacked_switch", + "merged_source_group": "research_stacked_switch", + "parent_lineage": "research_stacked_switch" + }, + { + "task_id": "draft_E3_stacked_switch_edit02", + "target": "stacked_switch", + "source_group": "research_stacked_switch", + "merged_source_group": "research_stacked_switch", + "parent_lineage": "research_stacked_switch" + }, + { + "task_id": "draft_E3_stacked_switch_edit03", + "target": "stacked_switch", + "source_group": "research_stacked_switch", + "merged_source_group": "research_stacked_switch", + "parent_lineage": "research_stacked_switch" + }, + { + "task_id": "draft_E3_common_source_stage_edit01", + "target": "common_source_stage", + "source_group": "research_common_source_stage", + "merged_source_group": "research_common_source_stage", + "parent_lineage": "research_common_source_stage" + }, + { + "task_id": "draft_E3_common_source_stage_edit02", + "target": "common_source_stage", + "source_group": "research_common_source_stage", + "merged_source_group": "research_common_source_stage", + "parent_lineage": "research_common_source_stage" + }, + { + "task_id": "draft_E3_common_source_stage_edit03", + "target": "common_source_stage", + "source_group": "research_common_source_stage", + "merged_source_group": "research_common_source_stage", + "parent_lineage": "research_common_source_stage" + }, + { + "task_id": "draft_E3_resistive_diff_edit01", + "target": "resistive_diff", + "source_group": "research_resistive_diff", + "merged_source_group": "research_resistive_diff", + "parent_lineage": "research_resistive_diff" + }, + { + "task_id": "draft_E3_resistive_diff_edit02", + "target": "resistive_diff", + "source_group": "research_resistive_diff", + "merged_source_group": "research_resistive_diff", + "parent_lineage": "research_resistive_diff" + }, + { + "task_id": "draft_E3_resistive_diff_edit03", + "target": "resistive_diff", + "source_group": "research_resistive_diff", + "merged_source_group": "research_resistive_diff", + "parent_lineage": "research_resistive_diff" + }, + { + "task_id": "draft_E3_five_t_edit01", + "target": "five_t", + "source_group": "research_five_t", + "merged_source_group": "research_five_t", + "parent_lineage": "research_five_t" + }, + { + "task_id": "draft_E3_five_t_edit02", + "target": "five_t", + "source_group": "research_five_t", + "merged_source_group": "research_five_t", + "parent_lineage": "research_five_t" + }, + { + "task_id": "draft_E3_five_t_edit03", + "target": "five_t", + "source_group": "research_five_t", + "merged_source_group": "research_five_t", + "parent_lineage": "research_five_t" + }, + { + "task_id": "draft_E3_compact_miller_edit01", + "target": "compact_miller", + "source_group": "research_compact_miller", + "merged_source_group": "research_compact_miller", + "parent_lineage": "research_compact_miller" + }, + { + "task_id": "draft_E3_compact_miller_edit02", + "target": "compact_miller", + "source_group": "research_compact_miller", + "merged_source_group": "research_compact_miller", + "parent_lineage": "research_compact_miller" + }, + { + "task_id": "draft_E3_compact_miller_edit03", + "target": "compact_miller", + "source_group": "research_compact_miller", + "merged_source_group": "research_compact_miller", + "parent_lineage": "research_compact_miller" + } + ], + "primary_source_groups": 8, + "merged_sensitivity_groups": 7, + "qualification": "/srv/code-behind-layout/runtime/protocol_freezes/E3_primary_v2/qualification", + "original_baseline_declared_points": 600, + "analysis": { + "primary_contrasts": [ + "C-R", + "C-B" + ], + "cluster_bootstrap_replicates": 2000, + "bootstrap_seed": 20261019, + "group_units": [ + 8, + 7 + ], + "baseline_regression": "Private original-pass denominator join" + }, + "GPT_sampling_seed": "Unavailable; five fresh trial identities, not claimed provider random seeds", + "parent_freeze_id": "E3_primary_v2", + "parent_manifest_path": "/srv/code-behind-layout/runtime/protocol_freezes/E3_primary_v2/manifest.json", + "parent_manifest_sha256": "94d7c817510e950eaa3e019894801bc88349473003e1d7cffdbfaa2d53e59120", + "policy_backend": "claude_cli", + "policy_model": "claude-opus-5-5", + "cohort_label": "E3-C", + "minimum_tier": { + "e3_trials": 3, + "e1_trials": 2, + "parameter_tasks": 4, + "signal_tasks": 4, + "local_tasks": 8, + "local_inference_trials": 1, + "local_seed_slots": [ + 41, + 73, + 109 + ] + }, + "protocol_amendment": "docs/protocol_amendments_20261019.md", + "cohort_rule": "Same tasks, anchors, visible and hidden configurations, references, benches, budgets, selection rules and gateway as the parent freeze; only the policy backend, the adapter implementation and the Minimum-tier matrix differ. Parent trials stay a separate matrix.", + "parameter_task_ids_minimum": [ + "draft_E3_cascode_mirror_edit02", + "draft_E3_common_source_stage_edit02", + "draft_E3_resistive_diff_edit02", + "draft_E3_stacked_switch_edit02" + ], + "signal_task_ids_minimum": [ + "draft_E3_cascode_mirror_edit02", + "draft_E3_common_source_stage_edit02", + "draft_E3_resistive_diff_edit02", + "draft_E3_stacked_switch_edit02" + ], + "local_task_ids_minimum": [ + "draft_E3_cascode_mirror_edit02", + "draft_E3_common_source_stage_edit02", + "draft_E3_compact_miller_edit02", + "draft_E3_five_t_edit02", + "draft_E3_mirror_edit02", + "draft_E3_resistive_diff_edit02", + "draft_E3_source_follower_edit02", + "draft_E3_stacked_switch_edit02" + ], + "subset_rule": "random.Random(dispatch_order_seed).sample(sorted(parent common subset), 4); local-model searches use the parent common eight-task subset", + "declared_searches": { + "gpt": 288, + "parameter": 24, + "signals": 24, + "local": 104 + }, + "pilot_evidence": "/srv/code-behind-layout/runtime/protocol_freezes/E3_primary_v2_claude/pilot_evidence", + "pilot_reinspection": { + "summary": "runtime/opus_cohort_pilots/E3/summary.json", + "jobs": [ + { + "method": "C", + "invocations": [ + "/srv/code-behind-layout/runtime/opus_cohort_pilots/E3/policy/C/decisions/e173f040-e676-4324-afba-d569c034eb27/decision_000/invocation.json", + "/srv/code-behind-layout/runtime/opus_cohort_pilots/E3/policy/C/decisions/e173f040-e676-4324-afba-d569c034eb27/decision_001/invocation.json" + ], + "real_replies": [ + { + "path": "/srv/code-behind-layout/runtime/opus_cohort_pilots/E3/policy/C/decisions/e173f040-e676-4324-afba-d569c034eb27/decision_000/invocation.json", + "status": "COMPLETED" + }, + { + "path": "/srv/code-behind-layout/runtime/opus_cohort_pilots/E3/policy/C/decisions/e173f040-e676-4324-afba-d569c034eb27/decision_001/invocation.json", + "status": "COMPLETED" + } + ], + "episode_directory": "/srv/code-behind-layout/runs/development/E3_episodes/20261020T014706774150Z_3b81ee4e", + "search_status": "DECISION_BUDGET_EXHAUSTED", + "actions_accepted": 2, + "hidden_calls": 0 + }, + { + "method": "A", + "invocations": [ + "/srv/code-behind-layout/runtime/opus_cohort_pilots/E3/policy/A/decisions/7ab89526-c6b8-4499-82ba-f5fc4d5faaa8/decision_000/invocation.json", + "/srv/code-behind-layout/runtime/opus_cohort_pilots/E3/policy/A/decisions/7ab89526-c6b8-4499-82ba-f5fc4d5faaa8/decision_001/invocation.json" + ], + "real_replies": [ + { + "path": "/srv/code-behind-layout/runtime/opus_cohort_pilots/E3/policy/A/decisions/7ab89526-c6b8-4499-82ba-f5fc4d5faaa8/decision_000/invocation.json", + "status": "COMPLETED" + }, + { + "path": "/srv/code-behind-layout/runtime/opus_cohort_pilots/E3/policy/A/decisions/7ab89526-c6b8-4499-82ba-f5fc4d5faaa8/decision_001/invocation.json", + "status": "COMPLETED" + } + ], + "episode_directory": "/srv/code-behind-layout/runs/development/E3_episodes/20261020T014905563877Z_1ce7d3b1", + "search_status": "DECISION_BUDGET_EXHAUSTED", + "actions_accepted": 2, + "hidden_calls": 0 + } + ], + "rule": "Bounded development interface control: at most two Claude decisions and one visible full evaluation per session, no hidden or post-freeze call, raw CLI envelopes retained." + }, + "pilot_runtime_differences": { + "files_changed_after_pilot": {}, + "allowed": [ + "scripts/opus_cohort/freeze_cohorts_opus.py" + ], + "reason": "The freeze tool itself was amended after the pilot (relaxed evidence rule, runtime-difference record); no runtime file changed." + } +} diff --git a/benchmarks/code_behind_layout/configs/models/claude_opus55_16k.json b/benchmarks/code_behind_layout/configs/models/claude_opus55_16k.json new file mode 100644 index 00000000..63a7e82b --- /dev/null +++ b/benchmarks/code_behind_layout/configs/models/claude_opus55_16k.json @@ -0,0 +1,24 @@ +{ + "status": "DRAFT_CLAUDE_COHORT_POLICY_NOT_FROZEN", + "backend": "claude_cli", + "executable": "claude", + "cli_version_observed": "2.1.295 (Claude CLI)", + "model": "claude-opus-5-5", + "model_identity": "claude-opus-5-5 through Claude CLI 2.1.295 print mode; tools, MCP servers, hooks, plugins, skills and project instructions disabled; one fresh non-persistent session per decision", + "reasoning_effort": "high", + "timeout_seconds_per_decision": 600, + "max_context_tokens": 16384, + "max_new_tokens": 1024, + "budget_tokenizer_backbone": "Qwen/Qwen2.5-Coder-32B-Instruct", + "budget_tokenizer_revision": "381fc969f78efac66bc87ff7ddeadb7e73c218a7", + "cli_flags": ["-p", "--output-format json", "--tools \"\"", "--strict-mcp-config", "--no-session-persistence", "--max-turns 1", "--permission-mode default", "--safe-mode", "--disable-slash-commands", "--exclude-dynamic-system-prompt-sections", "--settings {hooks:{},enabledPlugins:{},env:{}}", "--system-prompt ", "--effort high"], + "working_directory": "Empty scratch directory under /tmp/cbl-policy-cwd per decision, outside any project tree; removed after the call", + "tools_disabled": true, + "mcp_disabled": true, + "session_persistence": false, + "max_turns": 1, + "system_prompt_fixed": true, + "output_normalization": "A single outer ```json fence is stripped and recorded as fence_stripped; no other repair. Non-JSON or over-budget output is rejected and retained.", + "output_enforcement": "Posthoc shared-tokenizer cap; overlong raw outputs are retained with provider usage and rejected before execution. Provider usage and cost are reported from the CLI JSON envelope.", + "model_identity_scope": "Requested model name and effort; actual served model names are recorded from modelUsage per decision; no sampling seed is exposed." +} diff --git a/benchmarks/code_behind_layout/configs/models/gpt.json b/benchmarks/code_behind_layout/configs/models/gpt.json new file mode 100644 index 00000000..c3f129ff --- /dev/null +++ b/benchmarks/code_behind_layout/configs/models/gpt.json @@ -0,0 +1,9 @@ +{ + "status": "development_candidate_not_formal_freeze", + "backend": "authenticated_gpt_cli", + "model": "gpt-6.1-sol", + "reasoning_effort": "high", + "timeout_seconds_per_decision": 600, + "model_identity_scope": "Explicit catalog slug; no checkpoint or sampling seed is exposed", + "cli_version_observed": "gpt-cli 0.163.0-alpha.10.2" +} diff --git a/benchmarks/code_behind_layout/configs/models/gpt_bounded.draft.json b/benchmarks/code_behind_layout/configs/models/gpt_bounded.draft.json new file mode 100644 index 00000000..d5231696 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/models/gpt_bounded.draft.json @@ -0,0 +1,13 @@ +{ + "status": "draft_shared_budget_policy_not_formal_freeze", + "backend": "authenticated_gpt_cli", + "model": "gpt-6.1-sol", + "reasoning_effort": "high", + "timeout_seconds_per_decision": 600, + "max_context_tokens": 8192, + "max_new_tokens": 1024, + "budget_tokenizer_backbone": "Qwen/Qwen2.5-Coder-32B-Instruct", + "budget_tokenizer_revision": "381fc969f78efac66bc87ff7ddeadb7e73c218a7", + "output_enforcement": "Posthoc shared-tokenizer cap; overlong raw actions are retained with provider usage and rejected before execution. Provider reasoning tokens are separately reported.", + "model_identity_scope": "Explicit catalog slug; provider checkpoint, sampling seed and reasoning compute cap unavailable" +} diff --git a/benchmarks/code_behind_layout/configs/models/gpt_e3_12k.draft.json b/benchmarks/code_behind_layout/configs/models/gpt_e3_12k.draft.json new file mode 100644 index 00000000..ffbd1674 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/models/gpt_e3_12k.draft.json @@ -0,0 +1,13 @@ +{ + "status": "DRAFT_E3_PROPOSED12K_PENDING_ACTUAL_H100_CALIBRATION", + "backend": "authenticated_gpt_cli", + "model": "gpt-6.1-sol", + "reasoning_effort": "high", + "timeout_seconds_per_decision": 600, + "max_context_tokens": 12288, + "max_new_tokens": 1024, + "budget_tokenizer_backbone": "Qwen/Qwen2.5-Coder-32B-Instruct", + "budget_tokenizer_revision": "381fc969f78efac66bc87ff7ddeadb7e73c218a7", + "output_enforcement": "Posthoc shared-tokenizer cap; overlong raw actions are retained with provider usage and rejected before execution. Provider reasoning tokens are separately reported.", + "model_identity_scope": "Explicit catalog slug; provider checkpoint, sampling seed and reasoning compute cap unavailable" +} diff --git a/benchmarks/code_behind_layout/configs/models/gpt_e3_16k.draft.json b/benchmarks/code_behind_layout/configs/models/gpt_e3_16k.draft.json new file mode 100644 index 00000000..899aada2 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/models/gpt_e3_16k.draft.json @@ -0,0 +1,13 @@ +{ + "status": "DRAFT_16K_PENDING_ACTUAL_H100_AND_POLICY_CONTROL", + "backend": "authenticated_gpt_cli", + "model": "gpt-6.1-sol", + "reasoning_effort": "high", + "timeout_seconds_per_decision": 600, + "max_context_tokens": 16384, + "max_new_tokens": 1024, + "budget_tokenizer_backbone": "Qwen/Qwen2.5-Coder-32B-Instruct", + "budget_tokenizer_revision": "381fc969f78efac66bc87ff7ddeadb7e73c218a7", + "output_enforcement": "Posthoc shared-tokenizer cap; overlong raw actions are retained with provider usage and rejected before execution. Provider reasoning tokens are separately reported.", + "model_identity_scope": "Explicit catalog slug; provider checkpoint, sampling seed and reasoning compute cap unavailable" +} diff --git a/benchmarks/code_behind_layout/configs/study.json b/benchmarks/code_behind_layout/configs/study.json new file mode 100644 index 00000000..0c1340ec --- /dev/null +++ b/benchmarks/code_behind_layout/configs/study.json @@ -0,0 +1,88 @@ +{ + "schema_version": 1, + "status": "draft", + "title": "The Code Behind the Layout: AI Agents for Analog Layout Generators", + "primary_endpoint": "hidden_configuration_S2_coverage", + "secondary_endpoint": "regression_among_baseline_S2_passed_configurations", + "primary_comparisons": [ + "C_vs_R", + "C_vs_B", + "T4_vs_T3", + "T2_vs_T1" + ], + "experiments": { + "E1": { + "methods": [ + "G0", + "G1", + "G2" + ], + "target_tasks": 24, + "target_trials_per_method": 5 + }, + "E2": { + "target_ota_lineages": 4, + "sizings_per_lineage": 3, + "candidates_per_sizing": 64 + }, + "E3": { + "methods": [ + "A", + "R", + "B", + "C" + ], + "target_tasks": 24, + "target_trials_per_method": 5, + "parameter_baseline_min_tasks": 8 + }, + "E4": { + "methods": [ + "T0", + "T1", + "T2", + "T3", + "T4" + ], + "training_seeds_required_per_trained_method": 3, + "backbone_candidate": "Qwen2.5-Coder-32B-Instruct", + "checkpoint_revision": "381fc969f78efac66bc87ff7ddeadb7e73c218a7" + }, + "E5": { + "units": [ + "wall_seconds", + "cpu_seconds", + "gpu_hours", + "verification_calls", + "logged_visible_tokens" + ] + } + }, + "editing_domain_targets": { + "anchor": 1, + "development": 8, + "hidden": 16, + "independent_lineages": 8, + "topology_families": 4, + "complete_topology_holdouts": 2 + }, + "actual_pdk_versions": [], + "actual_device_flavors": [ + "sky130_fd_pr__nfet_01v8", + "sky130_fd_pr__pfet_01v8", + "sky130_fd_pr__cap_mim_m3_1" + ], + "actual_corners": [ + "tt", + "ss", + "ff" + ], + "episode_budgets": null, + "formal_tasks": [], + "freeze_blockers": [ + "fully materialized feasible task domains and independent source clusters", + "complete draft task/split admission", + "pilot-calibrated method budgets and source-context interfaces", + "train/validation calibration for selectors and fidelity models" + ] +} diff --git a/benchmarks/code_behind_layout/configs/tasks/development_components_20261019T012723Z/follower/task.json b/benchmarks/code_behind_layout/configs/tasks/development_components_20261019T012723Z/follower/task.json new file mode 100644 index 00000000..0baca952 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/tasks/development_components_20261019T012723Z/follower/task.json @@ -0,0 +1,1008 @@ +{ + "status": "DRAFT_REAL_SOURCE_AND_REFERENCES_NOT_FORMAL", + "task_id": "draft_follower_source_quality", + "parent_lineage": "glayout_fvf", + "source_revision": "d092211d7996c99159402451bc7141931d6a93c3", + "E1_stratum": "reuse", + "source_pack": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/follower/source_pack", + "editable_paths": [ + "glayout/cells/elementary/FVF/fvf.py" + ], + "entrypoint": "generator.py", + "representation": "G2", + "evidence_origin": "/srv/code-behind-layout/results/derived/follower_two_size_domain_development.json", + "bench": { + "supply_V": 1.8, + "temperature_C": 27, + "corners": [ + "tt", + "ss", + "ff" + ], + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "gain": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "impedance": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": 0.75, + "end": 1.25, + "points": 11, + "scale": "linear" + }, + "transient": { + "kind": "transient", + "columns": 4, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + }, + "bias_current_A": 1e-05, + "nominal_input_V": 0.9, + "C_load_F": 1e-12, + "level_shift": "intrinsic; no unity DC-tracking specification" + }, + "natural_shortfall": { + "origin": "unmodified_real_generator_natural_measurement", + "description": "At W4.15/L2, TT bandwidth falls from 100.3049MHz prelayout to 92.1982MHz post-RC (about 8.1%). The FVF level shift is intrinsic: unity DC tracking is not the objective. Layout bandwidth degradation is a natural quality shortfall.", + "evidence_file": "results/derived/follower_two_size_domain_development.json", + "run_ids": [ + "phase0_20261019T004600334942Z_follower_characterization", + "phase0_20261019T004603565583Z_follower_characterization" + ], + "repairability_established": false, + "formal_or_training_use": false + }, + "immutable_sizing": "Per-configuration W/L/multiplicity and independent N(z) cannot be edited; the same source patch must serve the whole domain", + "source_dependency_group": "vendor_elementary_targets_shared_with_OTA_closures; not four newly qualified independent clusters", + "qualification": { + "generation_preflight": { + "unique_parameter_points_with_actual_GDS": 25, + "generation_attempts": 25, + "failed_generation_attempts": 0, + "current_snapshot_all_25_generated_in_one_run": true, + "raw_generation_records": [ + "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/follower/preflight_attempt_20261019T013048353435Z/generation/generation.json" + ], + "establishes_S2": false + }, + "full_domain_baseline": null, + "feasible_edit_witness": null, + "isolated_evaluator_adapter": null, + "model_context_tokens": { + "kind": "follower", + "input_tokens_with_complete_source": 6610, + "reserved_output_tokens": 1024, + "fits_8192": true, + "source_truncated": false, + "PDK_rules_truncated": false + }, + "anchor_geometry_equivalence": { + "kind": "follower", + "new_gds": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/follower/preflight_attempt_20261019T013048353435Z/generation/anchor.gds", + "reference_gds": "/srv/code-behind-layout/runs/phase0/phase0_20261019T004600334942Z_follower_characterization/follower4.gds", + "units_m": 1e-06, + "precision_m": 1e-09, + "changed_layers": [], + "filled_geometry_equal": true, + "all_labels_equal": true, + "cell_names_excluded": true, + "physical_measurements_rerun": false + } + }, + "formal_admission": false, + "formal_trials": 0, + "training_examples": 0, + "main_benchmark_frozen": false, + "visible_configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "width": 4.15, + "length": 2.0 + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/follower/references/anchor.spice", + "reference_id": "independent_follower_anchor", + "contract": { + "task_id": "draft_follower_source_quality", + "configuration_id": "anchor", + "reference_id": "independent_follower_anchor", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "voltage_gain_10Hz", + "unit": "1", + "min": 0.8, + "max": 1.05 + }, + { + "name": "output_impedance_10Hz", + "unit": "ohm", + "max": 100.0 + } + ], + "objective": { + "id": "follower_bandwidth_max", + "metric": "bandwidth", + "unit": "Hz", + "direction": "max", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "gain": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "impedance": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": 0.75, + "end": 1.25, + "points": 11, + "scale": "linear" + }, + "transient": { + "kind": "transient", + "columns": 4, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + } + }, + "physical_result": null + }, + { + "configuration_id": "dev_01", + "role": "development", + "parameters": { + "width": 4.0, + "length": 2.0 + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/follower/references/dev_01.spice", + "reference_id": "independent_follower_dev_01", + "contract": { + "task_id": "draft_follower_source_quality", + "configuration_id": "dev_01", + "reference_id": "independent_follower_dev_01", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "voltage_gain_10Hz", + "unit": "1", + "min": 0.8, + "max": 1.05 + }, + { + "name": "output_impedance_10Hz", + "unit": "ohm", + "max": 100.0 + } + ], + "objective": { + "id": "follower_bandwidth_max", + "metric": "bandwidth", + "unit": "Hz", + "direction": "max", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "gain": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "impedance": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": 0.75, + "end": 1.25, + "points": 11, + "scale": "linear" + }, + "transient": { + "kind": "transient", + "columns": 4, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + } + }, + "physical_result": null + }, + { + "configuration_id": "dev_02", + "role": "development", + "parameters": { + "width": 3.35, + "length": 2.0 + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/follower/references/dev_02.spice", + "reference_id": "independent_follower_dev_02", + "contract": { + "task_id": "draft_follower_source_quality", + "configuration_id": "dev_02", + "reference_id": "independent_follower_dev_02", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "voltage_gain_10Hz", + "unit": "1", + "min": 0.8, + "max": 1.05 + }, + { + "name": "output_impedance_10Hz", + "unit": "ohm", + "max": 100.0 + } + ], + "objective": { + "id": "follower_bandwidth_max", + "metric": "bandwidth", + "unit": "Hz", + "direction": "max", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "gain": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "impedance": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": 0.75, + "end": 1.25, + "points": 11, + "scale": "linear" + }, + "transient": { + "kind": "transient", + "columns": 4, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + } + }, + "physical_result": null + }, + { + "configuration_id": "dev_03", + "role": "development", + "parameters": { + "width": 4.05, + "length": 2.0 + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/follower/references/dev_03.spice", + "reference_id": "independent_follower_dev_03", + "contract": { + "task_id": "draft_follower_source_quality", + "configuration_id": "dev_03", + "reference_id": "independent_follower_dev_03", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "voltage_gain_10Hz", + "unit": "1", + "min": 0.8, + "max": 1.05 + }, + { + "name": "output_impedance_10Hz", + "unit": "ohm", + "max": 100.0 + } + ], + "objective": { + "id": "follower_bandwidth_max", + "metric": "bandwidth", + "unit": "Hz", + "direction": "max", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "gain": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "impedance": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": 0.75, + "end": 1.25, + "points": 11, + "scale": "linear" + }, + "transient": { + "kind": "transient", + "columns": 4, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + } + }, + "physical_result": null + }, + { + "configuration_id": "dev_04", + "role": "development", + "parameters": { + "width": 3.65, + "length": 2.0 + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/follower/references/dev_04.spice", + "reference_id": "independent_follower_dev_04", + "contract": { + "task_id": "draft_follower_source_quality", + "configuration_id": "dev_04", + "reference_id": "independent_follower_dev_04", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "voltage_gain_10Hz", + "unit": "1", + "min": 0.8, + "max": 1.05 + }, + { + "name": "output_impedance_10Hz", + "unit": "ohm", + "max": 100.0 + } + ], + "objective": { + "id": "follower_bandwidth_max", + "metric": "bandwidth", + "unit": "Hz", + "direction": "max", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "gain": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "impedance": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": 0.75, + "end": 1.25, + "points": 11, + "scale": "linear" + }, + "transient": { + "kind": "transient", + "columns": 4, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + } + }, + "physical_result": null + }, + { + "configuration_id": "dev_05", + "role": "development", + "parameters": { + "width": 3.55, + "length": 2.0 + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/follower/references/dev_05.spice", + "reference_id": "independent_follower_dev_05", + "contract": { + "task_id": "draft_follower_source_quality", + "configuration_id": "dev_05", + "reference_id": "independent_follower_dev_05", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "voltage_gain_10Hz", + "unit": "1", + "min": 0.8, + "max": 1.05 + }, + { + "name": "output_impedance_10Hz", + "unit": "ohm", + "max": 100.0 + } + ], + "objective": { + "id": "follower_bandwidth_max", + "metric": "bandwidth", + "unit": "Hz", + "direction": "max", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "gain": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "impedance": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": 0.75, + "end": 1.25, + "points": 11, + "scale": "linear" + }, + "transient": { + "kind": "transient", + "columns": 4, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + } + }, + "physical_result": null + }, + { + "configuration_id": "dev_06", + "role": "development", + "parameters": { + "width": 3.45, + "length": 2.0 + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/follower/references/dev_06.spice", + "reference_id": "independent_follower_dev_06", + "contract": { + "task_id": "draft_follower_source_quality", + "configuration_id": "dev_06", + "reference_id": "independent_follower_dev_06", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "voltage_gain_10Hz", + "unit": "1", + "min": 0.8, + "max": 1.05 + }, + { + "name": "output_impedance_10Hz", + "unit": "ohm", + "max": 100.0 + } + ], + "objective": { + "id": "follower_bandwidth_max", + "metric": "bandwidth", + "unit": "Hz", + "direction": "max", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "gain": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "impedance": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": 0.75, + "end": 1.25, + "points": 11, + "scale": "linear" + }, + "transient": { + "kind": "transient", + "columns": 4, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + } + }, + "physical_result": null + }, + { + "configuration_id": "dev_07", + "role": "development", + "parameters": { + "width": 4.1, + "length": 2.0 + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/follower/references/dev_07.spice", + "reference_id": "independent_follower_dev_07", + "contract": { + "task_id": "draft_follower_source_quality", + "configuration_id": "dev_07", + "reference_id": "independent_follower_dev_07", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "voltage_gain_10Hz", + "unit": "1", + "min": 0.8, + "max": 1.05 + }, + { + "name": "output_impedance_10Hz", + "unit": "ohm", + "max": 100.0 + } + ], + "objective": { + "id": "follower_bandwidth_max", + "metric": "bandwidth", + "unit": "Hz", + "direction": "max", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "gain": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "impedance": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": 0.75, + "end": 1.25, + "points": 11, + "scale": "linear" + }, + "transient": { + "kind": "transient", + "columns": 4, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + } + }, + "physical_result": null + }, + { + "configuration_id": "dev_08", + "role": "development", + "parameters": { + "width": 3.6, + "length": 2.0 + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/follower/references/dev_08.spice", + "reference_id": "independent_follower_dev_08", + "contract": { + "task_id": "draft_follower_source_quality", + "configuration_id": "dev_08", + "reference_id": "independent_follower_dev_08", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "voltage_gain_10Hz", + "unit": "1", + "min": 0.8, + "max": 1.05 + }, + { + "name": "output_impedance_10Hz", + "unit": "ohm", + "max": 100.0 + } + ], + "objective": { + "id": "follower_bandwidth_max", + "metric": "bandwidth", + "unit": "Hz", + "direction": "max", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "gain": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "impedance": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": 0.75, + "end": 1.25, + "points": 11, + "scale": "linear" + }, + "transient": { + "kind": "transient", + "columns": 4, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + } + }, + "physical_result": null + } + ], + "hidden_configuration_count": 16, + "source_snapshot": { + "glayout/cells/elementary/FVF/fvf.py": "from glayout.pdk.mappedpdk import MappedPDK\nfrom glayout.pdk.sky130_mapped import sky130_mapped_pdk\nfrom gdsfactory.cell import cell\nfrom gdsfactory.component import Component\nfrom gdsfactory import Component\nfrom glayout.primitives.fet import nmos, pmos, multiplier\nfrom glayout.util.comp_utils import evaluate_bbox, prec_center, prec_ref_center, align_comp_to_port\nfrom glayout.util.snap_to_grid import component_snap_to_grid\nfrom glayout.util.port_utils import rename_ports_by_orientation\nfrom glayout.routing.straight_route import straight_route\nfrom glayout.routing.c_route import c_route\nfrom glayout.routing.L_route import L_route\nfrom glayout.primitives.guardring import tapring\nfrom glayout.util.port_utils import add_ports_perimeter\nfrom glayout.spice.netlist import Netlist\nfrom glayout.primitives.via_gen import via_stack\nfrom gdsfactory.components import text_freetype, rectangle\nfrom glayout.provenance import tracked_generator\ntry:\n from glayout.verification.evaluator_wrapper import run_evaluation\nexcept ImportError:\n print(\"Warning: evaluator_wrapper not found. Evaluation will be skipped.\")\n run_evaluation = None\n\ndef get_component_netlist(component):\n \"\"\"Helper function to get netlist object from component info, compatible with all gdsfactory versions\"\"\"\n from glayout.spice.netlist import Netlist\n \n # Try to get stored object first (for older gdsfactory versions)\n if 'netlist_obj' in component.info:\n return component.info['netlist_obj']\n \n # Try to reconstruct from netlist_data (for newer gdsfactory versions)\n if 'netlist_data' in component.info:\n data = component.info['netlist_data']\n netlist = Netlist(\n circuit_name=data['circuit_name'],\n nodes=data['nodes']\n )\n netlist.source_netlist = data['source_netlist']\n return netlist\n \n # Fallback: return the string representation (should not happen in normal operation)\n return component.info.get('netlist', '')\n\ndef fvf_netlist(fet_1: Component, fet_2: Component) -> Netlist:\n\n netlist = Netlist(circuit_name='FLIPPED_VOLTAGE_FOLLOWER', nodes=['VIN', 'VBULK', 'VOUT', 'Ib'])\n \n # Use helper function to get netlist objects regardless of gdsfactory version\n fet_1_netlist = get_component_netlist(fet_1)\n fet_2_netlist = get_component_netlist(fet_2)\n netlist.connect_netlist(fet_1_netlist, [('D', 'Ib'), ('G', 'VIN'), ('S', 'VOUT'), ('B', 'VBULK')])\n netlist.connect_netlist(fet_2_netlist, [('D', 'VOUT'), ('G', 'Ib'), ('S', 'VBULK'), ('B', 'VBULK')])\n\n return netlist\n\ndef add_fvf_labels(fvf_in: Component, pdk: MappedPDK) -> Component:\n \n fvf_in.unlock()\n move_info = list()\n label_pin_size = (0.27, 0.27)\n\n gnd2label = rectangle(layer=pdk.get_glayer(\"met1_pin\"),size=label_pin_size,centered=True).copy()\n gnd2label.add_label(text=\"VBULK\",layer=pdk.get_glayer(\"met1_label\"))\n move_info.append((gnd2label,fvf_in.ports[\"B_tie_N_top_met_N\"],None))\n \n ibiaslabel = rectangle(layer=pdk.get_glayer(\"met2_pin\"),size=label_pin_size,centered=True).copy()\n ibiaslabel.add_label(text=\"Ib\",layer=pdk.get_glayer(\"met2_label\"))\n move_info.append((ibiaslabel,fvf_in.ports[\"A_drain_bottom_met_N\"],None))\n \n outputlabel = rectangle(layer=pdk.get_glayer(\"met2_pin\"),size=label_pin_size,centered=True).copy()\n outputlabel.add_label(text=\"VOUT\",layer=pdk.get_glayer(\"met2_label\"))\n move_info.append((outputlabel,fvf_in.ports[\"A_source_bottom_met_N\"],None))\n \n inputlabel = rectangle(layer=pdk.get_glayer(\"met1_pin\"),size=label_pin_size,centered=True).copy()\n inputlabel.add_label(text=\"VIN\",layer=pdk.get_glayer(\"met1_label\"))\n move_info.append((inputlabel,fvf_in.ports[\"A_multiplier_0_gate_N\"], None))\n \n for comp, prt, alignment in move_info:\n alignment = ('c','b') if alignment is None else alignment\n compref = align_comp_to_port(comp, prt, alignment=alignment)\n fvf_in.add(compref)\n return fvf_in.flatten()\n\ndef sky130_add_fvf_labels(fvf_in: Component) -> Component:\n \n fvf_in.unlock()\n # define layers`\n met1_pin = (68,16)\n met1_label = (68,5)\n met2_pin = (69,16)\n met2_label = (69,5)\n # list that will contain all port/comp info\n move_info = list()\n # create labels and append to info list\n # gnd\n gnd2label = rectangle(layer=met1_pin,size=(0.5,0.5),centered=True).copy()\n gnd2label.add_label(text=\"VBULK\",layer=met1_label)\n move_info.append((gnd2label,fvf_in.ports[\"B_tie_N_top_met_N\"],None))\n \n #currentbias\n ibiaslabel = rectangle(layer=met2_pin,size=(0.5,0.5),centered=True).copy()\n ibiaslabel.add_label(text=\"Ib\",layer=met2_label)\n move_info.append((ibiaslabel,fvf_in.ports[\"A_drain_bottom_met_N\"],None))\n \n # output (3rd stage)\n outputlabel = rectangle(layer=met2_pin,size=(0.5,0.5),centered=True).copy()\n outputlabel.add_label(text=\"VOUT\",layer=met2_label)\n move_info.append((outputlabel,fvf_in.ports[\"A_source_bottom_met_N\"],None))\n \n # input\n inputlabel = rectangle(layer=met1_pin,size=(0.5,0.5),centered=True).copy()\n inputlabel.add_label(text=\"VIN\",layer=met1_label)\n move_info.append((inputlabel,fvf_in.ports[\"A_multiplier_0_gate_N\"], None))\n \n # move everything to position\n for comp, prt, alignment in move_info:\n alignment = ('c','b') if alignment is None else alignment\n compref = align_comp_to_port(comp, prt, alignment=alignment)\n fvf_in.add(compref)\n return fvf_in.flatten() \n\n@tracked_generator(\"flipped_voltage_follower\")\n@cell\ndef flipped_voltage_follower(\n pdk: MappedPDK,\n device_type: str = \"nmos\", \n placement: str = \"horizontal\",\n width: tuple[float,float] = (6.605703928526579, 3.713220935212418),\n length: tuple[float,float] = (2.3659471990041707, 1.9639325665440608),\n fingers: tuple[int,int] = (1, 1),\n multipliers: tuple[int,int] = (2, 2),\n dummy_1: tuple[bool,bool] = (True,True),\n dummy_2: tuple[bool,bool] = (True,True),\n tie_layers1: tuple[str,str] = (\"met2\",\"met1\"),\n tie_layers2: tuple[str,str] = (\"met2\",\"met1\"),\n sd_rmult: int=1,\n with_labels: bool = True,\n **kwargs\n ) -> Component:\n \"\"\"\n creates a Flipped Voltage Follower\n pdk: pdk to use\n device_type: either \"nmos\" or \"pmos\"\n placement: either \"horizontal\" or \"vertical\"\n width: (input fet, feedback fet)\n length: (input fet, feedback fet)\n fingers: (input fet, feedback fet)\n multipliers: (input fet, feedback fet)\n dummy_1: dummy for input fet\n dummy_2: dummy for feedback fet\n tie_layers1: tie layers for input fet\n tie_layers2: tie layers for feedback fet\n sd_rmult: sd_rmult for both fets\n with_labels: if true, add top-level LVS labels for standalone use\n **kwargs: any kwarg that is supported by nmos and pmos\n \"\"\"\n \n #top level component\n top_level = Component(name=\"flipped_voltage_follower\")\n\n #two fets\n device_map = {\n \"nmos\": nmos,\n \"pmos\": pmos,\n }\n device = device_map.get(device_type)\n\n if device_type == \"nmos\":\n kwargs[\"with_dnwell\"] = False # Set the parameter dynamically\n\n \n fet_1 = device(pdk, width=width[0], fingers=fingers[0], multipliers=multipliers[0], with_dummy=dummy_1, with_substrate_tap=False, length=length[0], tie_layers=tie_layers1, sd_rmult=sd_rmult, **kwargs)\n fet_2 = device(pdk, width=width[1], fingers=fingers[1], multipliers=multipliers[1], with_dummy=dummy_2, with_substrate_tap=False, length=length[1], tie_layers=tie_layers2, sd_rmult=sd_rmult, **kwargs)\n well = \"pwell\" if device == nmos else \"nwell\" \n fet_1_ref = top_level << fet_1\n fet_2_ref = top_level << fet_2 \n\n #Relative move\n ref_dimensions = evaluate_bbox(fet_2)\n if placement == \"horizontal\":\n fet_2_ref.movex(fet_1_ref.xmax + ref_dimensions[0]/2 + pdk.util_max_metal_seperation())\n if placement == \"vertical\":\n fet_2_ref.movey(fet_1_ref.ymin - ref_dimensions[1]/2 - pdk.util_max_metal_seperation()-1)\n \n #Routing\n viam2m3 = via_stack(pdk, \"met2\", \"met3\", centered=True)\n drain_1_via = top_level << viam2m3\n source_1_via = top_level << viam2m3\n drain_2_via = top_level << viam2m3\n gate_2_via = top_level << viam2m3\n drain_1_via.move(fet_1_ref.ports[\"multiplier_0_drain_W\"].center).movex(-0.5*evaluate_bbox(fet_1)[1])\n source_1_via.move(fet_1_ref.ports[\"multiplier_0_source_E\"].center).movex(1.5)\n drain_2_via.move(fet_2_ref.ports[\"multiplier_0_drain_W\"].center).movex(-1.6)\n gate_2_via.move(fet_2_ref.ports[\"multiplier_0_gate_E\"].center).movex(1.15)\n\n top_level << straight_route(pdk, fet_1_ref.ports[\"multiplier_0_source_E\"], source_1_via.ports[\"bottom_met_W\"])\n top_level << straight_route(pdk, fet_2_ref.ports[\"multiplier_0_drain_W\"], drain_2_via.ports[\"bottom_met_E\"])\n top_level << c_route(pdk, source_1_via.ports[\"top_met_N\"], drain_2_via.ports[\"top_met_N\"], extension=1.2*max(width[0],width[1]), e1glayer=\"met3\", e2glayer=\"met3\", cglayer=\"met2\", cwidth=0.4, viaoffset=False)\n top_level << straight_route(pdk, fet_1_ref.ports[\"multiplier_0_drain_W\"], drain_1_via.ports[\"bottom_met_E\"])\n top_level << c_route(pdk, drain_1_via.ports[\"top_met_S\"], gate_2_via.ports[\"top_met_S\"], extension=1.2*max(width[0],width[1]), cglayer=\"met2\", cwidth=0.4, viaoffset=False)\n top_level << straight_route(pdk, fet_2_ref.ports[\"multiplier_0_gate_E\"], gate_2_via.ports[\"bottom_met_W\"], fullbottom=True)\n try:\n top_level << straight_route(pdk, fet_2_ref.ports[\"multiplier_0_source_W\"], fet_2_ref.ports[\"tie_W_top_met_W\"], glayer1=tie_layers2[1], width=0.2*sd_rmult, fullbottom=True)\n except:\n pass\n #Renaming Ports\n top_level.add_ports(fet_1_ref.get_ports_list(), prefix=\"A_\")\n top_level.add_ports(fet_2_ref.get_ports_list(), prefix=\"B_\")\n top_level.add_ports(drain_1_via.get_ports_list(), prefix=\"A_drain_\")\n top_level.add_ports(source_1_via.get_ports_list(), prefix=\"A_source_\")\n top_level.add_ports(drain_2_via.get_ports_list(), prefix=\"B_drain_\")\n top_level.add_ports(gate_2_via.get_ports_list(), prefix=\"B_gate_\")\n #add nwell\n if well == \"nwell\": \n top_level.add_padding(layers=(pdk.get_glayer(\"nwell\"),),default= 1 )\n \n netlist_obj = fvf_netlist(fet_1, fet_2)\n component = component_snap_to_grid(rename_ports_by_orientation(top_level))\n if with_labels:\n component = add_fvf_labels(component, pdk)\n # Store netlist as string for LVS (avoids gymnasium info dict type restrictions)\n # Compatible with both gdsfactory 7.7.0 and 7.16.0+ strict Pydantic validation\n component.info['netlist'] = netlist_obj.generate_netlist()\n # Store the Netlist object for hierarchical netlist building (used by lvcm.py etc.)\n component.info['netlist_obj'] = netlist_obj\n # Store serialized netlist data for reconstruction if needed\n component.info['netlist_data'] = {\n 'circuit_name': netlist_obj.circuit_name,\n 'nodes': netlist_obj.nodes,\n 'source_netlist': netlist_obj.source_netlist\n }\n \n return component\n\nif __name__==\"__main__\":\n fvf = sky130_add_fvf_labels(flipped_voltage_follower(sky130_mapped_pdk, width=(2,1), sd_rmult=3))\n fvf.show()\n fvf.name = \"fvf\"\n fvf_gds = fvf.write_gds(\"fvf.gds\")\n result = run_evaluation(\"fvf.gds\",fvf.name,fvf)\n print(result)\n" + }, + "domain_shape": { + "anchor": 1, + "development": 8, + "hidden": 16 + }, + "source_role": "draft_task_materialization_not_a_new_lineage", + "pdk_revision": "0fe599b2afb6708d281543108caf8310912f54af", + "frozen_source_pack": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/follower/source_pack", + "frozen_source_files": [ + "component_build.py", + "generator.py", + "glayout/__init__.py", + "glayout/cells/__init__.py", + "glayout/cells/elementary/FVF/__init__.py", + "glayout/cells/elementary/__init__.py", + "glayout/pdk/__init__.py", + "glayout/pdk/gf180_mapped/__init__.py", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x02p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x04p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x08p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x16p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_05p00x05p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_10p00x10p00.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_05p00x00p42.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_05p00x05p00.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_10p00x00p42.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_10p00x10p00.gds", + "glayout/pdk/gf180_mapped/gf180_grules.py", + "glayout/pdk/gf180_mapped/gf180_mapped.py", + "glayout/pdk/gf180_mapped/gf180mcu.drc", + "glayout/pdk/gf180_mapped/gf180mcu_drc.lydrc", + "glayout/pdk/gf180_mapped/gf180mcu_osu_sc_9T.spice", + "glayout/pdk/ihp130_mapped/__init__.py", + "glayout/pdk/ihp130_mapped/ihp130_drc.lydrc", + "glayout/pdk/ihp130_mapped/ihp130_grules.py", + "glayout/pdk/ihp130_mapped/ihp130_mapped.py", + "glayout/pdk/mappedpdk.py", + "glayout/pdk/sky130_mapped/__init__.py", + "glayout/pdk/sky130_mapped/sky130.lydrc", + "glayout/pdk/sky130_mapped/sky130_add_npc.py", + "glayout/pdk/sky130_mapped/sky130_fd_sc_hd.spice", + "glayout/pdk/sky130_mapped/sky130_grules.py", + "glayout/pdk/sky130_mapped/sky130_mapped.py", + "glayout/placement/__init__.py", + "glayout/placement/common_centroid_ab_ba.py", + "glayout/placement/four_transistor_interdigitized.py", + "glayout/placement/two_transistor_interdigitized.py", + "glayout/placement/two_transistor_place.py", + "glayout/primitives/__init__.py", + "glayout/primitives/bjt.py", + "glayout/primitives/fet.py", + "glayout/primitives/guardring.py", + "glayout/primitives/mimcap.py", + "glayout/primitives/resistor.py", + "glayout/primitives/via_gen.py", + "glayout/provenance/__init__.py", + "glayout/provenance/netlist_summary.py", + "glayout/provenance/runtime.py", + "glayout/routing/L_route.py", + "glayout/routing/__init__.py", + "glayout/routing/c_route.py", + "glayout/routing/smart_route.py", + "glayout/routing/straight_route.py", + "glayout/spice/__init__.py", + "glayout/spice/netlist.py", + "glayout/util/__init__.py", + "glayout/util/comp_utils.py", + "glayout/util/component_array_create.py", + "glayout/util/geometry.py", + "glayout/util/pattern.py", + "glayout/util/port_utils.py", + "glayout/util/print_rules.py", + "glayout/util/routing.py", + "glayout/util/snap_to_grid.py" + ] +} diff --git a/benchmarks/code_behind_layout/configs/tasks/development_components_20261019T012723Z/follower/task_packet.json b/benchmarks/code_behind_layout/configs/tasks/development_components_20261019T012723Z/follower/task_packet.json new file mode 100644 index 00000000..2635f653 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/tasks/development_components_20261019T012723Z/follower/task_packet.json @@ -0,0 +1,443 @@ +{ + "task_id": "draft_follower_source_quality", + "goal": "Improve the declared worst-corner post-RC objective by one shared source edit while preserving the independent circuit, full-rule DRC, LVS, all analysis coverage and every declared constraint. This is an unfrozen development task; layout edits cannot change circuit sizing or dummy count.", + "contract": { + "task_id": "draft_follower_source_quality", + "configuration_id": "anchor", + "reference_id": "independent_follower_anchor", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "voltage_gain_10Hz", + "unit": "1", + "min": 0.8, + "max": 1.05 + }, + { + "name": "output_impedance_10Hz", + "unit": "ohm", + "max": 100.0 + } + ], + "objective": { + "id": "follower_bandwidth_max", + "metric": "bandwidth", + "unit": "Hz", + "direction": "max", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "gain": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "impedance": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "dc": { + "kind": "dc", + "columns": 5, + "start": 0.75, + "end": 1.25, + "points": 11, + "scale": "linear" + }, + "transient": { + "kind": "transient", + "columns": 4, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + } + }, + "allowed_paths": [ + "glayout/cells/elementary/FVF/fvf.py" + ], + "visible_sources": { + "glayout/cells/elementary/FVF/fvf.py": "Use read_source for the complete current module" + }, + "documents": { + "configurations": [ + { + "configuration_id": "anchor", + "parameters": { + "width": 4.15, + "length": 2.0 + }, + "reference_id": "independent_follower_anchor" + }, + { + "configuration_id": "dev_01", + "parameters": { + "width": 4.0, + "length": 2.0 + }, + "reference_id": "independent_follower_dev_01" + }, + { + "configuration_id": "dev_02", + "parameters": { + "width": 3.35, + "length": 2.0 + }, + "reference_id": "independent_follower_dev_02" + }, + { + "configuration_id": "dev_03", + "parameters": { + "width": 4.05, + "length": 2.0 + }, + "reference_id": "independent_follower_dev_03" + }, + { + "configuration_id": "dev_04", + "parameters": { + "width": 3.65, + "length": 2.0 + }, + "reference_id": "independent_follower_dev_04" + }, + { + "configuration_id": "dev_05", + "parameters": { + "width": 3.55, + "length": 2.0 + }, + "reference_id": "independent_follower_dev_05" + }, + { + "configuration_id": "dev_06", + "parameters": { + "width": 3.45, + "length": 2.0 + }, + "reference_id": "independent_follower_dev_06" + }, + { + "configuration_id": "dev_07", + "parameters": { + "width": 4.1, + "length": 2.0 + }, + "reference_id": "independent_follower_dev_07" + }, + { + "configuration_id": "dev_08", + "parameters": { + "width": 3.6, + "length": 2.0 + }, + "reference_id": "independent_follower_dev_08" + } + ], + "bench": { + "supply_V": 1.8, + "temperature_C": 27, + "corners": [ + "tt", + "ss", + "ff" + ], + "bias_current_A": 1e-05, + "nominal_input_V": 0.9, + "C_load_F": 1e-12, + "level_shift": "intrinsic; no unity DC-tracking specification" + }, + "API": "Complete editable module is provided by read_source. Its exact imported common PDK/MOS/via/placement/routing/util/SPICE libraries and fixed marker/export wrapper are frozen; sibling target cells, complete OTAs, training compiler, trusted evaluator and hidden tables are absent. Import signatures match the existing module. Only ordinary unified source-content diffs are accepted.", + "circuit": "* Independent intended circuit; physical per-finger width retained\n.subckt follower4 VIN VBULK VOUT IB\nXINPUT IB VIN VOUT VBULK sky130_fd_pr__nfet_01v8 w=4.15 l=2 m=2\nXSHUNT VOUT IB VBULK VBULK sky130_fd_pr__nfet_01v8 w=4.15 l=2 m=2\nXDUMMY VBULK VBULK VBULK VBULK sky130_fd_pr__nfet_01v8 w=4.15 l=2 m=4\n.ends follower4\n", + "natural_shortfall": "At W4.15/L2, TT bandwidth falls from 100.3049MHz prelayout to 92.1982MHz post-RC (about 8.1%). The FVF level shift is intrinsic: unity DC tracking is not the objective. Layout bandwidth degradation is a natural quality shortfall.", + "PDK": { + "layers": { + "capmet": "capm", + "met5": "met4", + "via4": "via3", + "met4": "met3", + "via3": "via2", + "met3": "met2", + "via2": "via", + "met2": "met1", + "via1": "mcon", + "met1": "li1", + "mcon": "licon1", + "poly": "poly", + "active_diff": "diff", + "active_tap": "diff", + "n+s/d": "nsdm", + "p+s/d": "psdm", + "nwell": "nwell", + "pwell": [ + 64, + 44 + ], + "dnwell": "dnwell", + "met5_pin": "met4_pin", + "met4_pin": "met3_pin", + "met3_pin": "met2_pin", + "met2_pin": "met1_pin", + "met1_pin": "li1_pin", + "poly_pin": "poly_pin", + "active_diff_pin": "diff_pin", + "met5_label": "met4_label", + "met4_label": "met3_label", + "met3_label": "met2_label", + "met2_label": "met1_label", + "met1_label": "li1_label", + "poly_label": "poly_label", + "active_diff_label": "diff_label" + }, + "rules": { + "dnwell": { + "dnwell": { + "min_width": 3.0, + "min_separation": 6.3 + }, + "pwell": { + "min_enclosure": 0.0 + }, + "nwell": { + "min_separation": 4.5 + }, + "active_tap": { + "min_separation": 0.34 + } + }, + "pwell": { + "active_tap": { + "min_enclosure": 0.18 + } + }, + "nwell": { + "nwell": { + "min_width": 0.84, + "min_separation": 1.27 + }, + "active_tap": { + "min_enclosure": 0.18 + } + }, + "p+s/d": { + "p+s/d": { + "min_width": 0.38, + "min_separation": 0.38 + }, + "active_diff": { + "min_enclosure": 0.13, + "min_separation": 0.13 + }, + "active_tap": { + "min_enclosure": 0.13, + "min_separation": 0.13 + } + }, + "n+s/d": { + "n+s/d": { + "min_width": 0.38, + "min_separation": 0.38 + }, + "active_diff": { + "min_enclosure": 0.13, + "min_separation": 0.13 + }, + "active_tap": { + "min_enclosure": 0.13, + "min_separation": 0.13 + } + }, + "active_diff": { + "active_diff": { + "min_width": 0.15, + "min_separation": 0.27 + }, + "active_tap": { + "min_separation": 0.27 + }, + "poly": { + "overhang": 0.25 + }, + "mcon": { + "min_enclosure": 0.06 + } + }, + "active_tap": { + "active_tap": { + "min_width": 0.15, + "min_separation": 0.27 + }, + "mcon": { + "min_enclosure": 0.12 + } + }, + "poly": { + "poly": { + "min_width": 0.15, + "min_separation": 0.21, + "extension": 0.13 + }, + "mcon": { + "min_enclosure": 0.05, + "min_separation": 0.06 + } + }, + "mcon": { + "poly": { + "min_enclosure": 0.08 + }, + "mcon": { + "min_width": 0.17, + "min_separation": 0.17, + "width": 0.17 + }, + "met1": { + "min_enclosure": 0.08 + } + }, + "met1": { + "met1": { + "min_width": 0.17, + "min_separation": 0.17 + }, + "via1": { + "min_enclosure": 0.0 + } + }, + "via1": { + "via1": { + "min_width": 0.17, + "min_separation": 0.19, + "width": 0.17 + }, + "met2": { + "min_enclosure": 0.06 + } + }, + "met2": { + "met2": { + "min_width": 0.14, + "min_separation": 0.14 + }, + "via2": { + "min_enclosure": 0.14 + } + }, + "via2": { + "via2": { + "min_width": 0.21, + "min_separation": 0.17, + "width": 0.15 + }, + "met3": { + "min_enclosure": 0.09 + } + }, + "met3": { + "met3": { + "min_width": 0.14, + "min_separation": 0.28 + }, + "via3": { + "min_enclosure": 0.19 + } + }, + "via3": { + "via3": { + "min_width": 0.2, + "min_separation": 0.2, + "width": 0.2 + }, + "met4": { + "min_enclosure": 0.65 + } + }, + "met4": { + "met4": { + "min_width": 0.3, + "min_separation": 0.4 + }, + "via4": { + "min_enclosure": 0.09 + }, + "capmet": { + "min_enclosure": 0.14, + "min_separation": 1.34 + } + }, + "via4": { + "via4": { + "width": 0.2, + "min_separation": 0.35 + }, + "met5": { + "min_enclosure": 0.07 + } + }, + "met5": { + "met5": { + "min_width": 0.3, + "min_separation": 0.4 + } + }, + "capmet": { + "capmet": { + "capmettop": [ + 71, + 20 + ], + "capmetbottom": [ + 70, + 20 + ], + "min_separation": 1.2 + } + } + } + } + }, + "visible_configurations": [ + "anchor", + "dev_01", + "dev_02", + "dev_03", + "dev_04", + "dev_05", + "dev_06", + "dev_07", + "dev_08" + ], + "budget": { + "decisions": 10, + "physical_evaluations": 9, + "context_tokens": 8192, + "reserved_output_tokens": 1024, + "status": "DRAFT_BUDGET_REQUIRES_PILOT" + } +} diff --git a/benchmarks/code_behind_layout/configs/tasks/development_components_20261019T012723Z/mirror/task.json b/benchmarks/code_behind_layout/configs/tasks/development_components_20261019T012723Z/mirror/task.json new file mode 100644 index 00000000..c1748a39 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/tasks/development_components_20261019T012723Z/mirror/task.json @@ -0,0 +1,778 @@ +{ + "status": "DRAFT_REAL_SOURCE_AND_REFERENCES_NOT_FORMAL", + "task_id": "draft_mirror_source_quality", + "parent_lineage": "glayout_mirror", + "source_revision": "d092211d7996c99159402451bc7141931d6a93c3", + "E1_stratum": "reuse", + "source_pack": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/mirror/source_pack", + "editable_paths": [ + "glayout/cells/elementary/current_mirror/current_mirror.py" + ], + "entrypoint": "generator.py", + "representation": "G2", + "evidence_origin": "/srv/code-behind-layout/results/derived/mirror_domain_development.json", + "bench": { + "supply_V": 1.8, + "temperature_C": 27, + "corners": [ + "tt", + "ss", + "ff" + ], + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 5, + "expected_rows": 1 + }, + "compliance": { + "kind": "dc", + "columns": 5, + "start": 0.05, + "end": 1.75, + "points": 69, + "scale": "linear" + }, + "input_gain": { + "kind": "dc", + "columns": 5, + "start": 2e-06, + "end": 2e-05, + "points": 10, + "scale": "linear" + } + }, + "reference_current_A": 1e-05, + "nominal_output_V": 0.9, + "metrics_from": "steady DC row and central derivative; OP is health evidence" + }, + "natural_shortfall": { + "origin": "unmodified_real_generator_natural_measurement", + "description": "The measured W1/L0.5 mirror has worst-corner 2.3439% nominal current error and 1.3285Mohm output resistance; the longer anchor is better. This is a natural quality shortfall, not proof a source-only edit can remove the intrinsic device contribution.", + "evidence_file": "results/derived/mirror_domain_development.json", + "run_ids": [ + "phase0_20261018T234522533497Z_mirror_characterization", + "phase0_20261018T234525811276Z_mirror_characterization", + "phase0_20261018T234528733338Z_mirror_characterization" + ], + "repairability_established": false, + "formal_or_training_use": false + }, + "immutable_sizing": "Per-configuration W/L/multiplicity and independent N(z) cannot be edited; the same source patch must serve the whole domain", + "source_dependency_group": "vendor_elementary_targets_shared_with_OTA_closures; not four newly qualified independent clusters", + "qualification": { + "generation_preflight": { + "unique_parameter_points_with_actual_GDS": 25, + "generation_attempts": 26, + "failed_generation_attempts": 1, + "current_snapshot_all_25_generated_in_one_run": false, + "raw_generation_records": [ + "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/mirror/preflight_attempt_20261019T012813579668Z/generation/generation.json", + "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/mirror/preflight_attempt_20261019T013509598629Z/generation/generation.json" + ], + "establishes_S2": false + }, + "full_domain_baseline": null, + "feasible_edit_witness": null, + "isolated_evaluator_adapter": null, + "model_context_tokens": { + "kind": "mirror", + "input_tokens_with_complete_source": 6173, + "reserved_output_tokens": 1024, + "fits_8192": true, + "source_truncated": false, + "PDK_rules_truncated": false + }, + "anchor_geometry_equivalence": { + "kind": "mirror", + "new_gds": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/mirror/preflight_attempt_20261019T013509598629Z/generation/anchor.gds", + "reference_gds": "/srv/code-behind-layout/runs/phase0/phase0_20261018T234522533497Z_mirror_characterization/mirror4.gds", + "units_m": 1e-06, + "precision_m": 1e-09, + "changed_layers": [], + "filled_geometry_equal": true, + "all_labels_equal": true, + "cell_names_excluded": true, + "physical_measurements_rerun": false + } + }, + "formal_admission": false, + "formal_trials": 0, + "training_examples": 0, + "main_benchmark_frozen": false, + "visible_configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "width": 1.88, + "length": 3.0, + "numcols": 2, + "device": "pfet" + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/mirror/references/anchor.spice", + "reference_id": "independent_mirror_anchor", + "contract": { + "task_id": "draft_mirror_source_quality", + "configuration_id": "anchor", + "reference_id": "independent_mirror_anchor", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "absolute_current_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 1000000.0 + } + ], + "objective": { + "id": "mirror_error_min", + "metric": "absolute_current_error", + "unit": "1", + "direction": "min", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 5, + "expected_rows": 1 + }, + "compliance": { + "kind": "dc", + "columns": 5, + "start": 0.05, + "end": 1.75, + "points": 69, + "scale": "linear" + }, + "input_gain": { + "kind": "dc", + "columns": 5, + "start": 2e-06, + "end": 2e-05, + "points": 10, + "scale": "linear" + } + } + }, + "physical_result": null + }, + { + "configuration_id": "dev_01", + "role": "development", + "parameters": { + "width": 1.5, + "length": 3.0, + "numcols": 2, + "device": "pfet" + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/mirror/references/dev_01.spice", + "reference_id": "independent_mirror_dev_01", + "contract": { + "task_id": "draft_mirror_source_quality", + "configuration_id": "dev_01", + "reference_id": "independent_mirror_dev_01", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "absolute_current_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 1000000.0 + } + ], + "objective": { + "id": "mirror_error_min", + "metric": "absolute_current_error", + "unit": "1", + "direction": "min", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 5, + "expected_rows": 1 + }, + "compliance": { + "kind": "dc", + "columns": 5, + "start": 0.05, + "end": 1.75, + "points": 69, + "scale": "linear" + }, + "input_gain": { + "kind": "dc", + "columns": 5, + "start": 2e-06, + "end": 2e-05, + "points": 10, + "scale": "linear" + } + } + }, + "physical_result": null + }, + { + "configuration_id": "dev_02", + "role": "development", + "parameters": { + "width": 1.5, + "length": 0.5, + "numcols": 2, + "device": "pfet" + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/mirror/references/dev_02.spice", + "reference_id": "independent_mirror_dev_02", + "contract": { + "task_id": "draft_mirror_source_quality", + "configuration_id": "dev_02", + "reference_id": "independent_mirror_dev_02", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "absolute_current_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 1000000.0 + } + ], + "objective": { + "id": "mirror_error_min", + "metric": "absolute_current_error", + "unit": "1", + "direction": "min", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 5, + "expected_rows": 1 + }, + "compliance": { + "kind": "dc", + "columns": 5, + "start": 0.05, + "end": 1.75, + "points": 69, + "scale": "linear" + }, + "input_gain": { + "kind": "dc", + "columns": 5, + "start": 2e-06, + "end": 2e-05, + "points": 10, + "scale": "linear" + } + } + }, + "physical_result": null + }, + { + "configuration_id": "dev_03", + "role": "development", + "parameters": { + "width": 1.88, + "length": 1.0, + "numcols": 2, + "device": "pfet" + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/mirror/references/dev_03.spice", + "reference_id": "independent_mirror_dev_03", + "contract": { + "task_id": "draft_mirror_source_quality", + "configuration_id": "dev_03", + "reference_id": "independent_mirror_dev_03", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "absolute_current_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 1000000.0 + } + ], + "objective": { + "id": "mirror_error_min", + "metric": "absolute_current_error", + "unit": "1", + "direction": "min", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 5, + "expected_rows": 1 + }, + "compliance": { + "kind": "dc", + "columns": 5, + "start": 0.05, + "end": 1.75, + "points": 69, + "scale": "linear" + }, + "input_gain": { + "kind": "dc", + "columns": 5, + "start": 2e-06, + "end": 2e-05, + "points": 10, + "scale": "linear" + } + } + }, + "physical_result": null + }, + { + "configuration_id": "dev_04", + "role": "development", + "parameters": { + "width": 1.88, + "length": 0.5, + "numcols": 2, + "device": "pfet" + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/mirror/references/dev_04.spice", + "reference_id": "independent_mirror_dev_04", + "contract": { + "task_id": "draft_mirror_source_quality", + "configuration_id": "dev_04", + "reference_id": "independent_mirror_dev_04", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "absolute_current_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 1000000.0 + } + ], + "objective": { + "id": "mirror_error_min", + "metric": "absolute_current_error", + "unit": "1", + "direction": "min", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 5, + "expected_rows": 1 + }, + "compliance": { + "kind": "dc", + "columns": 5, + "start": 0.05, + "end": 1.75, + "points": 69, + "scale": "linear" + }, + "input_gain": { + "kind": "dc", + "columns": 5, + "start": 2e-06, + "end": 2e-05, + "points": 10, + "scale": "linear" + } + } + }, + "physical_result": null + }, + { + "configuration_id": "dev_05", + "role": "development", + "parameters": { + "width": 2.5, + "length": 2.0, + "numcols": 2, + "device": "pfet" + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/mirror/references/dev_05.spice", + "reference_id": "independent_mirror_dev_05", + "contract": { + "task_id": "draft_mirror_source_quality", + "configuration_id": "dev_05", + "reference_id": "independent_mirror_dev_05", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "absolute_current_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 1000000.0 + } + ], + "objective": { + "id": "mirror_error_min", + "metric": "absolute_current_error", + "unit": "1", + "direction": "min", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 5, + "expected_rows": 1 + }, + "compliance": { + "kind": "dc", + "columns": 5, + "start": 0.05, + "end": 1.75, + "points": 69, + "scale": "linear" + }, + "input_gain": { + "kind": "dc", + "columns": 5, + "start": 2e-06, + "end": 2e-05, + "points": 10, + "scale": "linear" + } + } + }, + "physical_result": null + }, + { + "configuration_id": "dev_06", + "role": "development", + "parameters": { + "width": 1.88, + "length": 1.5, + "numcols": 2, + "device": "pfet" + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/mirror/references/dev_06.spice", + "reference_id": "independent_mirror_dev_06", + "contract": { + "task_id": "draft_mirror_source_quality", + "configuration_id": "dev_06", + "reference_id": "independent_mirror_dev_06", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "absolute_current_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 1000000.0 + } + ], + "objective": { + "id": "mirror_error_min", + "metric": "absolute_current_error", + "unit": "1", + "direction": "min", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 5, + "expected_rows": 1 + }, + "compliance": { + "kind": "dc", + "columns": 5, + "start": 0.05, + "end": 1.75, + "points": 69, + "scale": "linear" + }, + "input_gain": { + "kind": "dc", + "columns": 5, + "start": 2e-06, + "end": 2e-05, + "points": 10, + "scale": "linear" + } + } + }, + "physical_result": null + }, + { + "configuration_id": "dev_07", + "role": "development", + "parameters": { + "width": 2.5, + "length": 0.5, + "numcols": 2, + "device": "pfet" + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/mirror/references/dev_07.spice", + "reference_id": "independent_mirror_dev_07", + "contract": { + "task_id": "draft_mirror_source_quality", + "configuration_id": "dev_07", + "reference_id": "independent_mirror_dev_07", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "absolute_current_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 1000000.0 + } + ], + "objective": { + "id": "mirror_error_min", + "metric": "absolute_current_error", + "unit": "1", + "direction": "min", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 5, + "expected_rows": 1 + }, + "compliance": { + "kind": "dc", + "columns": 5, + "start": 0.05, + "end": 1.75, + "points": 69, + "scale": "linear" + }, + "input_gain": { + "kind": "dc", + "columns": 5, + "start": 2e-06, + "end": 2e-05, + "points": 10, + "scale": "linear" + } + } + }, + "physical_result": null + }, + { + "configuration_id": "dev_08", + "role": "development", + "parameters": { + "width": 3.0, + "length": 2.0, + "numcols": 2, + "device": "pfet" + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/mirror/references/dev_08.spice", + "reference_id": "independent_mirror_dev_08", + "contract": { + "task_id": "draft_mirror_source_quality", + "configuration_id": "dev_08", + "reference_id": "independent_mirror_dev_08", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "absolute_current_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 1000000.0 + } + ], + "objective": { + "id": "mirror_error_min", + "metric": "absolute_current_error", + "unit": "1", + "direction": "min", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 5, + "expected_rows": 1 + }, + "compliance": { + "kind": "dc", + "columns": 5, + "start": 0.05, + "end": 1.75, + "points": 69, + "scale": "linear" + }, + "input_gain": { + "kind": "dc", + "columns": 5, + "start": 2e-06, + "end": 2e-05, + "points": 10, + "scale": "linear" + } + } + }, + "physical_result": null + } + ], + "hidden_configuration_count": 16, + "source_snapshot": { + "glayout/cells/elementary/current_mirror/current_mirror.py": "from glayout.placement.two_transistor_interdigitized import two_nfet_interdigitized, two_pfet_interdigitized, two_tran_interdigitized_netlist\nfrom glayout.pdk.mappedpdk import MappedPDK\nfrom glayout.routing.c_route import c_route\nfrom glayout.routing.L_route import L_route\nfrom glayout.routing.straight_route import straight_route\nfrom glayout.spice.netlist import Netlist\nfrom glayout.primitives.fet import nmos, pmos\nfrom glayout.primitives.guardring import tapring\nfrom glayout.util.port_utils import add_ports_perimeter,rename_ports_by_orientation\nfrom gdsfactory.component import Component\nfrom gdsfactory.cell import cell\nfrom glayout.util.comp_utils import evaluate_bbox, prec_center, prec_ref_center, align_comp_to_port\nfrom glayout.util.snap_to_grid import component_snap_to_grid\nfrom typing import Optional, Union \nfrom glayout.primitives.via_gen import via_stack\nfrom gdsfactory.components import text_freetype, rectangle\nfrom glayout.pdk.sky130_mapped import sky130_mapped_pdk\nfrom glayout.provenance import tracked_generator\ntry:\n from glayout.verification.evaluator_wrapper import run_evaluation\nexcept ImportError:\n print(\"Warning: evaluator_wrapper not found. Evaluation will be skipped.\")\n run_evaluation = None\n\n\ndef add_cm_labels(cm_in: Component,\n pdk: MappedPDK \n ) -> Component:\n\t\n cm_in.unlock()\n met2_pin = (68,16)\n met2_label = (68,5)\n\n # list that will contain all port/comp info\n move_info = list()\n # create labels and append to info list\n # vss\n vsslabel = rectangle(layer=pdk.get_glayer(\"met2_pin\"),size=(0.27,0.27),centered=True).copy()\n vsslabel.add_label(text=\"VSS\",layer=pdk.get_glayer(\"met2_label\"))\n move_info.append((vsslabel,cm_in.ports[\"fet_A_source_E\"],None))\n \n # vref\n vreflabel = rectangle(layer=pdk.get_glayer(\"met2_pin\"),size=(0.27,0.27),centered=True).copy()\n vreflabel.add_label(text=\"VREF\",layer=pdk.get_glayer(\"met2_label\"))\n move_info.append((vreflabel,cm_in.ports[\"fet_A_drain_N\"],None))\n \n # vcopy\n vcopylabel = rectangle(layer=pdk.get_glayer(\"met2_pin\"),size=(0.27,0.27),centered=True).copy()\n vcopylabel.add_label(text=\"VOUT\",layer=pdk.get_glayer(\"met2_label\"))\n move_info.append((vcopylabel,cm_in.ports[\"fet_B_drain_N\"],None))\n \n # VB\n vblabel = rectangle(layer=pdk.get_glayer(\"met2_pin\"),size=(0.5,0.5),centered=True).copy()\n vblabel.add_label(text=\"B\",layer=pdk.get_glayer(\"met2_label\"))\n move_info.append((vblabel,cm_in.ports[\"welltie_S_top_met_S\"], None))\n \n # move everything to position\n for comp, prt, alignment in move_info:\n alignment = ('c','b') if alignment is None else alignment\n compref = align_comp_to_port(comp, prt, alignment=alignment)\n cm_in.add(compref)\n return cm_in.flatten() \n\t\t\t\t\t\ndef current_mirror_interdigitized_netlist(\n pdk: MappedPDK,\n width: float,\n length: float,\n fingers: int,\n multipliers: int, \n with_dummy: bool = True,\n n_or_p_fet: Optional[str] = 'nfet',\n subckt_only: Optional[bool] = False\n) -> Netlist:\n \"\"\"\n Current mirror netlist built from a two-transistor interdigitized primitive\n \"\"\"\n\n current_mirror_netlist = Netlist(circuit_name=\"CMIRROR\", nodes=[\"VREF\", \"VOUT\", \"VSS\", \"B\"])\n\n current_mirror_netlist.connect_netlist(\n two_tran_interdigitized_netlist(\n pdk=pdk,\n width=width,\n length=length,\n fingers=fingers,\n multipliers=multipliers,\n with_dummy=with_dummy,\n n_or_p_fet=n_or_p_fet,\n ),\n [\n (\"VDD1\", \"VREF\"), # reference drain\n (\"VG1\", \"VREF\"), # reference gate (diode-connected)\n (\"VDD2\", \"VOUT\"), # mirror drain\n (\"VG2\", \"VREF\"), # mirror gate\n (\"VSS1\", \"VSS\"), # shared source\n (\"VSS2\", \"VSS\"),\n (\"VB\", \"B\"), # bulk\n ],\n )\n\n return current_mirror_netlist\n\n\n# Backward-compatible export used by __init__.py and downstream imports.\ncurrent_mirror_netlist = current_mirror_interdigitized_netlist\n\n@tracked_generator(\"current_mirror\")\ndef current_mirror(\n pdk: MappedPDK, \n numcols: int = 3,\n device: str = 'nfet',\n with_dummy: Optional[bool] = True,\n with_substrate_tap: Optional[bool] = False,\n with_tie: Optional[bool] = True,\n with_labels: bool = True,\n tie_layers: tuple[str,str]=(\"met2\",\"met1\"),\n **kwargs\n) -> Component:\n \"\"\"An instantiable current mirror that returns a Component object. The current mirror is a two transistor interdigitized structure with a shorted source and gate. It can be instantiated with either nmos or pmos devices. It can also be instantiated with a dummy device, a substrate tap, and a tie layer, and is centered at the origin. Transistor A acts as the reference and Transistor B acts as the mirror fet\n\n Args:\n pdk (MappedPDK): the process design kit to use\n numcols (int): number of columns of the interdigitized fets\n device (str): nfet or pfet (can only interdigitize one at a time with this option)\n with_dummy (bool): True places dummies on either side of the interdigitized fets\n with_substrate_tap (bool): boolean to decide whether to place a substrate tapring\n with_tie (bool): boolean to decide whether to place a tapring for tielayer\n tie_layers (tuple[str,str], optional): the layers to use for the tie. Defaults to (\"met2\",\"met1\").\n **kwargs: The keyword arguments are passed to the two_nfet_interdigitized or two_pfet_interdigitized functions and need to be valid arguments that can be accepted by the multiplier function\n\n Returns:\n Component: a current mirror component object\n \"\"\"\n top_level = Component(\"current mirror\")\n if device in ['nmos', 'nfet']:\n interdigitized_fets = two_nfet_interdigitized(\n pdk, \n numcols=numcols, \n dummy=with_dummy, \n with_substrate_tap=False, \n with_tie=False, \n **kwargs\n )\n elif device in ['pmos', 'pfet']:\n interdigitized_fets = two_pfet_interdigitized(\n pdk, \n numcols=numcols, \n dummy=with_dummy, \n with_substrate_tap=False, \n with_tie=False, \n **kwargs\n )\n top_level.add_ports(interdigitized_fets.get_ports_list(), prefix=\"fet_\")\n maxmet_sep = pdk.util_max_metal_seperation()\n # short source of the fets\n source_short = interdigitized_fets << c_route(pdk, interdigitized_fets.ports['A_source_E'], interdigitized_fets.ports['B_source_E'], extension=3*maxmet_sep, viaoffset=False)\n # short gates of the fets\n gate_short = interdigitized_fets << c_route(pdk, interdigitized_fets.ports['A_gate_W'], interdigitized_fets.ports['B_gate_W'], extension=3*maxmet_sep, viaoffset=False)\n # short gate and drain of one of the reference \n interdigitized_fets << L_route(pdk, interdigitized_fets.ports['A_drain_W'], gate_short.ports['con_N'], viaoffset=False, fullbottom=False)\n \n top_level << interdigitized_fets\n if with_tie:\n if device in ['nmos','nfet']:\n tap_layer = \"p+s/d\"\n if device in ['pmos','pfet']:\n tap_layer = \"n+s/d\"\n tap_sep = max(\n float(pdk.util_max_metal_seperation()),\n float(pdk.get_grule(\"active_diff\", \"active_tap\")[\"min_separation\"]),\n )\n tap_sep += float(pdk.get_grule(tap_layer, \"active_tap\")[\"min_enclosure\"])\n tap_encloses = (\n 2 * (tap_sep + interdigitized_fets.xmax),\n 2 * (tap_sep + interdigitized_fets.ymax),\n )\n tie_ref = top_level << tapring(pdk, enclosed_rectangle = tap_encloses, sdlayer = tap_layer, horizontal_glayer = tie_layers[0], vertical_glayer = tie_layers[1])\n top_level.add_ports(tie_ref.get_ports_list(), prefix=\"welltie_\")\n try:\n top_level << straight_route(pdk, top_level.ports[f\"fet_B_{numcols - 1}_dummy_R_gsdcon_top_met_E\"],top_level.ports[\"welltie_E_top_met_E\"],glayer2=\"met1\")\n top_level << straight_route(pdk, top_level.ports[\"fet_A_0_dummy_L_gsdcon_top_met_W\"],top_level.ports[\"welltie_W_top_met_W\"],glayer2=\"met1\")\n except KeyError:\n pass\n try:\n end_col = numcols - 1\n port1 = f'B_{end_col}_dummy_R_gdscon_top_met_E'\n top_level << straight_route(pdk, top_level.ports[port1], top_level.ports[\"welltie_E_top_met_E\"], glayer2=\"met1\")\n except KeyError:\n pass\n \n # add a pwell \n if device in ['nmos','nfet']:\n top_level.add_padding(layers = (pdk.get_glayer(\"pwell\"),), default = pdk.get_grule(\"pwell\", \"active_tap\")[\"min_enclosure\"], )\n top_level = add_ports_perimeter(top_level, layer = pdk.get_glayer(\"pwell\"), prefix=\"well_\")\n if device in ['pmos','pfet']:\n top_level.add_padding(layers = (pdk.get_glayer(\"nwell\"),), default = pdk.get_grule(\"nwell\", \"active_tap\")[\"min_enclosure\"], )\n top_level = add_ports_perimeter(top_level, layer = pdk.get_glayer(\"nwell\"), prefix=\"well_\")\n\n \n # add the substrate tap if specified\n if with_substrate_tap:\n subtap_sep = pdk.get_grule(\"dnwell\", \"active_tap\")[\"min_separation\"]\n subtap_enclosure = (\n 2.5 * (subtap_sep + interdigitized_fets.xmax),\n 2.5 * (subtap_sep + interdigitized_fets.ymax),\n )\n subtap_ring = top_level << tapring(pdk, enclosed_rectangle = subtap_enclosure, sdlayer = \"p+s/d\", horizontal_glayer = \"met2\", vertical_glayer = \"met1\")\n top_level.add_ports(subtap_ring.get_ports_list(), prefix=\"substrate_tap_\")\n \n top_level.add_ports(source_short.get_ports_list(), prefix='purposegndports')\n top_level.add_ports(gate_short.get_ports_list(), prefix='reference_bus_')\n\n netlist_obj = current_mirror_interdigitized_netlist(\n pdk=pdk,\n width=kwargs.get(\"width\", 3),\n length=kwargs.get(\"length\", 0.15),\n fingers=kwargs.get(\"fingers\",1),\n multipliers=numcols,\n with_dummy=with_dummy,\n n_or_p_fet=device,\n subckt_only=True\n )\n component = add_cm_labels(top_level, pdk) if with_labels else component_snap_to_grid(rename_ports_by_orientation(top_level))\n component.info[\"netlist\"] = netlist_obj.generate_netlist()\n component.info[\"netlist_obj\"] = netlist_obj\n component.info[\"netlist_data\"] = {\n \"circuit_name\": netlist_obj.circuit_name,\n \"nodes\": netlist_obj.nodes,\n \"source_netlist\": netlist_obj.source_netlist,\n }\n\n return component\n\nif __name__==\"__main__\":\n cm = add_cm_labels(current_mirror(sky130_mapped_pdk, device='pfet'),sky130_mapped_pdk)\n cm.show()\n cm.name = \"CMIRROR\"\n #magic_drc_result = sky130_mapped_pdk.drc_magic(current_mirror, current_mirror.name)\n #netgen_lvs_result = sky130_mapped_pdk.lvs_netgen(current_mirror, current_mirror.name)\n current_mirror_gds = cm.write_gds(\"cm.gds\")\n if run_evaluation is not None:\n res = run_evaluation(\"cm.gds\", cm.name, cm)\n else:\n print(\"Skipping evaluation because evaluator_wrapper was not found.\")\n" + }, + "domain_shape": { + "anchor": 1, + "development": 8, + "hidden": 16 + }, + "source_role": "draft_task_materialization_not_a_new_lineage", + "pdk_revision": "0fe599b2afb6708d281543108caf8310912f54af", + "frozen_source_pack": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/mirror/source_pack", + "frozen_source_files": [ + "component_build.py", + "generator.py", + "glayout/__init__.py", + "glayout/cells/__init__.py", + "glayout/cells/elementary/__init__.py", + "glayout/cells/elementary/current_mirror/__init__.py", + "glayout/pdk/__init__.py", + "glayout/pdk/gf180_mapped/__init__.py", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x02p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x04p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x08p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_00p54x16p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_05p00x05p00.gds", + "glayout/pdk/gf180_mapped/bjt/npn_10p00x10p00.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_05p00x00p42.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_05p00x05p00.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_10p00x00p42.gds", + "glayout/pdk/gf180_mapped/bjt/pnp_10p00x10p00.gds", + "glayout/pdk/gf180_mapped/gf180_grules.py", + "glayout/pdk/gf180_mapped/gf180_mapped.py", + "glayout/pdk/gf180_mapped/gf180mcu.drc", + "glayout/pdk/gf180_mapped/gf180mcu_drc.lydrc", + "glayout/pdk/gf180_mapped/gf180mcu_osu_sc_9T.spice", + "glayout/pdk/ihp130_mapped/__init__.py", + "glayout/pdk/ihp130_mapped/ihp130_drc.lydrc", + "glayout/pdk/ihp130_mapped/ihp130_grules.py", + "glayout/pdk/ihp130_mapped/ihp130_mapped.py", + "glayout/pdk/mappedpdk.py", + "glayout/pdk/sky130_mapped/__init__.py", + "glayout/pdk/sky130_mapped/sky130.lydrc", + "glayout/pdk/sky130_mapped/sky130_add_npc.py", + "glayout/pdk/sky130_mapped/sky130_fd_sc_hd.spice", + "glayout/pdk/sky130_mapped/sky130_grules.py", + "glayout/pdk/sky130_mapped/sky130_mapped.py", + "glayout/placement/__init__.py", + "glayout/placement/common_centroid_ab_ba.py", + "glayout/placement/four_transistor_interdigitized.py", + "glayout/placement/two_transistor_interdigitized.py", + "glayout/placement/two_transistor_place.py", + "glayout/primitives/__init__.py", + "glayout/primitives/bjt.py", + "glayout/primitives/fet.py", + "glayout/primitives/guardring.py", + "glayout/primitives/mimcap.py", + "glayout/primitives/resistor.py", + "glayout/primitives/via_gen.py", + "glayout/provenance/__init__.py", + "glayout/provenance/netlist_summary.py", + "glayout/provenance/runtime.py", + "glayout/routing/L_route.py", + "glayout/routing/__init__.py", + "glayout/routing/c_route.py", + "glayout/routing/smart_route.py", + "glayout/routing/straight_route.py", + "glayout/spice/__init__.py", + "glayout/spice/netlist.py", + "glayout/util/__init__.py", + "glayout/util/comp_utils.py", + "glayout/util/component_array_create.py", + "glayout/util/geometry.py", + "glayout/util/pattern.py", + "glayout/util/port_utils.py", + "glayout/util/print_rules.py", + "glayout/util/routing.py", + "glayout/util/snap_to_grid.py" + ] +} diff --git a/benchmarks/code_behind_layout/configs/tasks/development_components_20261019T012723Z/mirror/task_packet.json b/benchmarks/code_behind_layout/configs/tasks/development_components_20261019T012723Z/mirror/task_packet.json new file mode 100644 index 00000000..f92a3c8f --- /dev/null +++ b/benchmarks/code_behind_layout/configs/tasks/development_components_20261019T012723Z/mirror/task_packet.json @@ -0,0 +1,435 @@ +{ + "task_id": "draft_mirror_source_quality", + "goal": "Improve the declared worst-corner post-RC objective by one shared source edit while preserving the independent circuit, full-rule DRC, LVS, all analysis coverage and every declared constraint. This is an unfrozen development task; layout edits cannot change circuit sizing or dummy count.", + "contract": { + "task_id": "draft_mirror_source_quality", + "configuration_id": "anchor", + "reference_id": "independent_mirror_anchor", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "absolute_current_error", + "unit": "1", + "max": 0.05 + }, + { + "name": "output_resistance", + "unit": "ohm", + "min": 1000000.0 + } + ], + "objective": { + "id": "mirror_error_min", + "metric": "absolute_current_error", + "unit": "1", + "direction": "min", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 5, + "expected_rows": 1 + }, + "compliance": { + "kind": "dc", + "columns": 5, + "start": 0.05, + "end": 1.75, + "points": 69, + "scale": "linear" + }, + "input_gain": { + "kind": "dc", + "columns": 5, + "start": 2e-06, + "end": 2e-05, + "points": 10, + "scale": "linear" + } + } + }, + "allowed_paths": [ + "glayout/cells/elementary/current_mirror/current_mirror.py" + ], + "visible_sources": { + "glayout/cells/elementary/current_mirror/current_mirror.py": "Use read_source for the complete current module" + }, + "documents": { + "configurations": [ + { + "configuration_id": "anchor", + "parameters": { + "width": 1.88, + "length": 3.0, + "numcols": 2, + "device": "pfet" + }, + "reference_id": "independent_mirror_anchor" + }, + { + "configuration_id": "dev_01", + "parameters": { + "width": 1.5, + "length": 3.0, + "numcols": 2, + "device": "pfet" + }, + "reference_id": "independent_mirror_dev_01" + }, + { + "configuration_id": "dev_02", + "parameters": { + "width": 1.5, + "length": 0.5, + "numcols": 2, + "device": "pfet" + }, + "reference_id": "independent_mirror_dev_02" + }, + { + "configuration_id": "dev_03", + "parameters": { + "width": 1.88, + "length": 1.0, + "numcols": 2, + "device": "pfet" + }, + "reference_id": "independent_mirror_dev_03" + }, + { + "configuration_id": "dev_04", + "parameters": { + "width": 1.88, + "length": 0.5, + "numcols": 2, + "device": "pfet" + }, + "reference_id": "independent_mirror_dev_04" + }, + { + "configuration_id": "dev_05", + "parameters": { + "width": 2.5, + "length": 2.0, + "numcols": 2, + "device": "pfet" + }, + "reference_id": "independent_mirror_dev_05" + }, + { + "configuration_id": "dev_06", + "parameters": { + "width": 1.88, + "length": 1.5, + "numcols": 2, + "device": "pfet" + }, + "reference_id": "independent_mirror_dev_06" + }, + { + "configuration_id": "dev_07", + "parameters": { + "width": 2.5, + "length": 0.5, + "numcols": 2, + "device": "pfet" + }, + "reference_id": "independent_mirror_dev_07" + }, + { + "configuration_id": "dev_08", + "parameters": { + "width": 3.0, + "length": 2.0, + "numcols": 2, + "device": "pfet" + }, + "reference_id": "independent_mirror_dev_08" + } + ], + "bench": { + "supply_V": 1.8, + "temperature_C": 27, + "corners": [ + "tt", + "ss", + "ff" + ], + "reference_current_A": 1e-05, + "nominal_output_V": 0.9, + "metrics_from": "steady DC row and central derivative; OP is health evidence" + }, + "API": "Complete editable module is provided by read_source. Its exact imported common PDK/MOS/via/placement/routing/util/SPICE libraries and fixed marker/export wrapper are frozen; sibling target cells, complete OTAs, training compiler, trusted evaluator and hidden tables are absent. Import signatures match the existing module. Only ordinary unified source-content diffs are accepted.", + "circuit": "* Independent intended circuit; physical per-finger width retained\n.subckt mirror4 VREF VOUT VSS B\nXREF VREF VREF VSS B sky130_fd_pr__pfet_01v8 w=1.88 l=3 m=2\nXOUT VOUT VREF VSS B sky130_fd_pr__pfet_01v8 w=1.88 l=3 m=2\nXDUMMY B B B B sky130_fd_pr__pfet_01v8 w=1.88 l=3 m=2\n.ends mirror4\n", + "natural_shortfall": "The measured W1/L0.5 mirror has worst-corner 2.3439% nominal current error and 1.3285Mohm output resistance; the longer anchor is better. This is a natural quality shortfall, not proof a source-only edit can remove the intrinsic device contribution.", + "PDK": { + "layers": { + "capmet": "capm", + "met5": "met4", + "via4": "via3", + "met4": "met3", + "via3": "via2", + "met3": "met2", + "via2": "via", + "met2": "met1", + "via1": "mcon", + "met1": "li1", + "mcon": "licon1", + "poly": "poly", + "active_diff": "diff", + "active_tap": "diff", + "n+s/d": "nsdm", + "p+s/d": "psdm", + "nwell": "nwell", + "pwell": [ + 64, + 44 + ], + "dnwell": "dnwell", + "met5_pin": "met4_pin", + "met4_pin": "met3_pin", + "met3_pin": "met2_pin", + "met2_pin": "met1_pin", + "met1_pin": "li1_pin", + "poly_pin": "poly_pin", + "active_diff_pin": "diff_pin", + "met5_label": "met4_label", + "met4_label": "met3_label", + "met3_label": "met2_label", + "met2_label": "met1_label", + "met1_label": "li1_label", + "poly_label": "poly_label", + "active_diff_label": "diff_label" + }, + "rules": { + "dnwell": { + "dnwell": { + "min_width": 3.0, + "min_separation": 6.3 + }, + "pwell": { + "min_enclosure": 0.0 + }, + "nwell": { + "min_separation": 4.5 + }, + "active_tap": { + "min_separation": 0.34 + } + }, + "pwell": { + "active_tap": { + "min_enclosure": 0.18 + } + }, + "nwell": { + "nwell": { + "min_width": 0.84, + "min_separation": 1.27 + }, + "active_tap": { + "min_enclosure": 0.18 + } + }, + "p+s/d": { + "p+s/d": { + "min_width": 0.38, + "min_separation": 0.38 + }, + "active_diff": { + "min_enclosure": 0.13, + "min_separation": 0.13 + }, + "active_tap": { + "min_enclosure": 0.13, + "min_separation": 0.13 + } + }, + "n+s/d": { + "n+s/d": { + "min_width": 0.38, + "min_separation": 0.38 + }, + "active_diff": { + "min_enclosure": 0.13, + "min_separation": 0.13 + }, + "active_tap": { + "min_enclosure": 0.13, + "min_separation": 0.13 + } + }, + "active_diff": { + "active_diff": { + "min_width": 0.15, + "min_separation": 0.27 + }, + "active_tap": { + "min_separation": 0.27 + }, + "poly": { + "overhang": 0.25 + }, + "mcon": { + "min_enclosure": 0.06 + } + }, + "active_tap": { + "active_tap": { + "min_width": 0.15, + "min_separation": 0.27 + }, + "mcon": { + "min_enclosure": 0.12 + } + }, + "poly": { + "poly": { + "min_width": 0.15, + "min_separation": 0.21, + "extension": 0.13 + }, + "mcon": { + "min_enclosure": 0.05, + "min_separation": 0.06 + } + }, + "mcon": { + "poly": { + "min_enclosure": 0.08 + }, + "mcon": { + "min_width": 0.17, + "min_separation": 0.17, + "width": 0.17 + }, + "met1": { + "min_enclosure": 0.08 + } + }, + "met1": { + "met1": { + "min_width": 0.17, + "min_separation": 0.17 + }, + "via1": { + "min_enclosure": 0.0 + } + }, + "via1": { + "via1": { + "min_width": 0.17, + "min_separation": 0.19, + "width": 0.17 + }, + "met2": { + "min_enclosure": 0.06 + } + }, + "met2": { + "met2": { + "min_width": 0.14, + "min_separation": 0.14 + }, + "via2": { + "min_enclosure": 0.14 + } + }, + "via2": { + "via2": { + "min_width": 0.21, + "min_separation": 0.17, + "width": 0.15 + }, + "met3": { + "min_enclosure": 0.09 + } + }, + "met3": { + "met3": { + "min_width": 0.14, + "min_separation": 0.28 + }, + "via3": { + "min_enclosure": 0.19 + } + }, + "via3": { + "via3": { + "min_width": 0.2, + "min_separation": 0.2, + "width": 0.2 + }, + "met4": { + "min_enclosure": 0.65 + } + }, + "met4": { + "met4": { + "min_width": 0.3, + "min_separation": 0.4 + }, + "via4": { + "min_enclosure": 0.09 + }, + "capmet": { + "min_enclosure": 0.14, + "min_separation": 1.34 + } + }, + "via4": { + "via4": { + "width": 0.2, + "min_separation": 0.35 + }, + "met5": { + "min_enclosure": 0.07 + } + }, + "met5": { + "met5": { + "min_width": 0.3, + "min_separation": 0.4 + } + }, + "capmet": { + "capmet": { + "capmettop": [ + 71, + 20 + ], + "capmetbottom": [ + 70, + 20 + ], + "min_separation": 1.2 + } + } + } + } + }, + "visible_configurations": [ + "anchor", + "dev_01", + "dev_02", + "dev_03", + "dev_04", + "dev_05", + "dev_06", + "dev_07", + "dev_08" + ], + "budget": { + "decisions": 10, + "physical_evaluations": 9, + "context_tokens": 8192, + "reserved_output_tokens": 1024, + "status": "DRAFT_BUDGET_REQUIRES_PILOT" + } +} diff --git a/benchmarks/code_behind_layout/configs/tasks/development_components_20261019T012723Z/pair/task.json b/benchmarks/code_behind_layout/configs/tasks/development_components_20261019T012723Z/pair/task.json new file mode 100644 index 00000000..f76f95f0 --- /dev/null +++ b/benchmarks/code_behind_layout/configs/tasks/development_components_20261019T012723Z/pair/task.json @@ -0,0 +1,1068 @@ +{ + "status": "DRAFT_REAL_SOURCE_AND_REFERENCES_NOT_FORMAL", + "task_id": "draft_pair_source_quality", + "parent_lineage": "glayout_pair", + "source_revision": "d092211d7996c99159402451bc7141931d6a93c3", + "E1_stratum": "reuse", + "source_pack": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/pair/source_pack", + "editable_paths": [ + "glayout/cells/elementary/diff_pair/diff_pair_core.py" + ], + "entrypoint": "generator.py", + "representation": "G2", + "evidence_origin": "/srv/code-behind-layout/results/derived/pair_three_size_domain_development.json", + "bench": { + "supply_V": 1.8, + "temperature_C": 27, + "corners": [ + "tt", + "ss", + "ff" + ], + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "differential": { + "kind": "dc", + "columns": 6, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + }, + "common_mode": { + "kind": "dc", + "columns": 6, + "start": 0.65, + "end": 1.3, + "points": 14, + "scale": "linear" + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "transient": { + "kind": "transient", + "columns": 4, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + }, + "tail_current_A": 2e-05, + "common_mode_V": 0.9, + "drain_DC_clamp_V": 1.2, + "R_each_ohm": 10000, + "C_each_F": 1e-12, + "balance_scope": "deterministic only, no mismatch yield" + }, + "natural_shortfall": { + "origin": "unmodified_real_generator_natural_measurement", + "description": "W3/L1/fingers2 and W3/L0.5/fingers4 each preserve three post-RC transient timeouts. Prelayout and partial post-RC DC/AC values do not establish full-flow success. W1/L0.5/fingers2 is the complete anchor; candidate versus tool numerical classification still needs same-configuration controls.", + "evidence_file": "results/derived/pair_three_size_domain_development.json", + "run_ids": [ + "phase0_20261019T003758658087Z_pair_characterization", + "phase0_20261019T003801900834Z_pair_characterization", + "phase0_20261019T003804699917Z_pair_characterization" + ], + "repairability_established": false, + "formal_or_training_use": false + }, + "immutable_sizing": "Per-configuration W/L/multiplicity and independent N(z) cannot be edited; the same source patch must serve the whole domain", + "source_dependency_group": "vendor_elementary_targets_shared_with_OTA_closures; not four newly qualified independent clusters", + "qualification": { + "generation_preflight": { + "unique_parameter_points_with_actual_GDS": 25, + "generation_attempts": 27, + "failed_generation_attempts": 2, + "current_snapshot_all_25_generated_in_one_run": false, + "raw_generation_records": [ + "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/pair/preflight_attempt_20261019T012813579994Z/generation/generation.json", + "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/pair/preflight_attempt_20261019T013315954474Z/generation/generation.json", + "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/pair/preflight_attempt_20261019T013509599240Z/generation/generation.json" + ], + "establishes_S2": false + }, + "full_domain_baseline": null, + "feasible_edit_witness": null, + "isolated_evaluator_adapter": null, + "model_context_tokens": { + "kind": "pair", + "input_tokens_with_complete_source": 6824, + "reserved_output_tokens": 1024, + "fits_8192": true, + "source_truncated": false, + "PDK_rules_truncated": false, + "module_decomposition": "verbatim main algorithm plus all imports; original wrappers frozen; same lineage" + }, + "anchor_geometry_equivalence": { + "kind": "pair", + "new_gds": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/pair/preflight_attempt_20261019T013509599240Z/generation/anchor.gds", + "reference_gds": "/srv/code-behind-layout/runs/phase0/phase0_20261019T003804699917Z_pair_characterization/pair6.gds", + "units_m": 1e-06, + "precision_m": 1e-09, + "changed_layers": [], + "filled_geometry_equal": true, + "all_labels_equal": true, + "cell_names_excluded": true, + "physical_measurements_rerun": false + } + }, + "formal_admission": false, + "formal_trials": 0, + "training_examples": 0, + "main_benchmark_frozen": false, + "visible_configurations": [ + { + "configuration_id": "anchor", + "role": "anchor", + "parameters": { + "width": 1.0, + "length": 0.5, + "fingers": 2 + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/pair/references/anchor.spice", + "reference_id": "independent_pair_anchor", + "contract": { + "task_id": "draft_pair_source_quality", + "configuration_id": "anchor", + "reference_id": "independent_pair_anchor", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "absolute_branch_imbalance", + "unit": "1", + "max": 0.001 + }, + { + "name": "loaded_differential_gain", + "unit": "1", + "min": 1.0 + }, + { + "name": "differential_transconductance", + "unit": "S", + "min": 0.0001 + } + ], + "objective": { + "id": "pair_bandwidth_max", + "metric": "loaded_bandwidth", + "unit": "Hz", + "direction": "max", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "differential": { + "kind": "dc", + "columns": 6, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + }, + "common_mode": { + "kind": "dc", + "columns": 6, + "start": 0.65, + "end": 1.3, + "points": 14, + "scale": "linear" + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "transient": { + "kind": "transient", + "columns": 4, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + } + }, + "physical_result": null + }, + { + "configuration_id": "dev_01", + "role": "development", + "parameters": { + "width": 1.0, + "length": 0.6, + "fingers": 2 + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/pair/references/dev_01.spice", + "reference_id": "independent_pair_dev_01", + "contract": { + "task_id": "draft_pair_source_quality", + "configuration_id": "dev_01", + "reference_id": "independent_pair_dev_01", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "absolute_branch_imbalance", + "unit": "1", + "max": 0.001 + }, + { + "name": "loaded_differential_gain", + "unit": "1", + "min": 1.0 + }, + { + "name": "differential_transconductance", + "unit": "S", + "min": 0.0001 + } + ], + "objective": { + "id": "pair_bandwidth_max", + "metric": "loaded_bandwidth", + "unit": "Hz", + "direction": "max", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "differential": { + "kind": "dc", + "columns": 6, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + }, + "common_mode": { + "kind": "dc", + "columns": 6, + "start": 0.65, + "end": 1.3, + "points": 14, + "scale": "linear" + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "transient": { + "kind": "transient", + "columns": 4, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + } + }, + "physical_result": null + }, + { + "configuration_id": "dev_02", + "role": "development", + "parameters": { + "width": 1.0, + "length": 0.9, + "fingers": 2 + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/pair/references/dev_02.spice", + "reference_id": "independent_pair_dev_02", + "contract": { + "task_id": "draft_pair_source_quality", + "configuration_id": "dev_02", + "reference_id": "independent_pair_dev_02", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "absolute_branch_imbalance", + "unit": "1", + "max": 0.001 + }, + { + "name": "loaded_differential_gain", + "unit": "1", + "min": 1.0 + }, + { + "name": "differential_transconductance", + "unit": "S", + "min": 0.0001 + } + ], + "objective": { + "id": "pair_bandwidth_max", + "metric": "loaded_bandwidth", + "unit": "Hz", + "direction": "max", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "differential": { + "kind": "dc", + "columns": 6, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + }, + "common_mode": { + "kind": "dc", + "columns": 6, + "start": 0.65, + "end": 1.3, + "points": 14, + "scale": "linear" + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "transient": { + "kind": "transient", + "columns": 4, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + } + }, + "physical_result": null + }, + { + "configuration_id": "dev_03", + "role": "development", + "parameters": { + "width": 2.5, + "length": 1.0, + "fingers": 2 + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/pair/references/dev_03.spice", + "reference_id": "independent_pair_dev_03", + "contract": { + "task_id": "draft_pair_source_quality", + "configuration_id": "dev_03", + "reference_id": "independent_pair_dev_03", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "absolute_branch_imbalance", + "unit": "1", + "max": 0.001 + }, + { + "name": "loaded_differential_gain", + "unit": "1", + "min": 1.0 + }, + { + "name": "differential_transconductance", + "unit": "S", + "min": 0.0001 + } + ], + "objective": { + "id": "pair_bandwidth_max", + "metric": "loaded_bandwidth", + "unit": "Hz", + "direction": "max", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "differential": { + "kind": "dc", + "columns": 6, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + }, + "common_mode": { + "kind": "dc", + "columns": 6, + "start": 0.65, + "end": 1.3, + "points": 14, + "scale": "linear" + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "transient": { + "kind": "transient", + "columns": 4, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + } + }, + "physical_result": null + }, + { + "configuration_id": "dev_04", + "role": "development", + "parameters": { + "width": 2.0, + "length": 0.6, + "fingers": 2 + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/pair/references/dev_04.spice", + "reference_id": "independent_pair_dev_04", + "contract": { + "task_id": "draft_pair_source_quality", + "configuration_id": "dev_04", + "reference_id": "independent_pair_dev_04", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "absolute_branch_imbalance", + "unit": "1", + "max": 0.001 + }, + { + "name": "loaded_differential_gain", + "unit": "1", + "min": 1.0 + }, + { + "name": "differential_transconductance", + "unit": "S", + "min": 0.0001 + } + ], + "objective": { + "id": "pair_bandwidth_max", + "metric": "loaded_bandwidth", + "unit": "Hz", + "direction": "max", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "differential": { + "kind": "dc", + "columns": 6, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + }, + "common_mode": { + "kind": "dc", + "columns": 6, + "start": 0.65, + "end": 1.3, + "points": 14, + "scale": "linear" + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "transient": { + "kind": "transient", + "columns": 4, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + } + }, + "physical_result": null + }, + { + "configuration_id": "dev_05", + "role": "development", + "parameters": { + "width": 2.0, + "length": 1.0, + "fingers": 2 + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/pair/references/dev_05.spice", + "reference_id": "independent_pair_dev_05", + "contract": { + "task_id": "draft_pair_source_quality", + "configuration_id": "dev_05", + "reference_id": "independent_pair_dev_05", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "absolute_branch_imbalance", + "unit": "1", + "max": 0.001 + }, + { + "name": "loaded_differential_gain", + "unit": "1", + "min": 1.0 + }, + { + "name": "differential_transconductance", + "unit": "S", + "min": 0.0001 + } + ], + "objective": { + "id": "pair_bandwidth_max", + "metric": "loaded_bandwidth", + "unit": "Hz", + "direction": "max", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "differential": { + "kind": "dc", + "columns": 6, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + }, + "common_mode": { + "kind": "dc", + "columns": 6, + "start": 0.65, + "end": 1.3, + "points": 14, + "scale": "linear" + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "transient": { + "kind": "transient", + "columns": 4, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + } + }, + "physical_result": null + }, + { + "configuration_id": "dev_06", + "role": "development", + "parameters": { + "width": 3.0, + "length": 1.0, + "fingers": 2 + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/pair/references/dev_06.spice", + "reference_id": "independent_pair_dev_06", + "contract": { + "task_id": "draft_pair_source_quality", + "configuration_id": "dev_06", + "reference_id": "independent_pair_dev_06", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "absolute_branch_imbalance", + "unit": "1", + "max": 0.001 + }, + { + "name": "loaded_differential_gain", + "unit": "1", + "min": 1.0 + }, + { + "name": "differential_transconductance", + "unit": "S", + "min": 0.0001 + } + ], + "objective": { + "id": "pair_bandwidth_max", + "metric": "loaded_bandwidth", + "unit": "Hz", + "direction": "max", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "differential": { + "kind": "dc", + "columns": 6, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + }, + "common_mode": { + "kind": "dc", + "columns": 6, + "start": 0.65, + "end": 1.3, + "points": 14, + "scale": "linear" + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "transient": { + "kind": "transient", + "columns": 4, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + } + }, + "physical_result": null + }, + { + "configuration_id": "dev_07", + "role": "development", + "parameters": { + "width": 2.0, + "length": 0.75, + "fingers": 2 + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/pair/references/dev_07.spice", + "reference_id": "independent_pair_dev_07", + "contract": { + "task_id": "draft_pair_source_quality", + "configuration_id": "dev_07", + "reference_id": "independent_pair_dev_07", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "absolute_branch_imbalance", + "unit": "1", + "max": 0.001 + }, + { + "name": "loaded_differential_gain", + "unit": "1", + "min": 1.0 + }, + { + "name": "differential_transconductance", + "unit": "S", + "min": 0.0001 + } + ], + "objective": { + "id": "pair_bandwidth_max", + "metric": "loaded_bandwidth", + "unit": "Hz", + "direction": "max", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "differential": { + "kind": "dc", + "columns": 6, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + }, + "common_mode": { + "kind": "dc", + "columns": 6, + "start": 0.65, + "end": 1.3, + "points": 14, + "scale": "linear" + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "transient": { + "kind": "transient", + "columns": 4, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + } + }, + "physical_result": null + }, + { + "configuration_id": "dev_08", + "role": "development", + "parameters": { + "width": 3.0, + "length": 0.9, + "fingers": 2 + }, + "reference_file": "/srv/code-behind-layout/runtime/task_preparation/components_20261019T012723731624Z/private/pair/references/dev_08.spice", + "reference_id": "independent_pair_dev_08", + "contract": { + "task_id": "draft_pair_source_quality", + "configuration_id": "dev_08", + "reference_id": "independent_pair_dev_08", + "required_corners": [ + "tt", + "ss", + "ff" + ], + "specifications": [ + { + "name": "absolute_branch_imbalance", + "unit": "1", + "max": 0.001 + }, + { + "name": "loaded_differential_gain", + "unit": "1", + "min": 1.0 + }, + { + "name": "differential_transconductance", + "unit": "S", + "min": 0.0001 + } + ], + "objective": { + "id": "pair_bandwidth_max", + "metric": "loaded_bandwidth", + "unit": "Hz", + "direction": "max", + "corner_aggregation": "worst" + }, + "scope": "DRAFT_NOT_FROZEN_NOT_MEASURED", + "analysis_contracts": { + "op": { + "kind": "op", + "columns": 4, + "expected_rows": 1 + }, + "differential": { + "kind": "dc", + "columns": 6, + "start": -0.1, + "end": 0.1, + "points": 41, + "scale": "linear" + }, + "common_mode": { + "kind": "dc", + "columns": 6, + "start": 0.65, + "end": 1.3, + "points": 14, + "scale": "linear" + }, + "ac": { + "kind": "ac", + "columns": 3, + "start": 10, + "end": 1000000000.0, + "points": 241, + "scale": "log" + }, + "transient": { + "kind": "transient", + "columns": 4, + "start": 0, + "end": 4e-06, + "required_windows": [ + [ + 1.8e-06, + 1.99e-06 + ], + [ + 2.8e-06, + 2.99e-06 + ] + ] + } + } + }, + "physical_result": null + } + ], + "hidden_configuration_count": 16, + "source_snapshot": { + "glayout/cells/elementary/diff_pair/diff_pair_core.py": "from typing import Optional, Union\n\nfrom gdsfactory.cell import cell\nfrom gdsfactory.component import Component, copy\nfrom gdsfactory.components.rectangle import rectangle\nfrom gdsfactory.routing.route_quad import route_quad\nfrom gdsfactory.routing.route_sharp import route_sharp\nfrom glayout.pdk.mappedpdk import MappedPDK\nfrom glayout.util.comp_utils import align_comp_to_port, evaluate_bbox, movex, movey\nfrom glayout.util.port_utils import (\n add_ports_perimeter,\n get_orientation,\n print_ports,\n rename_ports_by_list,\n rename_ports_by_orientation,\n set_port_orientation,\n)\nfrom glayout.util.snap_to_grid import component_snap_to_grid\nfrom glayout.placement.common_centroid_ab_ba import common_centroid_ab_ba\nfrom glayout.primitives.fet import nmos, pmos\nfrom glayout.primitives.guardring import tapring\nfrom glayout.primitives.via_gen import via_stack\nfrom glayout.routing.c_route import c_route\nfrom glayout.routing.smart_route import smart_route\nfrom glayout.routing.straight_route import straight_route\nfrom glayout.spice import Netlist\nfrom glayout.pdk.sky130_mapped import sky130_mapped_pdk\nfrom gdsfactory.components import text_freetype\nfrom glayout.provenance import tracked_generator\ntry:\n from glayout.verification.evaluator_wrapper import run_evaluation\nexcept ImportError:\n print(\"Warning: evaluator_wrapper not found. Evaluation will be skipped.\")\n run_evaluation = None\n\n\nfrom .diff_pair_support import add_df_labels, add_df_generic_label_alias_ports, diff_pair_netlist\n\n@tracked_generator(\"diff_pair\")\n@cell\ndef diff_pair(\n\tpdk: MappedPDK,\n\twidth: float = 3,\n\tfingers: int = 4,\n\tlength: Optional[float] = None,\n\tn_or_p_fet: bool = True,\n\tplus_minus_seperation: float = 0,\n\trmult: int = 1,\n\tdummy: Union[bool, tuple[bool, bool]] = True,\n\tsubstrate_tap: bool=True\n) -> Component:\n\t\"\"\"create a diffpair with 2 transistors placed in two rows with common centroid place. Sources are shorted\n\twidth = width of the transistors\n\tfingers = number of fingers in the transistors (must be 2 or more)\n\tlength = length of the transistors, None or 0 means use min length\n\tshort_source = if true connects source of both transistors\n\tn_or_p_fet = if true the diffpair is made of nfets else it is made of pfets\n\tsubstrate_tap: if true place a tapring around the diffpair (connects on met1)\n\t\"\"\"\n\t# TODO: error checking\n\tpdk.activate()\n\tdiffpair = Component()\n\t# create transistors\n\twell = None\n\tif isinstance(dummy, bool):\n\t\tdummy = (dummy, dummy)\n\tif n_or_p_fet:\n\t\tfetL = nmos(pdk, width=width, fingers=fingers,length=length,multipliers=1,with_tie=False,with_dummy=(dummy[0], False),with_dnwell=False,with_substrate_tap=False,rmult=rmult)\n\t\tfetR = nmos(pdk, width=width, fingers=fingers,length=length,multipliers=1,with_tie=False,with_dummy=(False,dummy[1]),with_dnwell=False,with_substrate_tap=False,rmult=rmult)\n\t\tmin_spacing_x = pdk.get_grule(\"n+s/d\")[\"min_separation\"] - 2*(fetL.xmax - fetL.ports[\"multiplier_0_plusdoped_E\"].center[0])\n\t\twell = \"pwell\"\n\t\ttap_sdlayer = \"p+s/d\"\n\telse:\n\t\tfetL = pmos(pdk, width=width, fingers=fingers,length=length,multipliers=1,with_tie=False,with_dummy=(dummy[0], False),dnwell=False,with_substrate_tap=False,rmult=rmult)\n\t\tfetR = pmos(pdk, width=width, fingers=fingers,length=length,multipliers=1,with_tie=False,with_dummy=(False,dummy[1]),dnwell=False,with_substrate_tap=False,rmult=rmult)\n\t\tmin_spacing_x = pdk.get_grule(\"p+s/d\")[\"min_separation\"] - 2*(fetL.xmax - fetL.ports[\"multiplier_0_plusdoped_E\"].center[0])\n\t\twell = \"nwell\"\n\t\ttap_sdlayer = \"n+s/d\"\n\t# place transistors\n\tviam2m3 = via_stack(pdk,\"met2\",\"met3\",centered=True)\n\tmetal_min_dim = max(pdk.get_grule(\"met2\")[\"min_width\"],pdk.get_grule(\"met3\")[\"min_width\"])\n\tmetal_space = max(pdk.get_grule(\"met2\")[\"min_separation\"],pdk.get_grule(\"met3\")[\"min_separation\"],metal_min_dim)\n\tgate_route_os = evaluate_bbox(viam2m3)[0] - fetL.ports[\"multiplier_0_gate_W\"].width + metal_space\n\tmin_spacing_y = metal_space + 2*gate_route_os\n\tmin_spacing_y = min_spacing_y - 2*abs(fetL.ports[\"well_S\"].center[1] - fetL.ports[\"multiplier_0_gate_S\"].center[1])\n\t# TODO: fix spacing where you see +-0.5\n\ta_topl = (diffpair << fetL).movey(fetL.ymax+min_spacing_y/2+0.5).movex(0-fetL.xmax-min_spacing_x/2)\n\tb_topr = (diffpair << fetR).movey(fetR.ymax+min_spacing_y/2+0.5).movex(fetL.xmax+min_spacing_x/2)\n\ta_botr = (diffpair << fetR)\n\ta_botr = a_botr.mirror_y()\n\ta_botr.movey(0-0.5-fetL.ymax-min_spacing_y/2).movex(fetL.xmax+min_spacing_x/2)\n\tb_botl = (diffpair << fetL)\n\tb_botl = b_botl.mirror_y()\n\tb_botl.movey(0-0.5-fetR.ymax-min_spacing_y/2).movex(0-fetL.xmax-min_spacing_x/2)\n\t# if substrate tap place substrate tap\n\tif substrate_tap:\n\t\ttapref = diffpair << tapring(\n\t\t\tpdk,\n\t\t\tevaluate_bbox(diffpair,padding=1),\n\t\t\tsdlayer=tap_sdlayer,\n\t\t\thorizontal_glayer=\"met1\",\n\t\t)\n\t\tdiffpair.add_ports(tapref.get_ports_list(),prefix=\"tap_\")\n\t\ttry:\n\t\t\tdiffpair<