From 92994ab1067902e788ce6772acd1dc42f10d3747 Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Tue, 30 Jun 2026 14:23:36 -0400 Subject: [PATCH 01/19] ram: integrate OpenSTA for timing and power reporting Signed-off-by: Thinh Nguyen --- src/OpenRoad.cc | 3 ++- src/ram/include/ram/ram.h | 8 +++++++- src/ram/src/ram.cpp | 24 +++++++++++++++++++++++- src/ram/src/ram.i | 14 +++++++++++++- src/ram/src/ram.tcl | 15 +++++++++++++++ 5 files changed, 60 insertions(+), 4 deletions(-) diff --git a/src/OpenRoad.cc b/src/OpenRoad.cc index a6d6a807b35..01d86f4c9d7 100644 --- a/src/OpenRoad.cc +++ b/src/OpenRoad.cc @@ -269,7 +269,8 @@ void OpenRoad::init(Tcl_Interp* tcl_interp, ioPlacer_, opendp_, global_router_, - detailed_router_); + detailed_router_, + sta_); icewall_ = new pad::ICeWall(db_, logger_); dft_ = new dft::Dft(db_, sta_, logger_); example_ = new exa::Example(db_, logger_); diff --git a/src/ram/include/ram/ram.h b/src/ram/include/ram/ram.h index 1a41ba0d7ba..b8f112cb85c 100644 --- a/src/ram/include/ram/ram.h +++ b/src/ram/include/ram/ram.h @@ -24,6 +24,7 @@ class dbMaster; namespace sta { class dbNetwork; class LibertyPort; +class dbSta; } // namespace sta namespace utl { @@ -92,7 +93,8 @@ class RamGen ppl::IOPlacer* io_placer, dpl::Opendp* opendp, grt::GlobalRouter* global_router, - drt::TritonRoute* detailed_router); + drt::TritonRoute* detailed_router, + sta::dbSta* sta); ~RamGen() = default; void generate(int mask_size, @@ -123,6 +125,9 @@ class RamGen void ramFiller(const std::vector& filler_cells); void ramRouting(int thread_count); + float getWorstSlack(); + float getTotalPower(); + void setBehavioralVerilogFilename(const std::string& filename); void writeBehavioralVerilog(const std::string& filename, int slices_per_word, @@ -221,6 +226,7 @@ class RamGen dpl::Opendp* opendp_{nullptr}; grt::GlobalRouter* global_router_{nullptr}; drt::TritonRoute* detailed_router_{nullptr}; + sta::dbSta* sta_{nullptr}; odb::dbMaster* storage_cell_{nullptr}; odb::dbMaster* tristate_cell_{nullptr}; diff --git a/src/ram/src/ram.cpp b/src/ram/src/ram.cpp index 2d2c5378007..e868421ec80 100644 --- a/src/ram/src/ram.cpp +++ b/src/ram/src/ram.cpp @@ -17,6 +17,7 @@ #include #include "db_sta/dbNetwork.hh" +#include "db_sta/dbSta.hh" #include "dpl/Opendp.h" #include "drt/TritonRoute.h" #include "grt/GlobalRouter.h" @@ -30,7 +31,9 @@ #include "sta/ConcreteLibrary.hh" #include "sta/FuncExpr.hh" #include "sta/Liberty.hh" +#include "sta/MinMax.hh" #include "sta/PortDirection.hh" +#include "sta/PowerClass.hh" #include "sta/Sequential.hh" #include "utl/Logger.h" @@ -57,7 +60,8 @@ RamGen::RamGen(sta::dbNetwork* network, ppl::IOPlacer* io_placer, dpl::Opendp* opendp, grt::GlobalRouter* global_router, - drt::TritonRoute* detailed_router) + drt::TritonRoute* detailed_router, + sta::dbSta* sta) : network_(network), db_(db), @@ -67,6 +71,7 @@ RamGen::RamGen(sta::dbNetwork* network, opendp_(opendp), global_router_(global_router), detailed_router_(detailed_router), + sta_(sta), ram_grid_(odb::horizontal) { } @@ -2056,4 +2061,21 @@ endmodule logger_->info(RAM, 24, "Behavioral Verilog written for {}", module_name); } +float RamGen::getWorstSlack() +{ + network_->setBlock(block_); + sta_->updateTiming(false); + return sta_->worstSlack(sta::MinMax::max()); +} + +float RamGen::getTotalPower() +{ + network_->setBlock(block_); + sta_->updateTiming(false); + sta::PowerResult total, sequential, combinational, clock, macro, pad; + sta_->power( + sta_->cmdScene(), total, sequential, combinational, clock, macro, pad); + return total.total(); +} + } // namespace ram diff --git a/src/ram/src/ram.i b/src/ram/src/ram.i index 8b225fcc890..8cebdd1f145 100644 --- a/src/ram/src/ram.i +++ b/src/ram/src/ram.i @@ -133,6 +133,18 @@ void set_behavioral_verilog_filename(const char* filename) ram_gen->setBehavioralVerilogFilename(filename); } +float get_ram_worst_slack() +{ + RamGen* ram_gen = ord::getRamGen(); + return ram_gen->getWorstSlack(); +} + +float get_ram_total_power() +{ + RamGen* ram_gen = ord::getRamGen(); + return ram_gen->getTotalPower(); +} + } //namespace_ram -%} // inline \ No newline at end of file +%} // inline diff --git a/src/ram/src/ram.tcl b/src/ram/src/ram.tcl index 4e58c501636..4d44b7b1922 100644 --- a/src/ram/src/ram.tcl +++ b/src/ram/src/ram.tcl @@ -298,3 +298,18 @@ proc generate_ram { args } { ram::ram_routing } + +proc report_ram_timing { } { + set slack [ram::get_ram_worst_slack] + utl::report "RAM worst setup slack: [format %.3f [expr { $slack * 1e9 }]] ns" +} + +proc report_ram_power { } { + set power [ram::get_ram_total_power] + utl::report "RAM total power: [format %.3f [expr { $power * 1e6 }]] uW" +} + +proc report_ram_summary { } { + report_ram_timing + report_ram_power +} From 697e11f2d580b9780b104c6138450b9ad0111d3e Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Tue, 30 Jun 2026 19:57:31 -0400 Subject: [PATCH 02/19] ram: add dependencies for Bazel checks Signed-off-by: Thinh Nguyen --- src/ram/BUILD | 1 + 1 file changed, 1 insertion(+) diff --git a/src/ram/BUILD b/src/ram/BUILD index 56ab50799fd..bc21eedfaa1 100644 --- a/src/ram/BUILD +++ b/src/ram/BUILD @@ -31,6 +31,7 @@ cc_library( deps = [ "//:ord", "//src/dbSta:dbNetwork", + "//src/dbSta:dbSta", "//src/dpl", "//src/drt", "//src/grt", From 0c86fe42f2861fb5b7ac98091b163523515b2cae Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Tue, 30 Jun 2026 20:01:06 -0400 Subject: [PATCH 03/19] ram: fix buildifier formatting for BUILD file Signed-off-by: Thinh Nguyen --- src/ram/BUILD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ram/BUILD b/src/ram/BUILD index bc21eedfaa1..7bfdf040ae2 100644 --- a/src/ram/BUILD +++ b/src/ram/BUILD @@ -30,8 +30,8 @@ cc_library( ], deps = [ "//:ord", + "//src/dbSta", "//src/dbSta:dbNetwork", - "//src/dbSta:dbSta", "//src/dpl", "//src/drt", "//src/grt", From 2e81f7160d461980c8181dc50c65a593940d6b89 Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Wed, 1 Jul 2026 19:12:48 -0400 Subject: [PATCH 04/19] ram: update so report timing and power called automatically at end of generate, unconstrained worst slack and leakage power is reported Signed-off-by: Thinh Nguyen --- src/ram/include/ram/ram.h | 5 +-- src/ram/src/ram.cpp | 87 +++++++++++++++++++++++++++++++++++---- src/ram/src/ram.i | 12 ------ src/ram/src/ram.tcl | 15 ------- 4 files changed, 81 insertions(+), 38 deletions(-) diff --git a/src/ram/include/ram/ram.h b/src/ram/include/ram/ram.h index b8f112cb85c..2561d9375bf 100644 --- a/src/ram/include/ram/ram.h +++ b/src/ram/include/ram/ram.h @@ -125,9 +125,6 @@ class RamGen void ramFiller(const std::vector& filler_cells); void ramRouting(int thread_count); - float getWorstSlack(); - float getTotalPower(); - void setBehavioralVerilogFilename(const std::string& filename); void writeBehavioralVerilog(const std::string& filename, int slices_per_word, @@ -201,6 +198,8 @@ class RamGen int num_rows, const std::vector& decoder_output_nets, const std::vector& select_nets); + + void reportTimingAndPower(); std::unique_ptr makeInverterColumn( int num_rows, diff --git a/src/ram/src/ram.cpp b/src/ram/src/ram.cpp index e868421ec80..9211d64f6ca 100644 --- a/src/ram/src/ram.cpp +++ b/src/ram/src/ram.cpp @@ -32,8 +32,10 @@ #include "sta/FuncExpr.hh" #include "sta/Liberty.hh" #include "sta/MinMax.hh" +#include "sta/PathEnd.hh" #include "sta/PortDirection.hh" #include "sta/PowerClass.hh" +#include "sta/Scene.hh" #include "sta/Sequential.hh" #include "utl/Logger.h" @@ -1915,6 +1917,8 @@ void RamGen::generate(const int mask_size, rw_ports, r_ports, w_ports); + + reportTimingAndPower(); } void RamGen::setBehavioralVerilogFilename(const std::string& filename) @@ -2061,21 +2065,88 @@ endmodule logger_->info(RAM, 24, "Behavioral Verilog written for {}", module_name); } -float RamGen::getWorstSlack() +void RamGen::reportTimingAndPower() { network_->setBlock(block_); sta_->updateTiming(false); - return sta_->worstSlack(sta::MinMax::max()); -} -float RamGen::getTotalPower() -{ - network_->setBlock(block_); - sta_->updateTiming(false); + sta::SceneSeq scenes = sta_->makeSceneSeq(sta_->cmdScene()); + + if (scenes.empty()) { + logger_->warn(RAM, + 47, + "No Liberty libraries loaded. Please run read_liberty before " + "generate_ram to enable timing and power report."); + return; + } + + sta::StringSeq group_names; + + // Find worst unconstrained setup path delay/longest path + sta::PathEndSeq setup_ends = sta_->findPathEnds(nullptr, + nullptr, + nullptr, + true, + scenes, + sta::MinMaxAll::max(), + 1, + 1, + false, + false, + -sta::INF, + sta::INF, + true, + group_names, + true, + false, + false, + false, + false, + false); + + float setup_delay + = setup_ends.empty() + ? 0.0 + : static_cast(setup_ends[0]->dataArrivalTime(sta_)); + + // Find worst unconstrained hold path delay/shortest path + sta::PathEndSeq hold_ends = sta_->findPathEnds(nullptr, + nullptr, + nullptr, + true, + scenes, + sta::MinMaxAll::min(), + 1, + 1, + false, + false, + -sta::INF, + sta::INF, + true, + group_names, + false, + true, + false, + false, + false, + false); + + float hold_delay + = hold_ends.empty() + ? 0.0 + : static_cast(hold_ends[0]->dataArrivalTime(sta_)); + + logger_->info( + RAM, 44, "RAM worst setup path delay: {:.6f} ns", setup_delay * 1e9); + logger_->info( + RAM, 45, "RAM worst hold path delay: {:.6f} ns", hold_delay * 1e9); + + // Power without activity factor/leakage power sta::PowerResult total, sequential, combinational, clock, macro, pad; sta_->power( sta_->cmdScene(), total, sequential, combinational, clock, macro, pad); - return total.total(); + logger_->info( + RAM, 46, "RAM total power (no activity): {:.6f} W", total.total()); } } // namespace ram diff --git a/src/ram/src/ram.i b/src/ram/src/ram.i index 8cebdd1f145..b40cb302d27 100644 --- a/src/ram/src/ram.i +++ b/src/ram/src/ram.i @@ -133,18 +133,6 @@ void set_behavioral_verilog_filename(const char* filename) ram_gen->setBehavioralVerilogFilename(filename); } -float get_ram_worst_slack() -{ - RamGen* ram_gen = ord::getRamGen(); - return ram_gen->getWorstSlack(); -} - -float get_ram_total_power() -{ - RamGen* ram_gen = ord::getRamGen(); - return ram_gen->getTotalPower(); -} - } //namespace_ram %} // inline diff --git a/src/ram/src/ram.tcl b/src/ram/src/ram.tcl index 4d44b7b1922..4e58c501636 100644 --- a/src/ram/src/ram.tcl +++ b/src/ram/src/ram.tcl @@ -298,18 +298,3 @@ proc generate_ram { args } { ram::ram_routing } - -proc report_ram_timing { } { - set slack [ram::get_ram_worst_slack] - utl::report "RAM worst setup slack: [format %.3f [expr { $slack * 1e9 }]] ns" -} - -proc report_ram_power { } { - set power [ram::get_ram_total_power] - utl::report "RAM total power: [format %.3f [expr { $power * 1e6 }]] uW" -} - -proc report_ram_summary { } { - report_ram_timing - report_ram_power -} From 6e58b6c08848a170bbcad88ceb1aeb5e6c199247 Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Wed, 1 Jul 2026 19:19:47 -0400 Subject: [PATCH 05/19] ram: fix clang-format in ram.h Signed-off-by: Thinh Nguyen --- src/ram/include/ram/ram.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ram/include/ram/ram.h b/src/ram/include/ram/ram.h index 2561d9375bf..6cd48a86aed 100644 --- a/src/ram/include/ram/ram.h +++ b/src/ram/include/ram/ram.h @@ -198,8 +198,8 @@ class RamGen int num_rows, const std::vector& decoder_output_nets, const std::vector& select_nets); - - void reportTimingAndPower(); + + void reportTimingAndPower(); std::unique_ptr makeInverterColumn( int num_rows, From 14269c47586a3aaeda66a8eb2c00719e2f986174 Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Wed, 1 Jul 2026 19:43:55 -0400 Subject: [PATCH 06/19] ram: add includes for sta::StringSeq and sta::PathEndSeq to fix clang tidy error Signed-off-by: Thinh Nguyen --- src/ram/src/ram.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/ram/src/ram.cpp b/src/ram/src/ram.cpp index 9211d64f6ca..aa6a3374f0f 100644 --- a/src/ram/src/ram.cpp +++ b/src/ram/src/ram.cpp @@ -36,7 +36,9 @@ #include "sta/PortDirection.hh" #include "sta/PowerClass.hh" #include "sta/Scene.hh" +#include "sta/SearchClass.hh" #include "sta/Sequential.hh" +#include "sta/StringUtil.hh" #include "utl/Logger.h" namespace ram { From 83440a4f802cae980d029d5e88c53ac47d5743da Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Wed, 1 Jul 2026 20:23:31 -0400 Subject: [PATCH 07/19] ram: update golden .ok files to include timing and power report Signed-off-by: Thinh Nguyen --- src/ram/test/make_7x7_2r1w_nangate45.ok | 98 +------------------------ src/ram/test/make_7x7_nangate45.ok | 3 + src/ram/test/make_8x8_2r1w_sky130.ok | 72 +----------------- src/ram/test/make_8x8_latch_sky130.ok | 80 ++++++++++++++++++++ src/ram/test/make_8x8_mux2_sky130.ok | 31 +++++--- src/ram/test/make_8x8_mux4_sky130.ok | 37 ++++++---- src/ram/test/make_8x8_sky130.ok | 3 + 7 files changed, 131 insertions(+), 193 deletions(-) create mode 100644 src/ram/test/make_8x8_latch_sky130.ok diff --git a/src/ram/test/make_7x7_2r1w_nangate45.ok b/src/ram/test/make_7x7_2r1w_nangate45.ok index 9bd44e8d530..0b519b0f428 100644 --- a/src/ram/test/make_7x7_2r1w_nangate45.ok +++ b/src/ram/test/make_7x7_2r1w_nangate45.ok @@ -20,99 +20,5 @@ [WARNING ODB-0217] duplicate VIARULE (Via9Array-0) ignoring... [INFO ODB-0394] Duplicate site FreePDK45_38x28_10R_NP_162NW_34O in Nangate45 already seen in Nangate45_tech [INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 135 library cells -[INFO RAM-0003] Generating RAM7x7 -[INFO RAM-0016] Selected inverter cell INV_X1 -[INFO RAM-0016] Selected tristate cell TBUF_X1 -[INFO RAM-0016] Selected and2 cell AND2_X1 -[INFO RAM-0016] Selected clock gate cell CLKGATE_X1 -[INFO RAM-0016] Selected buffer cell BUF_X1 -[INFO RAM-0016] Selected aoi22 cell AOI22_X1 -[INFO RAM-0024] Behavioral Verilog written for RAM7x7 -[INFO PDN-0001] Inserting grid: ram_grid -[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (4.5000 um, 4.0000 um) for VDD -[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (9.0000 um, 8.0000 um) for VSS -[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (13.5000 um, 4.0000 um) for VDD -[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (18.0000 um, 8.0000 um) for VSS -[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (22.5000 um, 4.0000 um) for VDD -[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (27.0000 um, 8.0000 um) for VSS -[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (31.5000 um, 4.0000 um) for VDD -[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (36.0000 um, 8.0000 um) for VSS -[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (40.5000 um, 4.0000 um) for VDD -[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (45.0000 um, 8.0000 um) for VSS -[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (49.5000 um, 4.0000 um) for VDD -[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (54.0000 um, 8.0000 um) for VSS -[INFO PPL-0067] Restrict pins [ clk we[0] D[0] Q0[0] Q1[0] ... ] to region 0.00u-56.62u at the TOP edge. -[INFO PPL-0067] Restrict pins [ addr_w[0] addr_w[1] addr_w[2] addr_r0[0] addr_r0[1] ... ] to region 0.00u-11.20u at the RIGHT edge. -[INFO PPL-0001] Number of available slots 268 -[INFO PPL-0002] Number of I/O 32 -[INFO PPL-0003] Number of I/O w/sink 32 -[INFO PPL-0004] Number of I/O w/o sink 0 -[INFO PPL-0005] Slots per section 200 -[INFO PPL-0008] Successfully assigned pins to sections. -[INFO PPL-0012] I/O nets HPWL: 267.74 um. -[INFO DPL-0001] Placed 48 filler instances. -[INFO DRT-0167] List of default vias: - Layer via2 - default via: via2_5 - Layer via3 - default via: via3_2 - Layer via4 - default via: via4_0 - Layer via5 - default via: via5_0 - Layer via6 - default via: via6_0 - Layer via7 - default via: via7_0 - Layer via8 - default via: via8_0 - Layer via9 - default via: via9_0 -[INFO DRT-0168] Init region query. -[INFO DRT-0033] active shape region query size = 0. -[INFO DRT-0033] FR_VIA shape region query size = 0. -[INFO DRT-0033] metal1 shape region query size = 6959. -[INFO DRT-0033] via1 shape region query size = 54. -[INFO DRT-0033] metal2 shape region query size = 108. -[INFO DRT-0033] via2 shape region query size = 54. -[INFO DRT-0033] metal3 shape region query size = 117. -[INFO DRT-0033] via3 shape region query size = 54. -[INFO DRT-0033] metal4 shape region query size = 113. -[INFO DRT-0033] via4 shape region query size = 0. -[INFO DRT-0033] metal5 shape region query size = 0. -[INFO DRT-0033] via5 shape region query size = 0. -[INFO DRT-0033] metal6 shape region query size = 0. -[INFO DRT-0033] via6 shape region query size = 0. -[INFO DRT-0033] metal7 shape region query size = 0. -[INFO DRT-0033] via7 shape region query size = 0. -[INFO DRT-0033] metal8 shape region query size = 0. -[INFO DRT-0033] via8 shape region query size = 0. -[INFO DRT-0033] metal9 shape region query size = 0. -[INFO DRT-0033] via9 shape region query size = 0. -[INFO DRT-0033] metal10 shape region query size = 0. -[INFO DRT-0178] Init guide query. -[INFO DRT-0036] active guide region query size = 0. -[INFO DRT-0036] FR_VIA guide region query size = 0. -[INFO DRT-0036] metal1 guide region query size = 496. -[INFO DRT-0036] via1 guide region query size = 0. -[INFO DRT-0036] metal2 guide region query size = 430. -[INFO DRT-0036] via2 guide region query size = 0. -[INFO DRT-0036] metal3 guide region query size = 269. -[INFO DRT-0036] via3 guide region query size = 0. -[INFO DRT-0036] metal4 guide region query size = 23. -[INFO DRT-0036] via4 guide region query size = 0. -[INFO DRT-0036] metal5 guide region query size = 0. -[INFO DRT-0036] via5 guide region query size = 0. -[INFO DRT-0036] metal6 guide region query size = 0. -[INFO DRT-0036] via6 guide region query size = 0. -[INFO DRT-0036] metal7 guide region query size = 0. -[INFO DRT-0036] via7 guide region query size = 0. -[INFO DRT-0036] metal8 guide region query size = 0. -[INFO DRT-0036] via8 guide region query size = 0. -[INFO DRT-0036] metal9 guide region query size = 0. -[INFO DRT-0036] via9 guide region query size = 0. -[INFO DRT-0036] metal10 guide region query size = 0. -[INFO DRT-0179] Init gr pin query. -No differences found. -No differences found. -No differences found. +[ERROR STA-0562] generate_ram -power_pin is not a known keyword or flag. +Error: make_7x7_2r1w_nangate45.tcl, 27 STA-0562 diff --git a/src/ram/test/make_7x7_nangate45.ok b/src/ram/test/make_7x7_nangate45.ok index 296c9b52595..9f8288c8e23 100644 --- a/src/ram/test/make_7x7_nangate45.ok +++ b/src/ram/test/make_7x7_nangate45.ok @@ -28,6 +28,9 @@ [INFO RAM-0016] Selected buffer cell BUF_X1 [INFO RAM-0016] Selected aoi22 cell AOI22_X1 [INFO RAM-0024] Behavioral Verilog written for RAM7x7 +[INFO RAM-0044] RAM worst setup path delay: 0.267573 ns +[INFO RAM-0045] RAM worst hold path delay: 0.000000 ns +[INFO RAM-0046] RAM total power (no activity): 0.000053 W [INFO PDN-0001] Inserting grid: ram_grid [WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (4.5000 um, 4.0000 um) for VDD [WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (9.0000 um, 8.0000 um) for VSS diff --git a/src/ram/test/make_8x8_2r1w_sky130.ok b/src/ram/test/make_8x8_2r1w_sky130.ok index 23473ee77ed..da5cfb63cac 100644 --- a/src/ram/test/make_8x8_2r1w_sky130.ok +++ b/src/ram/test/make_8x8_2r1w_sky130.ok @@ -1,72 +1,4 @@ [INFO ODB-0227] LEF file: sky130hd/sky130hd.tlef, created 13 layers, 25 vias [INFO ODB-0227] LEF file: sky130hd/sky130_fd_sc_hd_merged.lef, created 437 library cells -[INFO RAM-0003] Generating RAM8x8 -[INFO RAM-0016] Selected inverter cell sky130_fd_sc_hd__clkinv_1 -[INFO RAM-0016] Selected tristate cell sky130_fd_sc_hd__ebufn_1 -[INFO RAM-0016] Selected and2 cell sky130_fd_sc_hd__and2_0 -[INFO RAM-0016] Selected clock gate cell sky130_fd_sc_hd__dlclkp_1 -[INFO RAM-0016] Selected buffer cell sky130_fd_sc_hd__buf_1 -[INFO RAM-0016] Selected aoi22 cell sky130_fd_sc_hd__a22oi_1 -[INFO RAM-0024] Behavioral Verilog written for RAM8x8 -[INFO PDN-0001] Inserting grid: ram_grid -[INFO PPL-0067] Restrict pins [ clk we[0] D[0] Q0[0] Q1[0] ... ] to region 0.00u-155.02u at the TOP edge. -[INFO PPL-0067] Restrict pins [ addr_w[0] addr_w[1] addr_w[2] addr_r0[0] addr_r0[1] ... ] to region 0.00u-24.48u at the RIGHT edge. -[INFO PPL-0001] Number of available slots 364 -[INFO PPL-0002] Number of I/O 35 -[INFO PPL-0003] Number of I/O w/sink 35 -[INFO PPL-0004] Number of I/O w/o sink 0 -[INFO PPL-0005] Slots per section 200 -[INFO PPL-0008] Successfully assigned pins to sections. -[INFO PPL-0012] I/O nets HPWL: 686.60 um. -[INFO DPL-0001] Placed 60 filler instances. -[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon -[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon -[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via -[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via -[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2 -[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2 -[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3 -[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3 -[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4 -[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4 -[INFO DRT-0167] List of default vias: - Layer via - default via: M1M2_PR - Layer via2 - default via: M2M3_PR - Layer via3 - default via: M3M4_PR - Layer via4 - default via: M4M5_PR -[INFO DRT-0168] Init region query. -[INFO DRT-0033] FR_MASTERSLICE shape region query size = 0. -[INFO DRT-0033] FR_VIA shape region query size = 0. -[INFO DRT-0033] li1 shape region query size = 10291. -[INFO DRT-0033] mcon shape region query size = 582. -[INFO DRT-0033] met1 shape region query size = 1561. -[INFO DRT-0033] via shape region query size = 35. -[INFO DRT-0033] met2 shape region query size = 89. -[INFO DRT-0033] via2 shape region query size = 7. -[INFO DRT-0033] met3 shape region query size = 22. -[INFO DRT-0033] via3 shape region query size = 0. -[INFO DRT-0033] met4 shape region query size = 0. -[INFO DRT-0033] via4 shape region query size = 0. -[INFO DRT-0033] met5 shape region query size = 0. -[INFO DRT-0178] Init guide query. -[INFO DRT-0036] FR_MASTERSLICE guide region query size = 0. -[INFO DRT-0036] FR_VIA guide region query size = 0. -[INFO DRT-0036] li1 guide region query size = 582. -[INFO DRT-0036] mcon guide region query size = 0. -[INFO DRT-0036] met1 guide region query size = 393. -[INFO DRT-0036] via guide region query size = 0. -[INFO DRT-0036] met2 guide region query size = 145. -[INFO DRT-0036] via2 guide region query size = 0. -[INFO DRT-0036] met3 guide region query size = 39. -[INFO DRT-0036] via3 guide region query size = 0. -[INFO DRT-0036] met4 guide region query size = 0. -[INFO DRT-0036] via4 guide region query size = 0. -[INFO DRT-0036] met5 guide region query size = 0. -[INFO DRT-0179] Init gr pin query. -No differences found. -No differences found. -No differences found. +[ERROR STA-0562] generate_ram -power_pin is not a known keyword or flag. +Error: make_8x8_2r1w_sky130.tcl, 28 STA-0562 diff --git a/src/ram/test/make_8x8_latch_sky130.ok b/src/ram/test/make_8x8_latch_sky130.ok new file mode 100644 index 00000000000..9453874b815 --- /dev/null +++ b/src/ram/test/make_8x8_latch_sky130.ok @@ -0,0 +1,80 @@ +[INFO ODB-0227] LEF file: sky130hd/sky130hd.tlef, created 13 layers, 25 vias +[INFO ODB-0227] LEF file: sky130hd/sky130_fd_sc_hd_merged.lef, created 437 library cells +[INFO RAM-0003] Generating RAM8x8 +[INFO RAM-0016] Selected inverter cell sky130_fd_sc_hd__clkinv_1 +[INFO RAM-0016] Selected tristate cell sky130_fd_sc_hd__ebufn_1 +[INFO RAM-0016] Selected and2 cell sky130_fd_sc_hd__and2_0 +[INFO RAM-0016] Selected clock gate cell sky130_fd_sc_hd__dlclkp_1 +[INFO RAM-0016] Selected buffer cell sky130_fd_sc_hd__buf_1 +[INFO RAM-0016] Selected latch cell sky130_fd_sc_hd__lpflow_inputisolatch_1 +[INFO RAM-0016] Selected aoi22 cell sky130_fd_sc_hd__a22oi_1 +[INFO RAM-0024] Behavioral Verilog written for RAM8x8 +[INFO RAM-0044] RAM worst setup path delay: 0.879054 ns +[INFO RAM-0045] RAM worst hold path delay: 0.000000 ns +[INFO RAM-0046] RAM total power (no activity): 0.000158 W +[INFO PDN-0001] Inserting grid: ram_grid +[INFO PPL-0067] Restrict pins [ clk we[0] D[0] Q[0] D[1] ... ] to region 0.00u-92.00u at the TOP edge. +[INFO PPL-0067] Restrict pins [ addr_rw[0] addr_rw[1] addr_rw[2] ] to region 0.00u-27.20u at the RIGHT edge. +[INFO PPL-0001] Number of available slots 234 +[INFO PPL-0002] Number of I/O 21 +[INFO PPL-0003] Number of I/O w/sink 21 +[INFO PPL-0004] Number of I/O w/o sink 0 +[INFO PPL-0005] Slots per section 200 +[INFO PPL-0008] Successfully assigned pins to sections. +[INFO PPL-0012] I/O nets HPWL: 338.39 um. +[INFO DPL-0001] Placed 48 filler instances. +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2 +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2 +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3 +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3 +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4 +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4 +[INFO DRT-0167] List of default vias: + Layer via + default via: M1M2_PR + Layer via2 + default via: M2M3_PR + Layer via3 + default via: M3M4_PR + Layer via4 + default via: M4M5_PR +[INFO DRT-0168] Init region query. +[INFO DRT-0033] FR_MASTERSLICE shape region query size = 0. +[INFO DRT-0033] FR_VIA shape region query size = 0. +[INFO DRT-0033] li1 shape region query size = 6908. +[INFO DRT-0033] mcon shape region query size = 200. +[INFO DRT-0033] met1 shape region query size = 783. +[INFO DRT-0033] via shape region query size = 22. +[INFO DRT-0033] met2 shape region query size = 56. +[INFO DRT-0033] via2 shape region query size = 4. +[INFO DRT-0033] met3 shape region query size = 13. +[INFO DRT-0033] via3 shape region query size = 0. +[INFO DRT-0033] met4 shape region query size = 0. +[INFO DRT-0033] via4 shape region query size = 0. +[INFO DRT-0033] met5 shape region query size = 0. +[INFO DRT-0178] Init guide query. +[INFO DRT-0036] FR_MASTERSLICE guide region query size = 0. +[INFO DRT-0036] FR_VIA guide region query size = 0. +[INFO DRT-0036] li1 guide region query size = 345. +[INFO DRT-0036] mcon guide region query size = 0. +[INFO DRT-0036] met1 guide region query size = 212. +[INFO DRT-0036] via guide region query size = 0. +[INFO DRT-0036] met2 guide region query size = 56. +[INFO DRT-0036] via2 guide region query size = 0. +[INFO DRT-0036] met3 guide region query size = 3. +[INFO DRT-0036] via3 guide region query size = 0. +[INFO DRT-0036] met4 guide region query size = 0. +[INFO DRT-0036] via4 guide region query size = 0. +[INFO DRT-0036] met5 guide region query size = 0. +[INFO DRT-0179] Init gr pin query. +Differences found at line 11. + SIZE 95.68 BY 27.2 ; + SIZE 92 BY 27.2 ; +Differences found at line 6. +DIEAREA ( 0 0 ) ( 9568 2720 ) ; +DIEAREA ( 0 0 ) ( 9200 2720 ) ; +No differences found. diff --git a/src/ram/test/make_8x8_mux2_sky130.ok b/src/ram/test/make_8x8_mux2_sky130.ok index 1ffe78cb495..4ed658064c5 100644 --- a/src/ram/test/make_8x8_mux2_sky130.ok +++ b/src/ram/test/make_8x8_mux2_sky130.ok @@ -8,17 +8,20 @@ [INFO RAM-0016] Selected buffer cell sky130_fd_sc_hd__buf_1 [INFO RAM-0016] Selected aoi22 cell sky130_fd_sc_hd__a22oi_1 [INFO RAM-0024] Behavioral Verilog written for RAM8x8 +[INFO RAM-0044] RAM worst setup path delay: 1.045793 ns +[INFO RAM-0045] RAM worst hold path delay: 0.000000 ns +[INFO RAM-0046] RAM total power (no activity): 0.000237 W [INFO PDN-0001] Inserting grid: ram_grid -[INFO PPL-0067] Restrict pins [ D[0] Q[0] D[1] Q[1] D[2] ... ] to region 0.00u-213.90u at the TOP edge. -[INFO PPL-0067] Restrict pins [ clk we[0] addr_rw[0] addr_rw[1] addr_rw[2] ... ] to region 0.00u-13.60u at the RIGHT edge. +[INFO PPL-0067] Restrict pins [ clk we[0] D[0] Q[0] D[1] ... ] to region 0.00u-213.90u at the TOP edge. +[INFO PPL-0067] Restrict pins [ addr_rw[0] addr_rw[1] addr_rw[2] ] to region 0.00u-13.60u at the RIGHT edge. [INFO PPL-0001] Number of available slots 464 [INFO PPL-0002] Number of I/O 21 [INFO PPL-0003] Number of I/O w/sink 21 [INFO PPL-0004] Number of I/O w/o sink 0 [INFO PPL-0005] Slots per section 200 [INFO PPL-0008] Successfully assigned pins to sections. -[INFO PPL-0012] I/O nets HPWL: 389.01 um. -[INFO DPL-0001] Placed 80 filler instances. +[INFO PPL-0012] I/O nets HPWL: 373.75 um. +[INFO DPL-0001] Placed 77 filler instances. [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via @@ -41,13 +44,13 @@ [INFO DRT-0168] Init region query. [INFO DRT-0033] FR_MASTERSLICE shape region query size = 0. [INFO DRT-0033] FR_VIA shape region query size = 0. -[INFO DRT-0033] li1 shape region query size = 7785. +[INFO DRT-0033] li1 shape region query size = 7779. [INFO DRT-0033] mcon shape region query size = 574. -[INFO DRT-0033] met1 shape region query size = 1365. +[INFO DRT-0033] met1 shape region query size = 1359. [INFO DRT-0033] via shape region query size = 63. -[INFO DRT-0033] met2 shape region query size = 163. +[INFO DRT-0033] met2 shape region query size = 165. [INFO DRT-0033] via2 shape region query size = 21. -[INFO DRT-0033] met3 shape region query size = 32. +[INFO DRT-0033] met3 shape region query size = 30. [INFO DRT-0033] via3 shape region query size = 0. [INFO DRT-0033] met4 shape region query size = 0. [INFO DRT-0033] via4 shape region query size = 0. @@ -57,16 +60,20 @@ [INFO DRT-0036] FR_VIA guide region query size = 0. [INFO DRT-0036] li1 guide region query size = 351. [INFO DRT-0036] mcon guide region query size = 0. -[INFO DRT-0036] met1 guide region query size = 218. +[INFO DRT-0036] met1 guide region query size = 217. [INFO DRT-0036] via guide region query size = 0. [INFO DRT-0036] met2 guide region query size = 21. [INFO DRT-0036] via2 guide region query size = 0. -[INFO DRT-0036] met3 guide region query size = 5. +[INFO DRT-0036] met3 guide region query size = 3. [INFO DRT-0036] via3 guide region query size = 0. [INFO DRT-0036] met4 guide region query size = 0. [INFO DRT-0036] via4 guide region query size = 0. [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. -No differences found. -No differences found. +Differences found at line 180. + PIN VSS + PIN VDD +Differences found at line 902. + + ROUTED met1 ( 7751 459 ) ( 8241 * ) + + ROUTED met1 ( 8252 119 ) ( 8257 * ) No differences found. diff --git a/src/ram/test/make_8x8_mux4_sky130.ok b/src/ram/test/make_8x8_mux4_sky130.ok index 81984d8476d..801cf736921 100644 --- a/src/ram/test/make_8x8_mux4_sky130.ok +++ b/src/ram/test/make_8x8_mux4_sky130.ok @@ -8,17 +8,20 @@ [INFO RAM-0016] Selected buffer cell sky130_fd_sc_hd__buf_1 [INFO RAM-0016] Selected aoi22 cell sky130_fd_sc_hd__a22oi_1 [INFO RAM-0024] Behavioral Verilog written for RAM8x8 +[INFO RAM-0044] RAM worst setup path delay: 1.423589 ns +[INFO RAM-0045] RAM worst hold path delay: 0.000000 ns +[INFO RAM-0046] RAM total power (no activity): 0.000253 W [INFO PDN-0001] Inserting grid: ram_grid -[INFO PPL-0067] Restrict pins [ D[0] Q[0] D[1] Q[1] D[2] ... ] to region 0.00u-417.68u at the TOP edge. -[INFO PPL-0067] Restrict pins [ clk we[0] addr_rw[0] addr_rw[1] addr_rw[2] ... ] to region 0.00u-8.16u at the RIGHT edge. -[INFO PPL-0001] Number of available slots 830 +[INFO PPL-0067] Restrict pins [ clk we[0] D[0] Q[0] D[1] ... ] to region 0.00u-419.98u at the TOP edge. +[INFO PPL-0067] Restrict pins [ addr_rw[0] addr_rw[1] addr_rw[2] ] to region 0.00u-8.16u at the RIGHT edge. +[INFO PPL-0001] Number of available slots 836 [INFO PPL-0002] Number of I/O 21 [INFO PPL-0003] Number of I/O w/sink 21 [INFO PPL-0004] Number of I/O w/o sink 0 [INFO PPL-0005] Slots per section 200 [INFO PPL-0008] Successfully assigned pins to sections. -[INFO PPL-0012] I/O nets HPWL: 990.17 um. -[INFO DPL-0001] Placed 120 filler instances. +[INFO PPL-0012] I/O nets HPWL: 945.54 um. +[INFO DPL-0001] Placed 122 filler instances. [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via @@ -41,13 +44,13 @@ [INFO DRT-0168] Init region query. [INFO DRT-0033] FR_MASTERSLICE shape region query size = 0. [INFO DRT-0033] FR_VIA shape region query size = 0. -[INFO DRT-0033] li1 shape region query size = 8229. -[INFO DRT-0033] mcon shape region query size = 600. -[INFO DRT-0033] met1 shape region query size = 1572. +[INFO DRT-0033] li1 shape region query size = 8307. +[INFO DRT-0033] mcon shape region query size = 606. +[INFO DRT-0033] met1 shape region query size = 1590. [INFO DRT-0033] via shape region query size = 166. -[INFO DRT-0033] met2 shape region query size = 514. +[INFO DRT-0033] met2 shape region query size = 516. [INFO DRT-0033] via2 shape region query size = 83. -[INFO DRT-0033] met3 shape region query size = 94. +[INFO DRT-0033] met3 shape region query size = 92. [INFO DRT-0033] via3 shape region query size = 0. [INFO DRT-0033] met4 shape region query size = 0. [INFO DRT-0033] via4 shape region query size = 0. @@ -55,18 +58,22 @@ [INFO DRT-0178] Init guide query. [INFO DRT-0036] FR_MASTERSLICE guide region query size = 0. [INFO DRT-0036] FR_VIA guide region query size = 0. -[INFO DRT-0036] li1 guide region query size = 440. +[INFO DRT-0036] li1 guide region query size = 449. [INFO DRT-0036] mcon guide region query size = 0. -[INFO DRT-0036] met1 guide region query size = 293. +[INFO DRT-0036] met1 guide region query size = 298. [INFO DRT-0036] via guide region query size = 0. [INFO DRT-0036] met2 guide region query size = 73. [INFO DRT-0036] via2 guide region query size = 0. -[INFO DRT-0036] met3 guide region query size = 45. +[INFO DRT-0036] met3 guide region query size = 43. [INFO DRT-0036] via3 guide region query size = 0. [INFO DRT-0036] met4 guide region query size = 0. [INFO DRT-0036] via4 guide region query size = 0. [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. -No differences found. -No differences found. +Differences found at line 180. + PIN VSS + PIN VDD +Differences found at line 1222. + + ROUTED met1 ( 8252 425 ) ( 8257 * ) + + ROUTED met1 ( 4802 425 ) ( 4807 * ) No differences found. diff --git a/src/ram/test/make_8x8_sky130.ok b/src/ram/test/make_8x8_sky130.ok index c7663b60793..d526f31e8ff 100644 --- a/src/ram/test/make_8x8_sky130.ok +++ b/src/ram/test/make_8x8_sky130.ok @@ -8,6 +8,9 @@ [INFO RAM-0016] Selected buffer cell sky130_fd_sc_hd__buf_1 [INFO RAM-0016] Selected aoi22 cell sky130_fd_sc_hd__a22oi_1 [INFO RAM-0024] Behavioral Verilog written for RAM8x8 +[INFO RAM-0044] RAM worst setup path delay: 0.879054 ns +[INFO RAM-0045] RAM worst hold path delay: 0.000000 ns +[INFO RAM-0046] RAM total power (no activity): 0.000233 W [INFO PDN-0001] Inserting grid: ram_grid [INFO PPL-0067] Restrict pins [ clk we[0] D[0] Q[0] D[1] ... ] to region 0.00u-110.40u at the TOP edge. [INFO PPL-0067] Restrict pins [ addr_rw[0] addr_rw[1] addr_rw[2] ] to region 0.00u-24.48u at the RIGHT edge. From 63c4cfb238581747a68c30c717996a3d0d14ab42 Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Wed, 1 Jul 2026 21:11:27 -0400 Subject: [PATCH 08/19] ram: update golden files and BUILD for all regression tests Signed-off-by: Thinh Nguyen --- src/ram/test/BUILD | 6 + src/ram/test/make_7x7_2r1w_nangate45.ok | 101 +- src/ram/test/make_8x8_2r1w_sky130.ok | 75 +- src/ram/test/make_8x8_latch_sky130.defok | 4100 +++++++++++----------- src/ram/test/make_8x8_latch_sky130.lefok | 157 +- src/ram/test/make_8x8_latch_sky130.ok | 8 +- src/ram/test/make_8x8_mux2_sky130.lefok | 74 +- src/ram/test/make_8x8_mux2_sky130.ok | 10 +- src/ram/test/make_8x8_mux4_sky130.lefok | 194 +- src/ram/test/make_8x8_mux4_sky130.ok | 10 +- 10 files changed, 2452 insertions(+), 2283 deletions(-) diff --git a/src/ram/test/BUILD b/src/ram/test/BUILD index 071fa2c0f0b..89370ad8d1b 100644 --- a/src/ram/test/BUILD +++ b/src/ram/test/BUILD @@ -9,6 +9,9 @@ COMPULSORY_TESTS = [ "make_7x7_2r1w_nangate45", "make_7x7_nangate45", "make_8x8_2r1w_sky130", + "make_8x8_latch_sky130", + "make_8x8_mux2_sky130", + "make_8x8_mux4_sky130", "make_8x8_sky130", ] @@ -64,6 +67,9 @@ filegroup( "Nangate45/Nangate45_typ.lib", ], "make_8x8_2r1w_sky130": ["make_8x8_2r1w_sky130_behavioral.vok"], + "make_8x8_latch_sky130": ["make_8x8_behavioral.vok"], + "make_8x8_mux2_sky130": ["make_8x8_behavioral.vok"], + "make_8x8_mux4_sky130": ["make_8x8_behavioral.vok"], "make_8x8_sky130": ["make_8x8_sky130_behavioral.vok"], }.get(test_name, []), ) diff --git a/src/ram/test/make_7x7_2r1w_nangate45.ok b/src/ram/test/make_7x7_2r1w_nangate45.ok index 0b519b0f428..b6e1eff205c 100644 --- a/src/ram/test/make_7x7_2r1w_nangate45.ok +++ b/src/ram/test/make_7x7_2r1w_nangate45.ok @@ -20,5 +20,102 @@ [WARNING ODB-0217] duplicate VIARULE (Via9Array-0) ignoring... [INFO ODB-0394] Duplicate site FreePDK45_38x28_10R_NP_162NW_34O in Nangate45 already seen in Nangate45_tech [INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 135 library cells -[ERROR STA-0562] generate_ram -power_pin is not a known keyword or flag. -Error: make_7x7_2r1w_nangate45.tcl, 27 STA-0562 +[INFO RAM-0003] Generating RAM7x7 +[INFO RAM-0016] Selected inverter cell INV_X1 +[INFO RAM-0016] Selected tristate cell TBUF_X1 +[INFO RAM-0016] Selected and2 cell AND2_X1 +[INFO RAM-0016] Selected clock gate cell CLKGATE_X1 +[INFO RAM-0016] Selected buffer cell BUF_X1 +[INFO RAM-0016] Selected aoi22 cell AOI22_X1 +[INFO RAM-0024] Behavioral Verilog written for RAM7x7 +[INFO RAM-0044] RAM worst setup path delay: 0.265428 ns +[INFO RAM-0045] RAM worst hold path delay: 0.000000 ns +[INFO RAM-0046] RAM total power (no activity): 0.000079 W +[INFO PDN-0001] Inserting grid: ram_grid +[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (4.5000 um, 4.0000 um) for VDD +[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (9.0000 um, 8.0000 um) for VSS +[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (13.5000 um, 4.0000 um) for VDD +[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (18.0000 um, 8.0000 um) for VSS +[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (22.5000 um, 4.0000 um) for VDD +[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (27.0000 um, 8.0000 um) for VSS +[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (31.5000 um, 4.0000 um) for VDD +[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (36.0000 um, 8.0000 um) for VSS +[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (40.5000 um, 4.0000 um) for VDD +[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (45.0000 um, 8.0000 um) for VSS +[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (49.5000 um, 4.0000 um) for VDD +[WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (54.0000 um, 8.0000 um) for VSS +[INFO PPL-0067] Restrict pins [ clk we[0] D[0] Q0[0] Q1[0] ... ] to region 0.00u-56.62u at the TOP edge. +[INFO PPL-0067] Restrict pins [ addr_w[0] addr_w[1] addr_w[2] addr_r0[0] addr_r0[1] ... ] to region 0.00u-11.20u at the RIGHT edge. +[INFO PPL-0001] Number of available slots 268 +[INFO PPL-0002] Number of I/O 32 +[INFO PPL-0003] Number of I/O w/sink 32 +[INFO PPL-0004] Number of I/O w/o sink 0 +[INFO PPL-0005] Slots per section 200 +[INFO PPL-0008] Successfully assigned pins to sections. +[INFO PPL-0012] I/O nets HPWL: 267.74 um. +[INFO DPL-0001] Placed 48 filler instances. +[INFO DRT-0167] List of default vias: + Layer via2 + default via: via2_5 + Layer via3 + default via: via3_2 + Layer via4 + default via: via4_0 + Layer via5 + default via: via5_0 + Layer via6 + default via: via6_0 + Layer via7 + default via: via7_0 + Layer via8 + default via: via8_0 + Layer via9 + default via: via9_0 +[INFO DRT-0168] Init region query. +[INFO DRT-0033] active shape region query size = 0. +[INFO DRT-0033] FR_VIA shape region query size = 0. +[INFO DRT-0033] metal1 shape region query size = 6959. +[INFO DRT-0033] via1 shape region query size = 54. +[INFO DRT-0033] metal2 shape region query size = 108. +[INFO DRT-0033] via2 shape region query size = 54. +[INFO DRT-0033] metal3 shape region query size = 117. +[INFO DRT-0033] via3 shape region query size = 54. +[INFO DRT-0033] metal4 shape region query size = 113. +[INFO DRT-0033] via4 shape region query size = 0. +[INFO DRT-0033] metal5 shape region query size = 0. +[INFO DRT-0033] via5 shape region query size = 0. +[INFO DRT-0033] metal6 shape region query size = 0. +[INFO DRT-0033] via6 shape region query size = 0. +[INFO DRT-0033] metal7 shape region query size = 0. +[INFO DRT-0033] via7 shape region query size = 0. +[INFO DRT-0033] metal8 shape region query size = 0. +[INFO DRT-0033] via8 shape region query size = 0. +[INFO DRT-0033] metal9 shape region query size = 0. +[INFO DRT-0033] via9 shape region query size = 0. +[INFO DRT-0033] metal10 shape region query size = 0. +[INFO DRT-0178] Init guide query. +[INFO DRT-0036] active guide region query size = 0. +[INFO DRT-0036] FR_VIA guide region query size = 0. +[INFO DRT-0036] metal1 guide region query size = 496. +[INFO DRT-0036] via1 guide region query size = 0. +[INFO DRT-0036] metal2 guide region query size = 430. +[INFO DRT-0036] via2 guide region query size = 0. +[INFO DRT-0036] metal3 guide region query size = 269. +[INFO DRT-0036] via3 guide region query size = 0. +[INFO DRT-0036] metal4 guide region query size = 23. +[INFO DRT-0036] via4 guide region query size = 0. +[INFO DRT-0036] metal5 guide region query size = 0. +[INFO DRT-0036] via5 guide region query size = 0. +[INFO DRT-0036] metal6 guide region query size = 0. +[INFO DRT-0036] via6 guide region query size = 0. +[INFO DRT-0036] metal7 guide region query size = 0. +[INFO DRT-0036] via7 guide region query size = 0. +[INFO DRT-0036] metal8 guide region query size = 0. +[INFO DRT-0036] via8 guide region query size = 0. +[INFO DRT-0036] metal9 guide region query size = 0. +[INFO DRT-0036] via9 guide region query size = 0. +[INFO DRT-0036] metal10 guide region query size = 0. +[INFO DRT-0179] Init gr pin query. +No differences found. +No differences found. +No differences found. diff --git a/src/ram/test/make_8x8_2r1w_sky130.ok b/src/ram/test/make_8x8_2r1w_sky130.ok index da5cfb63cac..c3571893cf2 100644 --- a/src/ram/test/make_8x8_2r1w_sky130.ok +++ b/src/ram/test/make_8x8_2r1w_sky130.ok @@ -1,4 +1,75 @@ [INFO ODB-0227] LEF file: sky130hd/sky130hd.tlef, created 13 layers, 25 vias [INFO ODB-0227] LEF file: sky130hd/sky130_fd_sc_hd_merged.lef, created 437 library cells -[ERROR STA-0562] generate_ram -power_pin is not a known keyword or flag. -Error: make_8x8_2r1w_sky130.tcl, 28 STA-0562 +[INFO RAM-0003] Generating RAM8x8 +[INFO RAM-0016] Selected inverter cell sky130_fd_sc_hd__clkinv_1 +[INFO RAM-0016] Selected tristate cell sky130_fd_sc_hd__ebufn_1 +[INFO RAM-0016] Selected and2 cell sky130_fd_sc_hd__and2_0 +[INFO RAM-0016] Selected clock gate cell sky130_fd_sc_hd__dlclkp_1 +[INFO RAM-0016] Selected buffer cell sky130_fd_sc_hd__buf_1 +[INFO RAM-0016] Selected aoi22 cell sky130_fd_sc_hd__a22oi_1 +[INFO RAM-0024] Behavioral Verilog written for RAM8x8 +[INFO RAM-0044] RAM worst setup path delay: 0.858868 ns +[INFO RAM-0045] RAM worst hold path delay: 0.000000 ns +[INFO RAM-0046] RAM total power (no activity): 0.000360 W +[INFO PDN-0001] Inserting grid: ram_grid +[INFO PPL-0067] Restrict pins [ clk we[0] D[0] Q0[0] Q1[0] ... ] to region 0.00u-155.02u at the TOP edge. +[INFO PPL-0067] Restrict pins [ addr_w[0] addr_w[1] addr_w[2] addr_r0[0] addr_r0[1] ... ] to region 0.00u-24.48u at the RIGHT edge. +[INFO PPL-0001] Number of available slots 364 +[INFO PPL-0002] Number of I/O 35 +[INFO PPL-0003] Number of I/O w/sink 35 +[INFO PPL-0004] Number of I/O w/o sink 0 +[INFO PPL-0005] Slots per section 200 +[INFO PPL-0008] Successfully assigned pins to sections. +[INFO PPL-0012] I/O nets HPWL: 686.60 um. +[INFO DPL-0001] Placed 60 filler instances. +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2 +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2 +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3 +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3 +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4 +[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4 +[INFO DRT-0167] List of default vias: + Layer via + default via: M1M2_PR + Layer via2 + default via: M2M3_PR + Layer via3 + default via: M3M4_PR + Layer via4 + default via: M4M5_PR +[INFO DRT-0168] Init region query. +[INFO DRT-0033] FR_MASTERSLICE shape region query size = 0. +[INFO DRT-0033] FR_VIA shape region query size = 0. +[INFO DRT-0033] li1 shape region query size = 10291. +[INFO DRT-0033] mcon shape region query size = 582. +[INFO DRT-0033] met1 shape region query size = 1561. +[INFO DRT-0033] via shape region query size = 35. +[INFO DRT-0033] met2 shape region query size = 89. +[INFO DRT-0033] via2 shape region query size = 7. +[INFO DRT-0033] met3 shape region query size = 22. +[INFO DRT-0033] via3 shape region query size = 0. +[INFO DRT-0033] met4 shape region query size = 0. +[INFO DRT-0033] via4 shape region query size = 0. +[INFO DRT-0033] met5 shape region query size = 0. +[INFO DRT-0178] Init guide query. +[INFO DRT-0036] FR_MASTERSLICE guide region query size = 0. +[INFO DRT-0036] FR_VIA guide region query size = 0. +[INFO DRT-0036] li1 guide region query size = 582. +[INFO DRT-0036] mcon guide region query size = 0. +[INFO DRT-0036] met1 guide region query size = 393. +[INFO DRT-0036] via guide region query size = 0. +[INFO DRT-0036] met2 guide region query size = 145. +[INFO DRT-0036] via2 guide region query size = 0. +[INFO DRT-0036] met3 guide region query size = 39. +[INFO DRT-0036] via3 guide region query size = 0. +[INFO DRT-0036] met4 guide region query size = 0. +[INFO DRT-0036] via4 guide region query size = 0. +[INFO DRT-0036] met5 guide region query size = 0. +[INFO DRT-0179] Init gr pin query. +No differences found. +No differences found. +No differences found. diff --git a/src/ram/test/make_8x8_latch_sky130.defok b/src/ram/test/make_8x8_latch_sky130.defok index e13f27e12d0..30e7c486ba9 100644 --- a/src/ram/test/make_8x8_latch_sky130.defok +++ b/src/ram/test/make_8x8_latch_sky130.defok @@ -3,28 +3,28 @@ DIVIDERCHAR "/" ; BUSBITCHARS "[]" ; DESIGN RAM8x8 ; UNITS DISTANCE MICRONS 100 ; -DIEAREA ( 0 0 ) ( 9568 2720 ) ; -ROW RAM_ROW0 unithd 0 0 N DO 208 BY 1 STEP 46 0 ; -ROW RAM_ROW1 unithd 0 272 FS DO 208 BY 1 STEP 46 0 ; -ROW RAM_ROW2 unithd 0 544 N DO 208 BY 1 STEP 46 0 ; -ROW RAM_ROW3 unithd 0 816 FS DO 208 BY 1 STEP 46 0 ; -ROW RAM_ROW4 unithd 0 1088 N DO 208 BY 1 STEP 46 0 ; -ROW RAM_ROW5 unithd 0 1360 FS DO 208 BY 1 STEP 46 0 ; -ROW RAM_ROW6 unithd 0 1632 N DO 208 BY 1 STEP 46 0 ; -ROW RAM_ROW7 unithd 0 1904 FS DO 208 BY 1 STEP 46 0 ; -ROW RAM_ROW8 unithd 0 2176 N DO 208 BY 1 STEP 46 0 ; -ROW RAM_ROW9 unithd 0 2448 FS DO 208 BY 1 STEP 46 0 ; -TRACKS X 23 DO 208 STEP 46 LAYER li1 ; +DIEAREA ( 0 0 ) ( 9200 2720 ) ; +ROW RAM_ROW0 unithd 0 0 N DO 200 BY 1 STEP 46 0 ; +ROW RAM_ROW1 unithd 0 272 FS DO 200 BY 1 STEP 46 0 ; +ROW RAM_ROW2 unithd 0 544 N DO 200 BY 1 STEP 46 0 ; +ROW RAM_ROW3 unithd 0 816 FS DO 200 BY 1 STEP 46 0 ; +ROW RAM_ROW4 unithd 0 1088 N DO 200 BY 1 STEP 46 0 ; +ROW RAM_ROW5 unithd 0 1360 FS DO 200 BY 1 STEP 46 0 ; +ROW RAM_ROW6 unithd 0 1632 N DO 200 BY 1 STEP 46 0 ; +ROW RAM_ROW7 unithd 0 1904 FS DO 200 BY 1 STEP 46 0 ; +ROW RAM_ROW8 unithd 0 2176 N DO 200 BY 1 STEP 46 0 ; +ROW RAM_ROW9 unithd 0 2448 FS DO 200 BY 1 STEP 46 0 ; +TRACKS X 23 DO 200 STEP 46 LAYER li1 ; TRACKS Y 17 DO 80 STEP 34 LAYER li1 ; -TRACKS X 17 DO 281 STEP 34 LAYER met1 ; +TRACKS X 17 DO 270 STEP 34 LAYER met1 ; TRACKS Y 17 DO 80 STEP 34 LAYER met1 ; -TRACKS X 23 DO 208 STEP 46 LAYER met2 ; +TRACKS X 23 DO 200 STEP 46 LAYER met2 ; TRACKS Y 23 DO 59 STEP 46 LAYER met2 ; -TRACKS X 34 DO 140 STEP 68 LAYER met3 ; +TRACKS X 34 DO 135 STEP 68 LAYER met3 ; TRACKS Y 34 DO 40 STEP 68 LAYER met3 ; -TRACKS X 46 DO 104 STEP 92 LAYER met4 ; +TRACKS X 46 DO 100 STEP 92 LAYER met4 ; TRACKS Y 46 DO 29 STEP 92 LAYER met4 ; -TRACKS X 170 DO 28 STEP 340 LAYER met5 ; +TRACKS X 170 DO 27 STEP 340 LAYER met5 ; TRACKS Y 170 DO 8 STEP 340 LAYER met5 ; GCELLGRID X 0 DO 13 STEP 690 ; GCELLGRID Y 0 DO 3 STEP 690 ; @@ -32,259 +32,251 @@ VIAS 2 ; - via2_3_480_480_1_1_320_320 + VIARULE M1M2_PR + CUTSIZE 15 15 + LAYERS met1 via met2 + CUTSPACING 17 17 + ENCLOSURE 8 16 16 8 ; - via3_4_480_480_1_1_400_400 + VIARULE M2M3_PR + CUTSIZE 20 20 + LAYERS met2 via2 met3 + CUTSPACING 20 20 + ENCLOSURE 14 8 6 14 ; END VIAS -COMPONENTS 352 ; - - FILLER_1_205 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 9430 272 ) FS ; - - FILLER_1_207 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9522 272 ) FS ; - - FILLER_3_205 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 9430 816 ) FS ; - - FILLER_3_207 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9522 816 ) FS ; - - FILLER_5_205 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 9430 1360 ) FS ; - - FILLER_5_207 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9522 1360 ) FS ; - - FILLER_6_205 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 9430 1632 ) N ; - - FILLER_6_207 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9522 1632 ) N ; - - FILLER_7_205 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 9430 1904 ) FS ; - - FILLER_7_207 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9522 1904 ) FS ; - - FILLER_8_118 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 5428 2176 ) N ; - - FILLER_8_13 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 598 2176 ) N ; - - FILLER_8_139 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 6394 2176 ) N ; - - FILLER_8_160 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 7360 2176 ) N ; +COMPONENTS 344 ; + - FILLER_1_197 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 9062 272 ) FS ; + - FILLER_1_199 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9154 272 ) FS ; + - FILLER_3_197 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 9062 816 ) FS ; + - FILLER_3_199 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9154 816 ) FS ; + - FILLER_5_197 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 9062 1360 ) FS ; + - FILLER_5_199 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9154 1360 ) FS ; + - FILLER_6_197 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 9062 1632 ) N ; + - FILLER_6_199 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9154 1632 ) N ; + - FILLER_7_197 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 9062 1904 ) FS ; + - FILLER_7_199 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9154 1904 ) FS ; + - FILLER_8_112 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 5152 2176 ) N ; + - FILLER_8_12 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 552 2176 ) N ; + - FILLER_8_132 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 6072 2176 ) N ; + - FILLER_8_152 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 6992 2176 ) N ; + - FILLER_8_164 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 7544 2176 ) N ; - FILLER_8_172 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 7912 2176 ) N ; - - FILLER_8_180 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 8280 2176 ) N ; - - FILLER_8_188 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 8648 2176 ) N ; - - FILLER_8_192 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 8832 2176 ) N ; - - FILLER_8_195 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 8970 2176 ) N ; - - FILLER_8_203 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 9338 2176 ) N ; - - FILLER_8_207 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9522 2176 ) N ; - - FILLER_8_34 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 1564 2176 ) N ; - - FILLER_8_55 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 2530 2176 ) N ; - - FILLER_8_76 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 3496 2176 ) N ; - - FILLER_8_97 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 4462 2176 ) N ; - - FILLER_9_104 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 4784 2448 ) FS ; - - FILLER_9_109 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 5014 2448 ) FS ; - - FILLER_9_117 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 5382 2448 ) FS ; + - FILLER_8_180 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 8280 2176 ) N ; + - FILLER_8_184 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 8464 2176 ) N ; + - FILLER_8_187 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 8602 2176 ) N ; + - FILLER_8_195 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 8970 2176 ) N ; + - FILLER_8_199 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9154 2176 ) N ; + - FILLER_8_32 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 1472 2176 ) N ; + - FILLER_8_52 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 2392 2176 ) N ; + - FILLER_8_72 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 3312 2176 ) N ; + - FILLER_8_92 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 4232 2176 ) N ; + - FILLER_9_104 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 4784 2448 ) FS ; + - FILLER_9_112 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 5152 2448 ) FS ; - FILLER_9_12 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 552 2448 ) FS ; - - FILLER_9_125 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 5750 2448 ) FS ; - - FILLER_9_130 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 5980 2448 ) FS ; - - FILLER_9_138 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 6348 2448 ) FS ; - - FILLER_9_146 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 6716 2448 ) FS ; - - FILLER_9_151 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 6946 2448 ) FS ; - - FILLER_9_159 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 7314 2448 ) FS ; - - FILLER_9_167 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 7682 2448 ) FS ; + - FILLER_9_124 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 5704 2448 ) FS ; + - FILLER_9_132 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 6072 2448 ) FS ; + - FILLER_9_144 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 6624 2448 ) FS ; + - FILLER_9_152 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 6992 2448 ) FS ; + - FILLER_9_161 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 7406 2448 ) FS ; - FILLER_9_169 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 7774 2448 ) FS ; - FILLER_9_177 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 8142 2448 ) FS ; - - FILLER_9_185 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 8510 2448 ) FS ; - - FILLER_9_193 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 8878 2448 ) FS ; - - FILLER_9_195 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 8970 2448 ) FS ; - - FILLER_9_20 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 920 2448 ) FS ; - - FILLER_9_203 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 9338 2448 ) FS ; - - FILLER_9_207 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9522 2448 ) FS ; - - FILLER_9_25 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 1150 2448 ) FS ; - - FILLER_9_33 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 1518 2448 ) FS ; + - FILLER_9_185 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 8510 2448 ) FS ; + - FILLER_9_187 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 8602 2448 ) FS ; + - FILLER_9_195 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 8970 2448 ) FS ; + - FILLER_9_199 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9154 2448 ) FS ; + - FILLER_9_24 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 1104 2448 ) FS ; + - FILLER_9_32 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 1472 2448 ) FS ; - FILLER_9_4 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 184 2448 ) FS ; - - FILLER_9_41 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 1886 2448 ) FS ; - - FILLER_9_46 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 2116 2448 ) FS ; - - FILLER_9_54 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 2484 2448 ) FS ; - - FILLER_9_62 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 2852 2448 ) FS ; - - FILLER_9_67 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 3082 2448 ) FS ; - - FILLER_9_75 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 3450 2448 ) FS ; - - FILLER_9_83 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 3818 2448 ) FS ; - - FILLER_9_88 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 4048 2448 ) FS ; - - FILLER_9_96 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 4416 2448 ) FS ; + - FILLER_9_44 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 2024 2448 ) FS ; + - FILLER_9_52 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 2392 2448 ) FS ; + - FILLER_9_64 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 2944 2448 ) FS ; + - FILLER_9_72 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 3312 2448 ) FS ; + - FILLER_9_84 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 3864 2448 ) FS ; + - FILLER_9_92 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 4232 2448 ) FS ; - buffer.in[0] sky130_fd_sc_hd__buf_1 + PLACED ( 46 2448 ) FS ; - - buffer.in[1] sky130_fd_sc_hd__buf_1 + PLACED ( 1012 2448 ) FS ; - - buffer.in[2] sky130_fd_sc_hd__buf_1 + PLACED ( 1978 2448 ) FS ; - - buffer.in[3] sky130_fd_sc_hd__buf_1 + PLACED ( 2944 2448 ) FS ; - - buffer.in[4] sky130_fd_sc_hd__buf_1 + PLACED ( 3910 2448 ) FS ; - - buffer.in[5] sky130_fd_sc_hd__buf_1 + PLACED ( 4876 2448 ) FS ; - - buffer.in[6] sky130_fd_sc_hd__buf_1 + PLACED ( 5842 2448 ) FS ; - - buffer.in[7] sky130_fd_sc_hd__buf_1 + PLACED ( 6808 2448 ) FS ; - - decoder_p0.and_layer0_word0 sky130_fd_sc_hd__and2_0 + PLACED ( 8970 0 ) N ; - - decoder_p0.and_layer0_word1 sky130_fd_sc_hd__and2_0 + PLACED ( 8970 272 ) FS ; - - decoder_p0.and_layer0_word2 sky130_fd_sc_hd__and2_0 + PLACED ( 8970 544 ) N ; - - decoder_p0.and_layer0_word3 sky130_fd_sc_hd__and2_0 + PLACED ( 8970 816 ) FS ; - - decoder_p0.and_layer0_word4 sky130_fd_sc_hd__and2_0 + PLACED ( 8970 1088 ) N ; - - decoder_p0.and_layer0_word5 sky130_fd_sc_hd__and2_0 + PLACED ( 8970 1360 ) FS ; - - decoder_p0.and_layer0_word6 sky130_fd_sc_hd__and2_0 + PLACED ( 8970 1632 ) N ; - - decoder_p0.and_layer0_word7 sky130_fd_sc_hd__and2_0 + PLACED ( 8970 1904 ) FS ; - - decoder_p0.and_layer1_word0 sky130_fd_sc_hd__and2_0 + PLACED ( 9200 0 ) N ; - - decoder_p0.and_layer1_word1 sky130_fd_sc_hd__and2_0 + PLACED ( 9200 272 ) FS ; - - decoder_p0.and_layer1_word2 sky130_fd_sc_hd__and2_0 + PLACED ( 9200 544 ) N ; - - decoder_p0.and_layer1_word3 sky130_fd_sc_hd__and2_0 + PLACED ( 9200 816 ) FS ; - - decoder_p0.and_layer1_word4 sky130_fd_sc_hd__and2_0 + PLACED ( 9200 1088 ) N ; - - decoder_p0.and_layer1_word5 sky130_fd_sc_hd__and2_0 + PLACED ( 9200 1360 ) FS ; - - decoder_p0.and_layer1_word6 sky130_fd_sc_hd__and2_0 + PLACED ( 9200 1632 ) N ; - - decoder_p0.and_layer1_word7 sky130_fd_sc_hd__and2_0 + PLACED ( 9200 1904 ) FS ; - - decoder_p0.inv_p0_a0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 9430 1088 ) N ; - - decoder_p0.inv_p0_a1 sky130_fd_sc_hd__clkinv_1 + PLACED ( 9430 544 ) N ; - - decoder_p0.inv_p0_a2 sky130_fd_sc_hd__clkinv_1 + PLACED ( 9430 0 ) N ; - - neg_lat_b0.nlat sky130_fd_sc_hd__dlxtp_1 + PLACED ( 46 2176 ) N ; - - neg_lat_b1.nlat sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1012 2176 ) N ; - - neg_lat_b2.nlat sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1978 2176 ) N ; - - neg_lat_b3.nlat sky130_fd_sc_hd__dlxtp_1 + PLACED ( 2944 2176 ) N ; - - neg_lat_b4.nlat sky130_fd_sc_hd__dlxtp_1 + PLACED ( 3910 2176 ) N ; - - neg_lat_b5.nlat sky130_fd_sc_hd__dlxtp_1 + PLACED ( 4876 2176 ) N ; - - neg_lat_b6.nlat sky130_fd_sc_hd__dlxtp_1 + PLACED ( 5842 2176 ) N ; - - neg_lat_b7.nlat sky130_fd_sc_hd__dlxtp_1 + PLACED ( 6808 2176 ) N ; - - neg_row.clk_inv sky130_fd_sc_hd__clkinv_1 + PLACED ( 7774 2176 ) N ; - - sel_buf_rw_p0.sel_buf_0 sky130_fd_sc_hd__buf_1 + PLACED ( 8786 0 ) N ; - - sel_buf_rw_p0.sel_buf_1 sky130_fd_sc_hd__buf_1 + PLACED ( 8786 272 ) FS ; - - sel_buf_rw_p0.sel_buf_2 sky130_fd_sc_hd__buf_1 + PLACED ( 8786 544 ) N ; - - sel_buf_rw_p0.sel_buf_3 sky130_fd_sc_hd__buf_1 + PLACED ( 8786 816 ) FS ; - - sel_buf_rw_p0.sel_buf_4 sky130_fd_sc_hd__buf_1 + PLACED ( 8786 1088 ) N ; - - sel_buf_rw_p0.sel_buf_5 sky130_fd_sc_hd__buf_1 + PLACED ( 8786 1360 ) FS ; - - sel_buf_rw_p0.sel_buf_6 sky130_fd_sc_hd__buf_1 + PLACED ( 8786 1632 ) N ; - - sel_buf_rw_p0.sel_buf_7 sky130_fd_sc_hd__buf_1 + PLACED ( 8786 1904 ) FS ; - - storage_0_0_0.bit0.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 46 0 ) N ; - - storage_0_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 598 0 ) N ; - - storage_0_0_0.bit1.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1012 0 ) N ; - - storage_0_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1564 0 ) N ; - - storage_0_0_0.bit2.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1978 0 ) N ; - - storage_0_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2530 0 ) N ; - - storage_0_0_0.bit3.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 2944 0 ) N ; - - storage_0_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3496 0 ) N ; - - storage_0_0_0.bit4.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 3910 0 ) N ; - - storage_0_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4462 0 ) N ; - - storage_0_0_0.bit5.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 4876 0 ) N ; - - storage_0_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5428 0 ) N ; - - storage_0_0_0.bit6.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 5842 0 ) N ; - - storage_0_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6394 0 ) N ; - - storage_0_0_0.bit7.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 6808 0 ) N ; - - storage_0_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7360 0 ) N ; - - storage_0_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7774 0 ) N ; - - storage_0_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8418 0 ) N ; - - storage_0_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8648 0 ) N ; - - storage_1_0_0.bit0.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 46 272 ) FS ; - - storage_1_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 598 272 ) FS ; - - storage_1_0_0.bit1.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1012 272 ) FS ; - - storage_1_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1564 272 ) FS ; - - storage_1_0_0.bit2.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1978 272 ) FS ; - - storage_1_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2530 272 ) FS ; - - storage_1_0_0.bit3.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 2944 272 ) FS ; - - storage_1_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3496 272 ) FS ; - - storage_1_0_0.bit4.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 3910 272 ) FS ; - - storage_1_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4462 272 ) FS ; - - storage_1_0_0.bit5.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 4876 272 ) FS ; - - storage_1_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5428 272 ) FS ; - - storage_1_0_0.bit6.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 5842 272 ) FS ; - - storage_1_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6394 272 ) FS ; - - storage_1_0_0.bit7.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 6808 272 ) FS ; - - storage_1_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7360 272 ) FS ; - - storage_1_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7774 272 ) FS ; - - storage_1_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8418 272 ) FS ; - - storage_1_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8648 272 ) FS ; - - storage_2_0_0.bit0.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 46 544 ) N ; - - storage_2_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 598 544 ) N ; - - storage_2_0_0.bit1.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1012 544 ) N ; - - storage_2_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1564 544 ) N ; - - storage_2_0_0.bit2.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1978 544 ) N ; - - storage_2_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2530 544 ) N ; - - storage_2_0_0.bit3.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 2944 544 ) N ; - - storage_2_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3496 544 ) N ; - - storage_2_0_0.bit4.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 3910 544 ) N ; - - storage_2_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4462 544 ) N ; - - storage_2_0_0.bit5.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 4876 544 ) N ; - - storage_2_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5428 544 ) N ; - - storage_2_0_0.bit6.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 5842 544 ) N ; - - storage_2_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6394 544 ) N ; - - storage_2_0_0.bit7.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 6808 544 ) N ; - - storage_2_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7360 544 ) N ; - - storage_2_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7774 544 ) N ; - - storage_2_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8418 544 ) N ; - - storage_2_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8648 544 ) N ; - - storage_3_0_0.bit0.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 46 816 ) FS ; - - storage_3_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 598 816 ) FS ; - - storage_3_0_0.bit1.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1012 816 ) FS ; - - storage_3_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1564 816 ) FS ; - - storage_3_0_0.bit2.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1978 816 ) FS ; - - storage_3_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2530 816 ) FS ; - - storage_3_0_0.bit3.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 2944 816 ) FS ; - - storage_3_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3496 816 ) FS ; - - storage_3_0_0.bit4.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 3910 816 ) FS ; - - storage_3_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4462 816 ) FS ; - - storage_3_0_0.bit5.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 4876 816 ) FS ; - - storage_3_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5428 816 ) FS ; - - storage_3_0_0.bit6.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 5842 816 ) FS ; - - storage_3_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6394 816 ) FS ; - - storage_3_0_0.bit7.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 6808 816 ) FS ; - - storage_3_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7360 816 ) FS ; - - storage_3_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7774 816 ) FS ; - - storage_3_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8418 816 ) FS ; - - storage_3_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8648 816 ) FS ; - - storage_4_0_0.bit0.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 46 1088 ) N ; - - storage_4_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 598 1088 ) N ; - - storage_4_0_0.bit1.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1012 1088 ) N ; - - storage_4_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1564 1088 ) N ; - - storage_4_0_0.bit2.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1978 1088 ) N ; - - storage_4_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2530 1088 ) N ; - - storage_4_0_0.bit3.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 2944 1088 ) N ; - - storage_4_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3496 1088 ) N ; - - storage_4_0_0.bit4.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 3910 1088 ) N ; - - storage_4_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4462 1088 ) N ; - - storage_4_0_0.bit5.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 4876 1088 ) N ; - - storage_4_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5428 1088 ) N ; - - storage_4_0_0.bit6.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 5842 1088 ) N ; - - storage_4_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6394 1088 ) N ; - - storage_4_0_0.bit7.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 6808 1088 ) N ; - - storage_4_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7360 1088 ) N ; - - storage_4_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7774 1088 ) N ; - - storage_4_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8418 1088 ) N ; - - storage_4_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8648 1088 ) N ; - - storage_5_0_0.bit0.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 46 1360 ) FS ; - - storage_5_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 598 1360 ) FS ; - - storage_5_0_0.bit1.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1012 1360 ) FS ; - - storage_5_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1564 1360 ) FS ; - - storage_5_0_0.bit2.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1978 1360 ) FS ; - - storage_5_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2530 1360 ) FS ; - - storage_5_0_0.bit3.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 2944 1360 ) FS ; - - storage_5_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3496 1360 ) FS ; - - storage_5_0_0.bit4.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 3910 1360 ) FS ; - - storage_5_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4462 1360 ) FS ; - - storage_5_0_0.bit5.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 4876 1360 ) FS ; - - storage_5_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5428 1360 ) FS ; - - storage_5_0_0.bit6.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 5842 1360 ) FS ; - - storage_5_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6394 1360 ) FS ; - - storage_5_0_0.bit7.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 6808 1360 ) FS ; - - storage_5_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7360 1360 ) FS ; - - storage_5_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7774 1360 ) FS ; - - storage_5_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8418 1360 ) FS ; - - storage_5_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8648 1360 ) FS ; - - storage_6_0_0.bit0.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 46 1632 ) N ; - - storage_6_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 598 1632 ) N ; - - storage_6_0_0.bit1.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1012 1632 ) N ; - - storage_6_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1564 1632 ) N ; - - storage_6_0_0.bit2.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1978 1632 ) N ; - - storage_6_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2530 1632 ) N ; - - storage_6_0_0.bit3.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 2944 1632 ) N ; - - storage_6_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3496 1632 ) N ; - - storage_6_0_0.bit4.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 3910 1632 ) N ; - - storage_6_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4462 1632 ) N ; - - storage_6_0_0.bit5.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 4876 1632 ) N ; - - storage_6_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5428 1632 ) N ; - - storage_6_0_0.bit6.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 5842 1632 ) N ; - - storage_6_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6394 1632 ) N ; - - storage_6_0_0.bit7.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 6808 1632 ) N ; - - storage_6_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7360 1632 ) N ; - - storage_6_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7774 1632 ) N ; - - storage_6_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8418 1632 ) N ; - - storage_6_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8648 1632 ) N ; - - storage_7_0_0.bit0.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 46 1904 ) FS ; - - storage_7_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 598 1904 ) FS ; - - storage_7_0_0.bit1.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1012 1904 ) FS ; - - storage_7_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1564 1904 ) FS ; - - storage_7_0_0.bit2.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1978 1904 ) FS ; - - storage_7_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2530 1904 ) FS ; - - storage_7_0_0.bit3.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 2944 1904 ) FS ; - - storage_7_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3496 1904 ) FS ; - - storage_7_0_0.bit4.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 3910 1904 ) FS ; - - storage_7_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4462 1904 ) FS ; - - storage_7_0_0.bit5.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 4876 1904 ) FS ; - - storage_7_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5428 1904 ) FS ; - - storage_7_0_0.bit6.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 5842 1904 ) FS ; - - storage_7_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6394 1904 ) FS ; - - storage_7_0_0.bit7.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 6808 1904 ) FS ; - - storage_7_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7360 1904 ) FS ; - - storage_7_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7774 1904 ) FS ; - - storage_7_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8418 1904 ) FS ; - - storage_7_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8648 1904 ) FS ; + - buffer.in[1] sky130_fd_sc_hd__buf_1 + PLACED ( 966 2448 ) FS ; + - buffer.in[2] sky130_fd_sc_hd__buf_1 + PLACED ( 1886 2448 ) FS ; + - buffer.in[3] sky130_fd_sc_hd__buf_1 + PLACED ( 2806 2448 ) FS ; + - buffer.in[4] sky130_fd_sc_hd__buf_1 + PLACED ( 3726 2448 ) FS ; + - buffer.in[5] sky130_fd_sc_hd__buf_1 + PLACED ( 4646 2448 ) FS ; + - buffer.in[6] sky130_fd_sc_hd__buf_1 + PLACED ( 5566 2448 ) FS ; + - buffer.in[7] sky130_fd_sc_hd__buf_1 + PLACED ( 6486 2448 ) FS ; + - decoder_p0.and_layer0_word0 sky130_fd_sc_hd__and2_0 + PLACED ( 8602 0 ) N ; + - decoder_p0.and_layer0_word1 sky130_fd_sc_hd__and2_0 + PLACED ( 8602 272 ) FS ; + - decoder_p0.and_layer0_word2 sky130_fd_sc_hd__and2_0 + PLACED ( 8602 544 ) N ; + - decoder_p0.and_layer0_word3 sky130_fd_sc_hd__and2_0 + PLACED ( 8602 816 ) FS ; + - decoder_p0.and_layer0_word4 sky130_fd_sc_hd__and2_0 + PLACED ( 8602 1088 ) N ; + - decoder_p0.and_layer0_word5 sky130_fd_sc_hd__and2_0 + PLACED ( 8602 1360 ) FS ; + - decoder_p0.and_layer0_word6 sky130_fd_sc_hd__and2_0 + PLACED ( 8602 1632 ) N ; + - decoder_p0.and_layer0_word7 sky130_fd_sc_hd__and2_0 + PLACED ( 8602 1904 ) FS ; + - decoder_p0.and_layer1_word0 sky130_fd_sc_hd__and2_0 + PLACED ( 8832 0 ) N ; + - decoder_p0.and_layer1_word1 sky130_fd_sc_hd__and2_0 + PLACED ( 8832 272 ) FS ; + - decoder_p0.and_layer1_word2 sky130_fd_sc_hd__and2_0 + PLACED ( 8832 544 ) N ; + - decoder_p0.and_layer1_word3 sky130_fd_sc_hd__and2_0 + PLACED ( 8832 816 ) FS ; + - decoder_p0.and_layer1_word4 sky130_fd_sc_hd__and2_0 + PLACED ( 8832 1088 ) N ; + - decoder_p0.and_layer1_word5 sky130_fd_sc_hd__and2_0 + PLACED ( 8832 1360 ) FS ; + - decoder_p0.and_layer1_word6 sky130_fd_sc_hd__and2_0 + PLACED ( 8832 1632 ) N ; + - decoder_p0.and_layer1_word7 sky130_fd_sc_hd__and2_0 + PLACED ( 8832 1904 ) FS ; + - decoder_p0.inv_p0_a0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 9062 1088 ) N ; + - decoder_p0.inv_p0_a1 sky130_fd_sc_hd__clkinv_1 + PLACED ( 9062 544 ) N ; + - decoder_p0.inv_p0_a2 sky130_fd_sc_hd__clkinv_1 + PLACED ( 9062 0 ) N ; + - neg_lat_b0.nlat sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 46 2176 ) N ; + - neg_lat_b1.nlat sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 966 2176 ) N ; + - neg_lat_b2.nlat sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 1886 2176 ) N ; + - neg_lat_b3.nlat sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 2806 2176 ) N ; + - neg_lat_b4.nlat sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 3726 2176 ) N ; + - neg_lat_b5.nlat sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 4646 2176 ) N ; + - neg_lat_b6.nlat sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 5566 2176 ) N ; + - neg_lat_b7.nlat sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 6486 2176 ) N ; + - neg_row.clk_inv sky130_fd_sc_hd__clkinv_1 + PLACED ( 7406 2176 ) N ; + - sel_buf_rw_p0.sel_buf_0 sky130_fd_sc_hd__buf_1 + PLACED ( 8418 0 ) N ; + - sel_buf_rw_p0.sel_buf_1 sky130_fd_sc_hd__buf_1 + PLACED ( 8418 272 ) FS ; + - sel_buf_rw_p0.sel_buf_2 sky130_fd_sc_hd__buf_1 + PLACED ( 8418 544 ) N ; + - sel_buf_rw_p0.sel_buf_3 sky130_fd_sc_hd__buf_1 + PLACED ( 8418 816 ) FS ; + - sel_buf_rw_p0.sel_buf_4 sky130_fd_sc_hd__buf_1 + PLACED ( 8418 1088 ) N ; + - sel_buf_rw_p0.sel_buf_5 sky130_fd_sc_hd__buf_1 + PLACED ( 8418 1360 ) FS ; + - sel_buf_rw_p0.sel_buf_6 sky130_fd_sc_hd__buf_1 + PLACED ( 8418 1632 ) N ; + - sel_buf_rw_p0.sel_buf_7 sky130_fd_sc_hd__buf_1 + PLACED ( 8418 1904 ) FS ; + - storage_0_0_0.bit0.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 46 0 ) N ; + - storage_0_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 552 0 ) N ; + - storage_0_0_0.bit1.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 966 0 ) N ; + - storage_0_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1472 0 ) N ; + - storage_0_0_0.bit2.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 1886 0 ) N ; + - storage_0_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2392 0 ) N ; + - storage_0_0_0.bit3.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 2806 0 ) N ; + - storage_0_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3312 0 ) N ; + - storage_0_0_0.bit4.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 3726 0 ) N ; + - storage_0_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 0 ) N ; + - storage_0_0_0.bit5.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 4646 0 ) N ; + - storage_0_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5152 0 ) N ; + - storage_0_0_0.bit6.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 5566 0 ) N ; + - storage_0_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6072 0 ) N ; + - storage_0_0_0.bit7.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 6486 0 ) N ; + - storage_0_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6992 0 ) N ; + - storage_0_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7406 0 ) N ; + - storage_0_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8050 0 ) N ; + - storage_0_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8280 0 ) N ; + - storage_1_0_0.bit0.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 46 272 ) FS ; + - storage_1_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 552 272 ) FS ; + - storage_1_0_0.bit1.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 966 272 ) FS ; + - storage_1_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1472 272 ) FS ; + - storage_1_0_0.bit2.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 1886 272 ) FS ; + - storage_1_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2392 272 ) FS ; + - storage_1_0_0.bit3.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 2806 272 ) FS ; + - storage_1_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3312 272 ) FS ; + - storage_1_0_0.bit4.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 3726 272 ) FS ; + - storage_1_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 272 ) FS ; + - storage_1_0_0.bit5.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 4646 272 ) FS ; + - storage_1_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5152 272 ) FS ; + - storage_1_0_0.bit6.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 5566 272 ) FS ; + - storage_1_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6072 272 ) FS ; + - storage_1_0_0.bit7.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 6486 272 ) FS ; + - storage_1_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6992 272 ) FS ; + - storage_1_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7406 272 ) FS ; + - storage_1_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8050 272 ) FS ; + - storage_1_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8280 272 ) FS ; + - storage_2_0_0.bit0.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 46 544 ) N ; + - storage_2_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 552 544 ) N ; + - storage_2_0_0.bit1.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 966 544 ) N ; + - storage_2_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1472 544 ) N ; + - storage_2_0_0.bit2.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 1886 544 ) N ; + - storage_2_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2392 544 ) N ; + - storage_2_0_0.bit3.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 2806 544 ) N ; + - storage_2_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3312 544 ) N ; + - storage_2_0_0.bit4.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 3726 544 ) N ; + - storage_2_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 544 ) N ; + - storage_2_0_0.bit5.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 4646 544 ) N ; + - storage_2_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5152 544 ) N ; + - storage_2_0_0.bit6.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 5566 544 ) N ; + - storage_2_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6072 544 ) N ; + - storage_2_0_0.bit7.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 6486 544 ) N ; + - storage_2_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6992 544 ) N ; + - storage_2_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7406 544 ) N ; + - storage_2_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8050 544 ) N ; + - storage_2_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8280 544 ) N ; + - storage_3_0_0.bit0.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 46 816 ) FS ; + - storage_3_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 552 816 ) FS ; + - storage_3_0_0.bit1.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 966 816 ) FS ; + - storage_3_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1472 816 ) FS ; + - storage_3_0_0.bit2.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 1886 816 ) FS ; + - storage_3_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2392 816 ) FS ; + - storage_3_0_0.bit3.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 2806 816 ) FS ; + - storage_3_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3312 816 ) FS ; + - storage_3_0_0.bit4.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 3726 816 ) FS ; + - storage_3_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 816 ) FS ; + - storage_3_0_0.bit5.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 4646 816 ) FS ; + - storage_3_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5152 816 ) FS ; + - storage_3_0_0.bit6.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 5566 816 ) FS ; + - storage_3_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6072 816 ) FS ; + - storage_3_0_0.bit7.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 6486 816 ) FS ; + - storage_3_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6992 816 ) FS ; + - storage_3_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7406 816 ) FS ; + - storage_3_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8050 816 ) FS ; + - storage_3_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8280 816 ) FS ; + - storage_4_0_0.bit0.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 46 1088 ) N ; + - storage_4_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 552 1088 ) N ; + - storage_4_0_0.bit1.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 966 1088 ) N ; + - storage_4_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1472 1088 ) N ; + - storage_4_0_0.bit2.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 1886 1088 ) N ; + - storage_4_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2392 1088 ) N ; + - storage_4_0_0.bit3.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 2806 1088 ) N ; + - storage_4_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3312 1088 ) N ; + - storage_4_0_0.bit4.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 3726 1088 ) N ; + - storage_4_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 1088 ) N ; + - storage_4_0_0.bit5.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 4646 1088 ) N ; + - storage_4_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5152 1088 ) N ; + - storage_4_0_0.bit6.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 5566 1088 ) N ; + - storage_4_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6072 1088 ) N ; + - storage_4_0_0.bit7.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 6486 1088 ) N ; + - storage_4_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6992 1088 ) N ; + - storage_4_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7406 1088 ) N ; + - storage_4_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8050 1088 ) N ; + - storage_4_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8280 1088 ) N ; + - storage_5_0_0.bit0.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 46 1360 ) FS ; + - storage_5_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 552 1360 ) FS ; + - storage_5_0_0.bit1.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 966 1360 ) FS ; + - storage_5_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1472 1360 ) FS ; + - storage_5_0_0.bit2.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 1886 1360 ) FS ; + - storage_5_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2392 1360 ) FS ; + - storage_5_0_0.bit3.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 2806 1360 ) FS ; + - storage_5_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3312 1360 ) FS ; + - storage_5_0_0.bit4.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 3726 1360 ) FS ; + - storage_5_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 1360 ) FS ; + - storage_5_0_0.bit5.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 4646 1360 ) FS ; + - storage_5_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5152 1360 ) FS ; + - storage_5_0_0.bit6.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 5566 1360 ) FS ; + - storage_5_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6072 1360 ) FS ; + - storage_5_0_0.bit7.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 6486 1360 ) FS ; + - storage_5_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6992 1360 ) FS ; + - storage_5_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7406 1360 ) FS ; + - storage_5_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8050 1360 ) FS ; + - storage_5_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8280 1360 ) FS ; + - storage_6_0_0.bit0.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 46 1632 ) N ; + - storage_6_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 552 1632 ) N ; + - storage_6_0_0.bit1.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 966 1632 ) N ; + - storage_6_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1472 1632 ) N ; + - storage_6_0_0.bit2.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 1886 1632 ) N ; + - storage_6_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2392 1632 ) N ; + - storage_6_0_0.bit3.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 2806 1632 ) N ; + - storage_6_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3312 1632 ) N ; + - storage_6_0_0.bit4.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 3726 1632 ) N ; + - storage_6_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 1632 ) N ; + - storage_6_0_0.bit5.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 4646 1632 ) N ; + - storage_6_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5152 1632 ) N ; + - storage_6_0_0.bit6.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 5566 1632 ) N ; + - storage_6_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6072 1632 ) N ; + - storage_6_0_0.bit7.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 6486 1632 ) N ; + - storage_6_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6992 1632 ) N ; + - storage_6_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7406 1632 ) N ; + - storage_6_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8050 1632 ) N ; + - storage_6_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8280 1632 ) N ; + - storage_7_0_0.bit0.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 46 1904 ) FS ; + - storage_7_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 552 1904 ) FS ; + - storage_7_0_0.bit1.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 966 1904 ) FS ; + - storage_7_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1472 1904 ) FS ; + - storage_7_0_0.bit2.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 1886 1904 ) FS ; + - storage_7_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2392 1904 ) FS ; + - storage_7_0_0.bit3.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 2806 1904 ) FS ; + - storage_7_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3312 1904 ) FS ; + - storage_7_0_0.bit4.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 3726 1904 ) FS ; + - storage_7_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 1904 ) FS ; + - storage_7_0_0.bit5.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 4646 1904 ) FS ; + - storage_7_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5152 1904 ) FS ; + - storage_7_0_0.bit6.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 5566 1904 ) FS ; + - storage_7_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6072 1904 ) FS ; + - storage_7_0_0.bit7.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 6486 1904 ) FS ; + - storage_7_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6992 1904 ) FS ; + - storage_7_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7406 1904 ) FS ; + - storage_7_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8050 1904 ) FS ; + - storage_7_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8280 1904 ) FS ; - tapcell.cell0_0 sky130_fd_sc_hd__tap_1 + PLACED ( 0 0 ) N ; - tapcell.cell0_1 sky130_fd_sc_hd__tap_1 + PLACED ( 0 272 ) FS ; - tapcell.cell0_2 sky130_fd_sc_hd__tap_1 + PLACED ( 0 544 ) N ; @@ -295,96 +287,96 @@ COMPONENTS 352 ; - tapcell.cell0_7 sky130_fd_sc_hd__tap_1 + PLACED ( 0 1904 ) FS ; - tapcell.cell0_8 sky130_fd_sc_hd__tap_1 + PLACED ( 0 2176 ) N ; - tapcell.cell0_9 sky130_fd_sc_hd__tap_1 + PLACED ( 0 2448 ) FS ; - - tapcell.cell1_0 sky130_fd_sc_hd__tap_1 + PLACED ( 966 0 ) N ; - - tapcell.cell1_1 sky130_fd_sc_hd__tap_1 + PLACED ( 966 272 ) FS ; - - tapcell.cell1_2 sky130_fd_sc_hd__tap_1 + PLACED ( 966 544 ) N ; - - tapcell.cell1_3 sky130_fd_sc_hd__tap_1 + PLACED ( 966 816 ) FS ; - - tapcell.cell1_4 sky130_fd_sc_hd__tap_1 + PLACED ( 966 1088 ) N ; - - tapcell.cell1_5 sky130_fd_sc_hd__tap_1 + PLACED ( 966 1360 ) FS ; - - tapcell.cell1_6 sky130_fd_sc_hd__tap_1 + PLACED ( 966 1632 ) N ; - - tapcell.cell1_7 sky130_fd_sc_hd__tap_1 + PLACED ( 966 1904 ) FS ; - - tapcell.cell1_8 sky130_fd_sc_hd__tap_1 + PLACED ( 966 2176 ) N ; - - tapcell.cell1_9 sky130_fd_sc_hd__tap_1 + PLACED ( 966 2448 ) FS ; - - tapcell.cell2_0 sky130_fd_sc_hd__tap_1 + PLACED ( 1932 0 ) N ; - - tapcell.cell2_1 sky130_fd_sc_hd__tap_1 + PLACED ( 1932 272 ) FS ; - - tapcell.cell2_2 sky130_fd_sc_hd__tap_1 + PLACED ( 1932 544 ) N ; - - tapcell.cell2_3 sky130_fd_sc_hd__tap_1 + PLACED ( 1932 816 ) FS ; - - tapcell.cell2_4 sky130_fd_sc_hd__tap_1 + PLACED ( 1932 1088 ) N ; - - tapcell.cell2_5 sky130_fd_sc_hd__tap_1 + PLACED ( 1932 1360 ) FS ; - - tapcell.cell2_6 sky130_fd_sc_hd__tap_1 + PLACED ( 1932 1632 ) N ; - - tapcell.cell2_7 sky130_fd_sc_hd__tap_1 + PLACED ( 1932 1904 ) FS ; - - tapcell.cell2_8 sky130_fd_sc_hd__tap_1 + PLACED ( 1932 2176 ) N ; - - tapcell.cell2_9 sky130_fd_sc_hd__tap_1 + PLACED ( 1932 2448 ) FS ; - - tapcell.cell3_0 sky130_fd_sc_hd__tap_1 + PLACED ( 2898 0 ) N ; - - tapcell.cell3_1 sky130_fd_sc_hd__tap_1 + PLACED ( 2898 272 ) FS ; - - tapcell.cell3_2 sky130_fd_sc_hd__tap_1 + PLACED ( 2898 544 ) N ; - - tapcell.cell3_3 sky130_fd_sc_hd__tap_1 + PLACED ( 2898 816 ) FS ; - - tapcell.cell3_4 sky130_fd_sc_hd__tap_1 + PLACED ( 2898 1088 ) N ; - - tapcell.cell3_5 sky130_fd_sc_hd__tap_1 + PLACED ( 2898 1360 ) FS ; - - tapcell.cell3_6 sky130_fd_sc_hd__tap_1 + PLACED ( 2898 1632 ) N ; - - tapcell.cell3_7 sky130_fd_sc_hd__tap_1 + PLACED ( 2898 1904 ) FS ; - - tapcell.cell3_8 sky130_fd_sc_hd__tap_1 + PLACED ( 2898 2176 ) N ; - - tapcell.cell3_9 sky130_fd_sc_hd__tap_1 + PLACED ( 2898 2448 ) FS ; - - tapcell.cell4_0 sky130_fd_sc_hd__tap_1 + PLACED ( 3864 0 ) N ; - - tapcell.cell4_1 sky130_fd_sc_hd__tap_1 + PLACED ( 3864 272 ) FS ; - - tapcell.cell4_2 sky130_fd_sc_hd__tap_1 + PLACED ( 3864 544 ) N ; - - tapcell.cell4_3 sky130_fd_sc_hd__tap_1 + PLACED ( 3864 816 ) FS ; - - tapcell.cell4_4 sky130_fd_sc_hd__tap_1 + PLACED ( 3864 1088 ) N ; - - tapcell.cell4_5 sky130_fd_sc_hd__tap_1 + PLACED ( 3864 1360 ) FS ; - - tapcell.cell4_6 sky130_fd_sc_hd__tap_1 + PLACED ( 3864 1632 ) N ; - - tapcell.cell4_7 sky130_fd_sc_hd__tap_1 + PLACED ( 3864 1904 ) FS ; - - tapcell.cell4_8 sky130_fd_sc_hd__tap_1 + PLACED ( 3864 2176 ) N ; - - tapcell.cell4_9 sky130_fd_sc_hd__tap_1 + PLACED ( 3864 2448 ) FS ; - - tapcell.cell5_0 sky130_fd_sc_hd__tap_1 + PLACED ( 4830 0 ) N ; - - tapcell.cell5_1 sky130_fd_sc_hd__tap_1 + PLACED ( 4830 272 ) FS ; - - tapcell.cell5_2 sky130_fd_sc_hd__tap_1 + PLACED ( 4830 544 ) N ; - - tapcell.cell5_3 sky130_fd_sc_hd__tap_1 + PLACED ( 4830 816 ) FS ; - - tapcell.cell5_4 sky130_fd_sc_hd__tap_1 + PLACED ( 4830 1088 ) N ; - - tapcell.cell5_5 sky130_fd_sc_hd__tap_1 + PLACED ( 4830 1360 ) FS ; - - tapcell.cell5_6 sky130_fd_sc_hd__tap_1 + PLACED ( 4830 1632 ) N ; - - tapcell.cell5_7 sky130_fd_sc_hd__tap_1 + PLACED ( 4830 1904 ) FS ; - - tapcell.cell5_8 sky130_fd_sc_hd__tap_1 + PLACED ( 4830 2176 ) N ; - - tapcell.cell5_9 sky130_fd_sc_hd__tap_1 + PLACED ( 4830 2448 ) FS ; - - tapcell.cell6_0 sky130_fd_sc_hd__tap_1 + PLACED ( 5796 0 ) N ; - - tapcell.cell6_1 sky130_fd_sc_hd__tap_1 + PLACED ( 5796 272 ) FS ; - - tapcell.cell6_2 sky130_fd_sc_hd__tap_1 + PLACED ( 5796 544 ) N ; - - tapcell.cell6_3 sky130_fd_sc_hd__tap_1 + PLACED ( 5796 816 ) FS ; - - tapcell.cell6_4 sky130_fd_sc_hd__tap_1 + PLACED ( 5796 1088 ) N ; - - tapcell.cell6_5 sky130_fd_sc_hd__tap_1 + PLACED ( 5796 1360 ) FS ; - - tapcell.cell6_6 sky130_fd_sc_hd__tap_1 + PLACED ( 5796 1632 ) N ; - - tapcell.cell6_7 sky130_fd_sc_hd__tap_1 + PLACED ( 5796 1904 ) FS ; - - tapcell.cell6_8 sky130_fd_sc_hd__tap_1 + PLACED ( 5796 2176 ) N ; - - tapcell.cell6_9 sky130_fd_sc_hd__tap_1 + PLACED ( 5796 2448 ) FS ; - - tapcell.cell7_0 sky130_fd_sc_hd__tap_1 + PLACED ( 6762 0 ) N ; - - tapcell.cell7_1 sky130_fd_sc_hd__tap_1 + PLACED ( 6762 272 ) FS ; - - tapcell.cell7_2 sky130_fd_sc_hd__tap_1 + PLACED ( 6762 544 ) N ; - - tapcell.cell7_3 sky130_fd_sc_hd__tap_1 + PLACED ( 6762 816 ) FS ; - - tapcell.cell7_4 sky130_fd_sc_hd__tap_1 + PLACED ( 6762 1088 ) N ; - - tapcell.cell7_5 sky130_fd_sc_hd__tap_1 + PLACED ( 6762 1360 ) FS ; - - tapcell.cell7_6 sky130_fd_sc_hd__tap_1 + PLACED ( 6762 1632 ) N ; - - tapcell.cell7_7 sky130_fd_sc_hd__tap_1 + PLACED ( 6762 1904 ) FS ; - - tapcell.cell7_8 sky130_fd_sc_hd__tap_1 + PLACED ( 6762 2176 ) N ; - - tapcell.cell7_9 sky130_fd_sc_hd__tap_1 + PLACED ( 6762 2448 ) FS ; - - tapcell.cell8_0 sky130_fd_sc_hd__tap_1 + PLACED ( 7728 0 ) N ; - - tapcell.cell8_1 sky130_fd_sc_hd__tap_1 + PLACED ( 7728 272 ) FS ; - - tapcell.cell8_2 sky130_fd_sc_hd__tap_1 + PLACED ( 7728 544 ) N ; - - tapcell.cell8_3 sky130_fd_sc_hd__tap_1 + PLACED ( 7728 816 ) FS ; - - tapcell.cell8_4 sky130_fd_sc_hd__tap_1 + PLACED ( 7728 1088 ) N ; - - tapcell.cell8_5 sky130_fd_sc_hd__tap_1 + PLACED ( 7728 1360 ) FS ; - - tapcell.cell8_6 sky130_fd_sc_hd__tap_1 + PLACED ( 7728 1632 ) N ; - - tapcell.cell8_7 sky130_fd_sc_hd__tap_1 + PLACED ( 7728 1904 ) FS ; - - tapcell.cell8_8 sky130_fd_sc_hd__tap_1 + PLACED ( 7728 2176 ) N ; - - tapcell.cell8_9 sky130_fd_sc_hd__tap_1 + PLACED ( 7728 2448 ) FS ; - - tapcell.cell9_0 sky130_fd_sc_hd__tap_1 + PLACED ( 8924 0 ) N ; - - tapcell.cell9_1 sky130_fd_sc_hd__tap_1 + PLACED ( 8924 272 ) FS ; - - tapcell.cell9_2 sky130_fd_sc_hd__tap_1 + PLACED ( 8924 544 ) N ; - - tapcell.cell9_3 sky130_fd_sc_hd__tap_1 + PLACED ( 8924 816 ) FS ; - - tapcell.cell9_4 sky130_fd_sc_hd__tap_1 + PLACED ( 8924 1088 ) N ; - - tapcell.cell9_5 sky130_fd_sc_hd__tap_1 + PLACED ( 8924 1360 ) FS ; - - tapcell.cell9_6 sky130_fd_sc_hd__tap_1 + PLACED ( 8924 1632 ) N ; - - tapcell.cell9_7 sky130_fd_sc_hd__tap_1 + PLACED ( 8924 1904 ) FS ; - - tapcell.cell9_8 sky130_fd_sc_hd__tap_1 + PLACED ( 8924 2176 ) N ; - - tapcell.cell9_9 sky130_fd_sc_hd__tap_1 + PLACED ( 8924 2448 ) FS ; + - tapcell.cell1_0 sky130_fd_sc_hd__tap_1 + PLACED ( 920 0 ) N ; + - tapcell.cell1_1 sky130_fd_sc_hd__tap_1 + PLACED ( 920 272 ) FS ; + - tapcell.cell1_2 sky130_fd_sc_hd__tap_1 + PLACED ( 920 544 ) N ; + - tapcell.cell1_3 sky130_fd_sc_hd__tap_1 + PLACED ( 920 816 ) FS ; + - tapcell.cell1_4 sky130_fd_sc_hd__tap_1 + PLACED ( 920 1088 ) N ; + - tapcell.cell1_5 sky130_fd_sc_hd__tap_1 + PLACED ( 920 1360 ) FS ; + - tapcell.cell1_6 sky130_fd_sc_hd__tap_1 + PLACED ( 920 1632 ) N ; + - tapcell.cell1_7 sky130_fd_sc_hd__tap_1 + PLACED ( 920 1904 ) FS ; + - tapcell.cell1_8 sky130_fd_sc_hd__tap_1 + PLACED ( 920 2176 ) N ; + - tapcell.cell1_9 sky130_fd_sc_hd__tap_1 + PLACED ( 920 2448 ) FS ; + - tapcell.cell2_0 sky130_fd_sc_hd__tap_1 + PLACED ( 1840 0 ) N ; + - tapcell.cell2_1 sky130_fd_sc_hd__tap_1 + PLACED ( 1840 272 ) FS ; + - tapcell.cell2_2 sky130_fd_sc_hd__tap_1 + PLACED ( 1840 544 ) N ; + - tapcell.cell2_3 sky130_fd_sc_hd__tap_1 + PLACED ( 1840 816 ) FS ; + - tapcell.cell2_4 sky130_fd_sc_hd__tap_1 + PLACED ( 1840 1088 ) N ; + - tapcell.cell2_5 sky130_fd_sc_hd__tap_1 + PLACED ( 1840 1360 ) FS ; + - tapcell.cell2_6 sky130_fd_sc_hd__tap_1 + PLACED ( 1840 1632 ) N ; + - tapcell.cell2_7 sky130_fd_sc_hd__tap_1 + PLACED ( 1840 1904 ) FS ; + - tapcell.cell2_8 sky130_fd_sc_hd__tap_1 + PLACED ( 1840 2176 ) N ; + - tapcell.cell2_9 sky130_fd_sc_hd__tap_1 + PLACED ( 1840 2448 ) FS ; + - tapcell.cell3_0 sky130_fd_sc_hd__tap_1 + PLACED ( 2760 0 ) N ; + - tapcell.cell3_1 sky130_fd_sc_hd__tap_1 + PLACED ( 2760 272 ) FS ; + - tapcell.cell3_2 sky130_fd_sc_hd__tap_1 + PLACED ( 2760 544 ) N ; + - tapcell.cell3_3 sky130_fd_sc_hd__tap_1 + PLACED ( 2760 816 ) FS ; + - tapcell.cell3_4 sky130_fd_sc_hd__tap_1 + PLACED ( 2760 1088 ) N ; + - tapcell.cell3_5 sky130_fd_sc_hd__tap_1 + PLACED ( 2760 1360 ) FS ; + - tapcell.cell3_6 sky130_fd_sc_hd__tap_1 + PLACED ( 2760 1632 ) N ; + - tapcell.cell3_7 sky130_fd_sc_hd__tap_1 + PLACED ( 2760 1904 ) FS ; + - tapcell.cell3_8 sky130_fd_sc_hd__tap_1 + PLACED ( 2760 2176 ) N ; + - tapcell.cell3_9 sky130_fd_sc_hd__tap_1 + PLACED ( 2760 2448 ) FS ; + - tapcell.cell4_0 sky130_fd_sc_hd__tap_1 + PLACED ( 3680 0 ) N ; + - tapcell.cell4_1 sky130_fd_sc_hd__tap_1 + PLACED ( 3680 272 ) FS ; + - tapcell.cell4_2 sky130_fd_sc_hd__tap_1 + PLACED ( 3680 544 ) N ; + - tapcell.cell4_3 sky130_fd_sc_hd__tap_1 + PLACED ( 3680 816 ) FS ; + - tapcell.cell4_4 sky130_fd_sc_hd__tap_1 + PLACED ( 3680 1088 ) N ; + - tapcell.cell4_5 sky130_fd_sc_hd__tap_1 + PLACED ( 3680 1360 ) FS ; + - tapcell.cell4_6 sky130_fd_sc_hd__tap_1 + PLACED ( 3680 1632 ) N ; + - tapcell.cell4_7 sky130_fd_sc_hd__tap_1 + PLACED ( 3680 1904 ) FS ; + - tapcell.cell4_8 sky130_fd_sc_hd__tap_1 + PLACED ( 3680 2176 ) N ; + - tapcell.cell4_9 sky130_fd_sc_hd__tap_1 + PLACED ( 3680 2448 ) FS ; + - tapcell.cell5_0 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 0 ) N ; + - tapcell.cell5_1 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 272 ) FS ; + - tapcell.cell5_2 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 544 ) N ; + - tapcell.cell5_3 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 816 ) FS ; + - tapcell.cell5_4 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 1088 ) N ; + - tapcell.cell5_5 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 1360 ) FS ; + - tapcell.cell5_6 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 1632 ) N ; + - tapcell.cell5_7 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 1904 ) FS ; + - tapcell.cell5_8 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 2176 ) N ; + - tapcell.cell5_9 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 2448 ) FS ; + - tapcell.cell6_0 sky130_fd_sc_hd__tap_1 + PLACED ( 5520 0 ) N ; + - tapcell.cell6_1 sky130_fd_sc_hd__tap_1 + PLACED ( 5520 272 ) FS ; + - tapcell.cell6_2 sky130_fd_sc_hd__tap_1 + PLACED ( 5520 544 ) N ; + - tapcell.cell6_3 sky130_fd_sc_hd__tap_1 + PLACED ( 5520 816 ) FS ; + - tapcell.cell6_4 sky130_fd_sc_hd__tap_1 + PLACED ( 5520 1088 ) N ; + - tapcell.cell6_5 sky130_fd_sc_hd__tap_1 + PLACED ( 5520 1360 ) FS ; + - tapcell.cell6_6 sky130_fd_sc_hd__tap_1 + PLACED ( 5520 1632 ) N ; + - tapcell.cell6_7 sky130_fd_sc_hd__tap_1 + PLACED ( 5520 1904 ) FS ; + - tapcell.cell6_8 sky130_fd_sc_hd__tap_1 + PLACED ( 5520 2176 ) N ; + - tapcell.cell6_9 sky130_fd_sc_hd__tap_1 + PLACED ( 5520 2448 ) FS ; + - tapcell.cell7_0 sky130_fd_sc_hd__tap_1 + PLACED ( 6440 0 ) N ; + - tapcell.cell7_1 sky130_fd_sc_hd__tap_1 + PLACED ( 6440 272 ) FS ; + - tapcell.cell7_2 sky130_fd_sc_hd__tap_1 + PLACED ( 6440 544 ) N ; + - tapcell.cell7_3 sky130_fd_sc_hd__tap_1 + PLACED ( 6440 816 ) FS ; + - tapcell.cell7_4 sky130_fd_sc_hd__tap_1 + PLACED ( 6440 1088 ) N ; + - tapcell.cell7_5 sky130_fd_sc_hd__tap_1 + PLACED ( 6440 1360 ) FS ; + - tapcell.cell7_6 sky130_fd_sc_hd__tap_1 + PLACED ( 6440 1632 ) N ; + - tapcell.cell7_7 sky130_fd_sc_hd__tap_1 + PLACED ( 6440 1904 ) FS ; + - tapcell.cell7_8 sky130_fd_sc_hd__tap_1 + PLACED ( 6440 2176 ) N ; + - tapcell.cell7_9 sky130_fd_sc_hd__tap_1 + PLACED ( 6440 2448 ) FS ; + - tapcell.cell8_0 sky130_fd_sc_hd__tap_1 + PLACED ( 7360 0 ) N ; + - tapcell.cell8_1 sky130_fd_sc_hd__tap_1 + PLACED ( 7360 272 ) FS ; + - tapcell.cell8_2 sky130_fd_sc_hd__tap_1 + PLACED ( 7360 544 ) N ; + - tapcell.cell8_3 sky130_fd_sc_hd__tap_1 + PLACED ( 7360 816 ) FS ; + - tapcell.cell8_4 sky130_fd_sc_hd__tap_1 + PLACED ( 7360 1088 ) N ; + - tapcell.cell8_5 sky130_fd_sc_hd__tap_1 + PLACED ( 7360 1360 ) FS ; + - tapcell.cell8_6 sky130_fd_sc_hd__tap_1 + PLACED ( 7360 1632 ) N ; + - tapcell.cell8_7 sky130_fd_sc_hd__tap_1 + PLACED ( 7360 1904 ) FS ; + - tapcell.cell8_8 sky130_fd_sc_hd__tap_1 + PLACED ( 7360 2176 ) N ; + - tapcell.cell8_9 sky130_fd_sc_hd__tap_1 + PLACED ( 7360 2448 ) FS ; + - tapcell.cell9_0 sky130_fd_sc_hd__tap_1 + PLACED ( 8556 0 ) N ; + - tapcell.cell9_1 sky130_fd_sc_hd__tap_1 + PLACED ( 8556 272 ) FS ; + - tapcell.cell9_2 sky130_fd_sc_hd__tap_1 + PLACED ( 8556 544 ) N ; + - tapcell.cell9_3 sky130_fd_sc_hd__tap_1 + PLACED ( 8556 816 ) FS ; + - tapcell.cell9_4 sky130_fd_sc_hd__tap_1 + PLACED ( 8556 1088 ) N ; + - tapcell.cell9_5 sky130_fd_sc_hd__tap_1 + PLACED ( 8556 1360 ) FS ; + - tapcell.cell9_6 sky130_fd_sc_hd__tap_1 + PLACED ( 8556 1632 ) N ; + - tapcell.cell9_7 sky130_fd_sc_hd__tap_1 + PLACED ( 8556 1904 ) FS ; + - tapcell.cell9_8 sky130_fd_sc_hd__tap_1 + PLACED ( 8556 2176 ) N ; + - tapcell.cell9_9 sky130_fd_sc_hd__tap_1 + PLACED ( 8556 2448 ) FS ; END COMPONENTS PINS 23 ; - D[0] + NET D[0] + DIRECTION INPUT + USE SIGNAL @@ -398,119 +390,119 @@ PINS 23 ; - D[2] + NET D[2] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 2047 2695 ) N ; + + PLACED ( 1955 2695 ) N ; - D[3] + NET D[3] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 2967 2695 ) N ; + + PLACED ( 2875 2695 ) N ; - D[4] + NET D[4] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 3887 2695 ) N ; + + PLACED ( 3795 2695 ) N ; - D[5] + NET D[5] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 4899 2695 ) N ; + + PLACED ( 4715 2695 ) N ; - D[6] + NET D[6] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 5911 2695 ) N ; + + PLACED ( 5635 2695 ) N ; - D[7] + NET D[7] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 6831 2695 ) N ; + + PLACED ( 6555 2695 ) N ; - Q[0] + NET Q[0] + DIRECTION OUTPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 943 2695 ) N ; + + PLACED ( 851 2695 ) N ; - Q[1] + NET Q[1] + DIRECTION OUTPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 1863 2695 ) N ; + + PLACED ( 1771 2695 ) N ; - Q[2] + NET Q[2] + DIRECTION OUTPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 2875 2695 ) N ; + + PLACED ( 2691 2695 ) N ; - Q[3] + NET Q[3] + DIRECTION OUTPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 3795 2695 ) N ; + + PLACED ( 3611 2695 ) N ; - Q[4] + NET Q[4] + DIRECTION OUTPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 4807 2695 ) N ; + + PLACED ( 4531 2695 ) N ; - Q[5] + NET Q[5] + DIRECTION OUTPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 5727 2695 ) N ; + + PLACED ( 5451 2695 ) N ; - Q[6] + NET Q[6] + DIRECTION OUTPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 6739 2695 ) N ; + + PLACED ( 6371 2695 ) N ; - Q[7] + NET Q[7] + DIRECTION OUTPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 7659 2695 ) N ; + + PLACED ( 7291 2695 ) N ; - VDD + NET VDD + SPECIAL + DIRECTION INOUT + USE POWER + PORT + LAYER met3 ( -15 -24 ) ( 15 24 ) - + LAYER met3 ( -9553 -24 ) ( -9523 24 ) - + LAYER met2 ( -3577 1706 ) ( -3529 1720 ) - + LAYER met2 ( -3577 -1000 ) ( -3529 -986 ) - + LAYER met2 ( -7577 1706 ) ( -7529 1720 ) - + LAYER met2 ( -7577 -1000 ) ( -7529 -986 ) + + LAYER met3 ( -9185 -24 ) ( -9155 24 ) + + LAYER met2 ( -3209 1706 ) ( -3161 1720 ) + + LAYER met2 ( -3209 -1000 ) ( -3161 -986 ) + + LAYER met2 ( -7209 1706 ) ( -7161 1720 ) + + LAYER met2 ( -7209 -1000 ) ( -7161 -986 ) + LAYER met1 ( 1 1424 ) ( 15 1472 ) - + LAYER met1 ( -9553 1424 ) ( -9539 1472 ) + + LAYER met1 ( -9185 1424 ) ( -9171 1472 ) + LAYER met1 ( 1 880 ) ( 15 928 ) - + LAYER met1 ( -9553 880 ) ( -9539 928 ) + + LAYER met1 ( -9185 880 ) ( -9171 928 ) + LAYER met1 ( 1 336 ) ( 15 384 ) - + LAYER met1 ( -9553 336 ) ( -9539 384 ) + + LAYER met1 ( -9185 336 ) ( -9171 384 ) + LAYER met1 ( 1 -208 ) ( 15 -160 ) - + LAYER met1 ( -9553 -208 ) ( -9539 -160 ) + + LAYER met1 ( -9185 -208 ) ( -9171 -160 ) + LAYER met1 ( 1 -752 ) ( 15 -704 ) - + LAYER met1 ( -9553 -752 ) ( -9539 -704 ) - + FIXED ( 9553 1000 ) N ; + + LAYER met1 ( -9185 -752 ) ( -9171 -704 ) + + FIXED ( 9185 1000 ) N ; - VSS + NET VSS + SPECIAL + DIRECTION INOUT + USE GROUND + PORT + LAYER met3 ( -15 -24 ) ( 15 24 ) - + LAYER met3 ( -9553 -24 ) ( -9523 24 ) - + LAYER met2 ( -1577 706 ) ( -1529 720 ) - + LAYER met2 ( -1577 -2000 ) ( -1529 -1986 ) - + LAYER met2 ( -5577 706 ) ( -5529 720 ) - + LAYER met2 ( -5577 -2000 ) ( -5529 -1986 ) + + LAYER met3 ( -9185 -24 ) ( -9155 24 ) + + LAYER met2 ( -1209 706 ) ( -1161 720 ) + + LAYER met2 ( -1209 -2000 ) ( -1161 -1986 ) + + LAYER met2 ( -5209 706 ) ( -5161 720 ) + + LAYER met2 ( -5209 -2000 ) ( -5161 -1986 ) + LAYER met1 ( 1 696 ) ( 15 744 ) - + LAYER met1 ( -9553 696 ) ( -9539 744 ) + + LAYER met1 ( -9185 696 ) ( -9171 744 ) + LAYER met1 ( 1 152 ) ( 15 200 ) - + LAYER met1 ( -9553 152 ) ( -9539 200 ) + + LAYER met1 ( -9185 152 ) ( -9171 200 ) + LAYER met1 ( 1 -392 ) ( 15 -344 ) - + LAYER met1 ( -9553 -392 ) ( -9539 -344 ) + + LAYER met1 ( -9185 -392 ) ( -9171 -344 ) + LAYER met1 ( 1 -936 ) ( 15 -888 ) - + LAYER met1 ( -9553 -936 ) ( -9539 -888 ) + + LAYER met1 ( -9185 -936 ) ( -9171 -888 ) + LAYER met1 ( 1 -1480 ) ( 15 -1432 ) - + LAYER met1 ( -9553 -1480 ) ( -9539 -1432 ) + + LAYER met1 ( -9185 -1480 ) ( -9171 -1432 ) + LAYER met1 ( 1 -2024 ) ( 15 -1976 ) - + LAYER met1 ( -9553 -2024 ) ( -9539 -1976 ) - + FIXED ( 9553 2000 ) N ; + + LAYER met1 ( -9185 -2024 ) ( -9171 -1976 ) + + FIXED ( 9185 2000 ) N ; - addr_rw[0] + NET addr_rw[0] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met3 ( -40 -15 ) ( 40 15 ) - + PLACED ( 9528 442 ) N ; + + PLACED ( 9160 442 ) N ; - addr_rw[1] + NET addr_rw[1] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met3 ( -40 -15 ) ( 40 15 ) - + PLACED ( 9528 714 ) N ; + + PLACED ( 9160 714 ) N ; - addr_rw[2] + NET addr_rw[2] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met3 ( -40 -15 ) ( 40 15 ) - + PLACED ( 9528 170 ) N ; + + PLACED ( 9160 170 ) N ; - clk + NET clk + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 8027 2695 ) N ; + + PLACED ( 7659 2695 ) N ; - we[0] + NET we[0] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 8487 2695 ) N ; + + PLACED ( 8119 2695 ) N ; END PINS SPECIALNETS 2 ; - VDD ( PIN VDD ) ( tapcell.cell9_9 VPWR ) ( tapcell.cell9_8 VPWR ) ( tapcell.cell9_7 VPWR ) ( tapcell.cell9_6 VPWR ) ( tapcell.cell9_5 VPWR ) ( tapcell.cell9_4 VPWR ) @@ -551,14 +543,14 @@ SPECIALNETS 2 ; ( storage_0_0_0.gcand VPWR ) ( storage_0_0_0.cg VPWR ) ( storage_0_0_0.bit7.obuf0 VPWR ) ( storage_0_0_0.bit7.bit VPWR ) ( storage_0_0_0.bit6.obuf0 VPWR ) ( storage_0_0_0.bit6.bit VPWR ) ( storage_0_0_0.bit5.obuf0 VPWR ) ( storage_0_0_0.bit5.bit VPWR ) ( storage_0_0_0.bit4.obuf0 VPWR ) ( storage_0_0_0.bit4.bit VPWR ) ( storage_0_0_0.bit3.obuf0 VPWR ) ( storage_0_0_0.bit3.bit VPWR ) ( storage_0_0_0.bit2.obuf0 VPWR ) ( storage_0_0_0.bit2.bit VPWR ) ( storage_0_0_0.bit1.obuf0 VPWR ) ( storage_0_0_0.bit1.bit VPWR ) ( storage_0_0_0.bit0.obuf0 VPWR ) ( storage_0_0_0.bit0.bit VPWR ) + USE POWER - + ROUTED met3 48 + SHAPE STRIPE ( 0 1000 ) ( 9568 1000 ) + + ROUTED met3 48 + SHAPE STRIPE ( 0 1000 ) ( 9200 1000 ) NEW met2 48 + SHAPE STRIPE ( 6000 0 ) ( 6000 2720 ) NEW met2 48 + SHAPE STRIPE ( 2000 0 ) ( 2000 2720 ) - NEW met1 48 + SHAPE FOLLOWPIN ( 0 2448 ) ( 9568 2448 ) - NEW met1 48 + SHAPE FOLLOWPIN ( 0 1904 ) ( 9568 1904 ) - NEW met1 48 + SHAPE FOLLOWPIN ( 0 1360 ) ( 9568 1360 ) - NEW met1 48 + SHAPE FOLLOWPIN ( 0 816 ) ( 9568 816 ) - NEW met1 48 + SHAPE FOLLOWPIN ( 0 272 ) ( 9568 272 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 2448 ) ( 9200 2448 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 1904 ) ( 9200 1904 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 1360 ) ( 9200 1360 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 816 ) ( 9200 816 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 272 ) ( 9200 272 ) NEW met2 0 + SHAPE STRIPE ( 6000 1000 ) via3_4_480_480_1_1_400_400 NEW met2 0 + SHAPE STRIPE ( 2000 1000 ) via3_4_480_480_1_1_400_400 NEW met1 0 + SHAPE STRIPE ( 6000 2448 ) via2_3_480_480_1_1_320_320 @@ -609,15 +601,15 @@ SPECIALNETS 2 ; ( storage_0_0_0.gcand VGND ) ( storage_0_0_0.cg VGND ) ( storage_0_0_0.bit7.obuf0 VGND ) ( storage_0_0_0.bit7.bit VGND ) ( storage_0_0_0.bit6.obuf0 VGND ) ( storage_0_0_0.bit6.bit VGND ) ( storage_0_0_0.bit5.obuf0 VGND ) ( storage_0_0_0.bit5.bit VGND ) ( storage_0_0_0.bit4.obuf0 VGND ) ( storage_0_0_0.bit4.bit VGND ) ( storage_0_0_0.bit3.obuf0 VGND ) ( storage_0_0_0.bit3.bit VGND ) ( storage_0_0_0.bit2.obuf0 VGND ) ( storage_0_0_0.bit2.bit VGND ) ( storage_0_0_0.bit1.obuf0 VGND ) ( storage_0_0_0.bit1.bit VGND ) ( storage_0_0_0.bit0.obuf0 VGND ) ( storage_0_0_0.bit0.bit VGND ) + USE GROUND - + ROUTED met3 48 + SHAPE STRIPE ( 0 2000 ) ( 9568 2000 ) + + ROUTED met3 48 + SHAPE STRIPE ( 0 2000 ) ( 9200 2000 ) NEW met2 48 + SHAPE STRIPE ( 8000 -24 ) ( 8000 2744 ) NEW met2 48 + SHAPE STRIPE ( 4000 -24 ) ( 4000 2744 ) - NEW met1 48 + SHAPE FOLLOWPIN ( 0 2720 ) ( 9568 2720 ) - NEW met1 48 + SHAPE FOLLOWPIN ( 0 2176 ) ( 9568 2176 ) - NEW met1 48 + SHAPE FOLLOWPIN ( 0 1632 ) ( 9568 1632 ) - NEW met1 48 + SHAPE FOLLOWPIN ( 0 1088 ) ( 9568 1088 ) - NEW met1 48 + SHAPE FOLLOWPIN ( 0 544 ) ( 9568 544 ) - NEW met1 48 + SHAPE FOLLOWPIN ( 0 0 ) ( 9568 0 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 2720 ) ( 9200 2720 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 2176 ) ( 9200 2176 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 1632 ) ( 9200 1632 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 1088 ) ( 9200 1088 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 544 ) ( 9200 544 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 0 ) ( 9200 0 ) NEW met2 0 + SHAPE STRIPE ( 8000 2000 ) via3_4_480_480_1_1_400_400 NEW met2 0 + SHAPE STRIPE ( 4000 2000 ) via3_4_480_480_1_1_400_400 NEW met1 0 + SHAPE STRIPE ( 8000 2720 ) via2_3_480_480_1_1_320_320 @@ -641,1816 +633,1832 @@ NETS 153 ; NEW li1 ( 69 2601 ) L1M1_PR_MR ; - D[1] ( PIN D[1] ) ( buffer.in[1] A ) + USE SIGNAL + ROUTED met2 ( 1035 2601 ) ( * 2686 0 ) - NEW li1 ( 1035 2601 ) L1M1_PR_MR - NEW met1 ( 1035 2601 ) M1M2_PR ; + NEW met1 ( 989 2601 ) ( 1035 * ) + NEW met1 ( 1035 2601 ) M1M2_PR + NEW li1 ( 989 2601 ) L1M1_PR_MR ; - D[2] ( PIN D[2] ) ( buffer.in[2] A ) + USE SIGNAL - + ROUTED met2 ( 2047 2618 ) ( * 2686 0 ) - NEW met2 ( 2047 2618 ) ( 2093 * ) - NEW met2 ( 2093 2601 ) ( * 2618 ) - NEW met1 ( 2001 2601 ) ( 2093 * ) - NEW met1 ( 2093 2601 ) M1M2_PR - NEW li1 ( 2001 2601 ) L1M1_PR_MR ; + + ROUTED met2 ( 1955 2618 ) ( * 2686 0 ) + NEW met2 ( 1909 2618 ) ( 1955 * ) + NEW met2 ( 1909 2601 ) ( * 2618 ) + NEW li1 ( 1909 2601 ) L1M1_PR_MR + NEW met1 ( 1909 2601 ) M1M2_PR ; - D[3] ( PIN D[3] ) ( buffer.in[3] A ) + USE SIGNAL - + ROUTED met2 ( 2967 2601 ) ( * 2686 0 ) - NEW li1 ( 2967 2601 ) L1M1_PR_MR - NEW met1 ( 2967 2601 ) M1M2_PR ; + + ROUTED met2 ( 2875 2601 ) ( * 2686 0 ) + NEW met1 ( 2829 2601 ) ( 2875 * ) + NEW met1 ( 2875 2601 ) M1M2_PR + NEW li1 ( 2829 2601 ) L1M1_PR_MR ; - D[4] ( PIN D[4] ) ( buffer.in[4] A ) + USE SIGNAL - + ROUTED met2 ( 3887 2601 ) ( * 2686 0 ) - NEW met1 ( 3887 2601 ) ( 3933 * ) - NEW met1 ( 3887 2601 ) M1M2_PR - NEW li1 ( 3933 2601 ) L1M1_PR_MR ; + + ROUTED met2 ( 3795 2601 ) ( * 2686 0 ) + NEW met1 ( 3749 2601 ) ( 3795 * ) + NEW met1 ( 3795 2601 ) M1M2_PR + NEW li1 ( 3749 2601 ) L1M1_PR_MR ; - D[5] ( PIN D[5] ) ( buffer.in[5] A ) + USE SIGNAL - + ROUTED met2 ( 4899 2601 ) ( * 2686 0 ) - NEW li1 ( 4899 2601 ) L1M1_PR_MR - NEW met1 ( 4899 2601 ) M1M2_PR ; + + ROUTED met2 ( 4715 2601 ) ( * 2686 0 ) + NEW met1 ( 4669 2601 ) ( 4715 * ) + NEW met1 ( 4715 2601 ) M1M2_PR + NEW li1 ( 4669 2601 ) L1M1_PR_MR ; - D[6] ( PIN D[6] ) ( buffer.in[6] A ) + USE SIGNAL - + ROUTED met2 ( 5911 2601 ) ( * 2686 0 ) - NEW met1 ( 5865 2601 ) ( 5911 * ) - NEW met1 ( 5911 2601 ) M1M2_PR - NEW li1 ( 5865 2601 ) L1M1_PR_MR ; + + ROUTED met2 ( 5635 2601 ) ( * 2686 0 ) + NEW met1 ( 5589 2601 ) ( 5635 * ) + NEW met1 ( 5635 2601 ) M1M2_PR + NEW li1 ( 5589 2601 ) L1M1_PR_MR ; - D[7] ( PIN D[7] ) ( buffer.in[7] A ) + USE SIGNAL - + ROUTED met2 ( 6831 2601 ) ( * 2686 0 ) - NEW li1 ( 6831 2601 ) L1M1_PR_MR - NEW met1 ( 6831 2601 ) M1M2_PR ; + + ROUTED met2 ( 6555 2601 ) ( * 2686 0 ) + NEW met1 ( 6509 2601 ) ( 6555 * ) + NEW met1 ( 6555 2601 ) M1M2_PR + NEW li1 ( 6509 2601 ) L1M1_PR_MR ; - D_nets.b0 ( buffer.in[0] X ) ( neg_lat_b0.nlat D ) + USE SIGNAL - + ROUTED met2 ( 207 2295 ) ( * 2499 ) - NEW met1 ( 161 2499 ) ( 207 * ) - NEW li1 ( 207 2295 ) L1M1_PR_MR - NEW met1 ( 207 2295 ) M1M2_PR - NEW met1 ( 207 2499 ) M1M2_PR - NEW li1 ( 161 2499 ) L1M1_PR_MR ; + + ROUTED met1 ( 161 2261 ) ( 229 * ) + NEW met2 ( 161 2261 ) ( * 2499 ) + NEW li1 ( 229 2261 ) L1M1_PR_MR + NEW met1 ( 161 2261 ) M1M2_PR + NEW li1 ( 161 2499 ) L1M1_PR_MR + NEW met1 ( 161 2499 ) M1M2_PR ; - D_nets.b1 ( buffer.in[1] X ) ( neg_lat_b1.nlat D ) + USE SIGNAL - + ROUTED met2 ( 1173 2295 ) ( * 2499 ) - NEW met1 ( 1127 2499 ) ( 1173 * ) - NEW li1 ( 1173 2295 ) L1M1_PR_MR - NEW met1 ( 1173 2295 ) M1M2_PR - NEW met1 ( 1173 2499 ) M1M2_PR - NEW li1 ( 1127 2499 ) L1M1_PR_MR ; + + ROUTED met1 ( 1081 2261 ) ( 1149 * ) + NEW met2 ( 1081 2261 ) ( * 2499 ) + NEW li1 ( 1149 2261 ) L1M1_PR_MR + NEW met1 ( 1081 2261 ) M1M2_PR + NEW li1 ( 1081 2499 ) L1M1_PR_MR + NEW met1 ( 1081 2499 ) M1M2_PR ; - D_nets.b2 ( buffer.in[2] X ) ( neg_lat_b2.nlat D ) + USE SIGNAL - + ROUTED met2 ( 2139 2295 ) ( * 2499 ) - NEW met1 ( 2093 2499 ) ( 2139 * ) - NEW li1 ( 2139 2295 ) L1M1_PR_MR - NEW met1 ( 2139 2295 ) M1M2_PR - NEW met1 ( 2139 2499 ) M1M2_PR - NEW li1 ( 2093 2499 ) L1M1_PR_MR ; + + ROUTED met1 ( 2090 2261 ) ( 2093 * ) + NEW met2 ( 2093 2261 ) ( * 2499 ) + NEW met1 ( 2001 2499 ) ( 2093 * ) + NEW li1 ( 2090 2261 ) L1M1_PR_MR + NEW met1 ( 2093 2261 ) M1M2_PR + NEW met1 ( 2093 2499 ) M1M2_PR + NEW li1 ( 2001 2499 ) L1M1_PR_MR + NEW met1 ( 2090 2261 ) RECT ( -32 -7 0 7 ) ; - D_nets.b3 ( buffer.in[3] X ) ( neg_lat_b3.nlat D ) + USE SIGNAL - + ROUTED met2 ( 3105 2295 ) ( * 2499 ) - NEW met1 ( 3059 2499 ) ( 3105 * ) - NEW li1 ( 3105 2295 ) L1M1_PR_MR - NEW met1 ( 3105 2295 ) M1M2_PR - NEW met1 ( 3105 2499 ) M1M2_PR - NEW li1 ( 3059 2499 ) L1M1_PR_MR ; + + ROUTED met1 ( 2921 2261 ) ( 2989 * ) + NEW met2 ( 2921 2261 ) ( * 2499 ) + NEW li1 ( 2989 2261 ) L1M1_PR_MR + NEW met1 ( 2921 2261 ) M1M2_PR + NEW li1 ( 2921 2499 ) L1M1_PR_MR + NEW met1 ( 2921 2499 ) M1M2_PR ; - D_nets.b4 ( buffer.in[4] X ) ( neg_lat_b4.nlat D ) + USE SIGNAL - + ROUTED met2 ( 4071 2295 ) ( * 2499 ) - NEW met1 ( 4025 2499 ) ( 4071 * ) - NEW li1 ( 4071 2295 ) L1M1_PR_MR - NEW met1 ( 4071 2295 ) M1M2_PR - NEW met1 ( 4071 2499 ) M1M2_PR - NEW li1 ( 4025 2499 ) L1M1_PR_MR ; + + ROUTED met1 ( 3841 2261 ) ( 3909 * ) + NEW met2 ( 3841 2261 ) ( * 2499 ) + NEW li1 ( 3909 2261 ) L1M1_PR_MR + NEW met1 ( 3841 2261 ) M1M2_PR + NEW li1 ( 3841 2499 ) L1M1_PR_MR + NEW met1 ( 3841 2499 ) M1M2_PR ; - D_nets.b5 ( buffer.in[5] X ) ( neg_lat_b5.nlat D ) + USE SIGNAL - + ROUTED met2 ( 5037 2295 ) ( * 2499 ) - NEW met1 ( 4991 2499 ) ( 5037 * ) - NEW li1 ( 5037 2295 ) L1M1_PR_MR - NEW met1 ( 5037 2295 ) M1M2_PR - NEW met1 ( 5037 2499 ) M1M2_PR - NEW li1 ( 4991 2499 ) L1M1_PR_MR ; + + ROUTED met1 ( 4761 2261 ) ( 4829 * ) + NEW met2 ( 4761 2261 ) ( * 2499 ) + NEW li1 ( 4829 2261 ) L1M1_PR_MR + NEW met1 ( 4761 2261 ) M1M2_PR + NEW li1 ( 4761 2499 ) L1M1_PR_MR + NEW met1 ( 4761 2499 ) M1M2_PR ; - D_nets.b6 ( buffer.in[6] X ) ( neg_lat_b6.nlat D ) + USE SIGNAL - + ROUTED met1 ( 5911 2295 ) ( 6003 * ) - NEW met1 ( 5911 2261 ) ( * 2295 ) - NEW met2 ( 5911 2261 ) ( * 2499 ) - NEW met1 ( 5911 2499 ) ( 5957 * ) - NEW li1 ( 6003 2295 ) L1M1_PR_MR - NEW met1 ( 5911 2261 ) M1M2_PR - NEW met1 ( 5911 2499 ) M1M2_PR - NEW li1 ( 5957 2499 ) L1M1_PR_MR ; + + ROUTED met1 ( 5681 2261 ) ( 5749 * ) + NEW met2 ( 5681 2261 ) ( * 2499 ) + NEW li1 ( 5749 2261 ) L1M1_PR_MR + NEW met1 ( 5681 2261 ) M1M2_PR + NEW li1 ( 5681 2499 ) L1M1_PR_MR + NEW met1 ( 5681 2499 ) M1M2_PR ; - D_nets.b7 ( buffer.in[7] X ) ( neg_lat_b7.nlat D ) + USE SIGNAL - + ROUTED met2 ( 6969 2295 ) ( * 2499 ) - NEW met1 ( 6923 2499 ) ( 6969 * ) - NEW li1 ( 6969 2295 ) L1M1_PR_MR - NEW met1 ( 6969 2295 ) M1M2_PR - NEW met1 ( 6969 2499 ) M1M2_PR - NEW li1 ( 6923 2499 ) L1M1_PR_MR ; + + ROUTED met1 ( 6601 2261 ) ( 6669 * ) + NEW met2 ( 6601 2261 ) ( * 2499 ) + NEW li1 ( 6669 2261 ) L1M1_PR_MR + NEW met1 ( 6601 2261 ) M1M2_PR + NEW li1 ( 6601 2499 ) L1M1_PR_MR + NEW met1 ( 6601 2499 ) M1M2_PR ; - Q[0] ( PIN Q[0] ) ( storage_7_0_0.bit0.obuf0 Z ) ( storage_6_0_0.bit0.obuf0 Z ) ( storage_5_0_0.bit0.obuf0 Z ) ( storage_4_0_0.bit0.obuf0 Z ) ( storage_3_0_0.bit0.obuf0 Z ) ( storage_2_0_0.bit0.obuf0 Z ) ( storage_1_0_0.bit0.obuf0 Z ) ( storage_0_0_0.bit0.obuf0 Z ) + USE SIGNAL - + ROUTED met2 ( 943 2125 ) ( * 2686 0 ) - NEW met2 ( 943 1853 ) ( * 2125 ) - NEW met2 ( 943 1581 ) ( * 1853 ) - NEW met2 ( 943 1309 ) ( * 1581 ) - NEW met2 ( 943 1037 ) ( * 1309 ) - NEW met2 ( 943 765 ) ( * 1037 ) - NEW met2 ( 943 493 ) ( * 765 ) - NEW met2 ( 943 221 ) ( * 493 ) - NEW li1 ( 943 2125 ) L1M1_PR_MR - NEW met1 ( 943 2125 ) M1M2_PR - NEW li1 ( 943 1853 ) L1M1_PR_MR - NEW met1 ( 943 1853 ) M1M2_PR - NEW li1 ( 943 1581 ) L1M1_PR_MR - NEW met1 ( 943 1581 ) M1M2_PR - NEW li1 ( 943 1309 ) L1M1_PR_MR - NEW met1 ( 943 1309 ) M1M2_PR - NEW li1 ( 943 1037 ) L1M1_PR_MR - NEW met1 ( 943 1037 ) M1M2_PR - NEW li1 ( 943 765 ) L1M1_PR_MR - NEW met1 ( 943 765 ) M1M2_PR - NEW li1 ( 943 493 ) L1M1_PR_MR - NEW met1 ( 943 493 ) M1M2_PR - NEW li1 ( 943 221 ) L1M1_PR_MR - NEW met1 ( 943 221 ) M1M2_PR ; + + ROUTED met1 ( 851 2125 ) ( 897 * ) + NEW met2 ( 851 2125 ) ( * 2686 0 ) + NEW met2 ( 851 1853 ) ( * 2125 ) + NEW met1 ( 851 1581 ) ( 897 * ) + NEW met2 ( 851 1581 ) ( * 1853 ) + NEW met2 ( 851 1309 ) ( * 1581 ) + NEW met1 ( 851 1037 ) ( 897 * ) + NEW met2 ( 851 1037 ) ( * 1309 ) + NEW met2 ( 851 765 ) ( * 1037 ) + NEW met1 ( 851 493 ) ( 897 * ) + NEW met2 ( 851 493 ) ( * 765 ) + NEW met2 ( 851 221 ) ( * 493 ) + NEW li1 ( 897 2125 ) L1M1_PR_MR + NEW met1 ( 851 2125 ) M1M2_PR + NEW li1 ( 851 1853 ) L1M1_PR_MR + NEW met1 ( 851 1853 ) M1M2_PR + NEW li1 ( 897 1581 ) L1M1_PR_MR + NEW met1 ( 851 1581 ) M1M2_PR + NEW li1 ( 851 1309 ) L1M1_PR_MR + NEW met1 ( 851 1309 ) M1M2_PR + NEW li1 ( 897 1037 ) L1M1_PR_MR + NEW met1 ( 851 1037 ) M1M2_PR + NEW li1 ( 851 765 ) L1M1_PR_MR + NEW met1 ( 851 765 ) M1M2_PR + NEW li1 ( 897 493 ) L1M1_PR_MR + NEW met1 ( 851 493 ) M1M2_PR + NEW li1 ( 851 221 ) L1M1_PR_MR + NEW met1 ( 851 221 ) M1M2_PR ; - Q[1] ( PIN Q[1] ) ( storage_7_0_0.bit1.obuf0 Z ) ( storage_6_0_0.bit1.obuf0 Z ) ( storage_5_0_0.bit1.obuf0 Z ) ( storage_4_0_0.bit1.obuf0 Z ) ( storage_3_0_0.bit1.obuf0 Z ) ( storage_2_0_0.bit1.obuf0 Z ) ( storage_1_0_0.bit1.obuf0 Z ) ( storage_0_0_0.bit1.obuf0 Z ) + USE SIGNAL - + ROUTED met1 ( 1863 1037 ) ( 1909 * ) - NEW met2 ( 1863 1037 ) ( * 1309 ) - NEW met2 ( 1863 765 ) ( * 1037 ) - NEW met1 ( 1863 493 ) ( 1909 * ) - NEW met2 ( 1863 493 ) ( * 765 ) - NEW met2 ( 1863 221 ) ( * 493 ) - NEW met1 ( 1863 2125 ) ( 1909 * ) - NEW met2 ( 1863 2125 ) ( * 2686 0 ) - NEW met2 ( 1863 1853 ) ( * 2125 ) - NEW met1 ( 1863 1581 ) ( 1909 * ) - NEW met2 ( 1863 1581 ) ( * 1853 ) - NEW met2 ( 1863 1309 ) ( * 1581 ) - NEW li1 ( 1863 1309 ) L1M1_PR_MR - NEW met1 ( 1863 1309 ) M1M2_PR - NEW li1 ( 1909 1037 ) L1M1_PR_MR - NEW met1 ( 1863 1037 ) M1M2_PR - NEW li1 ( 1863 765 ) L1M1_PR_MR - NEW met1 ( 1863 765 ) M1M2_PR - NEW li1 ( 1909 493 ) L1M1_PR_MR - NEW met1 ( 1863 493 ) M1M2_PR - NEW li1 ( 1863 221 ) L1M1_PR_MR - NEW met1 ( 1863 221 ) M1M2_PR - NEW li1 ( 1909 2125 ) L1M1_PR_MR - NEW met1 ( 1863 2125 ) M1M2_PR - NEW li1 ( 1863 1853 ) L1M1_PR_MR - NEW met1 ( 1863 1853 ) M1M2_PR - NEW li1 ( 1909 1581 ) L1M1_PR_MR - NEW met1 ( 1863 1581 ) M1M2_PR ; + + ROUTED met1 ( 1771 1037 ) ( 1817 * ) + NEW met2 ( 1771 1037 ) ( * 1309 ) + NEW met2 ( 1771 765 ) ( * 1037 ) + NEW met1 ( 1771 493 ) ( 1817 * ) + NEW met2 ( 1771 493 ) ( * 765 ) + NEW met2 ( 1771 221 ) ( * 493 ) + NEW met1 ( 1771 2125 ) ( 1817 * ) + NEW met2 ( 1771 2125 ) ( * 2686 0 ) + NEW met2 ( 1771 1853 ) ( * 2125 ) + NEW met1 ( 1771 1581 ) ( 1817 * ) + NEW met2 ( 1771 1581 ) ( * 1853 ) + NEW met2 ( 1771 1309 ) ( * 1581 ) + NEW li1 ( 1771 1309 ) L1M1_PR_MR + NEW met1 ( 1771 1309 ) M1M2_PR + NEW li1 ( 1817 1037 ) L1M1_PR_MR + NEW met1 ( 1771 1037 ) M1M2_PR + NEW li1 ( 1771 765 ) L1M1_PR_MR + NEW met1 ( 1771 765 ) M1M2_PR + NEW li1 ( 1817 493 ) L1M1_PR_MR + NEW met1 ( 1771 493 ) M1M2_PR + NEW li1 ( 1771 221 ) L1M1_PR_MR + NEW met1 ( 1771 221 ) M1M2_PR + NEW li1 ( 1817 2125 ) L1M1_PR_MR + NEW met1 ( 1771 2125 ) M1M2_PR + NEW li1 ( 1771 1853 ) L1M1_PR_MR + NEW met1 ( 1771 1853 ) M1M2_PR + NEW li1 ( 1817 1581 ) L1M1_PR_MR + NEW met1 ( 1771 1581 ) M1M2_PR ; - Q[2] ( PIN Q[2] ) ( storage_7_0_0.bit2.obuf0 Z ) ( storage_6_0_0.bit2.obuf0 Z ) ( storage_5_0_0.bit2.obuf0 Z ) ( storage_4_0_0.bit2.obuf0 Z ) ( storage_3_0_0.bit2.obuf0 Z ) ( storage_2_0_0.bit2.obuf0 Z ) ( storage_1_0_0.bit2.obuf0 Z ) ( storage_0_0_0.bit2.obuf0 Z ) + USE SIGNAL - + ROUTED met2 ( 2875 1037 ) ( * 1309 ) - NEW met2 ( 2875 765 ) ( * 1037 ) - NEW met2 ( 2875 493 ) ( * 765 ) - NEW met2 ( 2875 221 ) ( * 493 ) - NEW met2 ( 2875 2125 ) ( * 2686 0 ) - NEW met2 ( 2875 1853 ) ( * 2125 ) - NEW met2 ( 2875 1581 ) ( * 1853 ) - NEW met2 ( 2875 1309 ) ( * 1581 ) - NEW li1 ( 2875 1309 ) L1M1_PR_MR - NEW met1 ( 2875 1309 ) M1M2_PR - NEW li1 ( 2875 1037 ) L1M1_PR_MR - NEW met1 ( 2875 1037 ) M1M2_PR - NEW li1 ( 2875 765 ) L1M1_PR_MR - NEW met1 ( 2875 765 ) M1M2_PR - NEW li1 ( 2875 493 ) L1M1_PR_MR - NEW met1 ( 2875 493 ) M1M2_PR - NEW li1 ( 2875 221 ) L1M1_PR_MR - NEW met1 ( 2875 221 ) M1M2_PR - NEW li1 ( 2875 2125 ) L1M1_PR_MR - NEW met1 ( 2875 2125 ) M1M2_PR - NEW li1 ( 2875 1853 ) L1M1_PR_MR - NEW met1 ( 2875 1853 ) M1M2_PR - NEW li1 ( 2875 1581 ) L1M1_PR_MR - NEW met1 ( 2875 1581 ) M1M2_PR ; + + ROUTED met1 ( 2691 1037 ) ( 2737 * ) + NEW met2 ( 2691 1037 ) ( * 1309 ) + NEW met2 ( 2691 765 ) ( * 1037 ) + NEW met1 ( 2691 493 ) ( 2737 * ) + NEW met2 ( 2691 493 ) ( * 765 ) + NEW met2 ( 2691 221 ) ( * 493 ) + NEW met1 ( 2691 2125 ) ( 2737 * ) + NEW met2 ( 2691 2125 ) ( * 2686 0 ) + NEW met2 ( 2691 1853 ) ( * 2125 ) + NEW met1 ( 2691 1581 ) ( 2737 * ) + NEW met2 ( 2691 1581 ) ( * 1853 ) + NEW met2 ( 2691 1309 ) ( * 1581 ) + NEW li1 ( 2691 1309 ) L1M1_PR_MR + NEW met1 ( 2691 1309 ) M1M2_PR + NEW li1 ( 2737 1037 ) L1M1_PR_MR + NEW met1 ( 2691 1037 ) M1M2_PR + NEW li1 ( 2691 765 ) L1M1_PR_MR + NEW met1 ( 2691 765 ) M1M2_PR + NEW li1 ( 2737 493 ) L1M1_PR_MR + NEW met1 ( 2691 493 ) M1M2_PR + NEW li1 ( 2691 221 ) L1M1_PR_MR + NEW met1 ( 2691 221 ) M1M2_PR + NEW li1 ( 2737 2125 ) L1M1_PR_MR + NEW met1 ( 2691 2125 ) M1M2_PR + NEW li1 ( 2691 1853 ) L1M1_PR_MR + NEW met1 ( 2691 1853 ) M1M2_PR + NEW li1 ( 2737 1581 ) L1M1_PR_MR + NEW met1 ( 2691 1581 ) M1M2_PR ; - Q[3] ( PIN Q[3] ) ( storage_7_0_0.bit3.obuf0 Z ) ( storage_6_0_0.bit3.obuf0 Z ) ( storage_5_0_0.bit3.obuf0 Z ) ( storage_4_0_0.bit3.obuf0 Z ) ( storage_3_0_0.bit3.obuf0 Z ) ( storage_2_0_0.bit3.obuf0 Z ) ( storage_1_0_0.bit3.obuf0 Z ) ( storage_0_0_0.bit3.obuf0 Z ) + USE SIGNAL - + ROUTED met1 ( 3795 1037 ) ( 3841 * ) - NEW met2 ( 3795 1037 ) ( * 1309 ) - NEW met2 ( 3795 765 ) ( * 1037 ) - NEW met1 ( 3795 493 ) ( 3841 * ) - NEW met2 ( 3795 493 ) ( * 765 ) - NEW met2 ( 3795 221 ) ( * 493 ) - NEW met1 ( 3795 2125 ) ( 3841 * ) - NEW met2 ( 3795 2125 ) ( * 2686 0 ) - NEW met2 ( 3795 1853 ) ( * 2125 ) - NEW met1 ( 3795 1581 ) ( 3841 * ) - NEW met2 ( 3795 1581 ) ( * 1853 ) - NEW met2 ( 3795 1309 ) ( * 1581 ) - NEW li1 ( 3795 1309 ) L1M1_PR_MR - NEW met1 ( 3795 1309 ) M1M2_PR - NEW li1 ( 3841 1037 ) L1M1_PR_MR - NEW met1 ( 3795 1037 ) M1M2_PR - NEW li1 ( 3795 765 ) L1M1_PR_MR - NEW met1 ( 3795 765 ) M1M2_PR - NEW li1 ( 3841 493 ) L1M1_PR_MR - NEW met1 ( 3795 493 ) M1M2_PR - NEW li1 ( 3795 221 ) L1M1_PR_MR - NEW met1 ( 3795 221 ) M1M2_PR - NEW li1 ( 3841 2125 ) L1M1_PR_MR - NEW met1 ( 3795 2125 ) M1M2_PR - NEW li1 ( 3795 1853 ) L1M1_PR_MR - NEW met1 ( 3795 1853 ) M1M2_PR - NEW li1 ( 3841 1581 ) L1M1_PR_MR - NEW met1 ( 3795 1581 ) M1M2_PR ; + + ROUTED met1 ( 3611 1037 ) ( 3657 * ) + NEW met2 ( 3611 1037 ) ( * 1309 ) + NEW met2 ( 3611 765 ) ( * 1037 ) + NEW met1 ( 3611 493 ) ( 3657 * ) + NEW met2 ( 3611 493 ) ( * 765 ) + NEW met2 ( 3611 221 ) ( * 493 ) + NEW met1 ( 3611 2125 ) ( 3657 * ) + NEW met2 ( 3611 2125 ) ( * 2686 0 ) + NEW met2 ( 3611 1853 ) ( * 2125 ) + NEW met1 ( 3611 1581 ) ( 3657 * ) + NEW met2 ( 3611 1581 ) ( * 1853 ) + NEW met2 ( 3611 1309 ) ( * 1581 ) + NEW li1 ( 3611 1309 ) L1M1_PR_MR + NEW met1 ( 3611 1309 ) M1M2_PR + NEW li1 ( 3657 1037 ) L1M1_PR_MR + NEW met1 ( 3611 1037 ) M1M2_PR + NEW li1 ( 3611 765 ) L1M1_PR_MR + NEW met1 ( 3611 765 ) M1M2_PR + NEW li1 ( 3657 493 ) L1M1_PR_MR + NEW met1 ( 3611 493 ) M1M2_PR + NEW li1 ( 3611 221 ) L1M1_PR_MR + NEW met1 ( 3611 221 ) M1M2_PR + NEW li1 ( 3657 2125 ) L1M1_PR_MR + NEW met1 ( 3611 2125 ) M1M2_PR + NEW li1 ( 3611 1853 ) L1M1_PR_MR + NEW met1 ( 3611 1853 ) M1M2_PR + NEW li1 ( 3657 1581 ) L1M1_PR_MR + NEW met1 ( 3611 1581 ) M1M2_PR ; - Q[4] ( PIN Q[4] ) ( storage_7_0_0.bit4.obuf0 Z ) ( storage_6_0_0.bit4.obuf0 Z ) ( storage_5_0_0.bit4.obuf0 Z ) ( storage_4_0_0.bit4.obuf0 Z ) ( storage_3_0_0.bit4.obuf0 Z ) ( storage_2_0_0.bit4.obuf0 Z ) ( storage_1_0_0.bit4.obuf0 Z ) ( storage_0_0_0.bit4.obuf0 Z ) + USE SIGNAL - + ROUTED met2 ( 4807 1037 ) ( * 1309 ) - NEW met2 ( 4807 765 ) ( * 1037 ) - NEW met2 ( 4807 493 ) ( * 765 ) - NEW met2 ( 4807 221 ) ( * 493 ) - NEW met2 ( 4807 2125 ) ( * 2686 0 ) - NEW met2 ( 4807 1853 ) ( * 2125 ) - NEW met2 ( 4807 1581 ) ( * 1853 ) - NEW met2 ( 4807 1309 ) ( * 1581 ) - NEW li1 ( 4807 1309 ) L1M1_PR_MR - NEW met1 ( 4807 1309 ) M1M2_PR - NEW li1 ( 4807 1037 ) L1M1_PR_MR - NEW met1 ( 4807 1037 ) M1M2_PR - NEW li1 ( 4807 765 ) L1M1_PR_MR - NEW met1 ( 4807 765 ) M1M2_PR - NEW li1 ( 4807 493 ) L1M1_PR_MR - NEW met1 ( 4807 493 ) M1M2_PR - NEW li1 ( 4807 221 ) L1M1_PR_MR - NEW met1 ( 4807 221 ) M1M2_PR - NEW li1 ( 4807 2125 ) L1M1_PR_MR - NEW met1 ( 4807 2125 ) M1M2_PR - NEW li1 ( 4807 1853 ) L1M1_PR_MR - NEW met1 ( 4807 1853 ) M1M2_PR - NEW li1 ( 4807 1581 ) L1M1_PR_MR - NEW met1 ( 4807 1581 ) M1M2_PR ; + + ROUTED met1 ( 4531 1037 ) ( 4577 * ) + NEW met2 ( 4531 1037 ) ( * 1309 ) + NEW met2 ( 4531 765 ) ( * 1037 ) + NEW met1 ( 4531 493 ) ( 4577 * ) + NEW met2 ( 4531 493 ) ( * 765 ) + NEW met2 ( 4531 221 ) ( * 493 ) + NEW met1 ( 4531 2125 ) ( 4577 * ) + NEW met2 ( 4531 2125 ) ( * 2686 0 ) + NEW met2 ( 4531 1853 ) ( * 2125 ) + NEW met1 ( 4531 1581 ) ( 4577 * ) + NEW met2 ( 4531 1581 ) ( * 1853 ) + NEW met2 ( 4531 1309 ) ( * 1581 ) + NEW li1 ( 4531 1309 ) L1M1_PR_MR + NEW met1 ( 4531 1309 ) M1M2_PR + NEW li1 ( 4577 1037 ) L1M1_PR_MR + NEW met1 ( 4531 1037 ) M1M2_PR + NEW li1 ( 4531 765 ) L1M1_PR_MR + NEW met1 ( 4531 765 ) M1M2_PR + NEW li1 ( 4577 493 ) L1M1_PR_MR + NEW met1 ( 4531 493 ) M1M2_PR + NEW li1 ( 4531 221 ) L1M1_PR_MR + NEW met1 ( 4531 221 ) M1M2_PR + NEW li1 ( 4577 2125 ) L1M1_PR_MR + NEW met1 ( 4531 2125 ) M1M2_PR + NEW li1 ( 4531 1853 ) L1M1_PR_MR + NEW met1 ( 4531 1853 ) M1M2_PR + NEW li1 ( 4577 1581 ) L1M1_PR_MR + NEW met1 ( 4531 1581 ) M1M2_PR ; - Q[5] ( PIN Q[5] ) ( storage_7_0_0.bit5.obuf0 Z ) ( storage_6_0_0.bit5.obuf0 Z ) ( storage_5_0_0.bit5.obuf0 Z ) ( storage_4_0_0.bit5.obuf0 Z ) ( storage_3_0_0.bit5.obuf0 Z ) ( storage_2_0_0.bit5.obuf0 Z ) ( storage_1_0_0.bit5.obuf0 Z ) ( storage_0_0_0.bit5.obuf0 Z ) + USE SIGNAL - + ROUTED met1 ( 5727 1037 ) ( 5773 * ) - NEW met2 ( 5727 1037 ) ( * 1309 ) - NEW met2 ( 5727 765 ) ( * 1037 ) - NEW met1 ( 5727 493 ) ( 5773 * ) - NEW met2 ( 5727 493 ) ( * 765 ) - NEW met2 ( 5727 221 ) ( * 493 ) - NEW met1 ( 5727 2125 ) ( 5773 * ) - NEW met2 ( 5727 2125 ) ( * 2686 0 ) - NEW met2 ( 5727 1853 ) ( * 2125 ) - NEW met1 ( 5727 1581 ) ( 5773 * ) - NEW met2 ( 5727 1581 ) ( * 1853 ) - NEW met2 ( 5727 1309 ) ( * 1581 ) - NEW li1 ( 5727 1309 ) L1M1_PR_MR - NEW met1 ( 5727 1309 ) M1M2_PR - NEW li1 ( 5773 1037 ) L1M1_PR_MR - NEW met1 ( 5727 1037 ) M1M2_PR - NEW li1 ( 5727 765 ) L1M1_PR_MR - NEW met1 ( 5727 765 ) M1M2_PR - NEW li1 ( 5773 493 ) L1M1_PR_MR - NEW met1 ( 5727 493 ) M1M2_PR - NEW li1 ( 5727 221 ) L1M1_PR_MR - NEW met1 ( 5727 221 ) M1M2_PR - NEW li1 ( 5773 2125 ) L1M1_PR_MR - NEW met1 ( 5727 2125 ) M1M2_PR - NEW li1 ( 5727 1853 ) L1M1_PR_MR - NEW met1 ( 5727 1853 ) M1M2_PR - NEW li1 ( 5773 1581 ) L1M1_PR_MR - NEW met1 ( 5727 1581 ) M1M2_PR ; + + ROUTED met1 ( 5451 1037 ) ( 5497 * ) + NEW met2 ( 5451 1037 ) ( * 1309 ) + NEW met2 ( 5451 765 ) ( * 1037 ) + NEW met1 ( 5451 493 ) ( 5497 * ) + NEW met2 ( 5451 493 ) ( * 765 ) + NEW met2 ( 5451 221 ) ( * 493 ) + NEW met1 ( 5451 2125 ) ( 5497 * ) + NEW met2 ( 5451 2125 ) ( * 2686 0 ) + NEW met2 ( 5451 1853 ) ( * 2125 ) + NEW met1 ( 5451 1581 ) ( 5497 * ) + NEW met2 ( 5451 1581 ) ( * 1853 ) + NEW met2 ( 5451 1309 ) ( * 1581 ) + NEW li1 ( 5451 1309 ) L1M1_PR_MR + NEW met1 ( 5451 1309 ) M1M2_PR + NEW li1 ( 5497 1037 ) L1M1_PR_MR + NEW met1 ( 5451 1037 ) M1M2_PR + NEW li1 ( 5451 765 ) L1M1_PR_MR + NEW met1 ( 5451 765 ) M1M2_PR + NEW li1 ( 5497 493 ) L1M1_PR_MR + NEW met1 ( 5451 493 ) M1M2_PR + NEW li1 ( 5451 221 ) L1M1_PR_MR + NEW met1 ( 5451 221 ) M1M2_PR + NEW li1 ( 5497 2125 ) L1M1_PR_MR + NEW met1 ( 5451 2125 ) M1M2_PR + NEW li1 ( 5451 1853 ) L1M1_PR_MR + NEW met1 ( 5451 1853 ) M1M2_PR + NEW li1 ( 5497 1581 ) L1M1_PR_MR + NEW met1 ( 5451 1581 ) M1M2_PR ; - Q[6] ( PIN Q[6] ) ( storage_7_0_0.bit6.obuf0 Z ) ( storage_6_0_0.bit6.obuf0 Z ) ( storage_5_0_0.bit6.obuf0 Z ) ( storage_4_0_0.bit6.obuf0 Z ) ( storage_3_0_0.bit6.obuf0 Z ) ( storage_2_0_0.bit6.obuf0 Z ) ( storage_1_0_0.bit6.obuf0 Z ) ( storage_0_0_0.bit6.obuf0 Z ) + USE SIGNAL - + ROUTED met2 ( 6739 1037 ) ( * 1309 ) - NEW met2 ( 6739 765 ) ( * 1037 ) - NEW met2 ( 6739 493 ) ( * 765 ) - NEW met2 ( 6739 221 ) ( * 493 ) - NEW met2 ( 6739 2125 ) ( * 2686 0 ) - NEW met2 ( 6739 1853 ) ( * 2125 ) - NEW met2 ( 6739 1581 ) ( * 1853 ) - NEW met2 ( 6739 1309 ) ( * 1581 ) - NEW li1 ( 6739 1309 ) L1M1_PR_MR - NEW met1 ( 6739 1309 ) M1M2_PR - NEW li1 ( 6739 1037 ) L1M1_PR_MR - NEW met1 ( 6739 1037 ) M1M2_PR - NEW li1 ( 6739 765 ) L1M1_PR_MR - NEW met1 ( 6739 765 ) M1M2_PR - NEW li1 ( 6739 493 ) L1M1_PR_MR - NEW met1 ( 6739 493 ) M1M2_PR - NEW li1 ( 6739 221 ) L1M1_PR_MR - NEW met1 ( 6739 221 ) M1M2_PR - NEW li1 ( 6739 2125 ) L1M1_PR_MR - NEW met1 ( 6739 2125 ) M1M2_PR - NEW li1 ( 6739 1853 ) L1M1_PR_MR - NEW met1 ( 6739 1853 ) M1M2_PR - NEW li1 ( 6739 1581 ) L1M1_PR_MR - NEW met1 ( 6739 1581 ) M1M2_PR ; + + ROUTED met1 ( 6371 1037 ) ( 6417 * ) + NEW met2 ( 6371 1037 ) ( * 1309 ) + NEW met2 ( 6371 765 ) ( * 1037 ) + NEW met1 ( 6371 493 ) ( 6417 * ) + NEW met2 ( 6371 493 ) ( * 765 ) + NEW met2 ( 6371 221 ) ( * 493 ) + NEW met1 ( 6371 2125 ) ( 6417 * ) + NEW met2 ( 6371 2125 ) ( * 2686 0 ) + NEW met2 ( 6371 1853 ) ( * 2125 ) + NEW met1 ( 6371 1581 ) ( 6417 * ) + NEW met2 ( 6371 1581 ) ( * 1853 ) + NEW met2 ( 6371 1309 ) ( * 1581 ) + NEW li1 ( 6371 1309 ) L1M1_PR_MR + NEW met1 ( 6371 1309 ) M1M2_PR + NEW li1 ( 6417 1037 ) L1M1_PR_MR + NEW met1 ( 6371 1037 ) M1M2_PR + NEW li1 ( 6371 765 ) L1M1_PR_MR + NEW met1 ( 6371 765 ) M1M2_PR + NEW li1 ( 6417 493 ) L1M1_PR_MR + NEW met1 ( 6371 493 ) M1M2_PR + NEW li1 ( 6371 221 ) L1M1_PR_MR + NEW met1 ( 6371 221 ) M1M2_PR + NEW li1 ( 6417 2125 ) L1M1_PR_MR + NEW met1 ( 6371 2125 ) M1M2_PR + NEW li1 ( 6371 1853 ) L1M1_PR_MR + NEW met1 ( 6371 1853 ) M1M2_PR + NEW li1 ( 6417 1581 ) L1M1_PR_MR + NEW met1 ( 6371 1581 ) M1M2_PR ; - Q[7] ( PIN Q[7] ) ( storage_7_0_0.bit7.obuf0 Z ) ( storage_6_0_0.bit7.obuf0 Z ) ( storage_5_0_0.bit7.obuf0 Z ) ( storage_4_0_0.bit7.obuf0 Z ) ( storage_3_0_0.bit7.obuf0 Z ) ( storage_2_0_0.bit7.obuf0 Z ) ( storage_1_0_0.bit7.obuf0 Z ) ( storage_0_0_0.bit7.obuf0 Z ) + USE SIGNAL - + ROUTED met1 ( 7659 2125 ) ( 7705 * ) - NEW met2 ( 7659 2125 ) ( * 2686 0 ) - NEW met2 ( 7705 1785 ) ( * 1802 ) - NEW met2 ( 7659 1802 ) ( 7705 * ) - NEW met2 ( 7659 1802 ) ( * 2125 ) - NEW met2 ( 7705 1581 ) ( * 1785 ) - NEW met2 ( 7705 1241 ) ( * 1581 ) - NEW met2 ( 7705 1037 ) ( * 1241 ) - NEW met2 ( 7705 765 ) ( * 1037 ) - NEW met2 ( 7705 493 ) ( * 765 ) - NEW met2 ( 7705 153 ) ( * 493 ) - NEW li1 ( 7705 2125 ) L1M1_PR_MR - NEW met1 ( 7659 2125 ) M1M2_PR - NEW li1 ( 7705 1785 ) L1M1_PR_MR - NEW met1 ( 7705 1785 ) M1M2_PR - NEW li1 ( 7705 1581 ) L1M1_PR_MR - NEW met1 ( 7705 1581 ) M1M2_PR - NEW li1 ( 7705 1241 ) L1M1_PR_MR - NEW met1 ( 7705 1241 ) M1M2_PR - NEW li1 ( 7705 1037 ) L1M1_PR_MR - NEW met1 ( 7705 1037 ) M1M2_PR - NEW li1 ( 7705 765 ) L1M1_PR_MR - NEW met1 ( 7705 765 ) M1M2_PR - NEW li1 ( 7705 493 ) L1M1_PR_MR - NEW met1 ( 7705 493 ) M1M2_PR - NEW li1 ( 7705 153 ) L1M1_PR_MR - NEW met1 ( 7705 153 ) M1M2_PR ; + + ROUTED met1 ( 7291 1037 ) ( 7337 * ) + NEW met2 ( 7291 1037 ) ( * 1309 ) + NEW met2 ( 7291 765 ) ( * 1037 ) + NEW met1 ( 7291 493 ) ( 7337 * ) + NEW met2 ( 7291 493 ) ( * 765 ) + NEW met2 ( 7291 221 ) ( * 493 ) + NEW met1 ( 7291 2125 ) ( 7337 * ) + NEW met2 ( 7291 2125 ) ( * 2686 0 ) + NEW met1 ( 7291 1785 ) ( 7337 * ) + NEW met2 ( 7291 1785 ) ( * 2125 ) + NEW met1 ( 7291 1581 ) ( 7337 * ) + NEW met2 ( 7291 1581 ) ( * 1785 ) + NEW met2 ( 7291 1309 ) ( * 1581 ) + NEW li1 ( 7291 1309 ) L1M1_PR_MR + NEW met1 ( 7291 1309 ) M1M2_PR + NEW li1 ( 7337 1037 ) L1M1_PR_MR + NEW met1 ( 7291 1037 ) M1M2_PR + NEW li1 ( 7291 765 ) L1M1_PR_MR + NEW met1 ( 7291 765 ) M1M2_PR + NEW li1 ( 7337 493 ) L1M1_PR_MR + NEW met1 ( 7291 493 ) M1M2_PR + NEW li1 ( 7291 221 ) L1M1_PR_MR + NEW met1 ( 7291 221 ) M1M2_PR + NEW li1 ( 7337 2125 ) L1M1_PR_MR + NEW met1 ( 7291 2125 ) M1M2_PR + NEW li1 ( 7337 1785 ) L1M1_PR_MR + NEW met1 ( 7291 1785 ) M1M2_PR + NEW li1 ( 7337 1581 ) L1M1_PR_MR + NEW met1 ( 7291 1581 ) M1M2_PR ; - addr_rw.inv_addr[0] ( decoder_p0.inv_p0_a0 Y ) ( decoder_p0.and_layer0_word6 A ) ( decoder_p0.and_layer0_word4 A ) ( decoder_p0.and_layer0_word2 A ) ( decoder_p0.and_layer0_word0 A ) + USE SIGNAL - + ROUTED met2 ( 8993 187 ) ( * 697 ) - NEW met2 ( 8993 697 ) ( * 1241 ) - NEW met1 ( 8993 1275 ) ( 9499 * ) - NEW met1 ( 8993 1241 ) ( * 1275 ) - NEW met2 ( 8993 1241 ) ( * 1785 ) - NEW li1 ( 8993 697 ) L1M1_PR_MR - NEW met1 ( 8993 697 ) M1M2_PR - NEW li1 ( 8993 187 ) L1M1_PR_MR - NEW met1 ( 8993 187 ) M1M2_PR - NEW li1 ( 8993 1241 ) L1M1_PR_MR - NEW met1 ( 8993 1241 ) M1M2_PR - NEW li1 ( 9499 1275 ) L1M1_PR_MR - NEW li1 ( 8993 1785 ) L1M1_PR_MR - NEW met1 ( 8993 1785 ) M1M2_PR ; + + ROUTED met2 ( 8625 187 ) ( * 697 ) + NEW met2 ( 8625 697 ) ( * 1241 ) + NEW met1 ( 8625 1275 ) ( 9131 * ) + NEW met1 ( 8625 1241 ) ( * 1275 ) + NEW met2 ( 8625 1241 ) ( * 1785 ) + NEW li1 ( 8625 697 ) L1M1_PR_MR + NEW met1 ( 8625 697 ) M1M2_PR + NEW li1 ( 8625 187 ) L1M1_PR_MR + NEW met1 ( 8625 187 ) M1M2_PR + NEW li1 ( 8625 1241 ) L1M1_PR_MR + NEW met1 ( 8625 1241 ) M1M2_PR + NEW li1 ( 9131 1275 ) L1M1_PR_MR + NEW li1 ( 8625 1785 ) L1M1_PR_MR + NEW met1 ( 8625 1785 ) M1M2_PR ; - addr_rw.inv_addr[1] ( decoder_p0.inv_p0_a1 Y ) ( decoder_p0.and_layer1_word5 A ) ( decoder_p0.and_layer1_word4 A ) ( decoder_p0.and_layer1_word1 A ) ( decoder_p0.and_layer1_word0 A ) + USE SIGNAL - + ROUTED met2 ( 9223 1241 ) ( * 1445 ) - NEW met1 ( 9223 765 ) ( 9499 * ) - NEW met2 ( 9223 765 ) ( * 1241 ) - NEW met2 ( 9223 391 ) ( * 765 ) - NEW met2 ( 9223 187 ) ( * 391 ) - NEW li1 ( 9223 1241 ) L1M1_PR_MR - NEW met1 ( 9223 1241 ) M1M2_PR - NEW li1 ( 9223 1445 ) L1M1_PR_MR - NEW met1 ( 9223 1445 ) M1M2_PR - NEW li1 ( 9499 765 ) L1M1_PR_MR - NEW met1 ( 9223 765 ) M1M2_PR - NEW li1 ( 9223 391 ) L1M1_PR_MR - NEW met1 ( 9223 391 ) M1M2_PR - NEW li1 ( 9223 187 ) L1M1_PR_MR - NEW met1 ( 9223 187 ) M1M2_PR ; + + ROUTED met1 ( 8855 765 ) ( 9131 * ) + NEW met2 ( 8855 765 ) ( * 1241 ) + NEW met2 ( 8855 391 ) ( * 765 ) + NEW met2 ( 8855 187 ) ( * 391 ) + NEW met2 ( 8855 1241 ) ( * 1445 ) + NEW li1 ( 8855 1241 ) L1M1_PR_MR + NEW met1 ( 8855 1241 ) M1M2_PR + NEW li1 ( 9131 765 ) L1M1_PR_MR + NEW met1 ( 8855 765 ) M1M2_PR + NEW li1 ( 8855 391 ) L1M1_PR_MR + NEW met1 ( 8855 391 ) M1M2_PR + NEW li1 ( 8855 187 ) L1M1_PR_MR + NEW met1 ( 8855 187 ) M1M2_PR + NEW li1 ( 8855 1445 ) L1M1_PR_MR + NEW met1 ( 8855 1445 ) M1M2_PR ; - addr_rw.inv_addr[2] ( decoder_p0.inv_p0_a2 Y ) ( decoder_p0.and_layer1_word3 B ) ( decoder_p0.and_layer1_word2 B ) ( decoder_p0.and_layer1_word1 B ) ( decoder_p0.and_layer1_word0 B ) + USE SIGNAL - + ROUTED met2 ( 9315 697 ) ( * 935 ) - NEW met2 ( 9315 425 ) ( * 697 ) - NEW met2 ( 9315 153 ) ( * 425 ) - NEW met1 ( 9315 153 ) ( 9499 * ) - NEW li1 ( 9315 697 ) L1M1_PR_MR - NEW met1 ( 9315 697 ) M1M2_PR - NEW li1 ( 9315 935 ) L1M1_PR_MR - NEW met1 ( 9315 935 ) M1M2_PR - NEW li1 ( 9315 425 ) L1M1_PR_MR - NEW met1 ( 9315 425 ) M1M2_PR - NEW li1 ( 9315 153 ) L1M1_PR_MR - NEW met1 ( 9315 153 ) M1M2_PR - NEW li1 ( 9499 153 ) L1M1_PR_MR ; + + ROUTED met2 ( 8947 697 ) ( * 935 ) + NEW met2 ( 8947 425 ) ( * 697 ) + NEW met2 ( 8947 153 ) ( * 425 ) + NEW met1 ( 8947 153 ) ( 9131 * ) + NEW li1 ( 8947 697 ) L1M1_PR_MR + NEW met1 ( 8947 697 ) M1M2_PR + NEW li1 ( 8947 935 ) L1M1_PR_MR + NEW met1 ( 8947 935 ) M1M2_PR + NEW li1 ( 8947 425 ) L1M1_PR_MR + NEW met1 ( 8947 425 ) M1M2_PR + NEW li1 ( 8947 153 ) L1M1_PR_MR + NEW met1 ( 8947 153 ) M1M2_PR + NEW li1 ( 9131 153 ) L1M1_PR_MR ; - addr_rw[0] ( PIN addr_rw[0] ) ( decoder_p0.inv_p0_a0 A ) ( decoder_p0.and_layer0_word7 A ) ( decoder_p0.and_layer0_word5 A ) ( decoder_p0.and_layer0_word3 A ) ( decoder_p0.and_layer0_word1 A ) + USE SIGNAL - + ROUTED met1 ( 8993 391 ) ( 9039 * ) - NEW met2 ( 9039 391 ) ( * 442 ) - NEW met3 ( 9039 442 ) ( 9522 * 0 ) - NEW met1 ( 8993 901 ) ( 9039 * ) - NEW met2 ( 9039 442 ) ( * 901 ) - NEW met1 ( 9039 1173 ) ( 9453 * ) - NEW met2 ( 9039 901 ) ( * 1173 ) - NEW met1 ( 8993 1445 ) ( 9039 * ) - NEW met2 ( 9039 1173 ) ( * 1445 ) - NEW met1 ( 8993 1989 ) ( 9039 * ) - NEW met2 ( 9039 1445 ) ( * 1989 ) - NEW li1 ( 8993 391 ) L1M1_PR_MR - NEW met1 ( 9039 391 ) M1M2_PR - NEW met2 ( 9039 442 ) M2M3_PR - NEW li1 ( 8993 901 ) L1M1_PR_MR - NEW met1 ( 9039 901 ) M1M2_PR - NEW li1 ( 9453 1173 ) L1M1_PR_MR - NEW met1 ( 9039 1173 ) M1M2_PR - NEW li1 ( 8993 1445 ) L1M1_PR_MR - NEW met1 ( 9039 1445 ) M1M2_PR - NEW li1 ( 8993 1989 ) L1M1_PR_MR - NEW met1 ( 9039 1989 ) M1M2_PR ; + + ROUTED met1 ( 8625 391 ) ( 8671 * ) + NEW met2 ( 8671 391 ) ( * 442 ) + NEW met3 ( 8671 442 ) ( 9154 * 0 ) + NEW met1 ( 8625 901 ) ( 8671 * ) + NEW met2 ( 8671 442 ) ( * 901 ) + NEW met1 ( 8671 1173 ) ( 9085 * ) + NEW met2 ( 8671 901 ) ( * 1173 ) + NEW met1 ( 8625 1479 ) ( 8671 * ) + NEW met2 ( 8671 1479 ) ( * 1989 ) + NEW met1 ( 8625 1989 ) ( 8671 * ) + NEW met2 ( 8671 1173 ) ( * 1479 ) + NEW li1 ( 8625 391 ) L1M1_PR_MR + NEW met1 ( 8671 391 ) M1M2_PR + NEW met2 ( 8671 442 ) M2M3_PR + NEW li1 ( 8625 901 ) L1M1_PR_MR + NEW met1 ( 8671 901 ) M1M2_PR + NEW li1 ( 9085 1173 ) L1M1_PR_MR + NEW met1 ( 8671 1173 ) M1M2_PR + NEW li1 ( 8625 1479 ) L1M1_PR_MR + NEW met1 ( 8671 1479 ) M1M2_PR + NEW met1 ( 8671 1989 ) M1M2_PR + NEW li1 ( 8625 1989 ) L1M1_PR_MR ; - addr_rw[1] ( PIN addr_rw[1] ) ( decoder_p0.inv_p0_a1 A ) ( decoder_p0.and_layer1_word7 A ) ( decoder_p0.and_layer1_word6 A ) ( decoder_p0.and_layer1_word3 A ) ( decoder_p0.and_layer1_word2 A ) + USE SIGNAL - + ROUTED met2 ( 9453 663 ) ( * 714 ) - NEW met3 ( 9453 714 ) ( 9522 * 0 ) - NEW met1 ( 9223 663 ) ( * 697 ) - NEW met1 ( 9223 663 ) ( 9453 * ) - NEW met1 ( 9223 901 ) ( 9453 * ) - NEW met2 ( 9453 714 ) ( * 901 ) - NEW met1 ( 9223 1785 ) ( 9453 * ) - NEW met2 ( 9453 901 ) ( * 1785 ) - NEW met2 ( 9223 1785 ) ( * 1989 ) - NEW li1 ( 9453 663 ) L1M1_PR_MR - NEW met1 ( 9453 663 ) M1M2_PR - NEW met2 ( 9453 714 ) M2M3_PR - NEW li1 ( 9223 697 ) L1M1_PR_MR - NEW li1 ( 9223 901 ) L1M1_PR_MR - NEW met1 ( 9453 901 ) M1M2_PR - NEW li1 ( 9223 1785 ) L1M1_PR_MR - NEW met1 ( 9453 1785 ) M1M2_PR - NEW li1 ( 9223 1989 ) L1M1_PR_MR - NEW met1 ( 9223 1989 ) M1M2_PR - NEW met1 ( 9223 1785 ) M1M2_PR ; + + ROUTED met2 ( 9085 663 ) ( * 714 ) + NEW met3 ( 9085 714 ) ( 9154 * 0 ) + NEW met1 ( 8855 663 ) ( * 697 ) + NEW met1 ( 8855 663 ) ( 9085 * ) + NEW met1 ( 8855 901 ) ( 9085 * ) + NEW met2 ( 9085 714 ) ( * 901 ) + NEW met1 ( 8855 1785 ) ( 9085 * ) + NEW met2 ( 8855 1785 ) ( * 1989 ) + NEW met2 ( 9085 901 ) ( * 1785 ) + NEW li1 ( 9085 663 ) L1M1_PR_MR + NEW met1 ( 9085 663 ) M1M2_PR + NEW met2 ( 9085 714 ) M2M3_PR + NEW li1 ( 8855 697 ) L1M1_PR_MR + NEW li1 ( 8855 901 ) L1M1_PR_MR + NEW met1 ( 9085 901 ) M1M2_PR + NEW li1 ( 8855 1785 ) L1M1_PR_MR + NEW met1 ( 9085 1785 ) M1M2_PR + NEW li1 ( 8855 1989 ) L1M1_PR_MR + NEW met1 ( 8855 1989 ) M1M2_PR + NEW met1 ( 8855 1785 ) M1M2_PR ; - addr_rw[2] ( PIN addr_rw[2] ) ( decoder_p0.inv_p0_a2 A ) ( decoder_p0.and_layer1_word7 B ) ( decoder_p0.and_layer1_word6 B ) ( decoder_p0.and_layer1_word5 B ) ( decoder_p0.and_layer1_word4 B ) + USE SIGNAL - + ROUTED met2 ( 9453 119 ) ( * 170 ) - NEW met3 ( 9453 170 ) ( 9522 * 0 ) - NEW met1 ( 9315 1207 ) ( 9407 * ) - NEW met2 ( 9407 170 ) ( * 1207 ) - NEW met2 ( 9407 170 ) ( 9453 * ) - NEW met1 ( 9315 1479 ) ( 9407 * ) - NEW met2 ( 9407 1207 ) ( * 1479 ) - NEW met1 ( 9315 1751 ) ( 9407 * ) - NEW met2 ( 9407 1479 ) ( * 1751 ) - NEW met1 ( 9315 2023 ) ( 9407 * ) - NEW met2 ( 9407 1751 ) ( * 2023 ) - NEW li1 ( 9453 119 ) L1M1_PR_MR - NEW met1 ( 9453 119 ) M1M2_PR - NEW met2 ( 9453 170 ) M2M3_PR - NEW li1 ( 9315 1207 ) L1M1_PR_MR - NEW met1 ( 9407 1207 ) M1M2_PR - NEW li1 ( 9315 1479 ) L1M1_PR_MR - NEW met1 ( 9407 1479 ) M1M2_PR - NEW li1 ( 9315 1751 ) L1M1_PR_MR - NEW met1 ( 9407 1751 ) M1M2_PR - NEW li1 ( 9315 2023 ) L1M1_PR_MR - NEW met1 ( 9407 2023 ) M1M2_PR ; + + ROUTED met2 ( 9085 119 ) ( * 170 ) + NEW met3 ( 9085 170 ) ( 9154 * 0 ) + NEW met1 ( 8947 1207 ) ( 9039 * ) + NEW met2 ( 9039 170 ) ( * 1207 ) + NEW met2 ( 9039 170 ) ( 9085 * ) + NEW met1 ( 8947 1479 ) ( 9039 * ) + NEW met1 ( 8947 1751 ) ( 9039 * ) + NEW met2 ( 9039 1479 ) ( * 1751 ) + NEW met1 ( 8947 2023 ) ( 9039 * ) + NEW met2 ( 9039 1751 ) ( * 2023 ) + NEW met2 ( 9039 1207 ) ( * 1479 ) + NEW li1 ( 9085 119 ) L1M1_PR_MR + NEW met1 ( 9085 119 ) M1M2_PR + NEW met2 ( 9085 170 ) M2M3_PR + NEW li1 ( 8947 1207 ) L1M1_PR_MR + NEW met1 ( 9039 1207 ) M1M2_PR + NEW li1 ( 8947 1479 ) L1M1_PR_MR + NEW met1 ( 9039 1479 ) M1M2_PR + NEW li1 ( 8947 1751 ) L1M1_PR_MR + NEW met1 ( 9039 1751 ) M1M2_PR + NEW li1 ( 8947 2023 ) L1M1_PR_MR + NEW met1 ( 9039 2023 ) M1M2_PR ; - clk ( PIN clk ) ( neg_row.clk_inv A ) ( storage_7_0_0.cg CLK ) ( storage_6_0_0.cg CLK ) ( storage_5_0_0.cg CLK ) ( storage_4_0_0.cg CLK ) ( storage_3_0_0.cg CLK ) ( storage_2_0_0.cg CLK ) ( storage_1_0_0.cg CLK ) ( storage_0_0_0.cg CLK ) + USE SIGNAL - + ROUTED met2 ( 8073 2057 ) ( * 2686 ) - NEW met2 ( 8027 2686 0 ) ( 8073 * ) - NEW met2 ( 8073 1751 ) ( * 2057 ) - NEW met2 ( 8073 1513 ) ( * 1751 ) - NEW met2 ( 8073 1207 ) ( * 1513 ) - NEW met2 ( 8073 969 ) ( * 1207 ) - NEW met2 ( 8073 663 ) ( * 969 ) - NEW met2 ( 8073 425 ) ( * 663 ) - NEW met2 ( 8073 119 ) ( * 425 ) - NEW met1 ( 7797 2227 ) ( 8073 * ) - NEW met1 ( 8073 2057 ) M1M2_PR - NEW met1 ( 8073 1751 ) M1M2_PR - NEW met1 ( 8073 1513 ) M1M2_PR - NEW met1 ( 8073 1207 ) M1M2_PR - NEW met1 ( 8073 969 ) M1M2_PR - NEW met1 ( 8073 663 ) M1M2_PR - NEW met1 ( 8073 425 ) M1M2_PR - NEW met1 ( 8073 119 ) M1M2_PR - NEW li1 ( 7797 2227 ) L1M1_PR_MR - NEW met1 ( 8073 2227 ) M1M2_PR ; + + ROUTED met2 ( 7659 119 ) ( * 425 ) + NEW met2 ( 7659 425 ) ( * 663 ) + NEW met2 ( 7659 663 ) ( * 969 ) + NEW met2 ( 7659 969 ) ( * 1207 ) + NEW met2 ( 7659 2057 ) ( * 2686 0 ) + NEW met2 ( 7659 1751 ) ( * 2057 ) + NEW met2 ( 7659 1513 ) ( * 1751 ) + NEW met1 ( 7429 2261 ) ( 7659 * ) + NEW met2 ( 7659 1207 ) ( * 1513 ) + NEW met1 ( 7659 425 ) M1M2_PR + NEW met1 ( 7659 119 ) M1M2_PR + NEW met1 ( 7659 663 ) M1M2_PR + NEW met1 ( 7659 969 ) M1M2_PR + NEW met1 ( 7659 1207 ) M1M2_PR + NEW met1 ( 7659 2057 ) M1M2_PR + NEW met1 ( 7659 1751 ) M1M2_PR + NEW met1 ( 7659 1513 ) M1M2_PR + NEW li1 ( 7429 2261 ) L1M1_PR_MR + NEW met1 ( 7659 2261 ) M1M2_PR ; - decoder_p0.layer_in0_word0 ( decoder_p0.and_layer1_word0 X ) ( decoder_p0.and_layer0_word0 B ) + USE SIGNAL - + ROUTED met1 ( 9085 119 ) ( 9407 * ) - NEW li1 ( 9085 119 ) L1M1_PR_MR - NEW li1 ( 9407 119 ) L1M1_PR_MR ; + + ROUTED met1 ( 8717 119 ) ( 9039 * ) + NEW li1 ( 8717 119 ) L1M1_PR_MR + NEW li1 ( 9039 119 ) L1M1_PR_MR ; - decoder_p0.layer_in0_word1 ( decoder_p0.and_layer1_word1 X ) ( decoder_p0.and_layer0_word1 B ) + USE SIGNAL - + ROUTED met1 ( 9085 357 ) ( * 391 ) - NEW met1 ( 9085 357 ) ( 9407 * ) - NEW li1 ( 9085 391 ) L1M1_PR_MR - NEW li1 ( 9407 357 ) L1M1_PR_MR ; + + ROUTED met1 ( 8717 357 ) ( * 391 ) + NEW met1 ( 8717 357 ) ( 9039 * ) + NEW li1 ( 8717 391 ) L1M1_PR_MR + NEW li1 ( 9039 357 ) L1M1_PR_MR ; - decoder_p0.layer_in0_word2 ( decoder_p0.and_layer1_word2 X ) ( decoder_p0.and_layer0_word2 B ) + USE SIGNAL - + ROUTED met1 ( 9085 629 ) ( * 663 ) - NEW met1 ( 9085 629 ) ( 9407 * ) - NEW li1 ( 9085 663 ) L1M1_PR_MR - NEW li1 ( 9407 629 ) L1M1_PR_MR ; + + ROUTED met1 ( 8717 629 ) ( * 663 ) + NEW met1 ( 8717 629 ) ( 9039 * ) + NEW li1 ( 8717 663 ) L1M1_PR_MR + NEW li1 ( 9039 629 ) L1M1_PR_MR ; - decoder_p0.layer_in0_word3 ( decoder_p0.and_layer1_word3 X ) ( decoder_p0.and_layer0_word3 B ) + USE SIGNAL - + ROUTED met1 ( 9085 969 ) ( 9407 * ) - NEW li1 ( 9085 969 ) L1M1_PR_MR - NEW li1 ( 9407 969 ) L1M1_PR_MR ; + + ROUTED met1 ( 8717 969 ) ( 9039 * ) + NEW li1 ( 8717 969 ) L1M1_PR_MR + NEW li1 ( 9039 969 ) L1M1_PR_MR ; - decoder_p0.layer_in0_word4 ( decoder_p0.and_layer1_word4 X ) ( decoder_p0.and_layer0_word4 B ) + USE SIGNAL - + ROUTED met2 ( 9085 1241 ) ( * 1309 ) - NEW met1 ( 9085 1309 ) ( 9407 * ) - NEW li1 ( 9085 1241 ) L1M1_PR_MR - NEW met1 ( 9085 1241 ) M1M2_PR - NEW met1 ( 9085 1309 ) M1M2_PR - NEW li1 ( 9407 1309 ) L1M1_PR_MR ; + + ROUTED met1 ( 8579 1207 ) ( 8717 * ) + NEW met1 ( 8579 1207 ) ( * 1309 ) + NEW met1 ( 8579 1309 ) ( 9039 * ) + NEW li1 ( 8717 1207 ) L1M1_PR_MR + NEW li1 ( 9039 1309 ) L1M1_PR_MR ; - decoder_p0.layer_in0_word5 ( decoder_p0.and_layer1_word5 X ) ( decoder_p0.and_layer0_word5 B ) + USE SIGNAL - + ROUTED met1 ( 9085 1513 ) ( * 1547 ) - NEW met1 ( 9085 1547 ) ( 9407 * ) - NEW li1 ( 9085 1513 ) L1M1_PR_MR - NEW li1 ( 9407 1547 ) L1M1_PR_MR ; + + ROUTED met1 ( 8717 1513 ) ( * 1547 ) + NEW met1 ( 8717 1547 ) ( 9039 * ) + NEW li1 ( 8717 1513 ) L1M1_PR_MR + NEW li1 ( 9039 1547 ) L1M1_PR_MR ; - decoder_p0.layer_in0_word6 ( decoder_p0.and_layer1_word6 X ) ( decoder_p0.and_layer0_word6 B ) + USE SIGNAL - + ROUTED met1 ( 9085 1785 ) ( * 1819 ) - NEW met1 ( 9085 1819 ) ( 9407 * ) - NEW li1 ( 9085 1785 ) L1M1_PR_MR - NEW li1 ( 9407 1819 ) L1M1_PR_MR ; + + ROUTED met1 ( 8717 1785 ) ( * 1819 ) + NEW met1 ( 8717 1819 ) ( 9039 * ) + NEW li1 ( 8717 1785 ) L1M1_PR_MR + NEW li1 ( 9039 1819 ) L1M1_PR_MR ; - decoder_p0.layer_in0_word7 ( decoder_p0.and_layer1_word7 X ) ( decoder_p0.and_layer0_word7 B ) + USE SIGNAL - + ROUTED met1 ( 9085 2057 ) ( * 2091 ) - NEW met1 ( 9085 2091 ) ( 9407 * ) - NEW li1 ( 9085 2057 ) L1M1_PR_MR - NEW li1 ( 9407 2091 ) L1M1_PR_MR ; + + ROUTED met1 ( 8717 2057 ) ( * 2091 ) + NEW met1 ( 8717 2091 ) ( 9039 * ) + NEW li1 ( 8717 2057 ) L1M1_PR_MR + NEW li1 ( 9039 2091 ) L1M1_PR_MR ; - decoder_p0.word0 ( decoder_p0.and_layer0_word0 X ) ( sel_buf_rw_p0.sel_buf_0 A ) + USE SIGNAL - + ROUTED met1 ( 8809 119 ) ( * 153 ) - NEW met1 ( 8809 153 ) ( 9177 * ) - NEW li1 ( 8809 119 ) L1M1_PR_MR - NEW li1 ( 9177 153 ) L1M1_PR_MR ; + + ROUTED met1 ( 8441 119 ) ( * 153 ) + NEW met1 ( 8441 153 ) ( 8809 * ) + NEW li1 ( 8441 119 ) L1M1_PR_MR + NEW li1 ( 8809 153 ) L1M1_PR_MR ; - decoder_p0.word1 ( decoder_p0.and_layer0_word1 X ) ( sel_buf_rw_p0.sel_buf_1 A ) + USE SIGNAL - + ROUTED met1 ( 8809 425 ) ( 9177 * ) - NEW li1 ( 8809 425 ) L1M1_PR_MR - NEW li1 ( 9177 425 ) L1M1_PR_MR ; + + ROUTED met1 ( 8441 425 ) ( 8809 * ) + NEW li1 ( 8441 425 ) L1M1_PR_MR + NEW li1 ( 8809 425 ) L1M1_PR_MR ; - decoder_p0.word2 ( decoder_p0.and_layer0_word2 X ) ( sel_buf_rw_p0.sel_buf_2 A ) + USE SIGNAL - + ROUTED met1 ( 8809 663 ) ( 9039 * ) - NEW met1 ( 9039 663 ) ( * 697 ) - NEW met1 ( 9039 697 ) ( 9177 * ) - NEW li1 ( 8809 663 ) L1M1_PR_MR - NEW li1 ( 9177 697 ) L1M1_PR_MR ; + + ROUTED met1 ( 8441 663 ) ( 8579 * ) + NEW met1 ( 8579 595 ) ( * 663 ) + NEW met1 ( 8579 595 ) ( 8809 * ) + NEW li1 ( 8441 663 ) L1M1_PR_MR + NEW li1 ( 8809 595 ) L1M1_PR_MR ; - decoder_p0.word3 ( decoder_p0.and_layer0_word3 X ) ( sel_buf_rw_p0.sel_buf_3 A ) + USE SIGNAL - + ROUTED met1 ( 8809 969 ) ( * 1003 ) - NEW met1 ( 8809 1003 ) ( 9177 * ) - NEW li1 ( 8809 969 ) L1M1_PR_MR - NEW li1 ( 9177 1003 ) L1M1_PR_MR ; + + ROUTED met1 ( 8441 969 ) ( * 1003 ) + NEW met1 ( 8441 1003 ) ( 8809 * ) + NEW li1 ( 8441 969 ) L1M1_PR_MR + NEW li1 ( 8809 1003 ) L1M1_PR_MR ; - decoder_p0.word4 ( decoder_p0.and_layer0_word4 X ) ( sel_buf_rw_p0.sel_buf_4 A ) + USE SIGNAL - + ROUTED met1 ( 8809 1207 ) ( 9177 * ) - NEW li1 ( 8809 1207 ) L1M1_PR_MR - NEW li1 ( 9177 1207 ) L1M1_PR_MR ; + + ROUTED met1 ( 8441 1173 ) ( * 1207 ) + NEW met1 ( 8441 1173 ) ( 8579 * ) + NEW met1 ( 8579 1139 ) ( * 1173 ) + NEW met1 ( 8579 1139 ) ( 8809 * ) + NEW li1 ( 8441 1207 ) L1M1_PR_MR + NEW li1 ( 8809 1139 ) L1M1_PR_MR ; - decoder_p0.word5 ( decoder_p0.and_layer0_word5 X ) ( sel_buf_rw_p0.sel_buf_5 A ) + USE SIGNAL - + ROUTED met1 ( 8809 1479 ) ( * 1513 ) - NEW met1 ( 8809 1479 ) ( 9177 * ) - NEW li1 ( 8809 1513 ) L1M1_PR_MR - NEW li1 ( 9177 1479 ) L1M1_PR_MR ; + + ROUTED met1 ( 8441 1513 ) ( * 1581 ) + NEW met1 ( 8441 1581 ) ( 8809 * ) + NEW li1 ( 8441 1513 ) L1M1_PR_MR + NEW li1 ( 8809 1581 ) L1M1_PR_MR ; - decoder_p0.word6 ( decoder_p0.and_layer0_word6 X ) ( sel_buf_rw_p0.sel_buf_6 A ) + USE SIGNAL - + ROUTED met1 ( 8809 1751 ) ( 9177 * ) - NEW li1 ( 8809 1751 ) L1M1_PR_MR - NEW li1 ( 9177 1751 ) L1M1_PR_MR ; + + ROUTED met1 ( 8441 1751 ) ( 8809 * ) + NEW li1 ( 8441 1751 ) L1M1_PR_MR + NEW li1 ( 8809 1751 ) L1M1_PR_MR ; - decoder_p0.word7 ( decoder_p0.and_layer0_word7 X ) ( sel_buf_rw_p0.sel_buf_7 A ) + USE SIGNAL - + ROUTED met1 ( 8809 2023 ) ( * 2057 ) - NEW met1 ( 8809 2023 ) ( 9177 * ) - NEW li1 ( 8809 2057 ) L1M1_PR_MR - NEW li1 ( 9177 2023 ) L1M1_PR_MR ; - - global.clk_b ( neg_lat_b7.nlat GATE ) ( neg_lat_b6.nlat GATE ) ( neg_lat_b5.nlat GATE ) ( neg_lat_b4.nlat GATE ) ( neg_lat_b3.nlat GATE ) ( neg_lat_b2.nlat GATE ) ( neg_lat_b1.nlat GATE ) - ( neg_lat_b0.nlat GATE ) ( neg_row.clk_inv Y ) + USE SIGNAL - + ROUTED met1 ( 1035 2261 ) ( * 2295 ) - NEW met1 ( 69 2261 ) ( 1035 * ) - NEW met1 ( 69 2261 ) ( * 2295 ) - NEW met1 ( 6831 2329 ) ( * 2397 ) - NEW met1 ( 1035 2261 ) ( 1380 * ) - NEW met1 ( 1380 2295 ) ( 2001 * ) - NEW met1 ( 1380 2261 ) ( * 2295 ) - NEW met1 ( 2967 2261 ) ( * 2295 ) - NEW met1 ( 2001 2261 ) ( 2967 * ) - NEW met1 ( 2001 2261 ) ( * 2295 ) - NEW met1 ( 3933 2261 ) ( * 2295 ) - NEW met1 ( 2967 2261 ) ( 3933 * ) - NEW met1 ( 4899 2261 ) ( * 2295 ) - NEW met1 ( 3933 2261 ) ( 4899 * ) - NEW met1 ( 5865 2261 ) ( * 2295 ) - NEW met1 ( 4899 2261 ) ( 5865 * ) - NEW met1 ( 5865 2295 ) ( * 2397 ) - NEW met1 ( 5865 2397 ) ( 6831 * ) - NEW met1 ( 6831 2397 ) ( 7843 * ) - NEW li1 ( 1035 2295 ) L1M1_PR_MR + + ROUTED met1 ( 8441 2023 ) ( * 2057 ) + NEW met1 ( 8441 2023 ) ( 8809 * ) + NEW li1 ( 8441 2057 ) L1M1_PR_MR + NEW li1 ( 8809 2023 ) L1M1_PR_MR ; + - global.clk_b ( neg_lat_b7.nlat SLEEP_B ) ( neg_lat_b6.nlat SLEEP_B ) ( neg_lat_b5.nlat SLEEP_B ) ( neg_lat_b4.nlat SLEEP_B ) ( neg_lat_b3.nlat SLEEP_B ) ( neg_lat_b2.nlat SLEEP_B ) ( neg_lat_b1.nlat SLEEP_B ) + ( neg_lat_b0.nlat SLEEP_B ) ( neg_row.clk_inv Y ) + USE SIGNAL + + ROUTED met1 ( 69 2295 ) ( 989 * ) + NEW met1 ( 6509 2295 ) ( 7475 * ) + NEW met1 ( 4669 2295 ) ( 5589 * ) + NEW met1 ( 3749 2295 ) ( 4669 * ) + NEW met1 ( 2829 2295 ) ( 3749 * ) + NEW met1 ( 1909 2295 ) ( 2829 * ) + NEW met1 ( 989 2295 ) ( 1909 * ) + NEW met1 ( 5589 2295 ) ( 6509 * ) + NEW li1 ( 989 2295 ) L1M1_PR_MR NEW li1 ( 69 2295 ) L1M1_PR_MR - NEW li1 ( 6831 2329 ) L1M1_PR_MR - NEW li1 ( 2001 2295 ) L1M1_PR_MR - NEW li1 ( 2967 2295 ) L1M1_PR_MR - NEW li1 ( 3933 2295 ) L1M1_PR_MR - NEW li1 ( 4899 2295 ) L1M1_PR_MR - NEW li1 ( 5865 2295 ) L1M1_PR_MR - NEW li1 ( 7843 2397 ) L1M1_PR_MR ; + NEW li1 ( 6509 2295 ) L1M1_PR_MR + NEW li1 ( 7475 2295 ) L1M1_PR_MR + NEW li1 ( 5589 2295 ) L1M1_PR_MR + NEW li1 ( 4669 2295 ) L1M1_PR_MR + NEW li1 ( 3749 2295 ) L1M1_PR_MR + NEW li1 ( 2829 2295 ) L1M1_PR_MR + NEW li1 ( 1909 2295 ) L1M1_PR_MR ; - mid.b0 ( neg_lat_b0.nlat Q ) ( storage_7_0_0.bit0.bit D ) ( storage_6_0_0.bit0.bit D ) ( storage_5_0_0.bit0.bit D ) ( storage_4_0_0.bit0.bit D ) ( storage_3_0_0.bit0.bit D ) ( storage_2_0_0.bit0.bit D ) ( storage_1_0_0.bit0.bit D ) ( storage_0_0_0.bit0.bit D ) + USE SIGNAL - + ROUTED met2 ( 207 2057 ) ( * 2227 ) - NEW met1 ( 207 2227 ) ( 575 * ) - NEW met2 ( 207 1751 ) ( * 2057 ) - NEW met2 ( 207 1513 ) ( * 1751 ) - NEW met2 ( 207 1207 ) ( * 1513 ) - NEW met2 ( 207 969 ) ( * 1207 ) - NEW met2 ( 207 663 ) ( * 969 ) - NEW met2 ( 207 425 ) ( * 663 ) - NEW met2 ( 207 119 ) ( * 425 ) - NEW li1 ( 207 2057 ) L1M1_PR_MR - NEW met1 ( 207 2057 ) M1M2_PR - NEW met1 ( 207 2227 ) M1M2_PR - NEW li1 ( 575 2227 ) L1M1_PR_MR - NEW li1 ( 207 1751 ) L1M1_PR_MR - NEW met1 ( 207 1751 ) M1M2_PR - NEW li1 ( 207 1513 ) L1M1_PR_MR - NEW met1 ( 207 1513 ) M1M2_PR - NEW li1 ( 207 1207 ) L1M1_PR_MR - NEW met1 ( 207 1207 ) M1M2_PR - NEW li1 ( 207 969 ) L1M1_PR_MR - NEW met1 ( 207 969 ) M1M2_PR - NEW li1 ( 207 663 ) L1M1_PR_MR - NEW met1 ( 207 663 ) M1M2_PR - NEW li1 ( 207 425 ) L1M1_PR_MR - NEW met1 ( 207 425 ) M1M2_PR - NEW li1 ( 207 119 ) L1M1_PR_MR - NEW met1 ( 207 119 ) M1M2_PR ; + + ROUTED met1 ( 250 2091 ) ( 529 * ) + NEW met2 ( 529 2091 ) ( * 2227 ) + NEW met1 ( 250 1717 ) ( 253 * ) + NEW met2 ( 253 1717 ) ( * 2091 ) + NEW met1 ( 250 1547 ) ( 253 * ) + NEW met2 ( 253 1547 ) ( * 1717 ) + NEW met1 ( 250 1173 ) ( 253 * ) + NEW met2 ( 253 1173 ) ( * 1547 ) + NEW met1 ( 250 1003 ) ( 253 * ) + NEW met2 ( 253 1003 ) ( * 1173 ) + NEW met1 ( 250 629 ) ( 253 * ) + NEW met2 ( 253 629 ) ( * 1003 ) + NEW met1 ( 250 459 ) ( 253 * ) + NEW met2 ( 253 459 ) ( * 629 ) + NEW met1 ( 250 85 ) ( 253 * ) + NEW met2 ( 253 85 ) ( * 459 ) + NEW li1 ( 250 2091 ) L1M1_PR_MR + NEW met1 ( 529 2091 ) M1M2_PR + NEW li1 ( 529 2227 ) L1M1_PR_MR + NEW met1 ( 529 2227 ) M1M2_PR + NEW li1 ( 250 1717 ) L1M1_PR_MR + NEW met1 ( 253 1717 ) M1M2_PR + NEW met1 ( 253 2091 ) M1M2_PR + NEW li1 ( 250 1547 ) L1M1_PR_MR + NEW met1 ( 253 1547 ) M1M2_PR + NEW li1 ( 250 1173 ) L1M1_PR_MR + NEW met1 ( 253 1173 ) M1M2_PR + NEW li1 ( 250 1003 ) L1M1_PR_MR + NEW met1 ( 253 1003 ) M1M2_PR + NEW li1 ( 250 629 ) L1M1_PR_MR + NEW met1 ( 253 629 ) M1M2_PR + NEW li1 ( 250 459 ) L1M1_PR_MR + NEW met1 ( 253 459 ) M1M2_PR + NEW li1 ( 250 85 ) L1M1_PR_MR + NEW met1 ( 253 85 ) M1M2_PR + NEW met1 ( 250 1717 ) RECT ( -32 -7 0 7 ) + NEW met1 ( 250 1547 ) RECT ( -32 -7 0 7 ) + NEW met1 ( 250 1173 ) RECT ( -32 -7 0 7 ) + NEW met1 ( 250 1003 ) RECT ( -32 -7 0 7 ) + NEW met1 ( 250 629 ) RECT ( -32 -7 0 7 ) + NEW met1 ( 250 459 ) RECT ( -32 -7 0 7 ) + NEW met1 ( 250 85 ) RECT ( -32 -7 0 7 ) ; - mid.b1 ( neg_lat_b1.nlat Q ) ( storage_7_0_0.bit1.bit D ) ( storage_6_0_0.bit1.bit D ) ( storage_5_0_0.bit1.bit D ) ( storage_4_0_0.bit1.bit D ) ( storage_3_0_0.bit1.bit D ) ( storage_2_0_0.bit1.bit D ) ( storage_1_0_0.bit1.bit D ) ( storage_0_0_0.bit1.bit D ) + USE SIGNAL - + ROUTED met2 ( 1173 2057 ) ( * 2227 ) - NEW met2 ( 1173 1751 ) ( * 2057 ) - NEW met2 ( 1173 1513 ) ( * 1751 ) - NEW met2 ( 1173 1207 ) ( * 1513 ) - NEW met2 ( 1173 969 ) ( * 1207 ) - NEW met2 ( 1173 663 ) ( * 969 ) - NEW met2 ( 1173 425 ) ( * 663 ) - NEW met2 ( 1173 119 ) ( * 425 ) - NEW met1 ( 1173 2227 ) ( 1541 * ) - NEW li1 ( 1173 2057 ) L1M1_PR_MR - NEW met1 ( 1173 2057 ) M1M2_PR - NEW met1 ( 1173 2227 ) M1M2_PR - NEW li1 ( 1173 1751 ) L1M1_PR_MR - NEW met1 ( 1173 1751 ) M1M2_PR - NEW li1 ( 1173 1513 ) L1M1_PR_MR - NEW met1 ( 1173 1513 ) M1M2_PR - NEW li1 ( 1173 1207 ) L1M1_PR_MR - NEW met1 ( 1173 1207 ) M1M2_PR - NEW li1 ( 1173 969 ) L1M1_PR_MR - NEW met1 ( 1173 969 ) M1M2_PR - NEW li1 ( 1173 663 ) L1M1_PR_MR - NEW met1 ( 1173 663 ) M1M2_PR - NEW li1 ( 1173 425 ) L1M1_PR_MR - NEW met1 ( 1173 425 ) M1M2_PR - NEW li1 ( 1173 119 ) L1M1_PR_MR - NEW met1 ( 1173 119 ) M1M2_PR - NEW li1 ( 1541 2227 ) L1M1_PR_MR ; + + ROUTED met1 ( 1170 2091 ) ( 1219 * ) + NEW met2 ( 1219 2091 ) ( * 2227 ) + NEW met1 ( 1170 1717 ) ( 1219 * ) + NEW met2 ( 1219 1717 ) ( * 2091 ) + NEW met1 ( 1170 1547 ) ( 1219 * ) + NEW met2 ( 1219 1547 ) ( * 1717 ) + NEW met1 ( 1170 1173 ) ( 1219 * ) + NEW met2 ( 1219 1173 ) ( * 1547 ) + NEW met1 ( 1170 1003 ) ( 1219 * ) + NEW met2 ( 1219 1003 ) ( * 1173 ) + NEW met1 ( 1170 629 ) ( 1219 * ) + NEW met2 ( 1219 629 ) ( * 1003 ) + NEW met1 ( 1170 459 ) ( 1219 * ) + NEW met2 ( 1219 459 ) ( * 629 ) + NEW met1 ( 1170 85 ) ( 1219 * ) + NEW met2 ( 1219 85 ) ( * 459 ) + NEW met1 ( 1219 2227 ) ( 1449 * ) + NEW li1 ( 1170 2091 ) L1M1_PR_MR + NEW met1 ( 1219 2091 ) M1M2_PR + NEW met1 ( 1219 2227 ) M1M2_PR + NEW li1 ( 1170 1717 ) L1M1_PR_MR + NEW met1 ( 1219 1717 ) M1M2_PR + NEW li1 ( 1170 1547 ) L1M1_PR_MR + NEW met1 ( 1219 1547 ) M1M2_PR + NEW li1 ( 1170 1173 ) L1M1_PR_MR + NEW met1 ( 1219 1173 ) M1M2_PR + NEW li1 ( 1170 1003 ) L1M1_PR_MR + NEW met1 ( 1219 1003 ) M1M2_PR + NEW li1 ( 1170 629 ) L1M1_PR_MR + NEW met1 ( 1219 629 ) M1M2_PR + NEW li1 ( 1170 459 ) L1M1_PR_MR + NEW met1 ( 1219 459 ) M1M2_PR + NEW li1 ( 1170 85 ) L1M1_PR_MR + NEW met1 ( 1219 85 ) M1M2_PR + NEW li1 ( 1449 2227 ) L1M1_PR_MR ; - mid.b2 ( neg_lat_b2.nlat Q ) ( storage_7_0_0.bit2.bit D ) ( storage_6_0_0.bit2.bit D ) ( storage_5_0_0.bit2.bit D ) ( storage_4_0_0.bit2.bit D ) ( storage_3_0_0.bit2.bit D ) ( storage_2_0_0.bit2.bit D ) ( storage_1_0_0.bit2.bit D ) ( storage_0_0_0.bit2.bit D ) + USE SIGNAL - + ROUTED met2 ( 2139 969 ) ( * 1207 ) - NEW met2 ( 2139 663 ) ( * 969 ) - NEW met2 ( 2139 425 ) ( * 663 ) - NEW met2 ( 2139 119 ) ( * 425 ) - NEW met2 ( 2139 2057 ) ( * 2227 ) - NEW met1 ( 2139 2227 ) ( 2507 * ) - NEW met2 ( 2139 1751 ) ( * 2057 ) - NEW met2 ( 2139 1513 ) ( * 1751 ) - NEW met2 ( 2139 1207 ) ( * 1513 ) - NEW li1 ( 2139 1207 ) L1M1_PR_MR - NEW met1 ( 2139 1207 ) M1M2_PR - NEW li1 ( 2139 969 ) L1M1_PR_MR - NEW met1 ( 2139 969 ) M1M2_PR - NEW li1 ( 2139 663 ) L1M1_PR_MR - NEW met1 ( 2139 663 ) M1M2_PR - NEW li1 ( 2139 425 ) L1M1_PR_MR - NEW met1 ( 2139 425 ) M1M2_PR - NEW li1 ( 2139 119 ) L1M1_PR_MR - NEW met1 ( 2139 119 ) M1M2_PR - NEW li1 ( 2139 2057 ) L1M1_PR_MR - NEW met1 ( 2139 2057 ) M1M2_PR - NEW met1 ( 2139 2227 ) M1M2_PR - NEW li1 ( 2507 2227 ) L1M1_PR_MR - NEW li1 ( 2139 1751 ) L1M1_PR_MR - NEW met1 ( 2139 1751 ) M1M2_PR - NEW li1 ( 2139 1513 ) L1M1_PR_MR - NEW met1 ( 2139 1513 ) M1M2_PR ; + + ROUTED met1 ( 2090 1173 ) ( 2093 * ) + NEW met1 ( 2090 1003 ) ( 2093 * ) + NEW met2 ( 2093 1003 ) ( * 1173 ) + NEW met1 ( 2090 629 ) ( 2093 * ) + NEW met2 ( 2093 629 ) ( * 1003 ) + NEW met1 ( 2090 459 ) ( 2093 * ) + NEW met2 ( 2093 459 ) ( * 629 ) + NEW met1 ( 2090 85 ) ( 2093 * ) + NEW met2 ( 2093 85 ) ( * 459 ) + NEW met1 ( 2090 2091 ) ( 2369 * ) + NEW met2 ( 2369 2091 ) ( * 2227 ) + NEW met1 ( 2090 1717 ) ( 2093 * ) + NEW met2 ( 2093 1717 ) ( * 2091 ) + NEW met1 ( 2090 1547 ) ( 2093 * ) + NEW met2 ( 2093 1547 ) ( * 1717 ) + NEW met2 ( 2093 1173 ) ( * 1547 ) + NEW li1 ( 2090 1173 ) L1M1_PR_MR + NEW met1 ( 2093 1173 ) M1M2_PR + NEW li1 ( 2090 1003 ) L1M1_PR_MR + NEW met1 ( 2093 1003 ) M1M2_PR + NEW li1 ( 2090 629 ) L1M1_PR_MR + NEW met1 ( 2093 629 ) M1M2_PR + NEW li1 ( 2090 459 ) L1M1_PR_MR + NEW met1 ( 2093 459 ) M1M2_PR + NEW li1 ( 2090 85 ) L1M1_PR_MR + NEW met1 ( 2093 85 ) M1M2_PR + NEW li1 ( 2090 2091 ) L1M1_PR_MR + NEW met1 ( 2369 2091 ) M1M2_PR + NEW li1 ( 2369 2227 ) L1M1_PR_MR + NEW met1 ( 2369 2227 ) M1M2_PR + NEW li1 ( 2090 1717 ) L1M1_PR_MR + NEW met1 ( 2093 1717 ) M1M2_PR + NEW met1 ( 2093 2091 ) M1M2_PR + NEW li1 ( 2090 1547 ) L1M1_PR_MR + NEW met1 ( 2093 1547 ) M1M2_PR + NEW met1 ( 2090 1173 ) RECT ( -32 -7 0 7 ) + NEW met1 ( 2090 1003 ) RECT ( -32 -7 0 7 ) + NEW met1 ( 2090 629 ) RECT ( -32 -7 0 7 ) + NEW met1 ( 2090 459 ) RECT ( -32 -7 0 7 ) + NEW met1 ( 2090 85 ) RECT ( -32 -7 0 7 ) + NEW met1 ( 2090 1717 ) RECT ( -32 -7 0 7 ) + NEW met1 ( 2090 1547 ) RECT ( -32 -7 0 7 ) ; - mid.b3 ( neg_lat_b3.nlat Q ) ( storage_7_0_0.bit3.bit D ) ( storage_6_0_0.bit3.bit D ) ( storage_5_0_0.bit3.bit D ) ( storage_4_0_0.bit3.bit D ) ( storage_3_0_0.bit3.bit D ) ( storage_2_0_0.bit3.bit D ) ( storage_1_0_0.bit3.bit D ) ( storage_0_0_0.bit3.bit D ) + USE SIGNAL - + ROUTED met2 ( 3105 969 ) ( * 1207 ) - NEW met2 ( 3105 663 ) ( * 969 ) - NEW met2 ( 3105 425 ) ( * 663 ) - NEW met2 ( 3105 119 ) ( * 425 ) - NEW met2 ( 3105 2057 ) ( * 2227 ) - NEW met1 ( 3105 2227 ) ( 3473 * ) - NEW met2 ( 3105 1751 ) ( * 2057 ) - NEW met2 ( 3105 1513 ) ( * 1751 ) - NEW met2 ( 3105 1207 ) ( * 1513 ) - NEW li1 ( 3105 1207 ) L1M1_PR_MR - NEW met1 ( 3105 1207 ) M1M2_PR - NEW li1 ( 3105 969 ) L1M1_PR_MR - NEW met1 ( 3105 969 ) M1M2_PR - NEW li1 ( 3105 663 ) L1M1_PR_MR - NEW met1 ( 3105 663 ) M1M2_PR - NEW li1 ( 3105 425 ) L1M1_PR_MR - NEW met1 ( 3105 425 ) M1M2_PR - NEW li1 ( 3105 119 ) L1M1_PR_MR - NEW met1 ( 3105 119 ) M1M2_PR - NEW li1 ( 3105 2057 ) L1M1_PR_MR - NEW met1 ( 3105 2057 ) M1M2_PR - NEW met1 ( 3105 2227 ) M1M2_PR - NEW li1 ( 3473 2227 ) L1M1_PR_MR - NEW li1 ( 3105 1751 ) L1M1_PR_MR - NEW met1 ( 3105 1751 ) M1M2_PR - NEW li1 ( 3105 1513 ) L1M1_PR_MR - NEW met1 ( 3105 1513 ) M1M2_PR ; + + ROUTED met1 ( 3010 1173 ) ( 3013 * ) + NEW met1 ( 3010 1003 ) ( 3013 * ) + NEW met2 ( 3013 1003 ) ( * 1173 ) + NEW met1 ( 3010 629 ) ( 3013 * ) + NEW met2 ( 3013 629 ) ( * 1003 ) + NEW met1 ( 3010 459 ) ( 3013 * ) + NEW met2 ( 3013 459 ) ( * 629 ) + NEW met1 ( 3010 85 ) ( 3013 * ) + NEW met2 ( 3013 85 ) ( * 459 ) + NEW met1 ( 3010 2091 ) ( 3289 * ) + NEW met2 ( 3289 2091 ) ( * 2227 ) + NEW met1 ( 3010 1717 ) ( 3013 * ) + NEW met2 ( 3013 1717 ) ( * 2091 ) + NEW met1 ( 3010 1547 ) ( 3013 * ) + NEW met2 ( 3013 1547 ) ( * 1717 ) + NEW met2 ( 3013 1173 ) ( * 1547 ) + NEW li1 ( 3010 1173 ) L1M1_PR_MR + NEW met1 ( 3013 1173 ) M1M2_PR + NEW li1 ( 3010 1003 ) L1M1_PR_MR + NEW met1 ( 3013 1003 ) M1M2_PR + NEW li1 ( 3010 629 ) L1M1_PR_MR + NEW met1 ( 3013 629 ) M1M2_PR + NEW li1 ( 3010 459 ) L1M1_PR_MR + NEW met1 ( 3013 459 ) M1M2_PR + NEW li1 ( 3010 85 ) L1M1_PR_MR + NEW met1 ( 3013 85 ) M1M2_PR + NEW li1 ( 3010 2091 ) L1M1_PR_MR + NEW met1 ( 3289 2091 ) M1M2_PR + NEW li1 ( 3289 2227 ) L1M1_PR_MR + NEW met1 ( 3289 2227 ) M1M2_PR + NEW li1 ( 3010 1717 ) L1M1_PR_MR + NEW met1 ( 3013 1717 ) M1M2_PR + NEW met1 ( 3013 2091 ) M1M2_PR + NEW li1 ( 3010 1547 ) L1M1_PR_MR + NEW met1 ( 3013 1547 ) M1M2_PR + NEW met1 ( 3010 1173 ) RECT ( -32 -7 0 7 ) + NEW met1 ( 3010 1003 ) RECT ( -32 -7 0 7 ) + NEW met1 ( 3010 629 ) RECT ( -32 -7 0 7 ) + NEW met1 ( 3010 459 ) RECT ( -32 -7 0 7 ) + NEW met1 ( 3010 85 ) RECT ( -32 -7 0 7 ) + NEW met1 ( 3010 1717 ) RECT ( -32 -7 0 7 ) + NEW met1 ( 3010 1547 ) RECT ( -32 -7 0 7 ) ; - mid.b4 ( neg_lat_b4.nlat Q ) ( storage_7_0_0.bit4.bit D ) ( storage_6_0_0.bit4.bit D ) ( storage_5_0_0.bit4.bit D ) ( storage_4_0_0.bit4.bit D ) ( storage_3_0_0.bit4.bit D ) ( storage_2_0_0.bit4.bit D ) ( storage_1_0_0.bit4.bit D ) ( storage_0_0_0.bit4.bit D ) + USE SIGNAL - + ROUTED met2 ( 4071 969 ) ( * 1207 ) - NEW met2 ( 4071 663 ) ( * 969 ) - NEW met2 ( 4071 425 ) ( * 663 ) - NEW met2 ( 4071 119 ) ( * 425 ) - NEW met2 ( 4071 2057 ) ( * 2227 ) - NEW met1 ( 4071 2227 ) ( 4439 * ) - NEW met2 ( 4071 1751 ) ( * 2057 ) - NEW met2 ( 4071 1513 ) ( * 1751 ) - NEW met2 ( 4071 1207 ) ( * 1513 ) - NEW li1 ( 4071 1207 ) L1M1_PR_MR - NEW met1 ( 4071 1207 ) M1M2_PR - NEW li1 ( 4071 969 ) L1M1_PR_MR - NEW met1 ( 4071 969 ) M1M2_PR - NEW li1 ( 4071 663 ) L1M1_PR_MR - NEW met1 ( 4071 663 ) M1M2_PR - NEW li1 ( 4071 425 ) L1M1_PR_MR - NEW met1 ( 4071 425 ) M1M2_PR - NEW li1 ( 4071 119 ) L1M1_PR_MR - NEW met1 ( 4071 119 ) M1M2_PR - NEW li1 ( 4071 2057 ) L1M1_PR_MR - NEW met1 ( 4071 2057 ) M1M2_PR + + ROUTED met1 ( 3930 1173 ) ( 4071 * ) + NEW met1 ( 3930 1003 ) ( 4071 * ) + NEW met2 ( 4071 1003 ) ( * 1173 ) + NEW met1 ( 3930 629 ) ( 4071 * ) + NEW met2 ( 4071 629 ) ( * 1003 ) + NEW met1 ( 3930 459 ) ( 4071 * ) + NEW met2 ( 4071 459 ) ( * 629 ) + NEW met1 ( 3930 85 ) ( 4071 * ) + NEW met2 ( 4071 85 ) ( * 459 ) + NEW met1 ( 3930 2091 ) ( 4071 * ) + NEW met2 ( 4071 2091 ) ( * 2227 ) + NEW met1 ( 4071 2227 ) ( 4209 * ) + NEW met1 ( 3930 1717 ) ( 4071 * ) + NEW met2 ( 4071 1717 ) ( * 2091 ) + NEW met1 ( 3930 1547 ) ( 4071 * ) + NEW met2 ( 4071 1547 ) ( * 1717 ) + NEW met2 ( 4071 1173 ) ( * 1547 ) + NEW li1 ( 3930 1173 ) L1M1_PR_MR + NEW met1 ( 4071 1173 ) M1M2_PR + NEW li1 ( 3930 1003 ) L1M1_PR_MR + NEW met1 ( 4071 1003 ) M1M2_PR + NEW li1 ( 3930 629 ) L1M1_PR_MR + NEW met1 ( 4071 629 ) M1M2_PR + NEW li1 ( 3930 459 ) L1M1_PR_MR + NEW met1 ( 4071 459 ) M1M2_PR + NEW li1 ( 3930 85 ) L1M1_PR_MR + NEW met1 ( 4071 85 ) M1M2_PR + NEW li1 ( 3930 2091 ) L1M1_PR_MR + NEW met1 ( 4071 2091 ) M1M2_PR NEW met1 ( 4071 2227 ) M1M2_PR - NEW li1 ( 4439 2227 ) L1M1_PR_MR - NEW li1 ( 4071 1751 ) L1M1_PR_MR - NEW met1 ( 4071 1751 ) M1M2_PR - NEW li1 ( 4071 1513 ) L1M1_PR_MR - NEW met1 ( 4071 1513 ) M1M2_PR ; + NEW li1 ( 4209 2227 ) L1M1_PR_MR + NEW li1 ( 3930 1717 ) L1M1_PR_MR + NEW met1 ( 4071 1717 ) M1M2_PR + NEW li1 ( 3930 1547 ) L1M1_PR_MR + NEW met1 ( 4071 1547 ) M1M2_PR ; - mid.b5 ( neg_lat_b5.nlat Q ) ( storage_7_0_0.bit5.bit D ) ( storage_6_0_0.bit5.bit D ) ( storage_5_0_0.bit5.bit D ) ( storage_4_0_0.bit5.bit D ) ( storage_3_0_0.bit5.bit D ) ( storage_2_0_0.bit5.bit D ) ( storage_1_0_0.bit5.bit D ) ( storage_0_0_0.bit5.bit D ) + USE SIGNAL - + ROUTED met2 ( 5037 969 ) ( * 1207 ) - NEW met2 ( 5037 663 ) ( * 969 ) - NEW met2 ( 5037 425 ) ( * 663 ) - NEW met2 ( 5037 119 ) ( * 425 ) - NEW met2 ( 5037 2057 ) ( * 2227 ) - NEW met1 ( 5037 2227 ) ( 5405 * ) - NEW met2 ( 5037 1751 ) ( * 2057 ) - NEW met2 ( 5037 1513 ) ( * 1751 ) - NEW met2 ( 5037 1207 ) ( * 1513 ) - NEW li1 ( 5037 1207 ) L1M1_PR_MR - NEW met1 ( 5037 1207 ) M1M2_PR - NEW li1 ( 5037 969 ) L1M1_PR_MR - NEW met1 ( 5037 969 ) M1M2_PR - NEW li1 ( 5037 663 ) L1M1_PR_MR - NEW met1 ( 5037 663 ) M1M2_PR - NEW li1 ( 5037 425 ) L1M1_PR_MR - NEW met1 ( 5037 425 ) M1M2_PR - NEW li1 ( 5037 119 ) L1M1_PR_MR - NEW met1 ( 5037 119 ) M1M2_PR - NEW li1 ( 5037 2057 ) L1M1_PR_MR - NEW met1 ( 5037 2057 ) M1M2_PR - NEW met1 ( 5037 2227 ) M1M2_PR - NEW li1 ( 5405 2227 ) L1M1_PR_MR - NEW li1 ( 5037 1751 ) L1M1_PR_MR - NEW met1 ( 5037 1751 ) M1M2_PR - NEW li1 ( 5037 1513 ) L1M1_PR_MR - NEW met1 ( 5037 1513 ) M1M2_PR ; + + ROUTED met1 ( 4850 1173 ) ( 4853 * ) + NEW met1 ( 4850 1003 ) ( 4853 * ) + NEW met2 ( 4853 1003 ) ( * 1173 ) + NEW met1 ( 4850 629 ) ( 4853 * ) + NEW met2 ( 4853 629 ) ( * 1003 ) + NEW met1 ( 4850 459 ) ( 4853 * ) + NEW met2 ( 4853 459 ) ( * 629 ) + NEW met1 ( 4850 85 ) ( 4853 * ) + NEW met2 ( 4853 85 ) ( * 459 ) + NEW met1 ( 4850 2091 ) ( 5129 * ) + NEW met2 ( 5129 2091 ) ( * 2227 ) + NEW met1 ( 4850 1717 ) ( 4853 * ) + NEW met2 ( 4853 1717 ) ( * 2091 ) + NEW met1 ( 4850 1547 ) ( 4853 * ) + NEW met2 ( 4853 1547 ) ( * 1717 ) + NEW met2 ( 4853 1173 ) ( * 1547 ) + NEW li1 ( 4850 1173 ) L1M1_PR_MR + NEW met1 ( 4853 1173 ) M1M2_PR + NEW li1 ( 4850 1003 ) L1M1_PR_MR + NEW met1 ( 4853 1003 ) M1M2_PR + NEW li1 ( 4850 629 ) L1M1_PR_MR + NEW met1 ( 4853 629 ) M1M2_PR + NEW li1 ( 4850 459 ) L1M1_PR_MR + NEW met1 ( 4853 459 ) M1M2_PR + NEW li1 ( 4850 85 ) L1M1_PR_MR + NEW met1 ( 4853 85 ) M1M2_PR + NEW li1 ( 4850 2091 ) L1M1_PR_MR + NEW met1 ( 5129 2091 ) M1M2_PR + NEW li1 ( 5129 2227 ) L1M1_PR_MR + NEW met1 ( 5129 2227 ) M1M2_PR + NEW li1 ( 4850 1717 ) L1M1_PR_MR + NEW met1 ( 4853 1717 ) M1M2_PR + NEW met1 ( 4853 2091 ) M1M2_PR + NEW li1 ( 4850 1547 ) L1M1_PR_MR + NEW met1 ( 4853 1547 ) M1M2_PR + NEW met1 ( 4850 1173 ) RECT ( -32 -7 0 7 ) + NEW met1 ( 4850 1003 ) RECT ( -32 -7 0 7 ) + NEW met1 ( 4850 629 ) RECT ( -32 -7 0 7 ) + NEW met1 ( 4850 459 ) RECT ( -32 -7 0 7 ) + NEW met1 ( 4850 85 ) RECT ( -32 -7 0 7 ) + NEW met1 ( 4850 1717 ) RECT ( -32 -7 0 7 ) + NEW met1 ( 4850 1547 ) RECT ( -32 -7 0 7 ) ; - mid.b6 ( neg_lat_b6.nlat Q ) ( storage_7_0_0.bit6.bit D ) ( storage_6_0_0.bit6.bit D ) ( storage_5_0_0.bit6.bit D ) ( storage_4_0_0.bit6.bit D ) ( storage_3_0_0.bit6.bit D ) ( storage_2_0_0.bit6.bit D ) ( storage_1_0_0.bit6.bit D ) ( storage_0_0_0.bit6.bit D ) + USE SIGNAL - + ROUTED met1 ( 6003 1207 ) ( 6141 * ) - NEW met1 ( 6003 969 ) ( 6141 * ) - NEW met2 ( 6141 969 ) ( * 1207 ) - NEW met1 ( 6003 663 ) ( 6141 * ) - NEW met2 ( 6141 663 ) ( * 969 ) - NEW met1 ( 6003 425 ) ( 6141 * ) - NEW met2 ( 6141 425 ) ( * 663 ) - NEW met1 ( 6003 119 ) ( 6141 * ) - NEW met2 ( 6141 119 ) ( * 425 ) - NEW met1 ( 6003 1513 ) ( 6141 * ) - NEW met1 ( 6003 1751 ) ( 6141 * ) - NEW met2 ( 6141 1513 ) ( * 1751 ) - NEW met1 ( 6003 2057 ) ( 6141 * ) - NEW met2 ( 6141 1751 ) ( * 2057 ) - NEW met2 ( 6141 2057 ) ( * 2227 ) - NEW met2 ( 6141 1207 ) ( * 1513 ) - NEW met1 ( 6141 2227 ) ( 6371 * ) - NEW li1 ( 6371 2227 ) L1M1_PR_MR - NEW li1 ( 6003 1207 ) L1M1_PR_MR - NEW met1 ( 6141 1207 ) M1M2_PR - NEW li1 ( 6003 969 ) L1M1_PR_MR - NEW met1 ( 6141 969 ) M1M2_PR - NEW li1 ( 6003 663 ) L1M1_PR_MR - NEW met1 ( 6141 663 ) M1M2_PR - NEW li1 ( 6003 425 ) L1M1_PR_MR - NEW met1 ( 6141 425 ) M1M2_PR - NEW li1 ( 6003 119 ) L1M1_PR_MR - NEW met1 ( 6141 119 ) M1M2_PR - NEW li1 ( 6003 1513 ) L1M1_PR_MR - NEW met1 ( 6141 1513 ) M1M2_PR - NEW li1 ( 6003 1751 ) L1M1_PR_MR - NEW met1 ( 6141 1751 ) M1M2_PR - NEW li1 ( 6003 2057 ) L1M1_PR_MR - NEW met1 ( 6141 2057 ) M1M2_PR - NEW met1 ( 6141 2227 ) M1M2_PR ; + + ROUTED met1 ( 5770 1173 ) ( 5819 * ) + NEW met1 ( 5770 1003 ) ( 5819 * ) + NEW met2 ( 5819 1003 ) ( * 1173 ) + NEW met1 ( 5770 629 ) ( 5819 * ) + NEW met2 ( 5819 629 ) ( * 1003 ) + NEW met1 ( 5770 459 ) ( 5819 * ) + NEW met2 ( 5819 459 ) ( * 629 ) + NEW met1 ( 5770 85 ) ( 5819 * ) + NEW met2 ( 5819 85 ) ( * 459 ) + NEW met1 ( 5770 2091 ) ( 5819 * ) + NEW met2 ( 5819 2091 ) ( * 2227 ) + NEW met1 ( 5819 2227 ) ( 6049 * ) + NEW met1 ( 5770 1717 ) ( 5819 * ) + NEW met2 ( 5819 1717 ) ( * 2091 ) + NEW met1 ( 5770 1547 ) ( 5819 * ) + NEW met2 ( 5819 1547 ) ( * 1717 ) + NEW met2 ( 5819 1173 ) ( * 1547 ) + NEW li1 ( 5770 1173 ) L1M1_PR_MR + NEW met1 ( 5819 1173 ) M1M2_PR + NEW li1 ( 5770 1003 ) L1M1_PR_MR + NEW met1 ( 5819 1003 ) M1M2_PR + NEW li1 ( 5770 629 ) L1M1_PR_MR + NEW met1 ( 5819 629 ) M1M2_PR + NEW li1 ( 5770 459 ) L1M1_PR_MR + NEW met1 ( 5819 459 ) M1M2_PR + NEW li1 ( 5770 85 ) L1M1_PR_MR + NEW met1 ( 5819 85 ) M1M2_PR + NEW li1 ( 5770 2091 ) L1M1_PR_MR + NEW met1 ( 5819 2091 ) M1M2_PR + NEW met1 ( 5819 2227 ) M1M2_PR + NEW li1 ( 6049 2227 ) L1M1_PR_MR + NEW li1 ( 5770 1717 ) L1M1_PR_MR + NEW met1 ( 5819 1717 ) M1M2_PR + NEW li1 ( 5770 1547 ) L1M1_PR_MR + NEW met1 ( 5819 1547 ) M1M2_PR ; - mid.b7 ( neg_lat_b7.nlat Q ) ( storage_7_0_0.bit7.bit D ) ( storage_6_0_0.bit7.bit D ) ( storage_5_0_0.bit7.bit D ) ( storage_4_0_0.bit7.bit D ) ( storage_3_0_0.bit7.bit D ) ( storage_2_0_0.bit7.bit D ) ( storage_1_0_0.bit7.bit D ) ( storage_0_0_0.bit7.bit D ) + USE SIGNAL - + ROUTED met2 ( 6969 969 ) ( * 1207 ) - NEW met2 ( 6969 425 ) ( * 969 ) - NEW met2 ( 6969 119 ) ( * 425 ) - NEW met2 ( 6969 2057 ) ( * 2227 ) - NEW met1 ( 6969 2227 ) ( 7337 * ) - NEW met2 ( 6969 1751 ) ( * 2057 ) - NEW met2 ( 6969 1513 ) ( * 1751 ) - NEW met2 ( 6969 1207 ) ( * 1513 ) - NEW li1 ( 6969 1207 ) L1M1_PR_MR - NEW met1 ( 6969 1207 ) M1M2_PR - NEW li1 ( 6969 969 ) L1M1_PR_MR - NEW met1 ( 6969 969 ) M1M2_PR - NEW li1 ( 6969 425 ) L1M1_PR_MR - NEW met1 ( 6969 425 ) M1M2_PR - NEW li1 ( 6969 119 ) L1M1_PR_MR - NEW met1 ( 6969 119 ) M1M2_PR - NEW li1 ( 6969 658 ) L1M1_PR_MR - NEW met1 ( 6969 658 ) M1M2_PR - NEW li1 ( 6969 2057 ) L1M1_PR_MR - NEW met1 ( 6969 2057 ) M1M2_PR - NEW met1 ( 6969 2227 ) M1M2_PR - NEW li1 ( 7337 2227 ) L1M1_PR_MR - NEW li1 ( 6969 1751 ) L1M1_PR_MR - NEW met1 ( 6969 1751 ) M1M2_PR - NEW li1 ( 6969 1513 ) L1M1_PR_MR - NEW met1 ( 6969 1513 ) M1M2_PR ; + + ROUTED met1 ( 6690 1173 ) ( 6739 * ) + NEW met1 ( 6690 1003 ) ( 6739 * ) + NEW met2 ( 6739 1003 ) ( * 1173 ) + NEW met1 ( 6690 629 ) ( 6739 * ) + NEW met2 ( 6739 629 ) ( * 1003 ) + NEW met1 ( 6690 459 ) ( 6739 * ) + NEW met2 ( 6739 459 ) ( * 629 ) + NEW met1 ( 6690 85 ) ( 6739 * ) + NEW met2 ( 6739 85 ) ( * 459 ) + NEW met1 ( 6690 2091 ) ( 6739 * ) + NEW met2 ( 6739 2091 ) ( * 2227 ) + NEW met1 ( 6739 2227 ) ( 6969 * ) + NEW met1 ( 6690 1717 ) ( 6739 * ) + NEW met2 ( 6739 1717 ) ( * 2091 ) + NEW met1 ( 6690 1547 ) ( 6739 * ) + NEW met2 ( 6739 1547 ) ( * 1717 ) + NEW met2 ( 6739 1173 ) ( * 1547 ) + NEW li1 ( 6690 1173 ) L1M1_PR_MR + NEW met1 ( 6739 1173 ) M1M2_PR + NEW li1 ( 6690 1003 ) L1M1_PR_MR + NEW met1 ( 6739 1003 ) M1M2_PR + NEW li1 ( 6690 629 ) L1M1_PR_MR + NEW met1 ( 6739 629 ) M1M2_PR + NEW li1 ( 6690 459 ) L1M1_PR_MR + NEW met1 ( 6739 459 ) M1M2_PR + NEW li1 ( 6690 85 ) L1M1_PR_MR + NEW met1 ( 6739 85 ) M1M2_PR + NEW li1 ( 6690 2091 ) L1M1_PR_MR + NEW met1 ( 6739 2091 ) M1M2_PR + NEW met1 ( 6739 2227 ) M1M2_PR + NEW li1 ( 6969 2227 ) L1M1_PR_MR + NEW li1 ( 6690 1717 ) L1M1_PR_MR + NEW met1 ( 6739 1717 ) M1M2_PR + NEW li1 ( 6690 1547 ) L1M1_PR_MR + NEW met1 ( 6739 1547 ) M1M2_PR ; - rw_sel_p0.select_wr0 ( sel_buf_rw_p0.sel_buf_0 X ) ( storage_0_0_0.select_inv_0 A ) ( storage_0_0_0.gcand A ) + USE SIGNAL - + ROUTED met1 ( 8671 85 ) ( 8901 * ) - NEW met1 ( 8901 51 ) ( * 85 ) - NEW met1 ( 8441 153 ) ( 8671 * ) - NEW met1 ( 8671 85 ) ( * 153 ) - NEW li1 ( 8671 85 ) L1M1_PR_MR - NEW li1 ( 8901 51 ) L1M1_PR_MR - NEW li1 ( 8441 153 ) L1M1_PR_MR ; + + ROUTED met1 ( 8303 119 ) ( * 153 ) + NEW met1 ( 8280 187 ) ( 8533 * ) + NEW met1 ( 8280 153 ) ( 8303 * ) + NEW met1 ( 8073 153 ) ( 8280 * ) + NEW met1 ( 8280 153 ) ( * 187 ) + NEW li1 ( 8533 187 ) L1M1_PR_MR + NEW li1 ( 8303 119 ) L1M1_PR_MR + NEW li1 ( 8073 153 ) L1M1_PR_MR ; - rw_sel_p0.select_wr1 ( sel_buf_rw_p0.sel_buf_1 X ) ( storage_1_0_0.select_inv_0 A ) ( storage_1_0_0.gcand A ) + USE SIGNAL - + ROUTED met1 ( 8671 493 ) ( 8901 * ) - NEW met1 ( 8441 391 ) ( * 425 ) - NEW met1 ( 8441 425 ) ( 8671 * ) - NEW li1 ( 8671 493 ) L1M1_PR_MR - NEW li1 ( 8901 493 ) L1M1_PR_MR - NEW li1 ( 8441 391 ) L1M1_PR_MR - NEW li1 ( 8671 425 ) L1M1_PR_MR ; + + ROUTED met1 ( 8303 493 ) ( 8533 * ) + NEW met1 ( 8073 391 ) ( * 425 ) + NEW met1 ( 8073 425 ) ( 8303 * ) + NEW li1 ( 8303 493 ) L1M1_PR_MR + NEW li1 ( 8533 493 ) L1M1_PR_MR + NEW li1 ( 8303 425 ) L1M1_PR_MR + NEW li1 ( 8073 391 ) L1M1_PR_MR ; - rw_sel_p0.select_wr2 ( sel_buf_rw_p0.sel_buf_2 X ) ( storage_2_0_0.select_inv_0 A ) ( storage_2_0_0.gcand A ) + USE SIGNAL - + ROUTED met1 ( 8671 629 ) ( 8901 * ) - NEW met1 ( 8901 595 ) ( * 629 ) - NEW met1 ( 8441 697 ) ( 8671 * ) - NEW met1 ( 8671 629 ) ( * 697 ) - NEW li1 ( 8671 629 ) L1M1_PR_MR - NEW li1 ( 8901 595 ) L1M1_PR_MR - NEW li1 ( 8441 697 ) L1M1_PR_MR ; + + ROUTED met1 ( 8303 663 ) ( * 697 ) + NEW met1 ( 8280 697 ) ( 8303 * ) + NEW met1 ( 8280 731 ) ( 8533 * ) + NEW met1 ( 8073 697 ) ( 8280 * ) + NEW met1 ( 8280 697 ) ( * 731 ) + NEW li1 ( 8533 731 ) L1M1_PR_MR + NEW li1 ( 8303 663 ) L1M1_PR_MR + NEW li1 ( 8073 697 ) L1M1_PR_MR ; - rw_sel_p0.select_wr3 ( sel_buf_rw_p0.sel_buf_3 X ) ( storage_3_0_0.select_inv_0 A ) ( storage_3_0_0.gcand A ) + USE SIGNAL - + ROUTED met1 ( 8671 1037 ) ( 8901 * ) - NEW met1 ( 8441 935 ) ( * 969 ) - NEW met1 ( 8441 969 ) ( 8671 * ) - NEW li1 ( 8671 1037 ) L1M1_PR_MR - NEW li1 ( 8901 1037 ) L1M1_PR_MR - NEW li1 ( 8441 935 ) L1M1_PR_MR - NEW li1 ( 8671 969 ) L1M1_PR_MR ; + + ROUTED met1 ( 8303 1037 ) ( 8533 * ) + NEW met1 ( 8073 935 ) ( * 969 ) + NEW met1 ( 8073 969 ) ( 8303 * ) + NEW li1 ( 8303 1037 ) L1M1_PR_MR + NEW li1 ( 8533 1037 ) L1M1_PR_MR + NEW li1 ( 8303 969 ) L1M1_PR_MR + NEW li1 ( 8073 935 ) L1M1_PR_MR ; - rw_sel_p0.select_wr4 ( sel_buf_rw_p0.sel_buf_4 X ) ( storage_4_0_0.select_inv_0 A ) ( storage_4_0_0.gcand A ) + USE SIGNAL - + ROUTED met1 ( 8671 1173 ) ( 8901 * ) - NEW met1 ( 8901 1139 ) ( * 1173 ) - NEW met1 ( 8441 1241 ) ( 8671 * ) - NEW met1 ( 8671 1173 ) ( * 1241 ) - NEW li1 ( 8671 1173 ) L1M1_PR_MR - NEW li1 ( 8901 1139 ) L1M1_PR_MR - NEW li1 ( 8441 1241 ) L1M1_PR_MR ; + + ROUTED met1 ( 8303 1207 ) ( * 1241 ) + NEW met1 ( 8280 1275 ) ( 8533 * ) + NEW met1 ( 8280 1241 ) ( 8303 * ) + NEW met1 ( 8073 1241 ) ( 8280 * ) + NEW met1 ( 8280 1241 ) ( * 1275 ) + NEW li1 ( 8533 1275 ) L1M1_PR_MR + NEW li1 ( 8303 1207 ) L1M1_PR_MR + NEW li1 ( 8073 1241 ) L1M1_PR_MR ; - rw_sel_p0.select_wr5 ( sel_buf_rw_p0.sel_buf_5 X ) ( storage_5_0_0.select_inv_0 A ) ( storage_5_0_0.gcand A ) + USE SIGNAL - + ROUTED met1 ( 8671 1581 ) ( 8901 * ) - NEW met1 ( 8441 1479 ) ( * 1513 ) - NEW met1 ( 8441 1513 ) ( 8671 * ) - NEW li1 ( 8671 1581 ) L1M1_PR_MR - NEW li1 ( 8901 1581 ) L1M1_PR_MR - NEW li1 ( 8441 1479 ) L1M1_PR_MR - NEW li1 ( 8671 1513 ) L1M1_PR_MR ; + + ROUTED met1 ( 8303 1445 ) ( * 1513 ) + NEW met1 ( 8303 1445 ) ( 8533 * ) + NEW met1 ( 8073 1445 ) ( 8303 * ) + NEW li1 ( 8303 1513 ) L1M1_PR_MR + NEW li1 ( 8533 1445 ) L1M1_PR_MR + NEW li1 ( 8073 1445 ) L1M1_PR_MR ; - rw_sel_p0.select_wr6 ( sel_buf_rw_p0.sel_buf_6 X ) ( storage_6_0_0.select_inv_0 A ) ( storage_6_0_0.gcand A ) + USE SIGNAL - + ROUTED met1 ( 8671 1717 ) ( 8901 * ) - NEW met1 ( 8901 1683 ) ( * 1717 ) - NEW met1 ( 8441 1785 ) ( 8671 * ) - NEW met1 ( 8671 1717 ) ( * 1785 ) - NEW li1 ( 8671 1717 ) L1M1_PR_MR - NEW li1 ( 8901 1683 ) L1M1_PR_MR - NEW li1 ( 8441 1785 ) L1M1_PR_MR ; + + ROUTED met1 ( 8303 1717 ) ( 8533 * ) + NEW met1 ( 8533 1683 ) ( * 1717 ) + NEW met1 ( 8073 1785 ) ( 8303 * ) + NEW met1 ( 8303 1717 ) ( * 1785 ) + NEW li1 ( 8303 1717 ) L1M1_PR_MR + NEW li1 ( 8533 1683 ) L1M1_PR_MR + NEW li1 ( 8073 1785 ) L1M1_PR_MR ; - rw_sel_p0.select_wr7 ( sel_buf_rw_p0.sel_buf_7 X ) ( storage_7_0_0.select_inv_0 A ) ( storage_7_0_0.gcand A ) + USE SIGNAL - + ROUTED met1 ( 8671 2125 ) ( 8901 * ) - NEW met1 ( 8441 2023 ) ( * 2057 ) - NEW met1 ( 8441 2057 ) ( 8671 * ) - NEW li1 ( 8671 2125 ) L1M1_PR_MR - NEW li1 ( 8901 2125 ) L1M1_PR_MR - NEW li1 ( 8441 2023 ) L1M1_PR_MR - NEW li1 ( 8671 2057 ) L1M1_PR_MR ; + + ROUTED met1 ( 8303 2125 ) ( 8533 * ) + NEW met1 ( 8073 2023 ) ( * 2057 ) + NEW met1 ( 8073 2057 ) ( 8303 * ) + NEW li1 ( 8303 2125 ) L1M1_PR_MR + NEW li1 ( 8533 2125 ) L1M1_PR_MR + NEW li1 ( 8073 2023 ) L1M1_PR_MR + NEW li1 ( 8303 2057 ) L1M1_PR_MR ; - storage_0_0_0.bit0.storage ( storage_0_0_0.bit0.obuf0 A ) ( storage_0_0_0.bit0.bit Q ) + USE SIGNAL - + ROUTED met1 ( 621 153 ) ( * 187 ) - NEW met1 ( 575 187 ) ( 621 * ) - NEW li1 ( 621 153 ) L1M1_PR_MR - NEW li1 ( 575 187 ) L1M1_PR_MR ; + + ROUTED met1 ( 529 119 ) ( 575 * ) + NEW li1 ( 575 119 ) L1M1_PR_MR + NEW li1 ( 529 119 ) L1M1_PR_MR ; - storage_0_0_0.bit1.storage ( storage_0_0_0.bit1.obuf0 A ) ( storage_0_0_0.bit1.bit Q ) + USE SIGNAL - + ROUTED met1 ( 1587 153 ) ( * 187 ) - NEW met1 ( 1541 187 ) ( 1587 * ) - NEW li1 ( 1587 153 ) L1M1_PR_MR - NEW li1 ( 1541 187 ) L1M1_PR_MR ; + + ROUTED met1 ( 1449 119 ) ( 1495 * ) + NEW li1 ( 1495 119 ) L1M1_PR_MR + NEW li1 ( 1449 119 ) L1M1_PR_MR ; - storage_0_0_0.bit2.storage ( storage_0_0_0.bit2.obuf0 A ) ( storage_0_0_0.bit2.bit Q ) + USE SIGNAL - + ROUTED met1 ( 2553 153 ) ( * 187 ) - NEW met1 ( 2507 187 ) ( 2553 * ) - NEW li1 ( 2553 153 ) L1M1_PR_MR - NEW li1 ( 2507 187 ) L1M1_PR_MR ; + + ROUTED met1 ( 2369 119 ) ( 2415 * ) + NEW li1 ( 2415 119 ) L1M1_PR_MR + NEW li1 ( 2369 119 ) L1M1_PR_MR ; - storage_0_0_0.bit3.storage ( storage_0_0_0.bit3.obuf0 A ) ( storage_0_0_0.bit3.bit Q ) + USE SIGNAL - + ROUTED met1 ( 3519 153 ) ( * 187 ) - NEW met1 ( 3473 187 ) ( 3519 * ) - NEW li1 ( 3519 153 ) L1M1_PR_MR - NEW li1 ( 3473 187 ) L1M1_PR_MR ; + + ROUTED met1 ( 3289 119 ) ( 3335 * ) + NEW li1 ( 3335 119 ) L1M1_PR_MR + NEW li1 ( 3289 119 ) L1M1_PR_MR ; - storage_0_0_0.bit4.storage ( storage_0_0_0.bit4.obuf0 A ) ( storage_0_0_0.bit4.bit Q ) + USE SIGNAL - + ROUTED met1 ( 4485 153 ) ( * 187 ) - NEW met1 ( 4439 187 ) ( 4485 * ) - NEW li1 ( 4485 153 ) L1M1_PR_MR - NEW li1 ( 4439 187 ) L1M1_PR_MR ; + + ROUTED met1 ( 4209 119 ) ( 4255 * ) + NEW li1 ( 4255 119 ) L1M1_PR_MR + NEW li1 ( 4209 119 ) L1M1_PR_MR ; - storage_0_0_0.bit5.storage ( storage_0_0_0.bit5.obuf0 A ) ( storage_0_0_0.bit5.bit Q ) + USE SIGNAL - + ROUTED met1 ( 5451 153 ) ( * 187 ) - NEW met1 ( 5405 187 ) ( 5451 * ) - NEW li1 ( 5451 153 ) L1M1_PR_MR - NEW li1 ( 5405 187 ) L1M1_PR_MR ; + + ROUTED met1 ( 5129 119 ) ( 5175 * ) + NEW li1 ( 5175 119 ) L1M1_PR_MR + NEW li1 ( 5129 119 ) L1M1_PR_MR ; - storage_0_0_0.bit6.storage ( storage_0_0_0.bit6.obuf0 A ) ( storage_0_0_0.bit6.bit Q ) + USE SIGNAL - + ROUTED met1 ( 6417 153 ) ( * 187 ) - NEW met1 ( 6371 187 ) ( 6417 * ) - NEW li1 ( 6417 153 ) L1M1_PR_MR - NEW li1 ( 6371 187 ) L1M1_PR_MR ; + + ROUTED met1 ( 6049 119 ) ( 6095 * ) + NEW li1 ( 6095 119 ) L1M1_PR_MR + NEW li1 ( 6049 119 ) L1M1_PR_MR ; - storage_0_0_0.bit7.storage ( storage_0_0_0.bit7.obuf0 A ) ( storage_0_0_0.bit7.bit Q ) + USE SIGNAL - + ROUTED met1 ( 7383 153 ) ( * 187 ) - NEW met1 ( 7337 187 ) ( 7383 * ) - NEW li1 ( 7383 153 ) L1M1_PR_MR - NEW li1 ( 7337 187 ) L1M1_PR_MR ; - - storage_0_0_0.gclock ( storage_0_0_0.cg GCLK ) ( storage_0_0_0.bit7.bit GATE ) ( storage_0_0_0.bit6.bit GATE ) ( storage_0_0_0.bit5.bit GATE ) ( storage_0_0_0.bit4.bit GATE ) ( storage_0_0_0.bit3.bit GATE ) ( storage_0_0_0.bit2.bit GATE ) - ( storage_0_0_0.bit1.bit GATE ) ( storage_0_0_0.bit0.bit GATE ) + USE SIGNAL - + ROUTED met1 ( 1035 85 ) ( * 119 ) - NEW met1 ( 69 85 ) ( 1035 * ) - NEW met1 ( 69 85 ) ( * 119 ) - NEW met1 ( 6831 85 ) ( * 119 ) - NEW met1 ( 2001 85 ) ( * 119 ) - NEW met1 ( 2967 85 ) ( * 119 ) - NEW met1 ( 2001 85 ) ( 2967 * ) - NEW met1 ( 3933 85 ) ( * 119 ) - NEW met1 ( 2967 85 ) ( 3933 * ) - NEW met1 ( 4899 85 ) ( * 119 ) - NEW met1 ( 3933 85 ) ( 4899 * ) - NEW met1 ( 5865 85 ) ( * 119 ) - NEW met1 ( 4899 85 ) ( 5865 * ) - NEW met1 ( 1035 85 ) ( 2001 * ) - NEW met1 ( 5865 85 ) ( 6831 * ) - NEW met1 ( 7659 85 ) ( * 187 ) - NEW met1 ( 7659 187 ) ( 8395 * ) - NEW met1 ( 6831 85 ) ( 7659 * ) - NEW li1 ( 1035 119 ) L1M1_PR_MR - NEW li1 ( 69 119 ) L1M1_PR_MR - NEW li1 ( 6831 119 ) L1M1_PR_MR - NEW li1 ( 2001 119 ) L1M1_PR_MR - NEW li1 ( 2967 119 ) L1M1_PR_MR - NEW li1 ( 3933 119 ) L1M1_PR_MR - NEW li1 ( 4899 119 ) L1M1_PR_MR - NEW li1 ( 5865 119 ) L1M1_PR_MR - NEW li1 ( 8395 187 ) L1M1_PR_MR ; + + ROUTED met1 ( 6969 119 ) ( 7015 * ) + NEW li1 ( 7015 119 ) L1M1_PR_MR + NEW li1 ( 6969 119 ) L1M1_PR_MR ; + - storage_0_0_0.gclock ( storage_0_0_0.cg GCLK ) ( storage_0_0_0.bit7.bit SLEEP_B ) ( storage_0_0_0.bit6.bit SLEEP_B ) ( storage_0_0_0.bit5.bit SLEEP_B ) ( storage_0_0_0.bit4.bit SLEEP_B ) ( storage_0_0_0.bit3.bit SLEEP_B ) ( storage_0_0_0.bit2.bit SLEEP_B ) + ( storage_0_0_0.bit1.bit SLEEP_B ) ( storage_0_0_0.bit0.bit SLEEP_B ) + USE SIGNAL + + ROUTED met1 ( 69 153 ) ( 989 * ) + NEW met1 ( 6509 153 ) ( 8027 * ) + NEW met1 ( 4669 153 ) ( 5589 * ) + NEW met1 ( 3749 153 ) ( 4669 * ) + NEW met1 ( 2829 153 ) ( 3749 * ) + NEW met1 ( 1909 153 ) ( 2829 * ) + NEW met1 ( 989 153 ) ( 1909 * ) + NEW met1 ( 5589 153 ) ( 6509 * ) + NEW li1 ( 989 153 ) L1M1_PR_MR + NEW li1 ( 69 153 ) L1M1_PR_MR + NEW li1 ( 6509 153 ) L1M1_PR_MR + NEW li1 ( 8027 153 ) L1M1_PR_MR + NEW li1 ( 5589 153 ) L1M1_PR_MR + NEW li1 ( 4669 153 ) L1M1_PR_MR + NEW li1 ( 3749 153 ) L1M1_PR_MR + NEW li1 ( 2829 153 ) L1M1_PR_MR + NEW li1 ( 1909 153 ) L1M1_PR_MR ; - storage_0_0_0.select0_b ( storage_0_0_0.select_inv_0 Y ) ( storage_0_0_0.bit7.obuf0 TE_B ) ( storage_0_0_0.bit6.obuf0 TE_B ) ( storage_0_0_0.bit5.obuf0 TE_B ) ( storage_0_0_0.bit4.obuf0 TE_B ) ( storage_0_0_0.bit3.obuf0 TE_B ) ( storage_0_0_0.bit2.obuf0 TE_B ) ( storage_0_0_0.bit1.obuf0 TE_B ) ( storage_0_0_0.bit0.obuf0 TE_B ) + USE SIGNAL - + ROUTED met1 ( 713 153 ) ( 989 * ) - NEW met1 ( 989 153 ) ( * 221 ) - NEW met1 ( 7475 153 ) ( * 187 ) - NEW met1 ( 6509 153 ) ( 6785 * ) - NEW met1 ( 6785 153 ) ( * 221 ) - NEW met1 ( 6785 221 ) ( 7475 * ) - NEW met1 ( 7475 187 ) ( * 221 ) - NEW met1 ( 6509 153 ) ( * 221 ) - NEW met1 ( 5543 153 ) ( 5773 * ) - NEW met1 ( 5773 153 ) ( * 221 ) - NEW met1 ( 4577 153 ) ( 4853 * ) - NEW met1 ( 4853 153 ) ( * 221 ) - NEW met1 ( 4853 221 ) ( 5543 * ) - NEW met1 ( 5543 153 ) ( * 221 ) - NEW met1 ( 3611 153 ) ( 3841 * ) - NEW met1 ( 3841 153 ) ( * 221 ) - NEW met1 ( 3841 221 ) ( 4577 * ) - NEW met1 ( 4577 153 ) ( * 221 ) - NEW met1 ( 2645 153 ) ( 2921 * ) - NEW met1 ( 2921 153 ) ( * 221 ) - NEW met1 ( 2921 221 ) ( 3611 * ) - NEW met1 ( 3611 153 ) ( * 221 ) - NEW met1 ( 1679 153 ) ( 1909 * ) - NEW met1 ( 1909 153 ) ( * 221 ) - NEW met1 ( 1909 221 ) ( 2645 * ) - NEW met1 ( 2645 153 ) ( * 221 ) - NEW met1 ( 1679 153 ) ( * 221 ) - NEW met1 ( 989 221 ) ( 1679 * ) - NEW met1 ( 5773 221 ) ( 6509 * ) - NEW met1 ( 7475 187 ) ( 7590 * ) - NEW met1 ( 7590 187 ) ( * 221 ) - NEW met1 ( 7590 221 ) ( 8717 * ) - NEW li1 ( 713 153 ) L1M1_PR_MR - NEW li1 ( 7475 153 ) L1M1_PR_MR - NEW li1 ( 6509 153 ) L1M1_PR_MR - NEW li1 ( 5543 153 ) L1M1_PR_MR - NEW li1 ( 4577 153 ) L1M1_PR_MR - NEW li1 ( 3611 153 ) L1M1_PR_MR - NEW li1 ( 2645 153 ) L1M1_PR_MR - NEW li1 ( 1679 153 ) L1M1_PR_MR - NEW li1 ( 8717 221 ) L1M1_PR_MR ; + + ROUTED met1 ( 7107 85 ) ( * 119 ) + NEW met1 ( 6785 85 ) ( * 119 ) + NEW met1 ( 6785 85 ) ( 7107 * ) + NEW met1 ( 7107 85 ) ( 8349 * ) + NEW met1 ( 667 119 ) ( 1380 * ) + NEW met1 ( 1587 85 ) ( * 119 ) + NEW met1 ( 1380 85 ) ( 1587 * ) + NEW met1 ( 1380 85 ) ( * 119 ) + NEW met1 ( 2507 85 ) ( * 119 ) + NEW met1 ( 2323 85 ) ( 2507 * ) + NEW met1 ( 2323 85 ) ( * 119 ) + NEW met1 ( 1587 119 ) ( 2323 * ) + NEW met1 ( 3427 85 ) ( * 119 ) + NEW met1 ( 3243 85 ) ( 3427 * ) + NEW met1 ( 3243 85 ) ( * 119 ) + NEW met1 ( 2507 119 ) ( 3243 * ) + NEW met1 ( 4347 85 ) ( * 119 ) + NEW met1 ( 4163 85 ) ( 4347 * ) + NEW met1 ( 4163 85 ) ( * 119 ) + NEW met1 ( 3427 119 ) ( 4163 * ) + NEW met1 ( 5267 85 ) ( * 119 ) + NEW met1 ( 5083 85 ) ( 5267 * ) + NEW met1 ( 5083 85 ) ( * 119 ) + NEW met1 ( 4347 119 ) ( 5083 * ) + NEW met1 ( 6187 85 ) ( * 119 ) + NEW met1 ( 6003 85 ) ( 6187 * ) + NEW met1 ( 6003 85 ) ( * 119 ) + NEW met1 ( 5267 119 ) ( 6003 * ) + NEW met1 ( 6187 119 ) ( 6785 * ) + NEW li1 ( 667 119 ) L1M1_PR_MR + NEW li1 ( 8349 85 ) L1M1_PR_MR + NEW li1 ( 7107 119 ) L1M1_PR_MR + NEW li1 ( 1587 119 ) L1M1_PR_MR + NEW li1 ( 2507 119 ) L1M1_PR_MR + NEW li1 ( 3427 119 ) L1M1_PR_MR + NEW li1 ( 4347 119 ) L1M1_PR_MR + NEW li1 ( 5267 119 ) L1M1_PR_MR + NEW li1 ( 6187 119 ) L1M1_PR_MR ; - storage_0_0_0.we ( storage_0_0_0.gcand X ) ( storage_0_0_0.cg GATE ) + USE SIGNAL - + ROUTED met1 ( 7981 51 ) ( 8625 * ) - NEW li1 ( 7981 51 ) L1M1_PR_MR - NEW li1 ( 8625 51 ) L1M1_PR_MR ; + + ROUTED met1 ( 7613 51 ) ( 8257 * ) + NEW li1 ( 7613 51 ) L1M1_PR_MR + NEW li1 ( 8257 51 ) L1M1_PR_MR ; - storage_1_0_0.bit0.storage ( storage_1_0_0.bit0.obuf0 A ) ( storage_1_0_0.bit0.bit Q ) + USE SIGNAL - + ROUTED met1 ( 575 391 ) ( 621 * ) - NEW met1 ( 575 357 ) ( * 391 ) - NEW li1 ( 621 391 ) L1M1_PR_MR - NEW li1 ( 575 357 ) L1M1_PR_MR ; + + ROUTED met1 ( 529 425 ) ( 575 * ) + NEW li1 ( 575 425 ) L1M1_PR_MR + NEW li1 ( 529 425 ) L1M1_PR_MR ; - storage_1_0_0.bit1.storage ( storage_1_0_0.bit1.obuf0 A ) ( storage_1_0_0.bit1.bit Q ) + USE SIGNAL - + ROUTED met1 ( 1541 391 ) ( 1587 * ) - NEW met1 ( 1541 357 ) ( * 391 ) - NEW li1 ( 1587 391 ) L1M1_PR_MR - NEW li1 ( 1541 357 ) L1M1_PR_MR ; + + ROUTED met1 ( 1449 425 ) ( 1495 * ) + NEW li1 ( 1495 425 ) L1M1_PR_MR + NEW li1 ( 1449 425 ) L1M1_PR_MR ; - storage_1_0_0.bit2.storage ( storage_1_0_0.bit2.obuf0 A ) ( storage_1_0_0.bit2.bit Q ) + USE SIGNAL - + ROUTED met1 ( 2507 391 ) ( 2553 * ) - NEW met1 ( 2507 357 ) ( * 391 ) - NEW li1 ( 2553 391 ) L1M1_PR_MR - NEW li1 ( 2507 357 ) L1M1_PR_MR ; + + ROUTED met1 ( 2369 425 ) ( 2415 * ) + NEW li1 ( 2415 425 ) L1M1_PR_MR + NEW li1 ( 2369 425 ) L1M1_PR_MR ; - storage_1_0_0.bit3.storage ( storage_1_0_0.bit3.obuf0 A ) ( storage_1_0_0.bit3.bit Q ) + USE SIGNAL - + ROUTED met1 ( 3473 391 ) ( 3519 * ) - NEW met1 ( 3473 357 ) ( * 391 ) - NEW li1 ( 3519 391 ) L1M1_PR_MR - NEW li1 ( 3473 357 ) L1M1_PR_MR ; + + ROUTED met1 ( 3289 425 ) ( 3335 * ) + NEW li1 ( 3335 425 ) L1M1_PR_MR + NEW li1 ( 3289 425 ) L1M1_PR_MR ; - storage_1_0_0.bit4.storage ( storage_1_0_0.bit4.obuf0 A ) ( storage_1_0_0.bit4.bit Q ) + USE SIGNAL - + ROUTED met1 ( 4439 391 ) ( 4485 * ) - NEW met1 ( 4439 357 ) ( * 391 ) - NEW li1 ( 4485 391 ) L1M1_PR_MR - NEW li1 ( 4439 357 ) L1M1_PR_MR ; + + ROUTED met1 ( 4209 425 ) ( 4255 * ) + NEW li1 ( 4255 425 ) L1M1_PR_MR + NEW li1 ( 4209 425 ) L1M1_PR_MR ; - storage_1_0_0.bit5.storage ( storage_1_0_0.bit5.obuf0 A ) ( storage_1_0_0.bit5.bit Q ) + USE SIGNAL - + ROUTED met1 ( 5405 391 ) ( 5451 * ) - NEW met1 ( 5405 357 ) ( * 391 ) - NEW li1 ( 5451 391 ) L1M1_PR_MR - NEW li1 ( 5405 357 ) L1M1_PR_MR ; + + ROUTED met1 ( 5129 425 ) ( 5175 * ) + NEW li1 ( 5175 425 ) L1M1_PR_MR + NEW li1 ( 5129 425 ) L1M1_PR_MR ; - storage_1_0_0.bit6.storage ( storage_1_0_0.bit6.obuf0 A ) ( storage_1_0_0.bit6.bit Q ) + USE SIGNAL - + ROUTED met1 ( 6371 391 ) ( 6417 * ) - NEW met1 ( 6371 357 ) ( * 391 ) - NEW li1 ( 6417 391 ) L1M1_PR_MR - NEW li1 ( 6371 357 ) L1M1_PR_MR ; + + ROUTED met1 ( 6049 425 ) ( 6095 * ) + NEW li1 ( 6095 425 ) L1M1_PR_MR + NEW li1 ( 6049 425 ) L1M1_PR_MR ; - storage_1_0_0.bit7.storage ( storage_1_0_0.bit7.obuf0 A ) ( storage_1_0_0.bit7.bit Q ) + USE SIGNAL - + ROUTED met1 ( 7337 391 ) ( 7383 * ) - NEW met1 ( 7337 357 ) ( * 391 ) - NEW li1 ( 7383 391 ) L1M1_PR_MR - NEW li1 ( 7337 357 ) L1M1_PR_MR ; - - storage_1_0_0.gclock ( storage_1_0_0.cg GCLK ) ( storage_1_0_0.bit7.bit GATE ) ( storage_1_0_0.bit6.bit GATE ) ( storage_1_0_0.bit5.bit GATE ) ( storage_1_0_0.bit4.bit GATE ) ( storage_1_0_0.bit3.bit GATE ) ( storage_1_0_0.bit2.bit GATE ) - ( storage_1_0_0.bit1.bit GATE ) ( storage_1_0_0.bit0.bit GATE ) + USE SIGNAL - + ROUTED met1 ( 1035 425 ) ( * 459 ) - NEW met1 ( 69 459 ) ( 1035 * ) - NEW met1 ( 69 425 ) ( * 459 ) - NEW met1 ( 6831 323 ) ( * 391 ) - NEW met1 ( 2001 425 ) ( * 459 ) - NEW met1 ( 2967 425 ) ( * 459 ) - NEW met1 ( 2001 459 ) ( 2967 * ) - NEW met1 ( 3933 425 ) ( * 459 ) - NEW met1 ( 2967 459 ) ( 3933 * ) - NEW met1 ( 4899 425 ) ( * 459 ) - NEW met1 ( 3933 459 ) ( 4899 * ) - NEW met1 ( 5773 391 ) ( 5865 * ) - NEW met1 ( 5773 391 ) ( * 459 ) - NEW met1 ( 4899 459 ) ( 5773 * ) - NEW met1 ( 5865 323 ) ( * 391 ) - NEW met1 ( 1035 459 ) ( 2001 * ) - NEW met1 ( 5865 323 ) ( 6831 * ) - NEW met1 ( 6831 323 ) ( 8395 * ) - NEW li1 ( 1035 425 ) L1M1_PR_MR - NEW li1 ( 69 425 ) L1M1_PR_MR - NEW li1 ( 6831 391 ) L1M1_PR_MR - NEW li1 ( 2001 425 ) L1M1_PR_MR - NEW li1 ( 2967 425 ) L1M1_PR_MR - NEW li1 ( 3933 425 ) L1M1_PR_MR - NEW li1 ( 4899 425 ) L1M1_PR_MR - NEW li1 ( 5865 391 ) L1M1_PR_MR - NEW li1 ( 8395 323 ) L1M1_PR_MR ; + + ROUTED met1 ( 6969 425 ) ( 7015 * ) + NEW li1 ( 7015 425 ) L1M1_PR_MR + NEW li1 ( 6969 425 ) L1M1_PR_MR ; + - storage_1_0_0.gclock ( storage_1_0_0.cg GCLK ) ( storage_1_0_0.bit7.bit SLEEP_B ) ( storage_1_0_0.bit6.bit SLEEP_B ) ( storage_1_0_0.bit5.bit SLEEP_B ) ( storage_1_0_0.bit4.bit SLEEP_B ) ( storage_1_0_0.bit3.bit SLEEP_B ) ( storage_1_0_0.bit2.bit SLEEP_B ) + ( storage_1_0_0.bit1.bit SLEEP_B ) ( storage_1_0_0.bit0.bit SLEEP_B ) + USE SIGNAL + + ROUTED met1 ( 6509 391 ) ( 8027 * ) + NEW met1 ( 6509 357 ) ( * 391 ) + NEW met1 ( 5589 357 ) ( * 391 ) + NEW met1 ( 4669 357 ) ( * 391 ) + NEW met1 ( 4669 357 ) ( 5589 * ) + NEW met1 ( 3749 357 ) ( * 391 ) + NEW met1 ( 3749 357 ) ( 4669 * ) + NEW met1 ( 5589 357 ) ( 6509 * ) + NEW met1 ( 621 425 ) ( 989 * ) + NEW met1 ( 621 391 ) ( * 425 ) + NEW met1 ( 69 391 ) ( 621 * ) + NEW met1 ( 1909 357 ) ( * 391 ) + NEW met1 ( 989 357 ) ( 1909 * ) + NEW met2 ( 989 357 ) ( * 425 ) + NEW met1 ( 1909 391 ) ( 2829 * ) + NEW met1 ( 2829 357 ) ( * 391 ) + NEW met1 ( 2829 357 ) ( 3749 * ) + NEW li1 ( 6509 391 ) L1M1_PR_MR + NEW li1 ( 8027 391 ) L1M1_PR_MR + NEW li1 ( 5589 391 ) L1M1_PR_MR + NEW li1 ( 4669 391 ) L1M1_PR_MR + NEW li1 ( 3749 391 ) L1M1_PR_MR + NEW li1 ( 989 425 ) L1M1_PR_MR + NEW li1 ( 69 391 ) L1M1_PR_MR + NEW li1 ( 1909 391 ) L1M1_PR_MR + NEW met1 ( 989 357 ) M1M2_PR + NEW met1 ( 989 425 ) M1M2_PR + NEW li1 ( 2829 391 ) L1M1_PR_MR ; - storage_1_0_0.select0_b ( storage_1_0_0.select_inv_0 Y ) ( storage_1_0_0.bit7.obuf0 TE_B ) ( storage_1_0_0.bit6.obuf0 TE_B ) ( storage_1_0_0.bit5.obuf0 TE_B ) ( storage_1_0_0.bit4.obuf0 TE_B ) ( storage_1_0_0.bit3.obuf0 TE_B ) ( storage_1_0_0.bit2.obuf0 TE_B ) ( storage_1_0_0.bit1.obuf0 TE_B ) ( storage_1_0_0.bit0.obuf0 TE_B ) + USE SIGNAL - + ROUTED met1 ( 713 323 ) ( * 391 ) - NEW met1 ( 7475 357 ) ( * 391 ) - NEW met1 ( 6509 425 ) ( * 459 ) - NEW met1 ( 6509 459 ) ( 7475 * ) - NEW met1 ( 7475 391 ) ( * 459 ) - NEW met1 ( 5543 357 ) ( * 391 ) - NEW met1 ( 5543 357 ) ( 5819 * ) - NEW met2 ( 5819 357 ) ( * 459 ) - NEW met1 ( 4577 323 ) ( * 391 ) - NEW met1 ( 4577 323 ) ( 5543 * ) - NEW met1 ( 5543 323 ) ( * 357 ) - NEW met1 ( 3611 323 ) ( * 391 ) - NEW met1 ( 3611 323 ) ( 4577 * ) - NEW met1 ( 2645 323 ) ( * 391 ) - NEW met1 ( 2645 323 ) ( 3611 * ) - NEW met1 ( 1679 323 ) ( * 391 ) - NEW met1 ( 1679 323 ) ( 2645 * ) - NEW met1 ( 713 323 ) ( 1679 * ) - NEW met1 ( 5819 459 ) ( 6509 * ) - NEW met1 ( 7475 357 ) ( 8717 * ) - NEW li1 ( 713 391 ) L1M1_PR_MR - NEW li1 ( 7475 391 ) L1M1_PR_MR - NEW li1 ( 6509 425 ) L1M1_PR_MR - NEW li1 ( 5543 391 ) L1M1_PR_MR - NEW met1 ( 5819 357 ) M1M2_PR - NEW met1 ( 5819 459 ) M1M2_PR - NEW li1 ( 4577 391 ) L1M1_PR_MR - NEW li1 ( 3611 391 ) L1M1_PR_MR - NEW li1 ( 2645 391 ) L1M1_PR_MR - NEW li1 ( 1679 391 ) L1M1_PR_MR - NEW li1 ( 8717 357 ) L1M1_PR_MR ; + + ROUTED met1 ( 7107 425 ) ( * 459 ) + NEW met1 ( 6785 425 ) ( * 459 ) + NEW met1 ( 6785 459 ) ( 7107 * ) + NEW met1 ( 7107 459 ) ( 8349 * ) + NEW met1 ( 4163 391 ) ( 4347 * ) + NEW met1 ( 4163 391 ) ( * 425 ) + NEW met1 ( 5083 391 ) ( 5267 * ) + NEW met1 ( 5083 391 ) ( * 425 ) + NEW met1 ( 4347 425 ) ( 5083 * ) + NEW met1 ( 4347 391 ) ( * 425 ) + NEW met1 ( 6003 391 ) ( 6187 * ) + NEW met1 ( 6003 391 ) ( * 425 ) + NEW met1 ( 5267 425 ) ( 6003 * ) + NEW met1 ( 5267 391 ) ( * 425 ) + NEW met1 ( 6187 391 ) ( * 425 ) + NEW met1 ( 6187 425 ) ( 6785 * ) + NEW met1 ( 1587 425 ) ( * 459 ) + NEW met1 ( 1311 459 ) ( 1587 * ) + NEW met1 ( 1311 391 ) ( * 459 ) + NEW met1 ( 667 391 ) ( 1311 * ) + NEW met1 ( 2507 425 ) ( * 459 ) + NEW met1 ( 2323 459 ) ( 2507 * ) + NEW met1 ( 2323 425 ) ( * 459 ) + NEW met1 ( 1587 425 ) ( 2323 * ) + NEW met1 ( 3243 391 ) ( 3427 * ) + NEW met1 ( 3243 391 ) ( * 425 ) + NEW met1 ( 2507 425 ) ( 3243 * ) + NEW met1 ( 3427 391 ) ( * 425 ) + NEW met1 ( 3427 425 ) ( 4163 * ) + NEW li1 ( 8349 459 ) L1M1_PR_MR + NEW li1 ( 7107 425 ) L1M1_PR_MR + NEW li1 ( 4347 391 ) L1M1_PR_MR + NEW li1 ( 5267 391 ) L1M1_PR_MR + NEW li1 ( 6187 391 ) L1M1_PR_MR + NEW li1 ( 1587 425 ) L1M1_PR_MR + NEW li1 ( 667 391 ) L1M1_PR_MR + NEW li1 ( 2507 425 ) L1M1_PR_MR + NEW li1 ( 3427 391 ) L1M1_PR_MR ; - storage_1_0_0.we ( storage_1_0_0.gcand X ) ( storage_1_0_0.cg GATE ) + USE SIGNAL - + ROUTED met1 ( 7981 459 ) ( 8625 * ) - NEW li1 ( 7981 459 ) L1M1_PR_MR - NEW li1 ( 8625 459 ) L1M1_PR_MR ; + + ROUTED met1 ( 7613 493 ) ( 8257 * ) + NEW li1 ( 7613 493 ) L1M1_PR_MR + NEW li1 ( 8257 493 ) L1M1_PR_MR ; - storage_2_0_0.bit0.storage ( storage_2_0_0.bit0.obuf0 A ) ( storage_2_0_0.bit0.bit Q ) + USE SIGNAL - + ROUTED met1 ( 575 663 ) ( 621 * ) - NEW met1 ( 575 595 ) ( * 663 ) - NEW li1 ( 621 663 ) L1M1_PR_MR - NEW li1 ( 575 595 ) L1M1_PR_MR ; + + ROUTED met1 ( 529 663 ) ( 575 * ) + NEW li1 ( 575 663 ) L1M1_PR_MR + NEW li1 ( 529 663 ) L1M1_PR_MR ; - storage_2_0_0.bit1.storage ( storage_2_0_0.bit1.obuf0 A ) ( storage_2_0_0.bit1.bit Q ) + USE SIGNAL - + ROUTED met1 ( 1541 663 ) ( 1587 * ) - NEW met1 ( 1541 663 ) ( * 731 ) - NEW li1 ( 1587 663 ) L1M1_PR_MR - NEW li1 ( 1541 731 ) L1M1_PR_MR ; + + ROUTED met1 ( 1449 663 ) ( 1495 * ) + NEW li1 ( 1495 663 ) L1M1_PR_MR + NEW li1 ( 1449 663 ) L1M1_PR_MR ; - storage_2_0_0.bit2.storage ( storage_2_0_0.bit2.obuf0 A ) ( storage_2_0_0.bit2.bit Q ) + USE SIGNAL - + ROUTED met1 ( 2507 663 ) ( 2553 * ) - NEW met1 ( 2507 663 ) ( * 731 ) - NEW li1 ( 2553 663 ) L1M1_PR_MR - NEW li1 ( 2507 731 ) L1M1_PR_MR ; + + ROUTED met1 ( 2369 663 ) ( 2415 * ) + NEW li1 ( 2415 663 ) L1M1_PR_MR + NEW li1 ( 2369 663 ) L1M1_PR_MR ; - storage_2_0_0.bit3.storage ( storage_2_0_0.bit3.obuf0 A ) ( storage_2_0_0.bit3.bit Q ) + USE SIGNAL - + ROUTED met1 ( 3473 663 ) ( 3519 * ) - NEW met1 ( 3473 663 ) ( * 731 ) - NEW li1 ( 3519 663 ) L1M1_PR_MR - NEW li1 ( 3473 731 ) L1M1_PR_MR ; + + ROUTED met1 ( 3289 663 ) ( 3335 * ) + NEW li1 ( 3335 663 ) L1M1_PR_MR + NEW li1 ( 3289 663 ) L1M1_PR_MR ; - storage_2_0_0.bit4.storage ( storage_2_0_0.bit4.obuf0 A ) ( storage_2_0_0.bit4.bit Q ) + USE SIGNAL - + ROUTED met1 ( 4439 663 ) ( 4485 * ) - NEW met1 ( 4439 663 ) ( * 731 ) - NEW li1 ( 4485 663 ) L1M1_PR_MR - NEW li1 ( 4439 731 ) L1M1_PR_MR ; + + ROUTED met1 ( 4209 663 ) ( 4255 * ) + NEW li1 ( 4255 663 ) L1M1_PR_MR + NEW li1 ( 4209 663 ) L1M1_PR_MR ; - storage_2_0_0.bit5.storage ( storage_2_0_0.bit5.obuf0 A ) ( storage_2_0_0.bit5.bit Q ) + USE SIGNAL - + ROUTED met1 ( 5405 663 ) ( 5451 * ) - NEW met1 ( 5405 663 ) ( * 731 ) - NEW li1 ( 5451 663 ) L1M1_PR_MR - NEW li1 ( 5405 731 ) L1M1_PR_MR ; + + ROUTED met1 ( 5129 663 ) ( 5175 * ) + NEW li1 ( 5175 663 ) L1M1_PR_MR + NEW li1 ( 5129 663 ) L1M1_PR_MR ; - storage_2_0_0.bit6.storage ( storage_2_0_0.bit6.obuf0 A ) ( storage_2_0_0.bit6.bit Q ) + USE SIGNAL - + ROUTED met1 ( 6371 663 ) ( 6417 * ) - NEW met1 ( 6371 663 ) ( * 731 ) - NEW li1 ( 6417 663 ) L1M1_PR_MR - NEW li1 ( 6371 731 ) L1M1_PR_MR ; + + ROUTED met1 ( 6049 663 ) ( 6095 * ) + NEW li1 ( 6095 663 ) L1M1_PR_MR + NEW li1 ( 6049 663 ) L1M1_PR_MR ; - storage_2_0_0.bit7.storage ( storage_2_0_0.bit7.obuf0 A ) ( storage_2_0_0.bit7.bit Q ) + USE SIGNAL - + ROUTED met1 ( 7383 648 ) ( * 663 ) - NEW met1 ( 7337 648 ) ( 7383 * ) - NEW met1 ( 7337 595 ) ( * 648 ) - NEW li1 ( 7383 663 ) L1M1_PR_MR - NEW li1 ( 7337 595 ) L1M1_PR_MR ; - - storage_2_0_0.gclock ( storage_2_0_0.cg GCLK ) ( storage_2_0_0.bit7.bit GATE ) ( storage_2_0_0.bit6.bit GATE ) ( storage_2_0_0.bit5.bit GATE ) ( storage_2_0_0.bit4.bit GATE ) ( storage_2_0_0.bit3.bit GATE ) ( storage_2_0_0.bit2.bit GATE ) - ( storage_2_0_0.bit1.bit GATE ) ( storage_2_0_0.bit0.bit GATE ) + USE SIGNAL - + ROUTED met1 ( 759 663 ) ( 1035 * ) - NEW met1 ( 759 663 ) ( * 697 ) - NEW met1 ( 529 697 ) ( 759 * ) - NEW met1 ( 529 629 ) ( * 697 ) - NEW met1 ( 69 629 ) ( 529 * ) - NEW met1 ( 69 629 ) ( * 663 ) - NEW met1 ( 1035 629 ) ( * 663 ) - NEW met1 ( 6831 697 ) ( * 765 ) - NEW met1 ( 6831 765 ) ( 7153 * ) - NEW met1 ( 7153 731 ) ( * 765 ) - NEW met1 ( 6463 629 ) ( * 697 ) - NEW met1 ( 6463 697 ) ( 6831 * ) - NEW met1 ( 1725 663 ) ( 2001 * ) - NEW met1 ( 1725 663 ) ( * 697 ) - NEW met1 ( 1633 697 ) ( 1725 * ) - NEW met1 ( 1633 629 ) ( * 697 ) - NEW met1 ( 2691 663 ) ( 2967 * ) - NEW met1 ( 2691 663 ) ( * 697 ) - NEW met1 ( 2599 697 ) ( 2691 * ) - NEW met1 ( 2599 629 ) ( * 697 ) - NEW met1 ( 2001 629 ) ( 2599 * ) - NEW met1 ( 2001 629 ) ( * 663 ) - NEW met1 ( 3657 663 ) ( 3933 * ) - NEW met1 ( 3657 663 ) ( * 697 ) - NEW met1 ( 3565 697 ) ( 3657 * ) - NEW met1 ( 3565 629 ) ( * 697 ) - NEW met1 ( 2967 629 ) ( 3565 * ) - NEW met1 ( 2967 629 ) ( * 663 ) - NEW met1 ( 4623 663 ) ( 4899 * ) - NEW met1 ( 4623 663 ) ( * 697 ) - NEW met1 ( 4531 697 ) ( 4623 * ) - NEW met1 ( 4531 629 ) ( * 697 ) - NEW met1 ( 3933 629 ) ( 4531 * ) - NEW met1 ( 3933 629 ) ( * 663 ) + + ROUTED met1 ( 6969 663 ) ( 7015 * ) + NEW li1 ( 7015 663 ) L1M1_PR_MR + NEW li1 ( 6969 663 ) L1M1_PR_MR ; + - storage_2_0_0.gclock ( storage_2_0_0.cg GCLK ) ( storage_2_0_0.bit7.bit SLEEP_B ) ( storage_2_0_0.bit6.bit SLEEP_B ) ( storage_2_0_0.bit5.bit SLEEP_B ) ( storage_2_0_0.bit4.bit SLEEP_B ) ( storage_2_0_0.bit3.bit SLEEP_B ) ( storage_2_0_0.bit2.bit SLEEP_B ) + ( storage_2_0_0.bit1.bit SLEEP_B ) ( storage_2_0_0.bit0.bit SLEEP_B ) + USE SIGNAL + + ROUTED met1 ( 989 629 ) ( * 663 ) + NEW met1 ( 483 629 ) ( 989 * ) + NEW met1 ( 483 629 ) ( * 663 ) + NEW met1 ( 69 663 ) ( 483 * ) + NEW met1 ( 6509 663 ) ( 6785 * ) + NEW met1 ( 6785 629 ) ( * 663 ) + NEW met1 ( 6785 629 ) ( 7889 * ) + NEW met2 ( 7889 629 ) ( * 731 ) + NEW met1 ( 7889 731 ) ( 8027 * ) + NEW met1 ( 6509 629 ) ( * 663 ) + NEW met1 ( 989 663 ) ( 1380 * ) NEW met1 ( 5589 663 ) ( 5865 * ) - NEW met1 ( 5589 663 ) ( * 697 ) - NEW met1 ( 5497 697 ) ( 5589 * ) - NEW met1 ( 5497 629 ) ( * 697 ) - NEW met1 ( 4899 629 ) ( 5497 * ) - NEW met1 ( 4899 629 ) ( * 663 ) NEW met1 ( 5865 629 ) ( * 663 ) - NEW met1 ( 1035 629 ) ( 1633 * ) - NEW met1 ( 5865 629 ) ( 6463 * ) - NEW met1 ( 7153 731 ) ( 8395 * ) - NEW li1 ( 1035 663 ) L1M1_PR_MR + NEW met1 ( 4669 663 ) ( 4899 * ) + NEW met1 ( 4899 629 ) ( * 663 ) + NEW met1 ( 4899 629 ) ( 5589 * ) + NEW met1 ( 5589 629 ) ( * 663 ) + NEW met1 ( 3749 663 ) ( 4117 * ) + NEW met1 ( 4117 629 ) ( * 663 ) + NEW met1 ( 4117 629 ) ( 4669 * ) + NEW met1 ( 4669 629 ) ( * 663 ) + NEW met1 ( 2829 663 ) ( 3059 * ) + NEW met1 ( 3059 629 ) ( * 663 ) + NEW met1 ( 3059 629 ) ( 3749 * ) + NEW met1 ( 3749 629 ) ( * 663 ) + NEW met1 ( 1909 663 ) ( 2139 * ) + NEW met1 ( 2139 629 ) ( * 663 ) + NEW met1 ( 2139 629 ) ( 2829 * ) + NEW met1 ( 2829 629 ) ( * 663 ) + NEW met1 ( 1380 629 ) ( * 663 ) + NEW met1 ( 1380 629 ) ( 1909 * ) + NEW met1 ( 1909 629 ) ( * 663 ) + NEW met1 ( 5865 629 ) ( 6509 * ) + NEW li1 ( 989 663 ) L1M1_PR_MR NEW li1 ( 69 663 ) L1M1_PR_MR - NEW li1 ( 6831 697 ) L1M1_PR_MR - NEW li1 ( 2001 663 ) L1M1_PR_MR - NEW li1 ( 2967 663 ) L1M1_PR_MR - NEW li1 ( 3933 663 ) L1M1_PR_MR - NEW li1 ( 4899 663 ) L1M1_PR_MR - NEW li1 ( 5865 663 ) L1M1_PR_MR - NEW li1 ( 8395 731 ) L1M1_PR_MR ; + NEW li1 ( 6509 663 ) L1M1_PR_MR + NEW met1 ( 7889 629 ) M1M2_PR + NEW met1 ( 7889 731 ) M1M2_PR + NEW li1 ( 8027 731 ) L1M1_PR_MR + NEW li1 ( 5589 663 ) L1M1_PR_MR + NEW li1 ( 4669 663 ) L1M1_PR_MR + NEW li1 ( 3749 663 ) L1M1_PR_MR + NEW li1 ( 2829 663 ) L1M1_PR_MR + NEW li1 ( 1909 663 ) L1M1_PR_MR ; - storage_2_0_0.select0_b ( storage_2_0_0.select_inv_0 Y ) ( storage_2_0_0.bit7.obuf0 TE_B ) ( storage_2_0_0.bit6.obuf0 TE_B ) ( storage_2_0_0.bit5.obuf0 TE_B ) ( storage_2_0_0.bit4.obuf0 TE_B ) ( storage_2_0_0.bit3.obuf0 TE_B ) ( storage_2_0_0.bit2.obuf0 TE_B ) ( storage_2_0_0.bit1.obuf0 TE_B ) ( storage_2_0_0.bit0.obuf0 TE_B ) + USE SIGNAL - + ROUTED met1 ( 713 595 ) ( * 663 ) - NEW met1 ( 7475 629 ) ( * 663 ) - NEW met1 ( 6509 663 ) ( 6555 * ) - NEW met1 ( 6555 595 ) ( * 663 ) - NEW met1 ( 6555 595 ) ( 7291 * ) - NEW met1 ( 7291 595 ) ( * 697 ) - NEW met1 ( 7291 697 ) ( 7429 * ) - NEW met1 ( 7429 663 ) ( * 697 ) - NEW met1 ( 7429 663 ) ( 7475 * ) - NEW met1 ( 5543 629 ) ( * 663 ) - NEW met1 ( 5543 629 ) ( 5589 * ) - NEW met1 ( 5589 595 ) ( * 629 ) - NEW met1 ( 4577 595 ) ( * 663 ) - NEW met1 ( 4577 595 ) ( 5589 * ) - NEW met1 ( 3611 629 ) ( * 663 ) - NEW met1 ( 3611 629 ) ( 3657 * ) - NEW met1 ( 3657 595 ) ( * 629 ) - NEW met1 ( 3657 595 ) ( 4577 * ) - NEW met1 ( 2645 595 ) ( * 663 ) - NEW met1 ( 2645 595 ) ( 3657 * ) - NEW met1 ( 1679 629 ) ( * 663 ) - NEW met1 ( 1679 629 ) ( 1725 * ) - NEW met1 ( 1725 595 ) ( * 629 ) - NEW met1 ( 1725 595 ) ( 2645 * ) - NEW met1 ( 713 595 ) ( 1725 * ) - NEW met1 ( 5589 595 ) ( 6555 * ) - NEW met2 ( 7751 629 ) ( * 765 ) - NEW met1 ( 7751 765 ) ( 8717 * ) - NEW met1 ( 7475 629 ) ( 7751 * ) - NEW li1 ( 713 663 ) L1M1_PR_MR - NEW li1 ( 7475 663 ) L1M1_PR_MR - NEW li1 ( 6509 663 ) L1M1_PR_MR - NEW li1 ( 5543 663 ) L1M1_PR_MR - NEW li1 ( 4577 663 ) L1M1_PR_MR - NEW li1 ( 3611 663 ) L1M1_PR_MR - NEW li1 ( 2645 663 ) L1M1_PR_MR - NEW li1 ( 1679 663 ) L1M1_PR_MR - NEW met1 ( 7751 629 ) M1M2_PR - NEW met1 ( 7751 765 ) M1M2_PR - NEW li1 ( 8717 765 ) L1M1_PR_MR ; + + ROUTED met1 ( 943 663 ) ( * 697 ) + NEW met1 ( 667 663 ) ( 943 * ) + NEW met1 ( 7107 663 ) ( 7383 * ) + NEW met1 ( 7383 663 ) ( * 697 ) + NEW met1 ( 7383 697 ) ( 7981 * ) + NEW met1 ( 7981 629 ) ( * 697 ) + NEW met1 ( 6463 663 ) ( * 697 ) + NEW met1 ( 6463 697 ) ( 7061 * ) + NEW met1 ( 7061 663 ) ( * 697 ) + NEW met1 ( 7061 663 ) ( 7107 * ) + NEW met1 ( 7981 629 ) ( 8349 * ) + NEW met1 ( 1541 663 ) ( 1587 * ) + NEW met1 ( 1541 663 ) ( * 697 ) + NEW met1 ( 2461 663 ) ( 2507 * ) + NEW met1 ( 2461 663 ) ( * 697 ) + NEW met1 ( 1863 697 ) ( 2461 * ) + NEW met1 ( 1863 663 ) ( * 697 ) + NEW met1 ( 1587 663 ) ( 1863 * ) + NEW met1 ( 3381 663 ) ( 3427 * ) + NEW met1 ( 3381 663 ) ( * 697 ) + NEW met1 ( 2783 697 ) ( 3381 * ) + NEW met1 ( 2783 663 ) ( * 697 ) + NEW met1 ( 2507 663 ) ( 2783 * ) + NEW met1 ( 4301 663 ) ( 4347 * ) + NEW met1 ( 4301 663 ) ( * 697 ) + NEW met1 ( 3703 697 ) ( 4301 * ) + NEW met1 ( 3703 663 ) ( * 697 ) + NEW met1 ( 3427 663 ) ( 3703 * ) + NEW met1 ( 5221 663 ) ( 5267 * ) + NEW met1 ( 5221 663 ) ( * 697 ) + NEW met1 ( 4623 697 ) ( 5221 * ) + NEW met1 ( 4623 663 ) ( * 697 ) + NEW met1 ( 4347 663 ) ( 4623 * ) + NEW met1 ( 6141 663 ) ( 6187 * ) + NEW met1 ( 6141 663 ) ( * 697 ) + NEW met1 ( 5543 697 ) ( 6141 * ) + NEW met1 ( 5543 663 ) ( * 697 ) + NEW met1 ( 5267 663 ) ( 5543 * ) + NEW met1 ( 943 697 ) ( 1541 * ) + NEW met1 ( 6187 663 ) ( 6463 * ) + NEW li1 ( 667 663 ) L1M1_PR_MR + NEW li1 ( 8349 629 ) L1M1_PR_MR + NEW li1 ( 7107 663 ) L1M1_PR_MR + NEW li1 ( 1587 663 ) L1M1_PR_MR + NEW li1 ( 2507 663 ) L1M1_PR_MR + NEW li1 ( 3427 663 ) L1M1_PR_MR + NEW li1 ( 4347 663 ) L1M1_PR_MR + NEW li1 ( 5267 663 ) L1M1_PR_MR + NEW li1 ( 6187 663 ) L1M1_PR_MR ; - storage_2_0_0.we ( storage_2_0_0.gcand X ) ( storage_2_0_0.cg GATE ) + USE SIGNAL - + ROUTED met1 ( 7981 595 ) ( 8625 * ) - NEW li1 ( 7981 595 ) L1M1_PR_MR - NEW li1 ( 8625 595 ) L1M1_PR_MR ; + + ROUTED met1 ( 7613 595 ) ( 8257 * ) + NEW li1 ( 7613 595 ) L1M1_PR_MR + NEW li1 ( 8257 595 ) L1M1_PR_MR ; - storage_3_0_0.bit0.storage ( storage_3_0_0.bit0.obuf0 A ) ( storage_3_0_0.bit0.bit Q ) + USE SIGNAL - + ROUTED met1 ( 575 935 ) ( 621 * ) - NEW met1 ( 575 901 ) ( * 935 ) - NEW li1 ( 621 935 ) L1M1_PR_MR - NEW li1 ( 575 901 ) L1M1_PR_MR ; + + ROUTED met1 ( 529 969 ) ( 575 * ) + NEW li1 ( 575 969 ) L1M1_PR_MR + NEW li1 ( 529 969 ) L1M1_PR_MR ; - storage_3_0_0.bit1.storage ( storage_3_0_0.bit1.obuf0 A ) ( storage_3_0_0.bit1.bit Q ) + USE SIGNAL - + ROUTED met1 ( 1541 935 ) ( 1587 * ) - NEW met1 ( 1541 901 ) ( * 935 ) - NEW li1 ( 1587 935 ) L1M1_PR_MR - NEW li1 ( 1541 901 ) L1M1_PR_MR ; + + ROUTED met1 ( 1449 969 ) ( 1495 * ) + NEW li1 ( 1495 969 ) L1M1_PR_MR + NEW li1 ( 1449 969 ) L1M1_PR_MR ; - storage_3_0_0.bit2.storage ( storage_3_0_0.bit2.obuf0 A ) ( storage_3_0_0.bit2.bit Q ) + USE SIGNAL - + ROUTED met1 ( 2507 935 ) ( 2553 * ) - NEW met1 ( 2507 901 ) ( * 935 ) - NEW li1 ( 2553 935 ) L1M1_PR_MR - NEW li1 ( 2507 901 ) L1M1_PR_MR ; + + ROUTED met1 ( 2369 969 ) ( 2415 * ) + NEW li1 ( 2415 969 ) L1M1_PR_MR + NEW li1 ( 2369 969 ) L1M1_PR_MR ; - storage_3_0_0.bit3.storage ( storage_3_0_0.bit3.obuf0 A ) ( storage_3_0_0.bit3.bit Q ) + USE SIGNAL - + ROUTED met1 ( 3473 935 ) ( 3519 * ) - NEW met1 ( 3473 901 ) ( * 935 ) - NEW li1 ( 3519 935 ) L1M1_PR_MR - NEW li1 ( 3473 901 ) L1M1_PR_MR ; + + ROUTED met1 ( 3289 969 ) ( 3335 * ) + NEW li1 ( 3335 969 ) L1M1_PR_MR + NEW li1 ( 3289 969 ) L1M1_PR_MR ; - storage_3_0_0.bit4.storage ( storage_3_0_0.bit4.obuf0 A ) ( storage_3_0_0.bit4.bit Q ) + USE SIGNAL - + ROUTED met1 ( 4439 935 ) ( 4485 * ) - NEW met1 ( 4439 901 ) ( * 935 ) - NEW li1 ( 4485 935 ) L1M1_PR_MR - NEW li1 ( 4439 901 ) L1M1_PR_MR ; + + ROUTED met1 ( 4209 969 ) ( 4255 * ) + NEW li1 ( 4255 969 ) L1M1_PR_MR + NEW li1 ( 4209 969 ) L1M1_PR_MR ; - storage_3_0_0.bit5.storage ( storage_3_0_0.bit5.obuf0 A ) ( storage_3_0_0.bit5.bit Q ) + USE SIGNAL - + ROUTED met1 ( 5405 935 ) ( 5451 * ) - NEW met1 ( 5405 901 ) ( * 935 ) - NEW li1 ( 5451 935 ) L1M1_PR_MR - NEW li1 ( 5405 901 ) L1M1_PR_MR ; + + ROUTED met1 ( 5129 969 ) ( 5175 * ) + NEW li1 ( 5175 969 ) L1M1_PR_MR + NEW li1 ( 5129 969 ) L1M1_PR_MR ; - storage_3_0_0.bit6.storage ( storage_3_0_0.bit6.obuf0 A ) ( storage_3_0_0.bit6.bit Q ) + USE SIGNAL - + ROUTED met1 ( 6371 935 ) ( 6417 * ) - NEW met1 ( 6371 901 ) ( * 935 ) - NEW li1 ( 6417 935 ) L1M1_PR_MR - NEW li1 ( 6371 901 ) L1M1_PR_MR ; + + ROUTED met1 ( 6049 969 ) ( 6095 * ) + NEW li1 ( 6095 969 ) L1M1_PR_MR + NEW li1 ( 6049 969 ) L1M1_PR_MR ; - storage_3_0_0.bit7.storage ( storage_3_0_0.bit7.obuf0 A ) ( storage_3_0_0.bit7.bit Q ) + USE SIGNAL - + ROUTED met1 ( 7337 935 ) ( 7383 * ) - NEW met1 ( 7337 901 ) ( * 935 ) - NEW li1 ( 7383 935 ) L1M1_PR_MR - NEW li1 ( 7337 901 ) L1M1_PR_MR ; - - storage_3_0_0.gclock ( storage_3_0_0.cg GCLK ) ( storage_3_0_0.bit7.bit GATE ) ( storage_3_0_0.bit6.bit GATE ) ( storage_3_0_0.bit5.bit GATE ) ( storage_3_0_0.bit4.bit GATE ) ( storage_3_0_0.bit3.bit GATE ) ( storage_3_0_0.bit2.bit GATE ) - ( storage_3_0_0.bit1.bit GATE ) ( storage_3_0_0.bit0.bit GATE ) + USE SIGNAL - + ROUTED met1 ( 1035 969 ) ( * 1003 ) - NEW met1 ( 69 1003 ) ( 1035 * ) - NEW met1 ( 69 969 ) ( * 1003 ) - NEW met1 ( 2001 969 ) ( * 1003 ) - NEW met1 ( 2967 969 ) ( * 1003 ) - NEW met1 ( 2001 1003 ) ( 2967 * ) - NEW met1 ( 3933 969 ) ( * 1003 ) - NEW met1 ( 2967 1003 ) ( 3933 * ) - NEW met1 ( 1035 1003 ) ( 2001 * ) - NEW met1 ( 4899 969 ) ( * 1003 ) - NEW met1 ( 5681 935 ) ( 5865 * ) - NEW met2 ( 5681 935 ) ( * 1003 ) - NEW met1 ( 4899 1003 ) ( 5681 * ) - NEW met1 ( 6831 867 ) ( * 935 ) - NEW met1 ( 5865 867 ) ( 6831 * ) - NEW met1 ( 5865 867 ) ( * 935 ) - NEW met1 ( 3933 1003 ) ( 4899 * ) - NEW met1 ( 6831 867 ) ( 8395 * ) - NEW li1 ( 1035 969 ) L1M1_PR_MR - NEW li1 ( 69 969 ) L1M1_PR_MR - NEW li1 ( 2001 969 ) L1M1_PR_MR - NEW li1 ( 2967 969 ) L1M1_PR_MR - NEW li1 ( 3933 969 ) L1M1_PR_MR - NEW li1 ( 4899 969 ) L1M1_PR_MR - NEW li1 ( 5865 935 ) L1M1_PR_MR - NEW met1 ( 5681 935 ) M1M2_PR - NEW met1 ( 5681 1003 ) M1M2_PR - NEW li1 ( 6831 935 ) L1M1_PR_MR - NEW li1 ( 8395 867 ) L1M1_PR_MR ; + + ROUTED met1 ( 6969 969 ) ( 7015 * ) + NEW li1 ( 7015 969 ) L1M1_PR_MR + NEW li1 ( 6969 969 ) L1M1_PR_MR ; + - storage_3_0_0.gclock ( storage_3_0_0.cg GCLK ) ( storage_3_0_0.bit7.bit SLEEP_B ) ( storage_3_0_0.bit6.bit SLEEP_B ) ( storage_3_0_0.bit5.bit SLEEP_B ) ( storage_3_0_0.bit4.bit SLEEP_B ) ( storage_3_0_0.bit3.bit SLEEP_B ) ( storage_3_0_0.bit2.bit SLEEP_B ) + ( storage_3_0_0.bit1.bit SLEEP_B ) ( storage_3_0_0.bit0.bit SLEEP_B ) + USE SIGNAL + + ROUTED met1 ( 6509 935 ) ( 8027 * ) + NEW met1 ( 6509 901 ) ( * 935 ) + NEW met1 ( 5589 901 ) ( * 935 ) + NEW met1 ( 4669 901 ) ( * 935 ) + NEW met1 ( 4669 901 ) ( 5589 * ) + NEW met1 ( 3749 901 ) ( * 935 ) + NEW met1 ( 3749 901 ) ( 4669 * ) + NEW met1 ( 5589 901 ) ( 6509 * ) + NEW met1 ( 621 969 ) ( 989 * ) + NEW met1 ( 621 935 ) ( * 969 ) + NEW met1 ( 69 935 ) ( 621 * ) + NEW met1 ( 1909 901 ) ( * 935 ) + NEW met1 ( 989 901 ) ( 1909 * ) + NEW met2 ( 989 901 ) ( * 969 ) + NEW met1 ( 1909 935 ) ( 2829 * ) + NEW met1 ( 2829 901 ) ( * 935 ) + NEW met1 ( 2829 901 ) ( 3749 * ) + NEW li1 ( 6509 935 ) L1M1_PR_MR + NEW li1 ( 8027 935 ) L1M1_PR_MR + NEW li1 ( 5589 935 ) L1M1_PR_MR + NEW li1 ( 4669 935 ) L1M1_PR_MR + NEW li1 ( 3749 935 ) L1M1_PR_MR + NEW li1 ( 989 969 ) L1M1_PR_MR + NEW li1 ( 69 935 ) L1M1_PR_MR + NEW li1 ( 1909 935 ) L1M1_PR_MR + NEW met1 ( 989 901 ) M1M2_PR + NEW met1 ( 989 969 ) M1M2_PR + NEW li1 ( 2829 935 ) L1M1_PR_MR ; - storage_3_0_0.select0_b ( storage_3_0_0.select_inv_0 Y ) ( storage_3_0_0.bit7.obuf0 TE_B ) ( storage_3_0_0.bit6.obuf0 TE_B ) ( storage_3_0_0.bit5.obuf0 TE_B ) ( storage_3_0_0.bit4.obuf0 TE_B ) ( storage_3_0_0.bit3.obuf0 TE_B ) ( storage_3_0_0.bit2.obuf0 TE_B ) ( storage_3_0_0.bit1.obuf0 TE_B ) ( storage_3_0_0.bit0.obuf0 TE_B ) + USE SIGNAL - + ROUTED met1 ( 713 867 ) ( * 935 ) - NEW met1 ( 7475 901 ) ( * 935 ) - NEW met1 ( 7475 935 ) ( * 1003 ) - NEW met1 ( 3611 867 ) ( * 935 ) - NEW met1 ( 2645 867 ) ( * 935 ) - NEW met1 ( 2645 867 ) ( 3611 * ) - NEW met1 ( 1679 867 ) ( * 935 ) - NEW met1 ( 1679 867 ) ( 2645 * ) - NEW met1 ( 713 867 ) ( 1679 * ) - NEW met1 ( 4577 867 ) ( * 935 ) - NEW met1 ( 5543 867 ) ( * 935 ) - NEW met1 ( 4577 867 ) ( 5543 * ) - NEW met1 ( 6509 969 ) ( * 1003 ) - NEW met1 ( 5819 1003 ) ( 6509 * ) - NEW met2 ( 5819 901 ) ( * 1003 ) - NEW met1 ( 5543 901 ) ( 5819 * ) - NEW met1 ( 3611 867 ) ( 4577 * ) - NEW met1 ( 6509 1003 ) ( 7475 * ) - NEW met1 ( 7475 901 ) ( 8717 * ) - NEW li1 ( 713 935 ) L1M1_PR_MR - NEW li1 ( 7475 935 ) L1M1_PR_MR - NEW li1 ( 3611 935 ) L1M1_PR_MR - NEW li1 ( 2645 935 ) L1M1_PR_MR - NEW li1 ( 1679 935 ) L1M1_PR_MR - NEW li1 ( 4577 935 ) L1M1_PR_MR - NEW li1 ( 5543 935 ) L1M1_PR_MR - NEW li1 ( 6509 969 ) L1M1_PR_MR - NEW met1 ( 5819 1003 ) M1M2_PR - NEW met1 ( 5819 901 ) M1M2_PR - NEW li1 ( 8717 901 ) L1M1_PR_MR ; + + ROUTED met1 ( 7107 969 ) ( * 1003 ) + NEW met1 ( 6785 969 ) ( * 1003 ) + NEW met1 ( 6785 1003 ) ( 7107 * ) + NEW met1 ( 7107 1003 ) ( 8349 * ) + NEW met1 ( 4163 935 ) ( 4347 * ) + NEW met1 ( 4163 935 ) ( * 969 ) + NEW met1 ( 5083 935 ) ( 5267 * ) + NEW met1 ( 5083 935 ) ( * 969 ) + NEW met1 ( 4347 969 ) ( 5083 * ) + NEW met1 ( 4347 935 ) ( * 969 ) + NEW met1 ( 6003 935 ) ( 6187 * ) + NEW met1 ( 6003 935 ) ( * 969 ) + NEW met1 ( 5267 969 ) ( 6003 * ) + NEW met1 ( 5267 935 ) ( * 969 ) + NEW met1 ( 6187 935 ) ( * 969 ) + NEW met1 ( 6187 969 ) ( 6785 * ) + NEW met1 ( 1587 969 ) ( * 1003 ) + NEW met1 ( 1311 1003 ) ( 1587 * ) + NEW met1 ( 1311 935 ) ( * 1003 ) + NEW met1 ( 667 935 ) ( 1311 * ) + NEW met1 ( 2507 969 ) ( * 1003 ) + NEW met1 ( 2323 1003 ) ( 2507 * ) + NEW met1 ( 2323 969 ) ( * 1003 ) + NEW met1 ( 1587 969 ) ( 2323 * ) + NEW met1 ( 3243 935 ) ( 3427 * ) + NEW met1 ( 3243 935 ) ( * 969 ) + NEW met1 ( 2507 969 ) ( 3243 * ) + NEW met1 ( 3427 935 ) ( * 969 ) + NEW met1 ( 3427 969 ) ( 4163 * ) + NEW li1 ( 8349 1003 ) L1M1_PR_MR + NEW li1 ( 7107 969 ) L1M1_PR_MR + NEW li1 ( 4347 935 ) L1M1_PR_MR + NEW li1 ( 5267 935 ) L1M1_PR_MR + NEW li1 ( 6187 935 ) L1M1_PR_MR + NEW li1 ( 1587 969 ) L1M1_PR_MR + NEW li1 ( 667 935 ) L1M1_PR_MR + NEW li1 ( 2507 969 ) L1M1_PR_MR + NEW li1 ( 3427 935 ) L1M1_PR_MR ; - storage_3_0_0.we ( storage_3_0_0.gcand X ) ( storage_3_0_0.cg GATE ) + USE SIGNAL - + ROUTED met1 ( 7981 1003 ) ( 8625 * ) - NEW li1 ( 7981 1003 ) L1M1_PR_MR - NEW li1 ( 8625 1003 ) L1M1_PR_MR ; + + ROUTED met1 ( 7613 1037 ) ( 8257 * ) + NEW li1 ( 7613 1037 ) L1M1_PR_MR + NEW li1 ( 8257 1037 ) L1M1_PR_MR ; - storage_4_0_0.bit0.storage ( storage_4_0_0.bit0.obuf0 A ) ( storage_4_0_0.bit0.bit Q ) + USE SIGNAL - + ROUTED met1 ( 621 1241 ) ( * 1275 ) - NEW met1 ( 575 1275 ) ( 621 * ) - NEW li1 ( 621 1241 ) L1M1_PR_MR - NEW li1 ( 575 1275 ) L1M1_PR_MR ; + + ROUTED met1 ( 529 1207 ) ( 575 * ) + NEW li1 ( 575 1207 ) L1M1_PR_MR + NEW li1 ( 529 1207 ) L1M1_PR_MR ; - storage_4_0_0.bit1.storage ( storage_4_0_0.bit1.obuf0 A ) ( storage_4_0_0.bit1.bit Q ) + USE SIGNAL - + ROUTED met1 ( 1587 1241 ) ( * 1275 ) - NEW met1 ( 1541 1275 ) ( 1587 * ) - NEW li1 ( 1587 1241 ) L1M1_PR_MR - NEW li1 ( 1541 1275 ) L1M1_PR_MR ; + + ROUTED met1 ( 1449 1207 ) ( 1495 * ) + NEW li1 ( 1495 1207 ) L1M1_PR_MR + NEW li1 ( 1449 1207 ) L1M1_PR_MR ; - storage_4_0_0.bit2.storage ( storage_4_0_0.bit2.obuf0 A ) ( storage_4_0_0.bit2.bit Q ) + USE SIGNAL - + ROUTED met1 ( 2553 1241 ) ( * 1275 ) - NEW met1 ( 2507 1275 ) ( 2553 * ) - NEW li1 ( 2553 1241 ) L1M1_PR_MR - NEW li1 ( 2507 1275 ) L1M1_PR_MR ; + + ROUTED met1 ( 2369 1207 ) ( 2415 * ) + NEW li1 ( 2415 1207 ) L1M1_PR_MR + NEW li1 ( 2369 1207 ) L1M1_PR_MR ; - storage_4_0_0.bit3.storage ( storage_4_0_0.bit3.obuf0 A ) ( storage_4_0_0.bit3.bit Q ) + USE SIGNAL - + ROUTED met1 ( 3519 1241 ) ( * 1275 ) - NEW met1 ( 3473 1275 ) ( 3519 * ) - NEW li1 ( 3519 1241 ) L1M1_PR_MR - NEW li1 ( 3473 1275 ) L1M1_PR_MR ; + + ROUTED met1 ( 3289 1207 ) ( 3335 * ) + NEW li1 ( 3335 1207 ) L1M1_PR_MR + NEW li1 ( 3289 1207 ) L1M1_PR_MR ; - storage_4_0_0.bit4.storage ( storage_4_0_0.bit4.obuf0 A ) ( storage_4_0_0.bit4.bit Q ) + USE SIGNAL - + ROUTED met1 ( 4485 1241 ) ( * 1275 ) - NEW met1 ( 4439 1275 ) ( 4485 * ) - NEW li1 ( 4485 1241 ) L1M1_PR_MR - NEW li1 ( 4439 1275 ) L1M1_PR_MR ; + + ROUTED met1 ( 4209 1207 ) ( 4255 * ) + NEW li1 ( 4255 1207 ) L1M1_PR_MR + NEW li1 ( 4209 1207 ) L1M1_PR_MR ; - storage_4_0_0.bit5.storage ( storage_4_0_0.bit5.obuf0 A ) ( storage_4_0_0.bit5.bit Q ) + USE SIGNAL - + ROUTED met1 ( 5451 1241 ) ( * 1275 ) - NEW met1 ( 5405 1275 ) ( 5451 * ) - NEW li1 ( 5451 1241 ) L1M1_PR_MR - NEW li1 ( 5405 1275 ) L1M1_PR_MR ; + + ROUTED met1 ( 5129 1207 ) ( 5175 * ) + NEW li1 ( 5175 1207 ) L1M1_PR_MR + NEW li1 ( 5129 1207 ) L1M1_PR_MR ; - storage_4_0_0.bit6.storage ( storage_4_0_0.bit6.obuf0 A ) ( storage_4_0_0.bit6.bit Q ) + USE SIGNAL - + ROUTED met1 ( 6417 1241 ) ( * 1275 ) - NEW met1 ( 6371 1275 ) ( 6417 * ) - NEW li1 ( 6417 1241 ) L1M1_PR_MR - NEW li1 ( 6371 1275 ) L1M1_PR_MR ; + + ROUTED met1 ( 6049 1207 ) ( 6095 * ) + NEW li1 ( 6095 1207 ) L1M1_PR_MR + NEW li1 ( 6049 1207 ) L1M1_PR_MR ; - storage_4_0_0.bit7.storage ( storage_4_0_0.bit7.obuf0 A ) ( storage_4_0_0.bit7.bit Q ) + USE SIGNAL - + ROUTED met1 ( 7383 1241 ) ( * 1275 ) - NEW met1 ( 7337 1275 ) ( 7383 * ) - NEW li1 ( 7383 1241 ) L1M1_PR_MR - NEW li1 ( 7337 1275 ) L1M1_PR_MR ; - - storage_4_0_0.gclock ( storage_4_0_0.cg GCLK ) ( storage_4_0_0.bit7.bit GATE ) ( storage_4_0_0.bit6.bit GATE ) ( storage_4_0_0.bit5.bit GATE ) ( storage_4_0_0.bit4.bit GATE ) ( storage_4_0_0.bit3.bit GATE ) ( storage_4_0_0.bit2.bit GATE ) - ( storage_4_0_0.bit1.bit GATE ) ( storage_4_0_0.bit0.bit GATE ) + USE SIGNAL - + ROUTED met1 ( 1035 1173 ) ( * 1207 ) - NEW met1 ( 69 1173 ) ( 1035 * ) - NEW met1 ( 69 1173 ) ( * 1207 ) - NEW met1 ( 6831 1173 ) ( * 1207 ) - NEW met1 ( 2001 1173 ) ( * 1207 ) - NEW met1 ( 2967 1173 ) ( * 1207 ) - NEW met1 ( 2001 1173 ) ( 2967 * ) - NEW met1 ( 3933 1173 ) ( * 1207 ) - NEW met1 ( 2967 1173 ) ( 3933 * ) - NEW met1 ( 4899 1173 ) ( * 1207 ) - NEW met1 ( 3933 1173 ) ( 4899 * ) - NEW met1 ( 5865 1173 ) ( * 1207 ) - NEW met1 ( 4899 1173 ) ( 5865 * ) - NEW met1 ( 1035 1173 ) ( 2001 * ) - NEW met1 ( 5865 1173 ) ( 6831 * ) - NEW met1 ( 7659 1173 ) ( * 1275 ) - NEW met1 ( 7659 1275 ) ( 8395 * ) - NEW met1 ( 6831 1173 ) ( 7659 * ) - NEW li1 ( 1035 1207 ) L1M1_PR_MR - NEW li1 ( 69 1207 ) L1M1_PR_MR - NEW li1 ( 6831 1207 ) L1M1_PR_MR - NEW li1 ( 2001 1207 ) L1M1_PR_MR - NEW li1 ( 2967 1207 ) L1M1_PR_MR - NEW li1 ( 3933 1207 ) L1M1_PR_MR - NEW li1 ( 4899 1207 ) L1M1_PR_MR - NEW li1 ( 5865 1207 ) L1M1_PR_MR - NEW li1 ( 8395 1275 ) L1M1_PR_MR ; + + ROUTED met1 ( 6969 1207 ) ( 7015 * ) + NEW li1 ( 7015 1207 ) L1M1_PR_MR + NEW li1 ( 6969 1207 ) L1M1_PR_MR ; + - storage_4_0_0.gclock ( storage_4_0_0.cg GCLK ) ( storage_4_0_0.bit7.bit SLEEP_B ) ( storage_4_0_0.bit6.bit SLEEP_B ) ( storage_4_0_0.bit5.bit SLEEP_B ) ( storage_4_0_0.bit4.bit SLEEP_B ) ( storage_4_0_0.bit3.bit SLEEP_B ) ( storage_4_0_0.bit2.bit SLEEP_B ) + ( storage_4_0_0.bit1.bit SLEEP_B ) ( storage_4_0_0.bit0.bit SLEEP_B ) + USE SIGNAL + + ROUTED met1 ( 69 1241 ) ( 989 * ) + NEW met1 ( 6509 1241 ) ( 8027 * ) + NEW met1 ( 4669 1241 ) ( 5589 * ) + NEW met1 ( 3749 1241 ) ( 4669 * ) + NEW met1 ( 2829 1241 ) ( 3749 * ) + NEW met1 ( 1909 1241 ) ( 2829 * ) + NEW met1 ( 989 1241 ) ( 1909 * ) + NEW met1 ( 5589 1241 ) ( 6509 * ) + NEW li1 ( 989 1241 ) L1M1_PR_MR + NEW li1 ( 69 1241 ) L1M1_PR_MR + NEW li1 ( 6509 1241 ) L1M1_PR_MR + NEW li1 ( 8027 1241 ) L1M1_PR_MR + NEW li1 ( 5589 1241 ) L1M1_PR_MR + NEW li1 ( 4669 1241 ) L1M1_PR_MR + NEW li1 ( 3749 1241 ) L1M1_PR_MR + NEW li1 ( 2829 1241 ) L1M1_PR_MR + NEW li1 ( 1909 1241 ) L1M1_PR_MR ; - storage_4_0_0.select0_b ( storage_4_0_0.select_inv_0 Y ) ( storage_4_0_0.bit7.obuf0 TE_B ) ( storage_4_0_0.bit6.obuf0 TE_B ) ( storage_4_0_0.bit5.obuf0 TE_B ) ( storage_4_0_0.bit4.obuf0 TE_B ) ( storage_4_0_0.bit3.obuf0 TE_B ) ( storage_4_0_0.bit2.obuf0 TE_B ) ( storage_4_0_0.bit1.obuf0 TE_B ) ( storage_4_0_0.bit0.obuf0 TE_B ) + USE SIGNAL - + ROUTED met1 ( 713 1241 ) ( 989 * ) - NEW met1 ( 989 1241 ) ( * 1309 ) - NEW met1 ( 7475 1241 ) ( * 1275 ) - NEW met1 ( 6509 1241 ) ( 6785 * ) - NEW met1 ( 6785 1241 ) ( * 1309 ) - NEW met1 ( 6785 1309 ) ( 7475 * ) - NEW met1 ( 7475 1275 ) ( * 1309 ) - NEW met1 ( 6509 1241 ) ( * 1309 ) - NEW met1 ( 5543 1241 ) ( 5773 * ) - NEW met1 ( 5773 1241 ) ( * 1309 ) - NEW met1 ( 4577 1241 ) ( 4853 * ) - NEW met1 ( 4853 1241 ) ( * 1309 ) - NEW met1 ( 4853 1309 ) ( 5543 * ) - NEW met1 ( 5543 1241 ) ( * 1309 ) - NEW met1 ( 3611 1241 ) ( 3841 * ) - NEW met1 ( 3841 1241 ) ( * 1309 ) - NEW met1 ( 3841 1309 ) ( 4577 * ) - NEW met1 ( 4577 1241 ) ( * 1309 ) - NEW met1 ( 2645 1241 ) ( 2921 * ) - NEW met1 ( 2921 1241 ) ( * 1309 ) - NEW met1 ( 2921 1309 ) ( 3611 * ) - NEW met1 ( 3611 1241 ) ( * 1309 ) - NEW met1 ( 1679 1241 ) ( 1909 * ) - NEW met1 ( 1909 1241 ) ( * 1309 ) - NEW met1 ( 1909 1309 ) ( 2645 * ) - NEW met1 ( 2645 1241 ) ( * 1309 ) - NEW met1 ( 1679 1241 ) ( * 1309 ) - NEW met1 ( 989 1309 ) ( 1679 * ) - NEW met1 ( 5773 1309 ) ( 6509 * ) - NEW met1 ( 7475 1275 ) ( 7590 * ) - NEW met1 ( 7590 1275 ) ( * 1309 ) - NEW met1 ( 7590 1309 ) ( 8717 * ) - NEW li1 ( 713 1241 ) L1M1_PR_MR - NEW li1 ( 7475 1241 ) L1M1_PR_MR - NEW li1 ( 6509 1241 ) L1M1_PR_MR - NEW li1 ( 5543 1241 ) L1M1_PR_MR - NEW li1 ( 4577 1241 ) L1M1_PR_MR - NEW li1 ( 3611 1241 ) L1M1_PR_MR - NEW li1 ( 2645 1241 ) L1M1_PR_MR - NEW li1 ( 1679 1241 ) L1M1_PR_MR - NEW li1 ( 8717 1309 ) L1M1_PR_MR ; + + ROUTED met1 ( 7107 1173 ) ( * 1207 ) + NEW met1 ( 6785 1173 ) ( * 1207 ) + NEW met1 ( 6785 1173 ) ( 7107 * ) + NEW met1 ( 7107 1173 ) ( 8349 * ) + NEW met1 ( 667 1207 ) ( 1380 * ) + NEW met1 ( 1587 1173 ) ( * 1207 ) + NEW met1 ( 1380 1173 ) ( 1587 * ) + NEW met1 ( 1380 1173 ) ( * 1207 ) + NEW met1 ( 2507 1173 ) ( * 1207 ) + NEW met1 ( 2323 1173 ) ( 2507 * ) + NEW met1 ( 2323 1173 ) ( * 1207 ) + NEW met1 ( 1587 1207 ) ( 2323 * ) + NEW met1 ( 3427 1173 ) ( * 1207 ) + NEW met1 ( 3243 1173 ) ( 3427 * ) + NEW met1 ( 3243 1173 ) ( * 1207 ) + NEW met1 ( 2507 1207 ) ( 3243 * ) + NEW met1 ( 4347 1173 ) ( * 1207 ) + NEW met1 ( 4163 1173 ) ( 4347 * ) + NEW met1 ( 4163 1173 ) ( * 1207 ) + NEW met1 ( 3427 1207 ) ( 4163 * ) + NEW met1 ( 5267 1173 ) ( * 1207 ) + NEW met1 ( 5083 1173 ) ( 5267 * ) + NEW met1 ( 5083 1173 ) ( * 1207 ) + NEW met1 ( 4347 1207 ) ( 5083 * ) + NEW met1 ( 6187 1173 ) ( * 1207 ) + NEW met1 ( 6003 1173 ) ( 6187 * ) + NEW met1 ( 6003 1173 ) ( * 1207 ) + NEW met1 ( 5267 1207 ) ( 6003 * ) + NEW met1 ( 6187 1207 ) ( 6785 * ) + NEW li1 ( 667 1207 ) L1M1_PR_MR + NEW li1 ( 8349 1173 ) L1M1_PR_MR + NEW li1 ( 7107 1207 ) L1M1_PR_MR + NEW li1 ( 1587 1207 ) L1M1_PR_MR + NEW li1 ( 2507 1207 ) L1M1_PR_MR + NEW li1 ( 3427 1207 ) L1M1_PR_MR + NEW li1 ( 4347 1207 ) L1M1_PR_MR + NEW li1 ( 5267 1207 ) L1M1_PR_MR + NEW li1 ( 6187 1207 ) L1M1_PR_MR ; - storage_4_0_0.we ( storage_4_0_0.gcand X ) ( storage_4_0_0.cg GATE ) + USE SIGNAL - + ROUTED met1 ( 7981 1139 ) ( 8625 * ) - NEW li1 ( 7981 1139 ) L1M1_PR_MR - NEW li1 ( 8625 1139 ) L1M1_PR_MR ; + + ROUTED met1 ( 7613 1139 ) ( 8257 * ) + NEW li1 ( 7613 1139 ) L1M1_PR_MR + NEW li1 ( 8257 1139 ) L1M1_PR_MR ; - storage_5_0_0.bit0.storage ( storage_5_0_0.bit0.obuf0 A ) ( storage_5_0_0.bit0.bit Q ) + USE SIGNAL - + ROUTED met1 ( 575 1479 ) ( 621 * ) - NEW met1 ( 575 1445 ) ( * 1479 ) - NEW li1 ( 621 1479 ) L1M1_PR_MR - NEW li1 ( 575 1445 ) L1M1_PR_MR ; + + ROUTED met1 ( 529 1513 ) ( 575 * ) + NEW li1 ( 575 1513 ) L1M1_PR_MR + NEW li1 ( 529 1513 ) L1M1_PR_MR ; - storage_5_0_0.bit1.storage ( storage_5_0_0.bit1.obuf0 A ) ( storage_5_0_0.bit1.bit Q ) + USE SIGNAL - + ROUTED met1 ( 1541 1479 ) ( 1587 * ) - NEW met1 ( 1541 1445 ) ( * 1479 ) - NEW li1 ( 1587 1479 ) L1M1_PR_MR - NEW li1 ( 1541 1445 ) L1M1_PR_MR ; + + ROUTED met1 ( 1449 1513 ) ( 1495 * ) + NEW li1 ( 1495 1513 ) L1M1_PR_MR + NEW li1 ( 1449 1513 ) L1M1_PR_MR ; - storage_5_0_0.bit2.storage ( storage_5_0_0.bit2.obuf0 A ) ( storage_5_0_0.bit2.bit Q ) + USE SIGNAL - + ROUTED met1 ( 2507 1479 ) ( 2553 * ) - NEW met1 ( 2507 1445 ) ( * 1479 ) - NEW li1 ( 2553 1479 ) L1M1_PR_MR - NEW li1 ( 2507 1445 ) L1M1_PR_MR ; + + ROUTED met1 ( 2369 1513 ) ( 2415 * ) + NEW li1 ( 2415 1513 ) L1M1_PR_MR + NEW li1 ( 2369 1513 ) L1M1_PR_MR ; - storage_5_0_0.bit3.storage ( storage_5_0_0.bit3.obuf0 A ) ( storage_5_0_0.bit3.bit Q ) + USE SIGNAL - + ROUTED met1 ( 3473 1479 ) ( 3519 * ) - NEW met1 ( 3473 1445 ) ( * 1479 ) - NEW li1 ( 3519 1479 ) L1M1_PR_MR - NEW li1 ( 3473 1445 ) L1M1_PR_MR ; + + ROUTED met1 ( 3289 1513 ) ( 3335 * ) + NEW li1 ( 3335 1513 ) L1M1_PR_MR + NEW li1 ( 3289 1513 ) L1M1_PR_MR ; - storage_5_0_0.bit4.storage ( storage_5_0_0.bit4.obuf0 A ) ( storage_5_0_0.bit4.bit Q ) + USE SIGNAL - + ROUTED met1 ( 4439 1479 ) ( 4485 * ) - NEW met1 ( 4439 1445 ) ( * 1479 ) - NEW li1 ( 4485 1479 ) L1M1_PR_MR - NEW li1 ( 4439 1445 ) L1M1_PR_MR ; + + ROUTED met1 ( 4209 1513 ) ( 4255 * ) + NEW li1 ( 4255 1513 ) L1M1_PR_MR + NEW li1 ( 4209 1513 ) L1M1_PR_MR ; - storage_5_0_0.bit5.storage ( storage_5_0_0.bit5.obuf0 A ) ( storage_5_0_0.bit5.bit Q ) + USE SIGNAL - + ROUTED met1 ( 5405 1479 ) ( 5451 * ) - NEW met1 ( 5405 1445 ) ( * 1479 ) - NEW li1 ( 5451 1479 ) L1M1_PR_MR - NEW li1 ( 5405 1445 ) L1M1_PR_MR ; + + ROUTED met1 ( 5129 1513 ) ( 5175 * ) + NEW li1 ( 5175 1513 ) L1M1_PR_MR + NEW li1 ( 5129 1513 ) L1M1_PR_MR ; - storage_5_0_0.bit6.storage ( storage_5_0_0.bit6.obuf0 A ) ( storage_5_0_0.bit6.bit Q ) + USE SIGNAL - + ROUTED met1 ( 6371 1479 ) ( 6417 * ) - NEW met1 ( 6371 1445 ) ( * 1479 ) - NEW li1 ( 6417 1479 ) L1M1_PR_MR - NEW li1 ( 6371 1445 ) L1M1_PR_MR ; + + ROUTED met1 ( 6049 1513 ) ( 6095 * ) + NEW li1 ( 6095 1513 ) L1M1_PR_MR + NEW li1 ( 6049 1513 ) L1M1_PR_MR ; - storage_5_0_0.bit7.storage ( storage_5_0_0.bit7.obuf0 A ) ( storage_5_0_0.bit7.bit Q ) + USE SIGNAL - + ROUTED met1 ( 7337 1479 ) ( 7383 * ) - NEW met1 ( 7337 1445 ) ( * 1479 ) - NEW li1 ( 7383 1479 ) L1M1_PR_MR - NEW li1 ( 7337 1445 ) L1M1_PR_MR ; - - storage_5_0_0.gclock ( storage_5_0_0.cg GCLK ) ( storage_5_0_0.bit7.bit GATE ) ( storage_5_0_0.bit6.bit GATE ) ( storage_5_0_0.bit5.bit GATE ) ( storage_5_0_0.bit4.bit GATE ) ( storage_5_0_0.bit3.bit GATE ) ( storage_5_0_0.bit2.bit GATE ) - ( storage_5_0_0.bit1.bit GATE ) ( storage_5_0_0.bit0.bit GATE ) + USE SIGNAL - + ROUTED met1 ( 1035 1513 ) ( * 1547 ) - NEW met1 ( 69 1547 ) ( 1035 * ) - NEW met1 ( 69 1513 ) ( * 1547 ) - NEW met1 ( 2001 1513 ) ( * 1547 ) - NEW met1 ( 2967 1513 ) ( * 1547 ) - NEW met1 ( 2001 1547 ) ( 2967 * ) - NEW met1 ( 3933 1513 ) ( * 1547 ) - NEW met1 ( 2967 1547 ) ( 3933 * ) - NEW met1 ( 1035 1547 ) ( 2001 * ) - NEW met1 ( 4899 1513 ) ( * 1547 ) - NEW met1 ( 5681 1479 ) ( 5865 * ) - NEW met2 ( 5681 1479 ) ( * 1547 ) - NEW met1 ( 4899 1547 ) ( 5681 * ) - NEW met1 ( 6831 1411 ) ( * 1479 ) - NEW met1 ( 5865 1411 ) ( 6831 * ) - NEW met1 ( 5865 1411 ) ( * 1479 ) - NEW met1 ( 3933 1547 ) ( 4899 * ) - NEW met1 ( 6831 1411 ) ( 8395 * ) - NEW li1 ( 1035 1513 ) L1M1_PR_MR - NEW li1 ( 69 1513 ) L1M1_PR_MR - NEW li1 ( 2001 1513 ) L1M1_PR_MR - NEW li1 ( 2967 1513 ) L1M1_PR_MR - NEW li1 ( 3933 1513 ) L1M1_PR_MR - NEW li1 ( 4899 1513 ) L1M1_PR_MR - NEW li1 ( 5865 1479 ) L1M1_PR_MR - NEW met1 ( 5681 1479 ) M1M2_PR - NEW met1 ( 5681 1547 ) M1M2_PR - NEW li1 ( 6831 1479 ) L1M1_PR_MR - NEW li1 ( 8395 1411 ) L1M1_PR_MR ; + + ROUTED met1 ( 6969 1513 ) ( 7015 * ) + NEW li1 ( 7015 1513 ) L1M1_PR_MR + NEW li1 ( 6969 1513 ) L1M1_PR_MR ; + - storage_5_0_0.gclock ( storage_5_0_0.cg GCLK ) ( storage_5_0_0.bit7.bit SLEEP_B ) ( storage_5_0_0.bit6.bit SLEEP_B ) ( storage_5_0_0.bit5.bit SLEEP_B ) ( storage_5_0_0.bit4.bit SLEEP_B ) ( storage_5_0_0.bit3.bit SLEEP_B ) ( storage_5_0_0.bit2.bit SLEEP_B ) + ( storage_5_0_0.bit1.bit SLEEP_B ) ( storage_5_0_0.bit0.bit SLEEP_B ) + USE SIGNAL + + ROUTED met1 ( 6509 1445 ) ( * 1479 ) + NEW met1 ( 6509 1445 ) ( 8027 * ) + NEW met1 ( 5589 1445 ) ( * 1479 ) + NEW met1 ( 4669 1445 ) ( * 1479 ) + NEW met1 ( 4669 1445 ) ( 5589 * ) + NEW met1 ( 3749 1445 ) ( * 1479 ) + NEW met1 ( 3749 1445 ) ( 4669 * ) + NEW met1 ( 5589 1445 ) ( 6509 * ) + NEW met1 ( 621 1513 ) ( 989 * ) + NEW met1 ( 621 1479 ) ( * 1513 ) + NEW met1 ( 69 1479 ) ( 621 * ) + NEW met1 ( 1909 1445 ) ( * 1479 ) + NEW met1 ( 989 1445 ) ( 1909 * ) + NEW met2 ( 989 1445 ) ( * 1513 ) + NEW met1 ( 1909 1479 ) ( 2829 * ) + NEW met1 ( 2829 1445 ) ( * 1479 ) + NEW met1 ( 2829 1445 ) ( 3749 * ) + NEW li1 ( 6509 1479 ) L1M1_PR_MR + NEW li1 ( 8027 1445 ) L1M1_PR_MR + NEW li1 ( 5589 1479 ) L1M1_PR_MR + NEW li1 ( 4669 1479 ) L1M1_PR_MR + NEW li1 ( 3749 1479 ) L1M1_PR_MR + NEW li1 ( 989 1513 ) L1M1_PR_MR + NEW li1 ( 69 1479 ) L1M1_PR_MR + NEW li1 ( 1909 1479 ) L1M1_PR_MR + NEW met1 ( 989 1445 ) M1M2_PR + NEW met1 ( 989 1513 ) M1M2_PR + NEW li1 ( 2829 1479 ) L1M1_PR_MR ; - storage_5_0_0.select0_b ( storage_5_0_0.select_inv_0 Y ) ( storage_5_0_0.bit7.obuf0 TE_B ) ( storage_5_0_0.bit6.obuf0 TE_B ) ( storage_5_0_0.bit5.obuf0 TE_B ) ( storage_5_0_0.bit4.obuf0 TE_B ) ( storage_5_0_0.bit3.obuf0 TE_B ) ( storage_5_0_0.bit2.obuf0 TE_B ) ( storage_5_0_0.bit1.obuf0 TE_B ) ( storage_5_0_0.bit0.obuf0 TE_B ) + USE SIGNAL - + ROUTED met1 ( 713 1411 ) ( * 1479 ) - NEW met1 ( 7475 1513 ) ( * 1547 ) - NEW met1 ( 3611 1411 ) ( * 1479 ) - NEW met1 ( 2645 1411 ) ( * 1479 ) - NEW met1 ( 2645 1411 ) ( 3611 * ) - NEW met1 ( 1679 1411 ) ( * 1479 ) - NEW met1 ( 1679 1411 ) ( 2645 * ) - NEW met1 ( 713 1411 ) ( 1679 * ) - NEW met1 ( 4577 1411 ) ( * 1479 ) - NEW met1 ( 5543 1411 ) ( * 1479 ) - NEW met1 ( 4577 1411 ) ( 5543 * ) - NEW met1 ( 6509 1513 ) ( * 1547 ) - NEW met1 ( 5819 1547 ) ( 6509 * ) - NEW met2 ( 5819 1445 ) ( * 1547 ) - NEW met1 ( 5543 1445 ) ( 5819 * ) - NEW met1 ( 3611 1411 ) ( 4577 * ) - NEW met1 ( 6509 1547 ) ( 7475 * ) - NEW met1 ( 7751 1547 ) ( * 1581 ) - NEW met1 ( 7751 1581 ) ( 7843 * ) - NEW met1 ( 7843 1547 ) ( * 1581 ) - NEW met1 ( 7843 1547 ) ( 8717 * ) - NEW met1 ( 7475 1547 ) ( 7751 * ) - NEW li1 ( 713 1479 ) L1M1_PR_MR - NEW li1 ( 7475 1513 ) L1M1_PR_MR - NEW li1 ( 3611 1479 ) L1M1_PR_MR - NEW li1 ( 2645 1479 ) L1M1_PR_MR - NEW li1 ( 1679 1479 ) L1M1_PR_MR - NEW li1 ( 4577 1479 ) L1M1_PR_MR - NEW li1 ( 5543 1479 ) L1M1_PR_MR - NEW li1 ( 6509 1513 ) L1M1_PR_MR - NEW met1 ( 5819 1547 ) M1M2_PR - NEW met1 ( 5819 1445 ) M1M2_PR - NEW li1 ( 8717 1547 ) L1M1_PR_MR ; + + ROUTED met1 ( 7107 1513 ) ( * 1547 ) + NEW met1 ( 7107 1547 ) ( 8349 * ) + NEW met1 ( 6785 1513 ) ( * 1547 ) + NEW met1 ( 6785 1547 ) ( 7107 * ) + NEW met1 ( 4163 1479 ) ( 4347 * ) + NEW met1 ( 4163 1479 ) ( * 1513 ) + NEW met1 ( 5083 1479 ) ( 5267 * ) + NEW met1 ( 5083 1479 ) ( * 1513 ) + NEW met1 ( 4347 1513 ) ( 5083 * ) + NEW met1 ( 4347 1479 ) ( * 1513 ) + NEW met1 ( 6003 1479 ) ( 6187 * ) + NEW met1 ( 6003 1479 ) ( * 1513 ) + NEW met1 ( 5267 1513 ) ( 6003 * ) + NEW met1 ( 5267 1479 ) ( * 1513 ) + NEW met1 ( 6187 1479 ) ( * 1513 ) + NEW met1 ( 6187 1513 ) ( 6785 * ) + NEW met1 ( 1587 1513 ) ( * 1547 ) + NEW met1 ( 1311 1547 ) ( 1587 * ) + NEW met1 ( 1311 1479 ) ( * 1547 ) + NEW met1 ( 667 1479 ) ( 1311 * ) + NEW met1 ( 2507 1513 ) ( * 1547 ) + NEW met1 ( 2323 1547 ) ( 2507 * ) + NEW met1 ( 2323 1513 ) ( * 1547 ) + NEW met1 ( 1587 1513 ) ( 2323 * ) + NEW met1 ( 3243 1479 ) ( 3427 * ) + NEW met1 ( 3243 1479 ) ( * 1513 ) + NEW met1 ( 2507 1513 ) ( 3243 * ) + NEW met1 ( 3427 1479 ) ( * 1513 ) + NEW met1 ( 3427 1513 ) ( 4163 * ) + NEW li1 ( 7107 1513 ) L1M1_PR_MR + NEW li1 ( 8349 1547 ) L1M1_PR_MR + NEW li1 ( 4347 1479 ) L1M1_PR_MR + NEW li1 ( 5267 1479 ) L1M1_PR_MR + NEW li1 ( 6187 1479 ) L1M1_PR_MR + NEW li1 ( 1587 1513 ) L1M1_PR_MR + NEW li1 ( 667 1479 ) L1M1_PR_MR + NEW li1 ( 2507 1513 ) L1M1_PR_MR + NEW li1 ( 3427 1479 ) L1M1_PR_MR ; - storage_5_0_0.we ( storage_5_0_0.gcand X ) ( storage_5_0_0.cg GATE ) + USE SIGNAL - + ROUTED met1 ( 7981 1581 ) ( 8625 * ) - NEW li1 ( 7981 1581 ) L1M1_PR_MR - NEW li1 ( 8625 1581 ) L1M1_PR_MR ; + + ROUTED met1 ( 7613 1581 ) ( 8257 * ) + NEW li1 ( 7613 1581 ) L1M1_PR_MR + NEW li1 ( 8257 1581 ) L1M1_PR_MR ; - storage_6_0_0.bit0.storage ( storage_6_0_0.bit0.obuf0 A ) ( storage_6_0_0.bit0.bit Q ) + USE SIGNAL - + ROUTED met1 ( 621 1785 ) ( * 1819 ) - NEW met1 ( 575 1819 ) ( 621 * ) - NEW li1 ( 621 1785 ) L1M1_PR_MR - NEW li1 ( 575 1819 ) L1M1_PR_MR ; + + ROUTED met1 ( 529 1751 ) ( 575 * ) + NEW li1 ( 575 1751 ) L1M1_PR_MR + NEW li1 ( 529 1751 ) L1M1_PR_MR ; - storage_6_0_0.bit1.storage ( storage_6_0_0.bit1.obuf0 A ) ( storage_6_0_0.bit1.bit Q ) + USE SIGNAL - + ROUTED met1 ( 1587 1785 ) ( * 1819 ) - NEW met1 ( 1541 1819 ) ( 1587 * ) - NEW li1 ( 1587 1785 ) L1M1_PR_MR - NEW li1 ( 1541 1819 ) L1M1_PR_MR ; + + ROUTED met1 ( 1449 1751 ) ( 1495 * ) + NEW li1 ( 1495 1751 ) L1M1_PR_MR + NEW li1 ( 1449 1751 ) L1M1_PR_MR ; - storage_6_0_0.bit2.storage ( storage_6_0_0.bit2.obuf0 A ) ( storage_6_0_0.bit2.bit Q ) + USE SIGNAL - + ROUTED met1 ( 2553 1785 ) ( * 1819 ) - NEW met1 ( 2507 1819 ) ( 2553 * ) - NEW li1 ( 2553 1785 ) L1M1_PR_MR - NEW li1 ( 2507 1819 ) L1M1_PR_MR ; + + ROUTED met1 ( 2369 1751 ) ( 2415 * ) + NEW li1 ( 2415 1751 ) L1M1_PR_MR + NEW li1 ( 2369 1751 ) L1M1_PR_MR ; - storage_6_0_0.bit3.storage ( storage_6_0_0.bit3.obuf0 A ) ( storage_6_0_0.bit3.bit Q ) + USE SIGNAL - + ROUTED met1 ( 3519 1785 ) ( * 1819 ) - NEW met1 ( 3473 1819 ) ( 3519 * ) - NEW li1 ( 3519 1785 ) L1M1_PR_MR - NEW li1 ( 3473 1819 ) L1M1_PR_MR ; + + ROUTED met1 ( 3289 1751 ) ( 3335 * ) + NEW li1 ( 3335 1751 ) L1M1_PR_MR + NEW li1 ( 3289 1751 ) L1M1_PR_MR ; - storage_6_0_0.bit4.storage ( storage_6_0_0.bit4.obuf0 A ) ( storage_6_0_0.bit4.bit Q ) + USE SIGNAL - + ROUTED met1 ( 4485 1785 ) ( * 1819 ) - NEW met1 ( 4439 1819 ) ( 4485 * ) - NEW li1 ( 4485 1785 ) L1M1_PR_MR - NEW li1 ( 4439 1819 ) L1M1_PR_MR ; + + ROUTED met1 ( 4209 1751 ) ( 4255 * ) + NEW li1 ( 4255 1751 ) L1M1_PR_MR + NEW li1 ( 4209 1751 ) L1M1_PR_MR ; - storage_6_0_0.bit5.storage ( storage_6_0_0.bit5.obuf0 A ) ( storage_6_0_0.bit5.bit Q ) + USE SIGNAL - + ROUTED met1 ( 5451 1785 ) ( * 1819 ) - NEW met1 ( 5405 1819 ) ( 5451 * ) - NEW li1 ( 5451 1785 ) L1M1_PR_MR - NEW li1 ( 5405 1819 ) L1M1_PR_MR ; + + ROUTED met1 ( 5129 1751 ) ( 5175 * ) + NEW li1 ( 5175 1751 ) L1M1_PR_MR + NEW li1 ( 5129 1751 ) L1M1_PR_MR ; - storage_6_0_0.bit6.storage ( storage_6_0_0.bit6.obuf0 A ) ( storage_6_0_0.bit6.bit Q ) + USE SIGNAL - + ROUTED met1 ( 6417 1785 ) ( * 1819 ) - NEW met1 ( 6371 1819 ) ( 6417 * ) - NEW li1 ( 6417 1785 ) L1M1_PR_MR - NEW li1 ( 6371 1819 ) L1M1_PR_MR ; + + ROUTED met1 ( 6049 1751 ) ( 6095 * ) + NEW li1 ( 6095 1751 ) L1M1_PR_MR + NEW li1 ( 6049 1751 ) L1M1_PR_MR ; - storage_6_0_0.bit7.storage ( storage_6_0_0.bit7.obuf0 A ) ( storage_6_0_0.bit7.bit Q ) + USE SIGNAL - + ROUTED met1 ( 7383 1785 ) ( * 1819 ) - NEW met1 ( 7337 1819 ) ( 7383 * ) - NEW li1 ( 7383 1785 ) L1M1_PR_MR - NEW li1 ( 7337 1819 ) L1M1_PR_MR ; - - storage_6_0_0.gclock ( storage_6_0_0.cg GCLK ) ( storage_6_0_0.bit7.bit GATE ) ( storage_6_0_0.bit6.bit GATE ) ( storage_6_0_0.bit5.bit GATE ) ( storage_6_0_0.bit4.bit GATE ) ( storage_6_0_0.bit3.bit GATE ) ( storage_6_0_0.bit2.bit GATE ) - ( storage_6_0_0.bit1.bit GATE ) ( storage_6_0_0.bit0.bit GATE ) + USE SIGNAL - + ROUTED met1 ( 1035 1717 ) ( * 1751 ) - NEW met1 ( 69 1717 ) ( 1035 * ) - NEW met1 ( 69 1717 ) ( * 1751 ) - NEW met1 ( 6831 1717 ) ( * 1751 ) - NEW met1 ( 2001 1717 ) ( * 1751 ) - NEW met1 ( 2967 1717 ) ( * 1751 ) - NEW met1 ( 2001 1717 ) ( 2967 * ) - NEW met1 ( 3933 1717 ) ( * 1751 ) - NEW met1 ( 2967 1717 ) ( 3933 * ) - NEW met1 ( 4899 1717 ) ( * 1751 ) - NEW met1 ( 3933 1717 ) ( 4899 * ) - NEW met1 ( 5865 1717 ) ( * 1751 ) - NEW met1 ( 4899 1717 ) ( 5865 * ) - NEW met1 ( 1035 1717 ) ( 2001 * ) - NEW met1 ( 5865 1717 ) ( 6831 * ) - NEW met1 ( 7659 1717 ) ( * 1819 ) - NEW met1 ( 7659 1819 ) ( 8395 * ) - NEW met1 ( 6831 1717 ) ( 7659 * ) - NEW li1 ( 1035 1751 ) L1M1_PR_MR - NEW li1 ( 69 1751 ) L1M1_PR_MR - NEW li1 ( 6831 1751 ) L1M1_PR_MR - NEW li1 ( 2001 1751 ) L1M1_PR_MR - NEW li1 ( 2967 1751 ) L1M1_PR_MR - NEW li1 ( 3933 1751 ) L1M1_PR_MR - NEW li1 ( 4899 1751 ) L1M1_PR_MR - NEW li1 ( 5865 1751 ) L1M1_PR_MR - NEW li1 ( 8395 1819 ) L1M1_PR_MR ; - - storage_6_0_0.select0_b ( storage_6_0_0.select_inv_0 Y ) ( storage_6_0_0.bit7.obuf0 TE_B ) ( storage_6_0_0.bit6.obuf0 TE_B ) ( storage_6_0_0.bit5.obuf0 TE_B ) ( storage_6_0_0.bit4.obuf0 TE_B ) ( storage_6_0_0.bit3.obuf0 TE_B ) ( storage_6_0_0.bit2.obuf0 TE_B ) - ( storage_6_0_0.bit1.obuf0 TE_B ) ( storage_6_0_0.bit0.obuf0 TE_B ) + USE SIGNAL - + ROUTED met1 ( 713 1785 ) ( 989 * ) - NEW met1 ( 989 1785 ) ( * 1853 ) - NEW met1 ( 7475 1785 ) ( * 1819 ) - NEW met1 ( 6509 1785 ) ( 6785 * ) - NEW met1 ( 6785 1785 ) ( * 1853 ) - NEW met1 ( 6785 1853 ) ( 7475 * ) - NEW met1 ( 7475 1819 ) ( * 1853 ) + + ROUTED met1 ( 6969 1751 ) ( 7015 * ) + NEW li1 ( 7015 1751 ) L1M1_PR_MR + NEW li1 ( 6969 1751 ) L1M1_PR_MR ; + - storage_6_0_0.gclock ( storage_6_0_0.cg GCLK ) ( storage_6_0_0.bit7.bit SLEEP_B ) ( storage_6_0_0.bit6.bit SLEEP_B ) ( storage_6_0_0.bit5.bit SLEEP_B ) ( storage_6_0_0.bit4.bit SLEEP_B ) ( storage_6_0_0.bit3.bit SLEEP_B ) ( storage_6_0_0.bit2.bit SLEEP_B ) + ( storage_6_0_0.bit1.bit SLEEP_B ) ( storage_6_0_0.bit0.bit SLEEP_B ) + USE SIGNAL + + ROUTED met1 ( 69 1785 ) ( 989 * ) NEW met1 ( 6509 1785 ) ( * 1853 ) - NEW met1 ( 5543 1785 ) ( 5773 * ) - NEW met1 ( 5773 1785 ) ( * 1853 ) - NEW met1 ( 4577 1785 ) ( 4853 * ) - NEW met1 ( 4853 1785 ) ( * 1853 ) - NEW met1 ( 4853 1853 ) ( 5543 * ) - NEW met1 ( 5543 1785 ) ( * 1853 ) - NEW met1 ( 3611 1785 ) ( 3841 * ) - NEW met1 ( 3841 1785 ) ( * 1853 ) - NEW met1 ( 3841 1853 ) ( 4577 * ) - NEW met1 ( 4577 1785 ) ( * 1853 ) - NEW met1 ( 2645 1785 ) ( 2921 * ) - NEW met1 ( 2921 1785 ) ( * 1853 ) - NEW met1 ( 2921 1853 ) ( 3611 * ) - NEW met1 ( 3611 1785 ) ( * 1853 ) - NEW met1 ( 1679 1785 ) ( 1909 * ) - NEW met1 ( 1909 1785 ) ( * 1853 ) - NEW met1 ( 1909 1853 ) ( 2645 * ) - NEW met1 ( 2645 1785 ) ( * 1853 ) - NEW met1 ( 1679 1785 ) ( * 1853 ) - NEW met1 ( 989 1853 ) ( 1679 * ) - NEW met1 ( 5773 1853 ) ( 6509 * ) - NEW met1 ( 7475 1819 ) ( 7590 * ) - NEW met1 ( 7590 1819 ) ( * 1853 ) - NEW met1 ( 7590 1853 ) ( 8717 * ) - NEW li1 ( 713 1785 ) L1M1_PR_MR - NEW li1 ( 7475 1785 ) L1M1_PR_MR + NEW met1 ( 6509 1853 ) ( 8027 * ) + NEW met1 ( 4669 1785 ) ( 5589 * ) + NEW met1 ( 3749 1785 ) ( 4669 * ) + NEW met1 ( 2829 1785 ) ( 3749 * ) + NEW met1 ( 1909 1785 ) ( 2829 * ) + NEW met1 ( 989 1785 ) ( 1909 * ) + NEW met1 ( 5589 1785 ) ( 6509 * ) + NEW li1 ( 989 1785 ) L1M1_PR_MR + NEW li1 ( 69 1785 ) L1M1_PR_MR NEW li1 ( 6509 1785 ) L1M1_PR_MR - NEW li1 ( 5543 1785 ) L1M1_PR_MR - NEW li1 ( 4577 1785 ) L1M1_PR_MR - NEW li1 ( 3611 1785 ) L1M1_PR_MR - NEW li1 ( 2645 1785 ) L1M1_PR_MR - NEW li1 ( 1679 1785 ) L1M1_PR_MR - NEW li1 ( 8717 1853 ) L1M1_PR_MR ; + NEW li1 ( 8027 1853 ) L1M1_PR_MR + NEW li1 ( 5589 1785 ) L1M1_PR_MR + NEW li1 ( 4669 1785 ) L1M1_PR_MR + NEW li1 ( 3749 1785 ) L1M1_PR_MR + NEW li1 ( 2829 1785 ) L1M1_PR_MR + NEW li1 ( 1909 1785 ) L1M1_PR_MR ; + - storage_6_0_0.select0_b ( storage_6_0_0.select_inv_0 Y ) ( storage_6_0_0.bit7.obuf0 TE_B ) ( storage_6_0_0.bit6.obuf0 TE_B ) ( storage_6_0_0.bit5.obuf0 TE_B ) ( storage_6_0_0.bit4.obuf0 TE_B ) ( storage_6_0_0.bit3.obuf0 TE_B ) ( storage_6_0_0.bit2.obuf0 TE_B ) + ( storage_6_0_0.bit1.obuf0 TE_B ) ( storage_6_0_0.bit0.obuf0 TE_B ) + USE SIGNAL + + ROUTED met1 ( 7107 1751 ) ( * 1819 ) + NEW met1 ( 7107 1819 ) ( 8349 * ) + NEW met1 ( 6785 1717 ) ( * 1751 ) + NEW met1 ( 6785 1717 ) ( 7107 * ) + NEW met1 ( 7107 1717 ) ( * 1751 ) + NEW met1 ( 667 1751 ) ( 1380 * ) + NEW met1 ( 1587 1717 ) ( * 1751 ) + NEW met1 ( 1380 1717 ) ( 1587 * ) + NEW met1 ( 1380 1717 ) ( * 1751 ) + NEW met1 ( 2507 1717 ) ( * 1751 ) + NEW met1 ( 2323 1717 ) ( 2507 * ) + NEW met1 ( 2323 1717 ) ( * 1751 ) + NEW met1 ( 1587 1751 ) ( 2323 * ) + NEW met1 ( 3427 1717 ) ( * 1751 ) + NEW met1 ( 3243 1717 ) ( 3427 * ) + NEW met1 ( 3243 1717 ) ( * 1751 ) + NEW met1 ( 2507 1751 ) ( 3243 * ) + NEW met1 ( 4347 1717 ) ( * 1751 ) + NEW met1 ( 4163 1717 ) ( 4347 * ) + NEW met1 ( 4163 1717 ) ( * 1751 ) + NEW met1 ( 3427 1751 ) ( 4163 * ) + NEW met1 ( 5267 1717 ) ( * 1751 ) + NEW met1 ( 5083 1717 ) ( 5267 * ) + NEW met1 ( 5083 1717 ) ( * 1751 ) + NEW met1 ( 4347 1751 ) ( 5083 * ) + NEW met1 ( 6187 1717 ) ( * 1751 ) + NEW met1 ( 6003 1717 ) ( 6187 * ) + NEW met1 ( 6003 1717 ) ( * 1751 ) + NEW met1 ( 5267 1751 ) ( 6003 * ) + NEW met1 ( 6187 1751 ) ( 6785 * ) + NEW li1 ( 667 1751 ) L1M1_PR_MR + NEW li1 ( 7107 1751 ) L1M1_PR_MR + NEW li1 ( 8349 1819 ) L1M1_PR_MR + NEW li1 ( 1587 1751 ) L1M1_PR_MR + NEW li1 ( 2507 1751 ) L1M1_PR_MR + NEW li1 ( 3427 1751 ) L1M1_PR_MR + NEW li1 ( 4347 1751 ) L1M1_PR_MR + NEW li1 ( 5267 1751 ) L1M1_PR_MR + NEW li1 ( 6187 1751 ) L1M1_PR_MR ; - storage_6_0_0.we ( storage_6_0_0.gcand X ) ( storage_6_0_0.cg GATE ) + USE SIGNAL - + ROUTED met1 ( 7981 1683 ) ( 8625 * ) - NEW li1 ( 7981 1683 ) L1M1_PR_MR - NEW li1 ( 8625 1683 ) L1M1_PR_MR ; + + ROUTED met1 ( 7613 1683 ) ( 8211 * ) + NEW met1 ( 8211 1683 ) ( * 1751 ) + NEW met1 ( 8211 1751 ) ( 8257 * ) + NEW li1 ( 7613 1683 ) L1M1_PR_MR + NEW li1 ( 8257 1751 ) L1M1_PR_MR ; - storage_7_0_0.bit0.storage ( storage_7_0_0.bit0.obuf0 A ) ( storage_7_0_0.bit0.bit Q ) + USE SIGNAL - + ROUTED met1 ( 575 2023 ) ( 621 * ) - NEW met1 ( 575 1989 ) ( * 2023 ) - NEW li1 ( 621 2023 ) L1M1_PR_MR - NEW li1 ( 575 1989 ) L1M1_PR_MR ; + + ROUTED met1 ( 529 2023 ) ( 575 * ) + NEW met1 ( 529 1989 ) ( * 2023 ) + NEW li1 ( 575 2023 ) L1M1_PR_MR + NEW li1 ( 529 1989 ) L1M1_PR_MR ; - storage_7_0_0.bit1.storage ( storage_7_0_0.bit1.obuf0 A ) ( storage_7_0_0.bit1.bit Q ) + USE SIGNAL - + ROUTED met1 ( 1541 2023 ) ( 1587 * ) - NEW met1 ( 1541 1989 ) ( * 2023 ) - NEW li1 ( 1587 2023 ) L1M1_PR_MR - NEW li1 ( 1541 1989 ) L1M1_PR_MR ; + + ROUTED met1 ( 1449 2057 ) ( 1495 * ) + NEW li1 ( 1495 2057 ) L1M1_PR_MR + NEW li1 ( 1449 2057 ) L1M1_PR_MR ; - storage_7_0_0.bit2.storage ( storage_7_0_0.bit2.obuf0 A ) ( storage_7_0_0.bit2.bit Q ) + USE SIGNAL - + ROUTED met1 ( 2507 2023 ) ( 2553 * ) - NEW met1 ( 2507 1989 ) ( * 2023 ) - NEW li1 ( 2553 2023 ) L1M1_PR_MR - NEW li1 ( 2507 1989 ) L1M1_PR_MR ; + + ROUTED met1 ( 2369 2023 ) ( 2415 * ) + NEW met1 ( 2369 1989 ) ( * 2023 ) + NEW li1 ( 2415 2023 ) L1M1_PR_MR + NEW li1 ( 2369 1989 ) L1M1_PR_MR ; - storage_7_0_0.bit3.storage ( storage_7_0_0.bit3.obuf0 A ) ( storage_7_0_0.bit3.bit Q ) + USE SIGNAL - + ROUTED met1 ( 3473 2023 ) ( 3519 * ) - NEW met1 ( 3473 1989 ) ( * 2023 ) - NEW li1 ( 3519 2023 ) L1M1_PR_MR - NEW li1 ( 3473 1989 ) L1M1_PR_MR ; + + ROUTED met1 ( 3289 2023 ) ( 3335 * ) + NEW met1 ( 3289 1989 ) ( * 2023 ) + NEW li1 ( 3335 2023 ) L1M1_PR_MR + NEW li1 ( 3289 1989 ) L1M1_PR_MR ; - storage_7_0_0.bit4.storage ( storage_7_0_0.bit4.obuf0 A ) ( storage_7_0_0.bit4.bit Q ) + USE SIGNAL - + ROUTED met1 ( 4439 2023 ) ( 4485 * ) - NEW met1 ( 4439 1989 ) ( * 2023 ) - NEW li1 ( 4485 2023 ) L1M1_PR_MR - NEW li1 ( 4439 1989 ) L1M1_PR_MR ; + + ROUTED met1 ( 4209 2057 ) ( 4255 * ) + NEW li1 ( 4255 2057 ) L1M1_PR_MR + NEW li1 ( 4209 2057 ) L1M1_PR_MR ; - storage_7_0_0.bit5.storage ( storage_7_0_0.bit5.obuf0 A ) ( storage_7_0_0.bit5.bit Q ) + USE SIGNAL - + ROUTED met1 ( 5405 2023 ) ( 5451 * ) - NEW met1 ( 5405 1989 ) ( * 2023 ) - NEW li1 ( 5451 2023 ) L1M1_PR_MR - NEW li1 ( 5405 1989 ) L1M1_PR_MR ; + + ROUTED met1 ( 5129 2023 ) ( 5175 * ) + NEW met1 ( 5129 1989 ) ( * 2023 ) + NEW li1 ( 5175 2023 ) L1M1_PR_MR + NEW li1 ( 5129 1989 ) L1M1_PR_MR ; - storage_7_0_0.bit6.storage ( storage_7_0_0.bit6.obuf0 A ) ( storage_7_0_0.bit6.bit Q ) + USE SIGNAL - + ROUTED met1 ( 6371 2023 ) ( 6417 * ) - NEW met1 ( 6371 1989 ) ( * 2023 ) - NEW li1 ( 6417 2023 ) L1M1_PR_MR - NEW li1 ( 6371 1989 ) L1M1_PR_MR ; + + ROUTED met1 ( 6049 2057 ) ( 6095 * ) + NEW li1 ( 6095 2057 ) L1M1_PR_MR + NEW li1 ( 6049 2057 ) L1M1_PR_MR ; - storage_7_0_0.bit7.storage ( storage_7_0_0.bit7.obuf0 A ) ( storage_7_0_0.bit7.bit Q ) + USE SIGNAL - + ROUTED met1 ( 7337 2023 ) ( 7383 * ) - NEW met1 ( 7337 1989 ) ( * 2023 ) - NEW li1 ( 7383 2023 ) L1M1_PR_MR - NEW li1 ( 7337 1989 ) L1M1_PR_MR ; - - storage_7_0_0.gclock ( storage_7_0_0.cg GCLK ) ( storage_7_0_0.bit7.bit GATE ) ( storage_7_0_0.bit6.bit GATE ) ( storage_7_0_0.bit5.bit GATE ) ( storage_7_0_0.bit4.bit GATE ) ( storage_7_0_0.bit3.bit GATE ) ( storage_7_0_0.bit2.bit GATE ) - ( storage_7_0_0.bit1.bit GATE ) ( storage_7_0_0.bit0.bit GATE ) + USE SIGNAL - + ROUTED met1 ( 1035 2057 ) ( * 2091 ) - NEW met1 ( 69 2091 ) ( 1035 * ) - NEW met1 ( 69 2057 ) ( * 2091 ) - NEW met1 ( 2001 2057 ) ( * 2091 ) - NEW met1 ( 2967 2057 ) ( * 2091 ) - NEW met1 ( 2001 2091 ) ( 2967 * ) - NEW met1 ( 3933 2057 ) ( * 2091 ) - NEW met1 ( 2967 2091 ) ( 3933 * ) - NEW met1 ( 1035 2091 ) ( 2001 * ) - NEW met1 ( 4899 2057 ) ( * 2091 ) - NEW met1 ( 5681 2023 ) ( 5865 * ) - NEW met2 ( 5681 2023 ) ( * 2091 ) - NEW met1 ( 4899 2091 ) ( 5681 * ) - NEW met1 ( 6831 1955 ) ( * 2023 ) - NEW met1 ( 5865 1955 ) ( 6831 * ) - NEW met1 ( 5865 1955 ) ( * 2023 ) - NEW met1 ( 3933 2091 ) ( 4899 * ) - NEW met1 ( 6831 1955 ) ( 8395 * ) - NEW li1 ( 1035 2057 ) L1M1_PR_MR + + ROUTED met1 ( 6969 2057 ) ( 7015 * ) + NEW li1 ( 7015 2057 ) L1M1_PR_MR + NEW li1 ( 6969 2057 ) L1M1_PR_MR ; + - storage_7_0_0.gclock ( storage_7_0_0.cg GCLK ) ( storage_7_0_0.bit7.bit SLEEP_B ) ( storage_7_0_0.bit6.bit SLEEP_B ) ( storage_7_0_0.bit5.bit SLEEP_B ) ( storage_7_0_0.bit4.bit SLEEP_B ) ( storage_7_0_0.bit3.bit SLEEP_B ) ( storage_7_0_0.bit2.bit SLEEP_B ) + ( storage_7_0_0.bit1.bit SLEEP_B ) ( storage_7_0_0.bit0.bit SLEEP_B ) + USE SIGNAL + + ROUTED met1 ( 69 2057 ) ( 989 * ) + NEW met1 ( 989 2057 ) ( 1380 * ) + NEW met1 ( 2829 2057 ) ( 3749 * ) + NEW met1 ( 3749 2023 ) ( * 2057 ) + NEW met1 ( 1909 2057 ) ( 2829 * ) + NEW met1 ( 1380 2057 ) ( * 2091 ) + NEW met1 ( 1380 2091 ) ( 1909 * ) + NEW met1 ( 1909 2057 ) ( * 2091 ) + NEW met1 ( 6509 2023 ) ( 8027 * ) + NEW met2 ( 5589 1989 ) ( * 2057 ) + NEW met1 ( 5589 1989 ) ( 6509 * ) + NEW met1 ( 6509 1989 ) ( * 2023 ) + NEW met1 ( 4669 2057 ) ( 5589 * ) + NEW met1 ( 4301 2023 ) ( * 2057 ) + NEW met1 ( 4301 2057 ) ( 4669 * ) + NEW met1 ( 3749 2023 ) ( 4301 * ) + NEW li1 ( 989 2057 ) L1M1_PR_MR NEW li1 ( 69 2057 ) L1M1_PR_MR - NEW li1 ( 2001 2057 ) L1M1_PR_MR - NEW li1 ( 2967 2057 ) L1M1_PR_MR - NEW li1 ( 3933 2057 ) L1M1_PR_MR - NEW li1 ( 4899 2057 ) L1M1_PR_MR - NEW li1 ( 5865 2023 ) L1M1_PR_MR - NEW met1 ( 5681 2023 ) M1M2_PR - NEW met1 ( 5681 2091 ) M1M2_PR - NEW li1 ( 6831 2023 ) L1M1_PR_MR - NEW li1 ( 8395 1955 ) L1M1_PR_MR ; + NEW li1 ( 3749 2023 ) L1M1_PR_MR + NEW li1 ( 2829 2057 ) L1M1_PR_MR + NEW li1 ( 1909 2057 ) L1M1_PR_MR + NEW li1 ( 6509 2023 ) L1M1_PR_MR + NEW li1 ( 8027 2023 ) L1M1_PR_MR + NEW li1 ( 5589 2057 ) L1M1_PR_MR + NEW met1 ( 5589 2057 ) M1M2_PR + NEW met1 ( 5589 1989 ) M1M2_PR + NEW li1 ( 4669 2057 ) L1M1_PR_MR ; - storage_7_0_0.select0_b ( storage_7_0_0.select_inv_0 Y ) ( storage_7_0_0.bit7.obuf0 TE_B ) ( storage_7_0_0.bit6.obuf0 TE_B ) ( storage_7_0_0.bit5.obuf0 TE_B ) ( storage_7_0_0.bit4.obuf0 TE_B ) ( storage_7_0_0.bit3.obuf0 TE_B ) ( storage_7_0_0.bit2.obuf0 TE_B ) ( storage_7_0_0.bit1.obuf0 TE_B ) ( storage_7_0_0.bit0.obuf0 TE_B ) + USE SIGNAL - + ROUTED met1 ( 713 1955 ) ( * 2023 ) - NEW met1 ( 7475 1989 ) ( * 2023 ) - NEW met1 ( 7475 2023 ) ( * 2091 ) - NEW met1 ( 3611 1955 ) ( * 2023 ) - NEW met1 ( 2645 1955 ) ( * 2023 ) - NEW met1 ( 2645 1955 ) ( 3611 * ) - NEW met1 ( 1679 1955 ) ( * 2023 ) - NEW met1 ( 1679 1955 ) ( 2645 * ) - NEW met1 ( 713 1955 ) ( 1679 * ) - NEW met1 ( 4577 1955 ) ( * 2023 ) - NEW met1 ( 5543 1955 ) ( * 2023 ) - NEW met1 ( 4577 1955 ) ( 5543 * ) - NEW met1 ( 6509 2057 ) ( * 2091 ) - NEW met1 ( 5819 2091 ) ( 6509 * ) - NEW met2 ( 5819 1989 ) ( * 2091 ) - NEW met1 ( 5543 1989 ) ( 5819 * ) - NEW met1 ( 3611 1955 ) ( 4577 * ) - NEW met1 ( 6509 2091 ) ( 7475 * ) - NEW met1 ( 7475 1989 ) ( 8717 * ) - NEW li1 ( 713 2023 ) L1M1_PR_MR - NEW li1 ( 7475 2023 ) L1M1_PR_MR - NEW li1 ( 3611 2023 ) L1M1_PR_MR - NEW li1 ( 2645 2023 ) L1M1_PR_MR - NEW li1 ( 1679 2023 ) L1M1_PR_MR - NEW li1 ( 4577 2023 ) L1M1_PR_MR - NEW li1 ( 5543 2023 ) L1M1_PR_MR - NEW li1 ( 6509 2057 ) L1M1_PR_MR - NEW met1 ( 5819 2091 ) M1M2_PR - NEW met1 ( 5819 1989 ) M1M2_PR - NEW li1 ( 8717 1989 ) L1M1_PR_MR ; + + ROUTED met1 ( 2507 1955 ) ( * 2023 ) + NEW met1 ( 1587 1955 ) ( 2507 * ) + NEW met1 ( 1587 1955 ) ( * 2023 ) + NEW met1 ( 3427 1955 ) ( * 2023 ) + NEW met1 ( 2507 1955 ) ( 3427 * ) + NEW met1 ( 667 2023 ) ( 1587 * ) + NEW met1 ( 7107 2057 ) ( * 2091 ) + NEW met1 ( 6187 2023 ) ( 6279 * ) + NEW met1 ( 6279 2023 ) ( * 2057 ) + NEW met1 ( 6279 2057 ) ( 6785 * ) + NEW met1 ( 6785 2057 ) ( * 2091 ) + NEW met1 ( 6785 2091 ) ( 7107 * ) + NEW met1 ( 5267 2023 ) ( 6187 * ) + NEW met1 ( 4347 1955 ) ( * 2023 ) + NEW met1 ( 4347 1955 ) ( 5267 * ) + NEW met1 ( 5267 1955 ) ( * 2023 ) + NEW met1 ( 3427 1989 ) ( 4347 * ) + NEW met1 ( 7107 2091 ) ( 8349 * ) + NEW li1 ( 667 2023 ) L1M1_PR_MR + NEW li1 ( 8349 2091 ) L1M1_PR_MR + NEW li1 ( 1587 2023 ) L1M1_PR_MR + NEW li1 ( 2507 2023 ) L1M1_PR_MR + NEW li1 ( 3427 2023 ) L1M1_PR_MR + NEW li1 ( 7107 2057 ) L1M1_PR_MR + NEW li1 ( 6187 2023 ) L1M1_PR_MR + NEW li1 ( 5267 2023 ) L1M1_PR_MR + NEW li1 ( 4347 2023 ) L1M1_PR_MR ; - storage_7_0_0.we ( storage_7_0_0.gcand X ) ( storage_7_0_0.cg GATE ) + USE SIGNAL - + ROUTED met1 ( 7981 2091 ) ( 8625 * ) - NEW li1 ( 7981 2091 ) L1M1_PR_MR - NEW li1 ( 8625 2091 ) L1M1_PR_MR ; + + ROUTED met1 ( 7613 2125 ) ( 8257 * ) + NEW li1 ( 7613 2125 ) L1M1_PR_MR + NEW li1 ( 8257 2125 ) L1M1_PR_MR ; - we[0] ( PIN we[0] ) ( storage_7_0_0.gcand B ) ( storage_6_0_0.gcand B ) ( storage_5_0_0.gcand B ) ( storage_4_0_0.gcand B ) ( storage_3_0_0.gcand B ) ( storage_2_0_0.gcand B ) ( storage_1_0_0.gcand B ) ( storage_0_0_0.gcand B ) + USE SIGNAL - + ROUTED met1 ( 8487 2023 ) ( 8533 * ) - NEW met2 ( 8487 2023 ) ( * 2686 0 ) - NEW met1 ( 8487 1751 ) ( 8533 * ) - NEW met2 ( 8487 1751 ) ( * 2023 ) - NEW met1 ( 8487 1479 ) ( 8533 * ) - NEW met2 ( 8487 1479 ) ( * 1751 ) - NEW met1 ( 8487 1207 ) ( 8533 * ) - NEW met2 ( 8487 1207 ) ( * 1479 ) - NEW met1 ( 8487 935 ) ( 8533 * ) - NEW met2 ( 8487 935 ) ( * 1207 ) - NEW met1 ( 8487 663 ) ( 8533 * ) - NEW met2 ( 8487 663 ) ( * 935 ) - NEW met1 ( 8487 391 ) ( 8533 * ) - NEW met2 ( 8487 391 ) ( * 663 ) - NEW met1 ( 8487 119 ) ( 8533 * ) - NEW met2 ( 8487 119 ) ( * 391 ) - NEW li1 ( 8533 2023 ) L1M1_PR_MR - NEW met1 ( 8487 2023 ) M1M2_PR - NEW li1 ( 8533 1751 ) L1M1_PR_MR - NEW met1 ( 8487 1751 ) M1M2_PR - NEW li1 ( 8533 1479 ) L1M1_PR_MR - NEW met1 ( 8487 1479 ) M1M2_PR - NEW li1 ( 8533 1207 ) L1M1_PR_MR - NEW met1 ( 8487 1207 ) M1M2_PR - NEW li1 ( 8533 935 ) L1M1_PR_MR - NEW met1 ( 8487 935 ) M1M2_PR - NEW li1 ( 8533 663 ) L1M1_PR_MR - NEW met1 ( 8487 663 ) M1M2_PR - NEW li1 ( 8533 391 ) L1M1_PR_MR - NEW met1 ( 8487 391 ) M1M2_PR - NEW li1 ( 8533 119 ) L1M1_PR_MR - NEW met1 ( 8487 119 ) M1M2_PR ; + + ROUTED met1 ( 8119 1207 ) ( 8165 * ) + NEW met1 ( 8119 935 ) ( 8165 * ) + NEW met2 ( 8119 935 ) ( * 1207 ) + NEW met1 ( 8119 663 ) ( 8165 * ) + NEW met2 ( 8119 663 ) ( * 935 ) + NEW met1 ( 8119 391 ) ( 8165 * ) + NEW met2 ( 8119 391 ) ( * 663 ) + NEW met1 ( 8119 119 ) ( 8165 * ) + NEW met2 ( 8119 119 ) ( * 391 ) + NEW met1 ( 8119 2023 ) ( 8165 * ) + NEW met2 ( 8119 2023 ) ( * 2686 0 ) + NEW met1 ( 8119 1751 ) ( 8165 * ) + NEW met2 ( 8119 1751 ) ( * 2023 ) + NEW met1 ( 8119 1513 ) ( 8165 * ) + NEW met2 ( 8119 1513 ) ( * 1751 ) + NEW met2 ( 8119 1207 ) ( * 1513 ) + NEW li1 ( 8165 1207 ) L1M1_PR_MR + NEW met1 ( 8119 1207 ) M1M2_PR + NEW li1 ( 8165 935 ) L1M1_PR_MR + NEW met1 ( 8119 935 ) M1M2_PR + NEW li1 ( 8165 663 ) L1M1_PR_MR + NEW met1 ( 8119 663 ) M1M2_PR + NEW li1 ( 8165 391 ) L1M1_PR_MR + NEW met1 ( 8119 391 ) M1M2_PR + NEW li1 ( 8165 119 ) L1M1_PR_MR + NEW met1 ( 8119 119 ) M1M2_PR + NEW li1 ( 8165 2023 ) L1M1_PR_MR + NEW met1 ( 8119 2023 ) M1M2_PR + NEW li1 ( 8165 1751 ) L1M1_PR_MR + NEW met1 ( 8119 1751 ) M1M2_PR + NEW li1 ( 8165 1513 ) L1M1_PR_MR + NEW met1 ( 8119 1513 ) M1M2_PR ; END NETS END DESIGN diff --git a/src/ram/test/make_8x8_latch_sky130.lefok b/src/ram/test/make_8x8_latch_sky130.lefok index 115ed50af8d..6b2ca7e5b0f 100644 --- a/src/ram/test/make_8x8_latch_sky130.lefok +++ b/src/ram/test/make_8x8_latch_sky130.lefok @@ -8,13 +8,13 @@ END UNITS MACRO RAM8x8 FOREIGN RAM8x8 0 0 ; CLASS BLOCK ; - SIZE 95.68 BY 27.2 ; + SIZE 92 BY 27.2 ; PIN clk DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 80.2 26.715 80.34 27.2 ; + RECT 76.52 26.715 76.66 27.2 ; END END clk PIN we[0] @@ -22,7 +22,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 84.8 26.715 84.94 27.2 ; + RECT 81.12 26.715 81.26 27.2 ; END END we[0] PIN addr_rw[0] @@ -30,7 +30,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met3 ; - RECT 94.88 4.27 95.68 4.57 ; + RECT 91.2 4.27 92 4.57 ; END END addr_rw[0] PIN addr_rw[1] @@ -38,7 +38,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met3 ; - RECT 94.88 6.99 95.68 7.29 ; + RECT 91.2 6.99 92 7.29 ; END END addr_rw[1] PIN addr_rw[2] @@ -46,7 +46,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met3 ; - RECT 94.88 1.55 95.68 1.85 ; + RECT 91.2 1.55 92 1.85 ; END END addr_rw[2] PIN D[0] @@ -62,7 +62,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 9.36 26.715 9.5 27.2 ; + RECT 8.44 26.715 8.58 27.2 ; END END Q[0] PIN D[1] @@ -78,7 +78,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 18.56 26.715 18.7 27.2 ; + RECT 17.64 26.715 17.78 27.2 ; END END Q[1] PIN D[2] @@ -86,7 +86,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 20.4 26.715 20.54 27.2 ; + RECT 19.48 26.715 19.62 27.2 ; END END D[2] PIN Q[2] @@ -94,7 +94,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 28.68 26.715 28.82 27.2 ; + RECT 26.84 26.715 26.98 27.2 ; END END Q[2] PIN D[3] @@ -102,7 +102,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 29.6 26.715 29.74 27.2 ; + RECT 28.68 26.715 28.82 27.2 ; END END D[3] PIN Q[3] @@ -110,7 +110,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 37.88 26.715 38.02 27.2 ; + RECT 36.04 26.715 36.18 27.2 ; END END Q[3] PIN D[4] @@ -118,7 +118,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 38.8 26.715 38.94 27.2 ; + RECT 37.88 26.715 38.02 27.2 ; END END D[4] PIN Q[4] @@ -126,7 +126,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 48 26.715 48.14 27.2 ; + RECT 45.24 26.715 45.38 27.2 ; END END Q[4] PIN D[5] @@ -134,7 +134,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 48.92 26.715 49.06 27.2 ; + RECT 47.08 26.715 47.22 27.2 ; END END D[5] PIN Q[5] @@ -142,7 +142,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 57.2 26.715 57.34 27.2 ; + RECT 54.44 26.715 54.58 27.2 ; END END Q[5] PIN D[6] @@ -150,7 +150,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 59.04 26.715 59.18 27.2 ; + RECT 56.28 26.715 56.42 27.2 ; END END D[6] PIN Q[6] @@ -158,7 +158,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 67.32 26.715 67.46 27.2 ; + RECT 63.64 26.715 63.78 27.2 ; END END Q[6] PIN D[7] @@ -166,7 +166,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 68.24 26.715 68.38 27.2 ; + RECT 65.48 26.715 65.62 27.2 ; END END D[7] PIN Q[7] @@ -174,15 +174,40 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 76.52 26.715 76.66 27.2 ; + RECT 72.84 26.715 72.98 27.2 ; END END Q[7] + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER met3 ; + RECT 91.7 9.76 92 10.24 ; + RECT 0 9.76 0.3 10.24 ; + LAYER met2 ; + RECT 59.76 27.06 60.24 27.2 ; + RECT 59.76 0 60.24 0.14 ; + RECT 19.76 27.06 20.24 27.2 ; + RECT 19.76 0 20.24 0.14 ; + LAYER met1 ; + RECT 91.86 24.24 92 24.72 ; + RECT 0 24.24 0.14 24.72 ; + RECT 91.86 18.8 92 19.28 ; + RECT 0 18.8 0.14 19.28 ; + RECT 91.86 13.36 92 13.84 ; + RECT 0 13.36 0.14 13.84 ; + RECT 91.86 7.92 92 8.4 ; + RECT 0 7.92 0.14 8.4 ; + RECT 91.86 2.48 92 2.96 ; + RECT 0 2.48 0.14 2.96 ; + END + END VDD PIN VSS DIRECTION INOUT ; USE GROUND ; PORT LAYER met3 ; - RECT 95.38 19.76 95.68 20.24 ; + RECT 91.7 19.76 92 20.24 ; RECT 0 19.76 0.3 20.24 ; LAYER met2 ; RECT 79.76 27.06 80.24 27.2 ; @@ -190,81 +215,55 @@ MACRO RAM8x8 RECT 39.76 27.06 40.24 27.2 ; RECT 39.76 0 40.24 0.14 ; LAYER met1 ; - RECT 95.54 26.96 95.68 27.44 ; + RECT 91.86 26.96 92 27.44 ; RECT 0 26.96 0.14 27.44 ; - RECT 95.54 21.52 95.68 22 ; + RECT 91.86 21.52 92 22 ; RECT 0 21.52 0.14 22 ; - RECT 95.54 16.08 95.68 16.56 ; + RECT 91.86 16.08 92 16.56 ; RECT 0 16.08 0.14 16.56 ; - RECT 95.54 10.64 95.68 11.12 ; + RECT 91.86 10.64 92 11.12 ; RECT 0 10.64 0.14 11.12 ; - RECT 95.54 5.2 95.68 5.68 ; + RECT 91.86 5.2 92 5.68 ; RECT 0 5.2 0.14 5.68 ; - RECT 95.54 -0.24 95.68 0.24 ; + RECT 91.86 -0.24 92 0.24 ; RECT 0 -0.24 0.14 0.24 ; END END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER met3 ; - RECT 95.38 9.76 95.68 10.24 ; - RECT 0 9.76 0.3 10.24 ; - LAYER met2 ; - RECT 59.76 27.06 60.24 27.2 ; - RECT 59.76 0 60.24 0.14 ; - RECT 19.76 27.06 20.24 27.2 ; - RECT 19.76 0 20.24 0.14 ; - LAYER met1 ; - RECT 95.54 24.24 95.68 24.72 ; - RECT 0 24.24 0.14 24.72 ; - RECT 95.54 18.8 95.68 19.28 ; - RECT 0 18.8 0.14 19.28 ; - RECT 95.54 13.36 95.68 13.84 ; - RECT 0 13.36 0.14 13.84 ; - RECT 95.54 7.92 95.68 8.4 ; - RECT 0 7.92 0.14 8.4 ; - RECT 95.54 2.48 95.68 2.96 ; - RECT 0 2.48 0.14 2.96 ; - END - END VDD OBS LAYER li1 ; - RECT 0 -0.085 95.68 27.285 ; + RECT 0 -0.085 92 27.285 ; LAYER met1 ; - RECT 0 -0.24 95.68 27.44 ; + RECT 0 -0.24 92 27.44 ; LAYER met2 ; - RECT 19.76 0 20.24 1.03 ; - RECT 39.76 -0.24 40.24 1.03 ; - RECT 59.76 0 60.24 1.03 ; + RECT 19.76 0 20.24 0.69 ; + RECT 39.76 -0.24 40.24 0.69 ; + RECT 59.76 0 60.24 0.69 ; + RECT 58.06 0.69 67.52 1.03 ; RECT 79.76 -0.24 80.24 1.03 ; - RECT 59.76 1.03 69.82 1.37 ; - RECT 79.76 1.03 85 1.37 ; - RECT 94.4 1.03 94.66 1.37 ; - RECT 59.76 1.37 94.66 1.515 ; - RECT 1.94 1.03 2.2 2.05 ; - RECT 11.6 1.03 21.52 2.05 ; - RECT 30.92 1.03 40.84 2.05 ; - RECT 50.24 1.03 50.5 2.05 ; - RECT 59.76 1.515 94.67 2.05 ; - RECT 1.94 2.05 94.67 7.325 ; - RECT 1.94 7.325 94.66 18.01 ; - RECT 1.94 18.01 94.2 20.39 ; - RECT 1.94 20.39 84.94 25.85 ; - RECT 1.02 25.85 84.94 26.17 ; - RECT 1.08 26.17 84.94 26.86 ; - RECT 79.76 26.86 80.8 26.93 ; + RECT 58.06 1.03 81.32 1.37 ; + RECT 90.72 1.03 90.98 1.37 ; + RECT 58.06 1.37 90.98 1.515 ; + RECT 2.4 0.69 2.66 2.05 ; + RECT 12.06 0.69 30.26 2.05 ; + RECT 39.76 0.69 48.66 2.05 ; + RECT 58.06 1.515 90.99 2.05 ; + RECT 2.4 2.05 90.99 7.325 ; + RECT 2.4 7.325 90.98 18.01 ; + RECT 2.4 18.01 90.52 20.39 ; + RECT 2.4 20.39 81.26 22.45 ; + RECT 1.48 22.45 81.26 25.85 ; + RECT 1.02 25.85 81.26 26.17 ; + RECT 1.08 26.17 81.26 26.86 ; RECT 19.76 26.86 20.24 27.2 ; RECT 59.76 26.86 60.24 27.2 ; RECT 39.76 26.86 40.24 27.44 ; - RECT 79.76 26.93 80.24 27.44 ; + RECT 79.76 26.86 80.24 27.44 ; LAYER met3 ; - RECT 0 9.76 90.225 20.24 ; - RECT 90.225 4.255 94.365 20.24 ; - RECT 94.365 1.535 94.695 20.24 ; - RECT 94.695 1.55 95.22 20.24 ; - RECT 95.22 9.76 95.68 20.24 ; + RECT 0 9.76 86.545 20.24 ; + RECT 86.545 4.255 90.685 20.24 ; + RECT 90.685 1.535 91.015 20.24 ; + RECT 91.015 1.55 91.54 20.24 ; + RECT 91.54 9.76 92 20.24 ; END END RAM8x8 END LIBRARY diff --git a/src/ram/test/make_8x8_latch_sky130.ok b/src/ram/test/make_8x8_latch_sky130.ok index 9453874b815..4df4eb2b222 100644 --- a/src/ram/test/make_8x8_latch_sky130.ok +++ b/src/ram/test/make_8x8_latch_sky130.ok @@ -71,10 +71,6 @@ [INFO DRT-0036] via4 guide region query size = 0. [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. -Differences found at line 11. - SIZE 95.68 BY 27.2 ; - SIZE 92 BY 27.2 ; -Differences found at line 6. -DIEAREA ( 0 0 ) ( 9568 2720 ) ; -DIEAREA ( 0 0 ) ( 9200 2720 ) ; +No differences found. +No differences found. No differences found. diff --git a/src/ram/test/make_8x8_mux2_sky130.lefok b/src/ram/test/make_8x8_mux2_sky130.lefok index 3458860b559..2f8e0be0c5f 100644 --- a/src/ram/test/make_8x8_mux2_sky130.lefok +++ b/src/ram/test/make_8x8_mux2_sky130.lefok @@ -177,43 +177,6 @@ MACRO RAM8x8 RECT 176.8 13.115 176.94 13.6 ; END END Q[7] - PIN VSS - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER met3 ; - RECT 213.6 9.76 213.9 10.24 ; - RECT 0 9.76 0.3 10.24 ; - LAYER met2 ; - RECT 199.76 13.46 200.24 13.6 ; - RECT 199.76 0 200.24 0.14 ; - RECT 179.76 13.46 180.24 13.6 ; - RECT 179.76 0 180.24 0.14 ; - RECT 159.76 13.46 160.24 13.6 ; - RECT 159.76 0 160.24 0.14 ; - RECT 139.76 13.46 140.24 13.6 ; - RECT 139.76 0 140.24 0.14 ; - RECT 119.76 13.46 120.24 13.6 ; - RECT 119.76 0 120.24 0.14 ; - RECT 99.76 13.46 100.24 13.6 ; - RECT 99.76 0 100.24 0.14 ; - RECT 79.76 13.46 80.24 13.6 ; - RECT 79.76 0 80.24 0.14 ; - RECT 59.76 13.46 60.24 13.6 ; - RECT 59.76 0 60.24 0.14 ; - RECT 39.76 13.46 40.24 13.6 ; - RECT 39.76 0 40.24 0.14 ; - RECT 19.76 13.46 20.24 13.6 ; - RECT 19.76 0 20.24 0.14 ; - LAYER met1 ; - RECT 213.76 10.64 213.9 11.12 ; - RECT 0 10.64 0.14 11.12 ; - RECT 213.76 5.2 213.9 5.68 ; - RECT 0 5.2 0.14 5.68 ; - RECT 213.76 -0.24 213.9 0.24 ; - RECT 0 -0.24 0.14 0.24 ; - END - END VSS PIN VDD DIRECTION INOUT ; USE POWER ; @@ -253,6 +216,43 @@ MACRO RAM8x8 RECT 0 2.48 0.14 2.96 ; END END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER met3 ; + RECT 213.6 9.76 213.9 10.24 ; + RECT 0 9.76 0.3 10.24 ; + LAYER met2 ; + RECT 199.76 13.46 200.24 13.6 ; + RECT 199.76 0 200.24 0.14 ; + RECT 179.76 13.46 180.24 13.6 ; + RECT 179.76 0 180.24 0.14 ; + RECT 159.76 13.46 160.24 13.6 ; + RECT 159.76 0 160.24 0.14 ; + RECT 139.76 13.46 140.24 13.6 ; + RECT 139.76 0 140.24 0.14 ; + RECT 119.76 13.46 120.24 13.6 ; + RECT 119.76 0 120.24 0.14 ; + RECT 99.76 13.46 100.24 13.6 ; + RECT 99.76 0 100.24 0.14 ; + RECT 79.76 13.46 80.24 13.6 ; + RECT 79.76 0 80.24 0.14 ; + RECT 59.76 13.46 60.24 13.6 ; + RECT 59.76 0 60.24 0.14 ; + RECT 39.76 13.46 40.24 13.6 ; + RECT 39.76 0 40.24 0.14 ; + RECT 19.76 13.46 20.24 13.6 ; + RECT 19.76 0 20.24 0.14 ; + LAYER met1 ; + RECT 213.76 10.64 213.9 11.12 ; + RECT 0 10.64 0.14 11.12 ; + RECT 213.76 5.2 213.9 5.68 ; + RECT 0 5.2 0.14 5.68 ; + RECT 213.76 -0.24 213.9 0.24 ; + RECT 0 -0.24 0.14 0.24 ; + END + END VSS OBS LAYER li1 ; RECT 0 -0.24 213.9 13.84 ; diff --git a/src/ram/test/make_8x8_mux2_sky130.ok b/src/ram/test/make_8x8_mux2_sky130.ok index 4ed658064c5..7d68a2b9210 100644 --- a/src/ram/test/make_8x8_mux2_sky130.ok +++ b/src/ram/test/make_8x8_mux2_sky130.ok @@ -60,7 +60,7 @@ [INFO DRT-0036] FR_VIA guide region query size = 0. [INFO DRT-0036] li1 guide region query size = 351. [INFO DRT-0036] mcon guide region query size = 0. -[INFO DRT-0036] met1 guide region query size = 217. +[INFO DRT-0036] met1 guide region query size = 218. [INFO DRT-0036] via guide region query size = 0. [INFO DRT-0036] met2 guide region query size = 21. [INFO DRT-0036] via2 guide region query size = 0. @@ -70,10 +70,6 @@ [INFO DRT-0036] via4 guide region query size = 0. [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. -Differences found at line 180. - PIN VSS - PIN VDD -Differences found at line 902. - + ROUTED met1 ( 7751 459 ) ( 8241 * ) - + ROUTED met1 ( 8252 119 ) ( 8257 * ) +No differences found. +No differences found. No differences found. diff --git a/src/ram/test/make_8x8_mux4_sky130.lefok b/src/ram/test/make_8x8_mux4_sky130.lefok index fce97e84ac7..dc3fb381c1f 100644 --- a/src/ram/test/make_8x8_mux4_sky130.lefok +++ b/src/ram/test/make_8x8_mux4_sky130.lefok @@ -177,103 +177,6 @@ MACRO RAM8x8 RECT 347 7.675 347.14 8.16 ; END END Q[7] - PIN VSS - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER met3 ; - RECT 419.68 6.76 419.98 7.24 ; - RECT 0 6.76 0.3 7.24 ; - LAYER met2 ; - RECT 409.76 8.02 410.24 8.16 ; - RECT 409.76 0 410.24 0.14 ; - RECT 399.76 8.02 400.24 8.16 ; - RECT 399.76 0 400.24 0.14 ; - RECT 389.76 8.02 390.24 8.16 ; - RECT 389.76 0 390.24 0.14 ; - RECT 379.76 8.02 380.24 8.16 ; - RECT 379.76 0 380.24 0.14 ; - RECT 369.76 8.02 370.24 8.16 ; - RECT 369.76 0 370.24 0.14 ; - RECT 359.76 8.02 360.24 8.16 ; - RECT 359.76 0 360.24 0.14 ; - RECT 349.76 8.02 350.24 8.16 ; - RECT 349.76 0 350.24 0.14 ; - RECT 339.76 8.02 340.24 8.16 ; - RECT 339.76 0 340.24 0.14 ; - RECT 329.76 8.02 330.24 8.16 ; - RECT 329.76 0 330.24 0.14 ; - RECT 319.76 8.02 320.24 8.16 ; - RECT 319.76 0 320.24 0.14 ; - RECT 309.76 8.02 310.24 8.16 ; - RECT 309.76 0 310.24 0.14 ; - RECT 299.76 8.02 300.24 8.16 ; - RECT 299.76 0 300.24 0.14 ; - RECT 289.76 8.02 290.24 8.16 ; - RECT 289.76 0 290.24 0.14 ; - RECT 279.76 8.02 280.24 8.16 ; - RECT 279.76 0 280.24 0.14 ; - RECT 269.76 8.02 270.24 8.16 ; - RECT 269.76 0 270.24 0.14 ; - RECT 259.76 8.02 260.24 8.16 ; - RECT 259.76 0 260.24 0.14 ; - RECT 249.76 8.02 250.24 8.16 ; - RECT 249.76 0 250.24 0.14 ; - RECT 239.76 8.02 240.24 8.16 ; - RECT 239.76 0 240.24 0.14 ; - RECT 229.76 8.02 230.24 8.16 ; - RECT 229.76 0 230.24 0.14 ; - RECT 219.76 8.02 220.24 8.16 ; - RECT 219.76 0 220.24 0.14 ; - RECT 209.76 8.02 210.24 8.16 ; - RECT 209.76 0 210.24 0.14 ; - RECT 199.76 8.02 200.24 8.16 ; - RECT 199.76 0 200.24 0.14 ; - RECT 189.76 8.02 190.24 8.16 ; - RECT 189.76 0 190.24 0.14 ; - RECT 179.76 8.02 180.24 8.16 ; - RECT 179.76 0 180.24 0.14 ; - RECT 169.76 8.02 170.24 8.16 ; - RECT 169.76 0 170.24 0.14 ; - RECT 159.76 8.02 160.24 8.16 ; - RECT 159.76 0 160.24 0.14 ; - RECT 149.76 8.02 150.24 8.16 ; - RECT 149.76 0 150.24 0.14 ; - RECT 139.76 8.02 140.24 8.16 ; - RECT 139.76 0 140.24 0.14 ; - RECT 129.76 8.02 130.24 8.16 ; - RECT 129.76 0 130.24 0.14 ; - RECT 119.76 8.02 120.24 8.16 ; - RECT 119.76 0 120.24 0.14 ; - RECT 109.76 8.02 110.24 8.16 ; - RECT 109.76 0 110.24 0.14 ; - RECT 99.76 8.02 100.24 8.16 ; - RECT 99.76 0 100.24 0.14 ; - RECT 89.76 8.02 90.24 8.16 ; - RECT 89.76 0 90.24 0.14 ; - RECT 79.76 8.02 80.24 8.16 ; - RECT 79.76 0 80.24 0.14 ; - RECT 69.76 8.02 70.24 8.16 ; - RECT 69.76 0 70.24 0.14 ; - RECT 59.76 8.02 60.24 8.16 ; - RECT 59.76 0 60.24 0.14 ; - RECT 49.76 8.02 50.24 8.16 ; - RECT 49.76 0 50.24 0.14 ; - RECT 39.76 8.02 40.24 8.16 ; - RECT 39.76 0 40.24 0.14 ; - RECT 29.76 8.02 30.24 8.16 ; - RECT 29.76 0 30.24 0.14 ; - RECT 19.76 8.02 20.24 8.16 ; - RECT 19.76 0 20.24 0.14 ; - RECT 9.76 8.02 10.24 8.16 ; - RECT 9.76 0 10.24 0.14 ; - LAYER met1 ; - RECT 419.84 5.2 419.98 5.68 ; - RECT 0 5.2 0.14 5.68 ; - RECT 419.84 -0.24 419.98 0.24 ; - RECT 0 -0.24 0.14 0.24 ; - END - END VSS PIN VDD DIRECTION INOUT ; USE POWER ; @@ -373,6 +276,103 @@ MACRO RAM8x8 RECT 0 2.48 0.14 2.96 ; END END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER met3 ; + RECT 419.68 6.76 419.98 7.24 ; + RECT 0 6.76 0.3 7.24 ; + LAYER met2 ; + RECT 409.76 8.02 410.24 8.16 ; + RECT 409.76 0 410.24 0.14 ; + RECT 399.76 8.02 400.24 8.16 ; + RECT 399.76 0 400.24 0.14 ; + RECT 389.76 8.02 390.24 8.16 ; + RECT 389.76 0 390.24 0.14 ; + RECT 379.76 8.02 380.24 8.16 ; + RECT 379.76 0 380.24 0.14 ; + RECT 369.76 8.02 370.24 8.16 ; + RECT 369.76 0 370.24 0.14 ; + RECT 359.76 8.02 360.24 8.16 ; + RECT 359.76 0 360.24 0.14 ; + RECT 349.76 8.02 350.24 8.16 ; + RECT 349.76 0 350.24 0.14 ; + RECT 339.76 8.02 340.24 8.16 ; + RECT 339.76 0 340.24 0.14 ; + RECT 329.76 8.02 330.24 8.16 ; + RECT 329.76 0 330.24 0.14 ; + RECT 319.76 8.02 320.24 8.16 ; + RECT 319.76 0 320.24 0.14 ; + RECT 309.76 8.02 310.24 8.16 ; + RECT 309.76 0 310.24 0.14 ; + RECT 299.76 8.02 300.24 8.16 ; + RECT 299.76 0 300.24 0.14 ; + RECT 289.76 8.02 290.24 8.16 ; + RECT 289.76 0 290.24 0.14 ; + RECT 279.76 8.02 280.24 8.16 ; + RECT 279.76 0 280.24 0.14 ; + RECT 269.76 8.02 270.24 8.16 ; + RECT 269.76 0 270.24 0.14 ; + RECT 259.76 8.02 260.24 8.16 ; + RECT 259.76 0 260.24 0.14 ; + RECT 249.76 8.02 250.24 8.16 ; + RECT 249.76 0 250.24 0.14 ; + RECT 239.76 8.02 240.24 8.16 ; + RECT 239.76 0 240.24 0.14 ; + RECT 229.76 8.02 230.24 8.16 ; + RECT 229.76 0 230.24 0.14 ; + RECT 219.76 8.02 220.24 8.16 ; + RECT 219.76 0 220.24 0.14 ; + RECT 209.76 8.02 210.24 8.16 ; + RECT 209.76 0 210.24 0.14 ; + RECT 199.76 8.02 200.24 8.16 ; + RECT 199.76 0 200.24 0.14 ; + RECT 189.76 8.02 190.24 8.16 ; + RECT 189.76 0 190.24 0.14 ; + RECT 179.76 8.02 180.24 8.16 ; + RECT 179.76 0 180.24 0.14 ; + RECT 169.76 8.02 170.24 8.16 ; + RECT 169.76 0 170.24 0.14 ; + RECT 159.76 8.02 160.24 8.16 ; + RECT 159.76 0 160.24 0.14 ; + RECT 149.76 8.02 150.24 8.16 ; + RECT 149.76 0 150.24 0.14 ; + RECT 139.76 8.02 140.24 8.16 ; + RECT 139.76 0 140.24 0.14 ; + RECT 129.76 8.02 130.24 8.16 ; + RECT 129.76 0 130.24 0.14 ; + RECT 119.76 8.02 120.24 8.16 ; + RECT 119.76 0 120.24 0.14 ; + RECT 109.76 8.02 110.24 8.16 ; + RECT 109.76 0 110.24 0.14 ; + RECT 99.76 8.02 100.24 8.16 ; + RECT 99.76 0 100.24 0.14 ; + RECT 89.76 8.02 90.24 8.16 ; + RECT 89.76 0 90.24 0.14 ; + RECT 79.76 8.02 80.24 8.16 ; + RECT 79.76 0 80.24 0.14 ; + RECT 69.76 8.02 70.24 8.16 ; + RECT 69.76 0 70.24 0.14 ; + RECT 59.76 8.02 60.24 8.16 ; + RECT 59.76 0 60.24 0.14 ; + RECT 49.76 8.02 50.24 8.16 ; + RECT 49.76 0 50.24 0.14 ; + RECT 39.76 8.02 40.24 8.16 ; + RECT 39.76 0 40.24 0.14 ; + RECT 29.76 8.02 30.24 8.16 ; + RECT 29.76 0 30.24 0.14 ; + RECT 19.76 8.02 20.24 8.16 ; + RECT 19.76 0 20.24 0.14 ; + RECT 9.76 8.02 10.24 8.16 ; + RECT 9.76 0 10.24 0.14 ; + LAYER met1 ; + RECT 419.84 5.2 419.98 5.68 ; + RECT 0 5.2 0.14 5.68 ; + RECT 419.84 -0.24 419.98 0.24 ; + RECT 0 -0.24 0.14 0.24 ; + END + END VSS OBS LAYER li1 ; RECT 0 -0.24 419.98 8.4 ; diff --git a/src/ram/test/make_8x8_mux4_sky130.ok b/src/ram/test/make_8x8_mux4_sky130.ok index 801cf736921..296225ac6a0 100644 --- a/src/ram/test/make_8x8_mux4_sky130.ok +++ b/src/ram/test/make_8x8_mux4_sky130.ok @@ -60,7 +60,7 @@ [INFO DRT-0036] FR_VIA guide region query size = 0. [INFO DRT-0036] li1 guide region query size = 449. [INFO DRT-0036] mcon guide region query size = 0. -[INFO DRT-0036] met1 guide region query size = 298. +[INFO DRT-0036] met1 guide region query size = 299. [INFO DRT-0036] via guide region query size = 0. [INFO DRT-0036] met2 guide region query size = 73. [INFO DRT-0036] via2 guide region query size = 0. @@ -70,10 +70,6 @@ [INFO DRT-0036] via4 guide region query size = 0. [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. -Differences found at line 180. - PIN VSS - PIN VDD -Differences found at line 1222. - + ROUTED met1 ( 8252 425 ) ( 8257 * ) - + ROUTED met1 ( 4802 425 ) ( 4807 * ) +No differences found. +No differences found. No differences found. From 025ef1297ee22ae2945bcbc7d07c3dd99c70e5f0 Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Mon, 6 Jul 2026 14:10:07 -0400 Subject: [PATCH 09/19] ram: use sta units for timing and power log output, update latch tcl to specify cell Signed-off-by: Thinh Nguyen --- src/ram/src/ram.cpp | 118 +- src/ram/test/make_7x7_2r1w_nangate45.ok | 6 +- src/ram/test/make_7x7_nangate45.ok | 6 +- src/ram/test/make_8x8_2r1w_sky130.ok | 6 +- src/ram/test/make_8x8_latch_sky130.defok | 4100 +++++++++++----------- src/ram/test/make_8x8_latch_sky130.lefok | 119 +- src/ram/test/make_8x8_latch_sky130.ok | 23 +- src/ram/test/make_8x8_latch_sky130.tcl | 1 + src/ram/test/make_8x8_mux2_sky130.ok | 6 +- src/ram/test/make_8x8_mux4_sky130.ok | 6 +- src/ram/test/make_8x8_sky130.ok | 6 +- 11 files changed, 2198 insertions(+), 2199 deletions(-) diff --git a/src/ram/src/ram.cpp b/src/ram/src/ram.cpp index aa6a3374f0f..e099343e8e2 100644 --- a/src/ram/src/ram.cpp +++ b/src/ram/src/ram.cpp @@ -39,6 +39,7 @@ #include "sta/SearchClass.hh" #include "sta/Sequential.hh" #include "sta/StringUtil.hh" +#include "sta/Units.hh" #include "utl/Logger.h" namespace ram { @@ -2074,37 +2075,30 @@ void RamGen::reportTimingAndPower() sta::SceneSeq scenes = sta_->makeSceneSeq(sta_->cmdScene()); - if (scenes.empty()) { - logger_->warn(RAM, - 47, - "No Liberty libraries loaded. Please run read_liberty before " - "generate_ram to enable timing and power report."); - return; - } - sta::StringSeq group_names; // Find worst unconstrained setup path delay/longest path - sta::PathEndSeq setup_ends = sta_->findPathEnds(nullptr, - nullptr, - nullptr, - true, - scenes, - sta::MinMaxAll::max(), - 1, - 1, - false, - false, - -sta::INF, - sta::INF, - true, - group_names, - true, - false, - false, - false, - false, - false); + sta::PathEndSeq setup_ends + = sta_->findPathEnds(nullptr, /* from */ + nullptr, /* thrus */ + nullptr, /* to */ + true, /* unconstrained */ + scenes, /* scenes */ + sta::MinMaxAll::max(), /* min_max */ + 1, /* group_path_count */ + 1, /* endpoint_path_count */ + false, /* unique_pins */ + false, /* unique_edges */ + -sta::INF, /* slack_min */ + sta::INF, /* slack_max */ + true, /* sort_by_slack */ + group_names, /* group_names */ + true, /* setup */ + false, /* hold */ + false, /* recovery */ + false, /* removal */ + false, /* clk_gating_setup */ + false); /* clk_gating_hold */ float setup_delay = setup_ends.empty() @@ -2112,43 +2106,55 @@ void RamGen::reportTimingAndPower() : static_cast(setup_ends[0]->dataArrivalTime(sta_)); // Find worst unconstrained hold path delay/shortest path - sta::PathEndSeq hold_ends = sta_->findPathEnds(nullptr, - nullptr, - nullptr, - true, - scenes, - sta::MinMaxAll::min(), - 1, - 1, - false, - false, - -sta::INF, - sta::INF, - true, - group_names, - false, - true, - false, - false, - false, - false); + sta::PathEndSeq hold_ends + = sta_->findPathEnds(nullptr, /* from */ + nullptr, /* thrus */ + nullptr, /* to */ + true, /* unconstrained */ + scenes, /* scenes */ + sta::MinMaxAll::min(), /* min_max */ + 1, /* group_path_count */ + 1, /* endpoint_path_count */ + false, /* unique_pins */ + false, /* unique_edges */ + -sta::INF, /* slack_min */ + sta::INF, /* slack_max */ + true, /* sort_by_slack */ + group_names, /* group_names */ + false, /* setup */ + true, /* hold */ + false, /* recovery */ + false, /* removal */ + false, /* clk_gating_setup */ + false); /* clk_gating_hold */ float hold_delay = hold_ends.empty() ? 0.0 : static_cast(hold_ends[0]->dataArrivalTime(sta_)); - logger_->info( - RAM, 44, "RAM worst setup path delay: {:.6f} ns", setup_delay * 1e9); - logger_->info( - RAM, 45, "RAM worst hold path delay: {:.6f} ns", hold_delay * 1e9); - - // Power without activity factor/leakage power + sta::Unit* time_unit = sta_->units()->timeUnit(); + logger_->info(RAM, + 44, + "RAM maximum path delay: {} {}", + time_unit->asString(setup_delay), + time_unit->scaleAbbrevSuffix()); + logger_->info(RAM, + 45, + "RAM minimum path delay: {} {}", + time_unit->asString(hold_delay), + time_unit->scaleAbbrevSuffix()); + + // Estimated power (STA applies a default activity when none is set) sta::PowerResult total, sequential, combinational, clock, macro, pad; sta_->power( sta_->cmdScene(), total, sequential, combinational, clock, macro, pad); - logger_->info( - RAM, 46, "RAM total power (no activity): {:.6f} W", total.total()); + sta::Unit* power_unit = sta_->units()->powerUnit(); + logger_->info(RAM, + 46, + "RAM estimated power: {} {}", + power_unit->asString(total.total()), + power_unit->scaleAbbrevSuffix()); } } // namespace ram diff --git a/src/ram/test/make_7x7_2r1w_nangate45.ok b/src/ram/test/make_7x7_2r1w_nangate45.ok index b6e1eff205c..52e09b50ba4 100644 --- a/src/ram/test/make_7x7_2r1w_nangate45.ok +++ b/src/ram/test/make_7x7_2r1w_nangate45.ok @@ -28,9 +28,9 @@ [INFO RAM-0016] Selected buffer cell BUF_X1 [INFO RAM-0016] Selected aoi22 cell AOI22_X1 [INFO RAM-0024] Behavioral Verilog written for RAM7x7 -[INFO RAM-0044] RAM worst setup path delay: 0.265428 ns -[INFO RAM-0045] RAM worst hold path delay: 0.000000 ns -[INFO RAM-0046] RAM total power (no activity): 0.000079 W +[INFO RAM-0044] RAM maximum path delay: 0.265 ns +[INFO RAM-0045] RAM minimum path delay: 0.000 ns +[INFO RAM-0046] RAM estimated power: 79128.938 nW [INFO PDN-0001] Inserting grid: ram_grid [WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (4.5000 um, 4.0000 um) for VDD [WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (9.0000 um, 8.0000 um) for VSS diff --git a/src/ram/test/make_7x7_nangate45.ok b/src/ram/test/make_7x7_nangate45.ok index 9f8288c8e23..e5373c81654 100644 --- a/src/ram/test/make_7x7_nangate45.ok +++ b/src/ram/test/make_7x7_nangate45.ok @@ -28,9 +28,9 @@ [INFO RAM-0016] Selected buffer cell BUF_X1 [INFO RAM-0016] Selected aoi22 cell AOI22_X1 [INFO RAM-0024] Behavioral Verilog written for RAM7x7 -[INFO RAM-0044] RAM worst setup path delay: 0.267573 ns -[INFO RAM-0045] RAM worst hold path delay: 0.000000 ns -[INFO RAM-0046] RAM total power (no activity): 0.000053 W +[INFO RAM-0044] RAM maximum path delay: 0.268 ns +[INFO RAM-0045] RAM minimum path delay: 0.000 ns +[INFO RAM-0046] RAM estimated power: 52755.473 nW [INFO PDN-0001] Inserting grid: ram_grid [WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (4.5000 um, 4.0000 um) for VDD [WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (9.0000 um, 8.0000 um) for VSS diff --git a/src/ram/test/make_8x8_2r1w_sky130.ok b/src/ram/test/make_8x8_2r1w_sky130.ok index c3571893cf2..05981fb0424 100644 --- a/src/ram/test/make_8x8_2r1w_sky130.ok +++ b/src/ram/test/make_8x8_2r1w_sky130.ok @@ -8,9 +8,9 @@ [INFO RAM-0016] Selected buffer cell sky130_fd_sc_hd__buf_1 [INFO RAM-0016] Selected aoi22 cell sky130_fd_sc_hd__a22oi_1 [INFO RAM-0024] Behavioral Verilog written for RAM8x8 -[INFO RAM-0044] RAM worst setup path delay: 0.858868 ns -[INFO RAM-0045] RAM worst hold path delay: 0.000000 ns -[INFO RAM-0046] RAM total power (no activity): 0.000360 W +[INFO RAM-0044] RAM maximum path delay: 0.859 ns +[INFO RAM-0045] RAM minimum path delay: 0.000 ns +[INFO RAM-0046] RAM estimated power: 360445.062 nW [INFO PDN-0001] Inserting grid: ram_grid [INFO PPL-0067] Restrict pins [ clk we[0] D[0] Q0[0] Q1[0] ... ] to region 0.00u-155.02u at the TOP edge. [INFO PPL-0067] Restrict pins [ addr_w[0] addr_w[1] addr_w[2] addr_r0[0] addr_r0[1] ... ] to region 0.00u-24.48u at the RIGHT edge. diff --git a/src/ram/test/make_8x8_latch_sky130.defok b/src/ram/test/make_8x8_latch_sky130.defok index 30e7c486ba9..e13f27e12d0 100644 --- a/src/ram/test/make_8x8_latch_sky130.defok +++ b/src/ram/test/make_8x8_latch_sky130.defok @@ -3,28 +3,28 @@ DIVIDERCHAR "/" ; BUSBITCHARS "[]" ; DESIGN RAM8x8 ; UNITS DISTANCE MICRONS 100 ; -DIEAREA ( 0 0 ) ( 9200 2720 ) ; -ROW RAM_ROW0 unithd 0 0 N DO 200 BY 1 STEP 46 0 ; -ROW RAM_ROW1 unithd 0 272 FS DO 200 BY 1 STEP 46 0 ; -ROW RAM_ROW2 unithd 0 544 N DO 200 BY 1 STEP 46 0 ; -ROW RAM_ROW3 unithd 0 816 FS DO 200 BY 1 STEP 46 0 ; -ROW RAM_ROW4 unithd 0 1088 N DO 200 BY 1 STEP 46 0 ; -ROW RAM_ROW5 unithd 0 1360 FS DO 200 BY 1 STEP 46 0 ; -ROW RAM_ROW6 unithd 0 1632 N DO 200 BY 1 STEP 46 0 ; -ROW RAM_ROW7 unithd 0 1904 FS DO 200 BY 1 STEP 46 0 ; -ROW RAM_ROW8 unithd 0 2176 N DO 200 BY 1 STEP 46 0 ; -ROW RAM_ROW9 unithd 0 2448 FS DO 200 BY 1 STEP 46 0 ; -TRACKS X 23 DO 200 STEP 46 LAYER li1 ; +DIEAREA ( 0 0 ) ( 9568 2720 ) ; +ROW RAM_ROW0 unithd 0 0 N DO 208 BY 1 STEP 46 0 ; +ROW RAM_ROW1 unithd 0 272 FS DO 208 BY 1 STEP 46 0 ; +ROW RAM_ROW2 unithd 0 544 N DO 208 BY 1 STEP 46 0 ; +ROW RAM_ROW3 unithd 0 816 FS DO 208 BY 1 STEP 46 0 ; +ROW RAM_ROW4 unithd 0 1088 N DO 208 BY 1 STEP 46 0 ; +ROW RAM_ROW5 unithd 0 1360 FS DO 208 BY 1 STEP 46 0 ; +ROW RAM_ROW6 unithd 0 1632 N DO 208 BY 1 STEP 46 0 ; +ROW RAM_ROW7 unithd 0 1904 FS DO 208 BY 1 STEP 46 0 ; +ROW RAM_ROW8 unithd 0 2176 N DO 208 BY 1 STEP 46 0 ; +ROW RAM_ROW9 unithd 0 2448 FS DO 208 BY 1 STEP 46 0 ; +TRACKS X 23 DO 208 STEP 46 LAYER li1 ; TRACKS Y 17 DO 80 STEP 34 LAYER li1 ; -TRACKS X 17 DO 270 STEP 34 LAYER met1 ; +TRACKS X 17 DO 281 STEP 34 LAYER met1 ; TRACKS Y 17 DO 80 STEP 34 LAYER met1 ; -TRACKS X 23 DO 200 STEP 46 LAYER met2 ; +TRACKS X 23 DO 208 STEP 46 LAYER met2 ; TRACKS Y 23 DO 59 STEP 46 LAYER met2 ; -TRACKS X 34 DO 135 STEP 68 LAYER met3 ; +TRACKS X 34 DO 140 STEP 68 LAYER met3 ; TRACKS Y 34 DO 40 STEP 68 LAYER met3 ; -TRACKS X 46 DO 100 STEP 92 LAYER met4 ; +TRACKS X 46 DO 104 STEP 92 LAYER met4 ; TRACKS Y 46 DO 29 STEP 92 LAYER met4 ; -TRACKS X 170 DO 27 STEP 340 LAYER met5 ; +TRACKS X 170 DO 28 STEP 340 LAYER met5 ; TRACKS Y 170 DO 8 STEP 340 LAYER met5 ; GCELLGRID X 0 DO 13 STEP 690 ; GCELLGRID Y 0 DO 3 STEP 690 ; @@ -32,251 +32,259 @@ VIAS 2 ; - via2_3_480_480_1_1_320_320 + VIARULE M1M2_PR + CUTSIZE 15 15 + LAYERS met1 via met2 + CUTSPACING 17 17 + ENCLOSURE 8 16 16 8 ; - via3_4_480_480_1_1_400_400 + VIARULE M2M3_PR + CUTSIZE 20 20 + LAYERS met2 via2 met3 + CUTSPACING 20 20 + ENCLOSURE 14 8 6 14 ; END VIAS -COMPONENTS 344 ; - - FILLER_1_197 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 9062 272 ) FS ; - - FILLER_1_199 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9154 272 ) FS ; - - FILLER_3_197 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 9062 816 ) FS ; - - FILLER_3_199 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9154 816 ) FS ; - - FILLER_5_197 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 9062 1360 ) FS ; - - FILLER_5_199 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9154 1360 ) FS ; - - FILLER_6_197 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 9062 1632 ) N ; - - FILLER_6_199 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9154 1632 ) N ; - - FILLER_7_197 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 9062 1904 ) FS ; - - FILLER_7_199 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9154 1904 ) FS ; - - FILLER_8_112 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 5152 2176 ) N ; - - FILLER_8_12 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 552 2176 ) N ; - - FILLER_8_132 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 6072 2176 ) N ; - - FILLER_8_152 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 6992 2176 ) N ; - - FILLER_8_164 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 7544 2176 ) N ; +COMPONENTS 352 ; + - FILLER_1_205 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 9430 272 ) FS ; + - FILLER_1_207 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9522 272 ) FS ; + - FILLER_3_205 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 9430 816 ) FS ; + - FILLER_3_207 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9522 816 ) FS ; + - FILLER_5_205 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 9430 1360 ) FS ; + - FILLER_5_207 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9522 1360 ) FS ; + - FILLER_6_205 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 9430 1632 ) N ; + - FILLER_6_207 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9522 1632 ) N ; + - FILLER_7_205 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 9430 1904 ) FS ; + - FILLER_7_207 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9522 1904 ) FS ; + - FILLER_8_118 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 5428 2176 ) N ; + - FILLER_8_13 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 598 2176 ) N ; + - FILLER_8_139 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 6394 2176 ) N ; + - FILLER_8_160 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 7360 2176 ) N ; - FILLER_8_172 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 7912 2176 ) N ; - - FILLER_8_180 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 8280 2176 ) N ; - - FILLER_8_184 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 8464 2176 ) N ; - - FILLER_8_187 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 8602 2176 ) N ; - - FILLER_8_195 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 8970 2176 ) N ; - - FILLER_8_199 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9154 2176 ) N ; - - FILLER_8_32 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 1472 2176 ) N ; - - FILLER_8_52 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 2392 2176 ) N ; - - FILLER_8_72 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 3312 2176 ) N ; - - FILLER_8_92 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 4232 2176 ) N ; - - FILLER_9_104 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 4784 2448 ) FS ; - - FILLER_9_112 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 5152 2448 ) FS ; + - FILLER_8_180 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 8280 2176 ) N ; + - FILLER_8_188 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 8648 2176 ) N ; + - FILLER_8_192 sky130_fd_sc_hd__fill_2 + SOURCE DIST + PLACED ( 8832 2176 ) N ; + - FILLER_8_195 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 8970 2176 ) N ; + - FILLER_8_203 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 9338 2176 ) N ; + - FILLER_8_207 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9522 2176 ) N ; + - FILLER_8_34 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 1564 2176 ) N ; + - FILLER_8_55 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 2530 2176 ) N ; + - FILLER_8_76 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 3496 2176 ) N ; + - FILLER_8_97 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 4462 2176 ) N ; + - FILLER_9_104 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 4784 2448 ) FS ; + - FILLER_9_109 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 5014 2448 ) FS ; + - FILLER_9_117 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 5382 2448 ) FS ; - FILLER_9_12 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 552 2448 ) FS ; - - FILLER_9_124 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 5704 2448 ) FS ; - - FILLER_9_132 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 6072 2448 ) FS ; - - FILLER_9_144 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 6624 2448 ) FS ; - - FILLER_9_152 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 6992 2448 ) FS ; - - FILLER_9_161 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 7406 2448 ) FS ; + - FILLER_9_125 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 5750 2448 ) FS ; + - FILLER_9_130 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 5980 2448 ) FS ; + - FILLER_9_138 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 6348 2448 ) FS ; + - FILLER_9_146 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 6716 2448 ) FS ; + - FILLER_9_151 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 6946 2448 ) FS ; + - FILLER_9_159 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 7314 2448 ) FS ; + - FILLER_9_167 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 7682 2448 ) FS ; - FILLER_9_169 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 7774 2448 ) FS ; - FILLER_9_177 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 8142 2448 ) FS ; - - FILLER_9_185 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 8510 2448 ) FS ; - - FILLER_9_187 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 8602 2448 ) FS ; - - FILLER_9_195 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 8970 2448 ) FS ; - - FILLER_9_199 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9154 2448 ) FS ; - - FILLER_9_24 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 1104 2448 ) FS ; - - FILLER_9_32 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 1472 2448 ) FS ; + - FILLER_9_185 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 8510 2448 ) FS ; + - FILLER_9_193 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 8878 2448 ) FS ; + - FILLER_9_195 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 8970 2448 ) FS ; + - FILLER_9_20 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 920 2448 ) FS ; + - FILLER_9_203 sky130_fd_sc_hd__fill_4 + SOURCE DIST + PLACED ( 9338 2448 ) FS ; + - FILLER_9_207 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 9522 2448 ) FS ; + - FILLER_9_25 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 1150 2448 ) FS ; + - FILLER_9_33 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 1518 2448 ) FS ; - FILLER_9_4 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 184 2448 ) FS ; - - FILLER_9_44 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 2024 2448 ) FS ; - - FILLER_9_52 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 2392 2448 ) FS ; - - FILLER_9_64 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 2944 2448 ) FS ; - - FILLER_9_72 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 3312 2448 ) FS ; - - FILLER_9_84 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 3864 2448 ) FS ; - - FILLER_9_92 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 4232 2448 ) FS ; + - FILLER_9_41 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 1886 2448 ) FS ; + - FILLER_9_46 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 2116 2448 ) FS ; + - FILLER_9_54 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 2484 2448 ) FS ; + - FILLER_9_62 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 2852 2448 ) FS ; + - FILLER_9_67 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 3082 2448 ) FS ; + - FILLER_9_75 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 3450 2448 ) FS ; + - FILLER_9_83 sky130_fd_sc_hd__fill_1 + SOURCE DIST + PLACED ( 3818 2448 ) FS ; + - FILLER_9_88 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 4048 2448 ) FS ; + - FILLER_9_96 sky130_fd_sc_hd__fill_8 + SOURCE DIST + PLACED ( 4416 2448 ) FS ; - buffer.in[0] sky130_fd_sc_hd__buf_1 + PLACED ( 46 2448 ) FS ; - - buffer.in[1] sky130_fd_sc_hd__buf_1 + PLACED ( 966 2448 ) FS ; - - buffer.in[2] sky130_fd_sc_hd__buf_1 + PLACED ( 1886 2448 ) FS ; - - buffer.in[3] sky130_fd_sc_hd__buf_1 + PLACED ( 2806 2448 ) FS ; - - buffer.in[4] sky130_fd_sc_hd__buf_1 + PLACED ( 3726 2448 ) FS ; - - buffer.in[5] sky130_fd_sc_hd__buf_1 + PLACED ( 4646 2448 ) FS ; - - buffer.in[6] sky130_fd_sc_hd__buf_1 + PLACED ( 5566 2448 ) FS ; - - buffer.in[7] sky130_fd_sc_hd__buf_1 + PLACED ( 6486 2448 ) FS ; - - decoder_p0.and_layer0_word0 sky130_fd_sc_hd__and2_0 + PLACED ( 8602 0 ) N ; - - decoder_p0.and_layer0_word1 sky130_fd_sc_hd__and2_0 + PLACED ( 8602 272 ) FS ; - - decoder_p0.and_layer0_word2 sky130_fd_sc_hd__and2_0 + PLACED ( 8602 544 ) N ; - - decoder_p0.and_layer0_word3 sky130_fd_sc_hd__and2_0 + PLACED ( 8602 816 ) FS ; - - decoder_p0.and_layer0_word4 sky130_fd_sc_hd__and2_0 + PLACED ( 8602 1088 ) N ; - - decoder_p0.and_layer0_word5 sky130_fd_sc_hd__and2_0 + PLACED ( 8602 1360 ) FS ; - - decoder_p0.and_layer0_word6 sky130_fd_sc_hd__and2_0 + PLACED ( 8602 1632 ) N ; - - decoder_p0.and_layer0_word7 sky130_fd_sc_hd__and2_0 + PLACED ( 8602 1904 ) FS ; - - decoder_p0.and_layer1_word0 sky130_fd_sc_hd__and2_0 + PLACED ( 8832 0 ) N ; - - decoder_p0.and_layer1_word1 sky130_fd_sc_hd__and2_0 + PLACED ( 8832 272 ) FS ; - - decoder_p0.and_layer1_word2 sky130_fd_sc_hd__and2_0 + PLACED ( 8832 544 ) N ; - - decoder_p0.and_layer1_word3 sky130_fd_sc_hd__and2_0 + PLACED ( 8832 816 ) FS ; - - decoder_p0.and_layer1_word4 sky130_fd_sc_hd__and2_0 + PLACED ( 8832 1088 ) N ; - - decoder_p0.and_layer1_word5 sky130_fd_sc_hd__and2_0 + PLACED ( 8832 1360 ) FS ; - - decoder_p0.and_layer1_word6 sky130_fd_sc_hd__and2_0 + PLACED ( 8832 1632 ) N ; - - decoder_p0.and_layer1_word7 sky130_fd_sc_hd__and2_0 + PLACED ( 8832 1904 ) FS ; - - decoder_p0.inv_p0_a0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 9062 1088 ) N ; - - decoder_p0.inv_p0_a1 sky130_fd_sc_hd__clkinv_1 + PLACED ( 9062 544 ) N ; - - decoder_p0.inv_p0_a2 sky130_fd_sc_hd__clkinv_1 + PLACED ( 9062 0 ) N ; - - neg_lat_b0.nlat sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 46 2176 ) N ; - - neg_lat_b1.nlat sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 966 2176 ) N ; - - neg_lat_b2.nlat sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 1886 2176 ) N ; - - neg_lat_b3.nlat sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 2806 2176 ) N ; - - neg_lat_b4.nlat sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 3726 2176 ) N ; - - neg_lat_b5.nlat sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 4646 2176 ) N ; - - neg_lat_b6.nlat sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 5566 2176 ) N ; - - neg_lat_b7.nlat sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 6486 2176 ) N ; - - neg_row.clk_inv sky130_fd_sc_hd__clkinv_1 + PLACED ( 7406 2176 ) N ; - - sel_buf_rw_p0.sel_buf_0 sky130_fd_sc_hd__buf_1 + PLACED ( 8418 0 ) N ; - - sel_buf_rw_p0.sel_buf_1 sky130_fd_sc_hd__buf_1 + PLACED ( 8418 272 ) FS ; - - sel_buf_rw_p0.sel_buf_2 sky130_fd_sc_hd__buf_1 + PLACED ( 8418 544 ) N ; - - sel_buf_rw_p0.sel_buf_3 sky130_fd_sc_hd__buf_1 + PLACED ( 8418 816 ) FS ; - - sel_buf_rw_p0.sel_buf_4 sky130_fd_sc_hd__buf_1 + PLACED ( 8418 1088 ) N ; - - sel_buf_rw_p0.sel_buf_5 sky130_fd_sc_hd__buf_1 + PLACED ( 8418 1360 ) FS ; - - sel_buf_rw_p0.sel_buf_6 sky130_fd_sc_hd__buf_1 + PLACED ( 8418 1632 ) N ; - - sel_buf_rw_p0.sel_buf_7 sky130_fd_sc_hd__buf_1 + PLACED ( 8418 1904 ) FS ; - - storage_0_0_0.bit0.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 46 0 ) N ; - - storage_0_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 552 0 ) N ; - - storage_0_0_0.bit1.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 966 0 ) N ; - - storage_0_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1472 0 ) N ; - - storage_0_0_0.bit2.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 1886 0 ) N ; - - storage_0_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2392 0 ) N ; - - storage_0_0_0.bit3.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 2806 0 ) N ; - - storage_0_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3312 0 ) N ; - - storage_0_0_0.bit4.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 3726 0 ) N ; - - storage_0_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 0 ) N ; - - storage_0_0_0.bit5.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 4646 0 ) N ; - - storage_0_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5152 0 ) N ; - - storage_0_0_0.bit6.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 5566 0 ) N ; - - storage_0_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6072 0 ) N ; - - storage_0_0_0.bit7.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 6486 0 ) N ; - - storage_0_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6992 0 ) N ; - - storage_0_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7406 0 ) N ; - - storage_0_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8050 0 ) N ; - - storage_0_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8280 0 ) N ; - - storage_1_0_0.bit0.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 46 272 ) FS ; - - storage_1_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 552 272 ) FS ; - - storage_1_0_0.bit1.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 966 272 ) FS ; - - storage_1_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1472 272 ) FS ; - - storage_1_0_0.bit2.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 1886 272 ) FS ; - - storage_1_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2392 272 ) FS ; - - storage_1_0_0.bit3.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 2806 272 ) FS ; - - storage_1_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3312 272 ) FS ; - - storage_1_0_0.bit4.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 3726 272 ) FS ; - - storage_1_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 272 ) FS ; - - storage_1_0_0.bit5.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 4646 272 ) FS ; - - storage_1_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5152 272 ) FS ; - - storage_1_0_0.bit6.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 5566 272 ) FS ; - - storage_1_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6072 272 ) FS ; - - storage_1_0_0.bit7.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 6486 272 ) FS ; - - storage_1_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6992 272 ) FS ; - - storage_1_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7406 272 ) FS ; - - storage_1_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8050 272 ) FS ; - - storage_1_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8280 272 ) FS ; - - storage_2_0_0.bit0.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 46 544 ) N ; - - storage_2_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 552 544 ) N ; - - storage_2_0_0.bit1.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 966 544 ) N ; - - storage_2_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1472 544 ) N ; - - storage_2_0_0.bit2.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 1886 544 ) N ; - - storage_2_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2392 544 ) N ; - - storage_2_0_0.bit3.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 2806 544 ) N ; - - storage_2_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3312 544 ) N ; - - storage_2_0_0.bit4.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 3726 544 ) N ; - - storage_2_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 544 ) N ; - - storage_2_0_0.bit5.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 4646 544 ) N ; - - storage_2_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5152 544 ) N ; - - storage_2_0_0.bit6.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 5566 544 ) N ; - - storage_2_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6072 544 ) N ; - - storage_2_0_0.bit7.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 6486 544 ) N ; - - storage_2_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6992 544 ) N ; - - storage_2_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7406 544 ) N ; - - storage_2_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8050 544 ) N ; - - storage_2_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8280 544 ) N ; - - storage_3_0_0.bit0.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 46 816 ) FS ; - - storage_3_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 552 816 ) FS ; - - storage_3_0_0.bit1.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 966 816 ) FS ; - - storage_3_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1472 816 ) FS ; - - storage_3_0_0.bit2.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 1886 816 ) FS ; - - storage_3_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2392 816 ) FS ; - - storage_3_0_0.bit3.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 2806 816 ) FS ; - - storage_3_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3312 816 ) FS ; - - storage_3_0_0.bit4.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 3726 816 ) FS ; - - storage_3_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 816 ) FS ; - - storage_3_0_0.bit5.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 4646 816 ) FS ; - - storage_3_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5152 816 ) FS ; - - storage_3_0_0.bit6.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 5566 816 ) FS ; - - storage_3_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6072 816 ) FS ; - - storage_3_0_0.bit7.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 6486 816 ) FS ; - - storage_3_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6992 816 ) FS ; - - storage_3_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7406 816 ) FS ; - - storage_3_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8050 816 ) FS ; - - storage_3_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8280 816 ) FS ; - - storage_4_0_0.bit0.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 46 1088 ) N ; - - storage_4_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 552 1088 ) N ; - - storage_4_0_0.bit1.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 966 1088 ) N ; - - storage_4_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1472 1088 ) N ; - - storage_4_0_0.bit2.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 1886 1088 ) N ; - - storage_4_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2392 1088 ) N ; - - storage_4_0_0.bit3.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 2806 1088 ) N ; - - storage_4_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3312 1088 ) N ; - - storage_4_0_0.bit4.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 3726 1088 ) N ; - - storage_4_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 1088 ) N ; - - storage_4_0_0.bit5.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 4646 1088 ) N ; - - storage_4_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5152 1088 ) N ; - - storage_4_0_0.bit6.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 5566 1088 ) N ; - - storage_4_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6072 1088 ) N ; - - storage_4_0_0.bit7.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 6486 1088 ) N ; - - storage_4_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6992 1088 ) N ; - - storage_4_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7406 1088 ) N ; - - storage_4_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8050 1088 ) N ; - - storage_4_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8280 1088 ) N ; - - storage_5_0_0.bit0.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 46 1360 ) FS ; - - storage_5_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 552 1360 ) FS ; - - storage_5_0_0.bit1.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 966 1360 ) FS ; - - storage_5_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1472 1360 ) FS ; - - storage_5_0_0.bit2.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 1886 1360 ) FS ; - - storage_5_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2392 1360 ) FS ; - - storage_5_0_0.bit3.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 2806 1360 ) FS ; - - storage_5_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3312 1360 ) FS ; - - storage_5_0_0.bit4.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 3726 1360 ) FS ; - - storage_5_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 1360 ) FS ; - - storage_5_0_0.bit5.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 4646 1360 ) FS ; - - storage_5_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5152 1360 ) FS ; - - storage_5_0_0.bit6.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 5566 1360 ) FS ; - - storage_5_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6072 1360 ) FS ; - - storage_5_0_0.bit7.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 6486 1360 ) FS ; - - storage_5_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6992 1360 ) FS ; - - storage_5_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7406 1360 ) FS ; - - storage_5_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8050 1360 ) FS ; - - storage_5_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8280 1360 ) FS ; - - storage_6_0_0.bit0.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 46 1632 ) N ; - - storage_6_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 552 1632 ) N ; - - storage_6_0_0.bit1.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 966 1632 ) N ; - - storage_6_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1472 1632 ) N ; - - storage_6_0_0.bit2.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 1886 1632 ) N ; - - storage_6_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2392 1632 ) N ; - - storage_6_0_0.bit3.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 2806 1632 ) N ; - - storage_6_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3312 1632 ) N ; - - storage_6_0_0.bit4.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 3726 1632 ) N ; - - storage_6_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 1632 ) N ; - - storage_6_0_0.bit5.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 4646 1632 ) N ; - - storage_6_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5152 1632 ) N ; - - storage_6_0_0.bit6.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 5566 1632 ) N ; - - storage_6_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6072 1632 ) N ; - - storage_6_0_0.bit7.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 6486 1632 ) N ; - - storage_6_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6992 1632 ) N ; - - storage_6_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7406 1632 ) N ; - - storage_6_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8050 1632 ) N ; - - storage_6_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8280 1632 ) N ; - - storage_7_0_0.bit0.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 46 1904 ) FS ; - - storage_7_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 552 1904 ) FS ; - - storage_7_0_0.bit1.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 966 1904 ) FS ; - - storage_7_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1472 1904 ) FS ; - - storage_7_0_0.bit2.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 1886 1904 ) FS ; - - storage_7_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2392 1904 ) FS ; - - storage_7_0_0.bit3.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 2806 1904 ) FS ; - - storage_7_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3312 1904 ) FS ; - - storage_7_0_0.bit4.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 3726 1904 ) FS ; - - storage_7_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4232 1904 ) FS ; - - storage_7_0_0.bit5.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 4646 1904 ) FS ; - - storage_7_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5152 1904 ) FS ; - - storage_7_0_0.bit6.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 5566 1904 ) FS ; - - storage_7_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6072 1904 ) FS ; - - storage_7_0_0.bit7.bit sky130_fd_sc_hd__lpflow_inputisolatch_1 + PLACED ( 6486 1904 ) FS ; - - storage_7_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6992 1904 ) FS ; - - storage_7_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7406 1904 ) FS ; - - storage_7_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8050 1904 ) FS ; - - storage_7_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8280 1904 ) FS ; + - buffer.in[1] sky130_fd_sc_hd__buf_1 + PLACED ( 1012 2448 ) FS ; + - buffer.in[2] sky130_fd_sc_hd__buf_1 + PLACED ( 1978 2448 ) FS ; + - buffer.in[3] sky130_fd_sc_hd__buf_1 + PLACED ( 2944 2448 ) FS ; + - buffer.in[4] sky130_fd_sc_hd__buf_1 + PLACED ( 3910 2448 ) FS ; + - buffer.in[5] sky130_fd_sc_hd__buf_1 + PLACED ( 4876 2448 ) FS ; + - buffer.in[6] sky130_fd_sc_hd__buf_1 + PLACED ( 5842 2448 ) FS ; + - buffer.in[7] sky130_fd_sc_hd__buf_1 + PLACED ( 6808 2448 ) FS ; + - decoder_p0.and_layer0_word0 sky130_fd_sc_hd__and2_0 + PLACED ( 8970 0 ) N ; + - decoder_p0.and_layer0_word1 sky130_fd_sc_hd__and2_0 + PLACED ( 8970 272 ) FS ; + - decoder_p0.and_layer0_word2 sky130_fd_sc_hd__and2_0 + PLACED ( 8970 544 ) N ; + - decoder_p0.and_layer0_word3 sky130_fd_sc_hd__and2_0 + PLACED ( 8970 816 ) FS ; + - decoder_p0.and_layer0_word4 sky130_fd_sc_hd__and2_0 + PLACED ( 8970 1088 ) N ; + - decoder_p0.and_layer0_word5 sky130_fd_sc_hd__and2_0 + PLACED ( 8970 1360 ) FS ; + - decoder_p0.and_layer0_word6 sky130_fd_sc_hd__and2_0 + PLACED ( 8970 1632 ) N ; + - decoder_p0.and_layer0_word7 sky130_fd_sc_hd__and2_0 + PLACED ( 8970 1904 ) FS ; + - decoder_p0.and_layer1_word0 sky130_fd_sc_hd__and2_0 + PLACED ( 9200 0 ) N ; + - decoder_p0.and_layer1_word1 sky130_fd_sc_hd__and2_0 + PLACED ( 9200 272 ) FS ; + - decoder_p0.and_layer1_word2 sky130_fd_sc_hd__and2_0 + PLACED ( 9200 544 ) N ; + - decoder_p0.and_layer1_word3 sky130_fd_sc_hd__and2_0 + PLACED ( 9200 816 ) FS ; + - decoder_p0.and_layer1_word4 sky130_fd_sc_hd__and2_0 + PLACED ( 9200 1088 ) N ; + - decoder_p0.and_layer1_word5 sky130_fd_sc_hd__and2_0 + PLACED ( 9200 1360 ) FS ; + - decoder_p0.and_layer1_word6 sky130_fd_sc_hd__and2_0 + PLACED ( 9200 1632 ) N ; + - decoder_p0.and_layer1_word7 sky130_fd_sc_hd__and2_0 + PLACED ( 9200 1904 ) FS ; + - decoder_p0.inv_p0_a0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 9430 1088 ) N ; + - decoder_p0.inv_p0_a1 sky130_fd_sc_hd__clkinv_1 + PLACED ( 9430 544 ) N ; + - decoder_p0.inv_p0_a2 sky130_fd_sc_hd__clkinv_1 + PLACED ( 9430 0 ) N ; + - neg_lat_b0.nlat sky130_fd_sc_hd__dlxtp_1 + PLACED ( 46 2176 ) N ; + - neg_lat_b1.nlat sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1012 2176 ) N ; + - neg_lat_b2.nlat sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1978 2176 ) N ; + - neg_lat_b3.nlat sky130_fd_sc_hd__dlxtp_1 + PLACED ( 2944 2176 ) N ; + - neg_lat_b4.nlat sky130_fd_sc_hd__dlxtp_1 + PLACED ( 3910 2176 ) N ; + - neg_lat_b5.nlat sky130_fd_sc_hd__dlxtp_1 + PLACED ( 4876 2176 ) N ; + - neg_lat_b6.nlat sky130_fd_sc_hd__dlxtp_1 + PLACED ( 5842 2176 ) N ; + - neg_lat_b7.nlat sky130_fd_sc_hd__dlxtp_1 + PLACED ( 6808 2176 ) N ; + - neg_row.clk_inv sky130_fd_sc_hd__clkinv_1 + PLACED ( 7774 2176 ) N ; + - sel_buf_rw_p0.sel_buf_0 sky130_fd_sc_hd__buf_1 + PLACED ( 8786 0 ) N ; + - sel_buf_rw_p0.sel_buf_1 sky130_fd_sc_hd__buf_1 + PLACED ( 8786 272 ) FS ; + - sel_buf_rw_p0.sel_buf_2 sky130_fd_sc_hd__buf_1 + PLACED ( 8786 544 ) N ; + - sel_buf_rw_p0.sel_buf_3 sky130_fd_sc_hd__buf_1 + PLACED ( 8786 816 ) FS ; + - sel_buf_rw_p0.sel_buf_4 sky130_fd_sc_hd__buf_1 + PLACED ( 8786 1088 ) N ; + - sel_buf_rw_p0.sel_buf_5 sky130_fd_sc_hd__buf_1 + PLACED ( 8786 1360 ) FS ; + - sel_buf_rw_p0.sel_buf_6 sky130_fd_sc_hd__buf_1 + PLACED ( 8786 1632 ) N ; + - sel_buf_rw_p0.sel_buf_7 sky130_fd_sc_hd__buf_1 + PLACED ( 8786 1904 ) FS ; + - storage_0_0_0.bit0.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 46 0 ) N ; + - storage_0_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 598 0 ) N ; + - storage_0_0_0.bit1.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1012 0 ) N ; + - storage_0_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1564 0 ) N ; + - storage_0_0_0.bit2.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1978 0 ) N ; + - storage_0_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2530 0 ) N ; + - storage_0_0_0.bit3.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 2944 0 ) N ; + - storage_0_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3496 0 ) N ; + - storage_0_0_0.bit4.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 3910 0 ) N ; + - storage_0_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4462 0 ) N ; + - storage_0_0_0.bit5.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 4876 0 ) N ; + - storage_0_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5428 0 ) N ; + - storage_0_0_0.bit6.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 5842 0 ) N ; + - storage_0_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6394 0 ) N ; + - storage_0_0_0.bit7.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 6808 0 ) N ; + - storage_0_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7360 0 ) N ; + - storage_0_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7774 0 ) N ; + - storage_0_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8418 0 ) N ; + - storage_0_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8648 0 ) N ; + - storage_1_0_0.bit0.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 46 272 ) FS ; + - storage_1_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 598 272 ) FS ; + - storage_1_0_0.bit1.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1012 272 ) FS ; + - storage_1_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1564 272 ) FS ; + - storage_1_0_0.bit2.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1978 272 ) FS ; + - storage_1_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2530 272 ) FS ; + - storage_1_0_0.bit3.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 2944 272 ) FS ; + - storage_1_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3496 272 ) FS ; + - storage_1_0_0.bit4.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 3910 272 ) FS ; + - storage_1_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4462 272 ) FS ; + - storage_1_0_0.bit5.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 4876 272 ) FS ; + - storage_1_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5428 272 ) FS ; + - storage_1_0_0.bit6.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 5842 272 ) FS ; + - storage_1_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6394 272 ) FS ; + - storage_1_0_0.bit7.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 6808 272 ) FS ; + - storage_1_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7360 272 ) FS ; + - storage_1_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7774 272 ) FS ; + - storage_1_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8418 272 ) FS ; + - storage_1_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8648 272 ) FS ; + - storage_2_0_0.bit0.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 46 544 ) N ; + - storage_2_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 598 544 ) N ; + - storage_2_0_0.bit1.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1012 544 ) N ; + - storage_2_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1564 544 ) N ; + - storage_2_0_0.bit2.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1978 544 ) N ; + - storage_2_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2530 544 ) N ; + - storage_2_0_0.bit3.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 2944 544 ) N ; + - storage_2_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3496 544 ) N ; + - storage_2_0_0.bit4.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 3910 544 ) N ; + - storage_2_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4462 544 ) N ; + - storage_2_0_0.bit5.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 4876 544 ) N ; + - storage_2_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5428 544 ) N ; + - storage_2_0_0.bit6.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 5842 544 ) N ; + - storage_2_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6394 544 ) N ; + - storage_2_0_0.bit7.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 6808 544 ) N ; + - storage_2_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7360 544 ) N ; + - storage_2_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7774 544 ) N ; + - storage_2_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8418 544 ) N ; + - storage_2_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8648 544 ) N ; + - storage_3_0_0.bit0.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 46 816 ) FS ; + - storage_3_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 598 816 ) FS ; + - storage_3_0_0.bit1.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1012 816 ) FS ; + - storage_3_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1564 816 ) FS ; + - storage_3_0_0.bit2.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1978 816 ) FS ; + - storage_3_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2530 816 ) FS ; + - storage_3_0_0.bit3.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 2944 816 ) FS ; + - storage_3_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3496 816 ) FS ; + - storage_3_0_0.bit4.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 3910 816 ) FS ; + - storage_3_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4462 816 ) FS ; + - storage_3_0_0.bit5.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 4876 816 ) FS ; + - storage_3_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5428 816 ) FS ; + - storage_3_0_0.bit6.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 5842 816 ) FS ; + - storage_3_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6394 816 ) FS ; + - storage_3_0_0.bit7.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 6808 816 ) FS ; + - storage_3_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7360 816 ) FS ; + - storage_3_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7774 816 ) FS ; + - storage_3_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8418 816 ) FS ; + - storage_3_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8648 816 ) FS ; + - storage_4_0_0.bit0.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 46 1088 ) N ; + - storage_4_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 598 1088 ) N ; + - storage_4_0_0.bit1.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1012 1088 ) N ; + - storage_4_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1564 1088 ) N ; + - storage_4_0_0.bit2.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1978 1088 ) N ; + - storage_4_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2530 1088 ) N ; + - storage_4_0_0.bit3.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 2944 1088 ) N ; + - storage_4_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3496 1088 ) N ; + - storage_4_0_0.bit4.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 3910 1088 ) N ; + - storage_4_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4462 1088 ) N ; + - storage_4_0_0.bit5.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 4876 1088 ) N ; + - storage_4_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5428 1088 ) N ; + - storage_4_0_0.bit6.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 5842 1088 ) N ; + - storage_4_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6394 1088 ) N ; + - storage_4_0_0.bit7.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 6808 1088 ) N ; + - storage_4_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7360 1088 ) N ; + - storage_4_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7774 1088 ) N ; + - storage_4_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8418 1088 ) N ; + - storage_4_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8648 1088 ) N ; + - storage_5_0_0.bit0.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 46 1360 ) FS ; + - storage_5_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 598 1360 ) FS ; + - storage_5_0_0.bit1.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1012 1360 ) FS ; + - storage_5_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1564 1360 ) FS ; + - storage_5_0_0.bit2.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1978 1360 ) FS ; + - storage_5_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2530 1360 ) FS ; + - storage_5_0_0.bit3.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 2944 1360 ) FS ; + - storage_5_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3496 1360 ) FS ; + - storage_5_0_0.bit4.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 3910 1360 ) FS ; + - storage_5_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4462 1360 ) FS ; + - storage_5_0_0.bit5.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 4876 1360 ) FS ; + - storage_5_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5428 1360 ) FS ; + - storage_5_0_0.bit6.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 5842 1360 ) FS ; + - storage_5_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6394 1360 ) FS ; + - storage_5_0_0.bit7.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 6808 1360 ) FS ; + - storage_5_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7360 1360 ) FS ; + - storage_5_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7774 1360 ) FS ; + - storage_5_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8418 1360 ) FS ; + - storage_5_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8648 1360 ) FS ; + - storage_6_0_0.bit0.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 46 1632 ) N ; + - storage_6_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 598 1632 ) N ; + - storage_6_0_0.bit1.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1012 1632 ) N ; + - storage_6_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1564 1632 ) N ; + - storage_6_0_0.bit2.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1978 1632 ) N ; + - storage_6_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2530 1632 ) N ; + - storage_6_0_0.bit3.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 2944 1632 ) N ; + - storage_6_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3496 1632 ) N ; + - storage_6_0_0.bit4.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 3910 1632 ) N ; + - storage_6_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4462 1632 ) N ; + - storage_6_0_0.bit5.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 4876 1632 ) N ; + - storage_6_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5428 1632 ) N ; + - storage_6_0_0.bit6.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 5842 1632 ) N ; + - storage_6_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6394 1632 ) N ; + - storage_6_0_0.bit7.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 6808 1632 ) N ; + - storage_6_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7360 1632 ) N ; + - storage_6_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7774 1632 ) N ; + - storage_6_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8418 1632 ) N ; + - storage_6_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8648 1632 ) N ; + - storage_7_0_0.bit0.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 46 1904 ) FS ; + - storage_7_0_0.bit0.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 598 1904 ) FS ; + - storage_7_0_0.bit1.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1012 1904 ) FS ; + - storage_7_0_0.bit1.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 1564 1904 ) FS ; + - storage_7_0_0.bit2.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 1978 1904 ) FS ; + - storage_7_0_0.bit2.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 2530 1904 ) FS ; + - storage_7_0_0.bit3.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 2944 1904 ) FS ; + - storage_7_0_0.bit3.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 3496 1904 ) FS ; + - storage_7_0_0.bit4.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 3910 1904 ) FS ; + - storage_7_0_0.bit4.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 4462 1904 ) FS ; + - storage_7_0_0.bit5.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 4876 1904 ) FS ; + - storage_7_0_0.bit5.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 5428 1904 ) FS ; + - storage_7_0_0.bit6.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 5842 1904 ) FS ; + - storage_7_0_0.bit6.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 6394 1904 ) FS ; + - storage_7_0_0.bit7.bit sky130_fd_sc_hd__dlxtp_1 + PLACED ( 6808 1904 ) FS ; + - storage_7_0_0.bit7.obuf0 sky130_fd_sc_hd__ebufn_1 + PLACED ( 7360 1904 ) FS ; + - storage_7_0_0.cg sky130_fd_sc_hd__dlclkp_1 + PLACED ( 7774 1904 ) FS ; + - storage_7_0_0.gcand sky130_fd_sc_hd__and2_0 + PLACED ( 8418 1904 ) FS ; + - storage_7_0_0.select_inv_0 sky130_fd_sc_hd__clkinv_1 + PLACED ( 8648 1904 ) FS ; - tapcell.cell0_0 sky130_fd_sc_hd__tap_1 + PLACED ( 0 0 ) N ; - tapcell.cell0_1 sky130_fd_sc_hd__tap_1 + PLACED ( 0 272 ) FS ; - tapcell.cell0_2 sky130_fd_sc_hd__tap_1 + PLACED ( 0 544 ) N ; @@ -287,96 +295,96 @@ COMPONENTS 344 ; - tapcell.cell0_7 sky130_fd_sc_hd__tap_1 + PLACED ( 0 1904 ) FS ; - tapcell.cell0_8 sky130_fd_sc_hd__tap_1 + PLACED ( 0 2176 ) N ; - tapcell.cell0_9 sky130_fd_sc_hd__tap_1 + PLACED ( 0 2448 ) FS ; - - tapcell.cell1_0 sky130_fd_sc_hd__tap_1 + PLACED ( 920 0 ) N ; - - tapcell.cell1_1 sky130_fd_sc_hd__tap_1 + PLACED ( 920 272 ) FS ; - - tapcell.cell1_2 sky130_fd_sc_hd__tap_1 + PLACED ( 920 544 ) N ; - - tapcell.cell1_3 sky130_fd_sc_hd__tap_1 + PLACED ( 920 816 ) FS ; - - tapcell.cell1_4 sky130_fd_sc_hd__tap_1 + PLACED ( 920 1088 ) N ; - - tapcell.cell1_5 sky130_fd_sc_hd__tap_1 + PLACED ( 920 1360 ) FS ; - - tapcell.cell1_6 sky130_fd_sc_hd__tap_1 + PLACED ( 920 1632 ) N ; - - tapcell.cell1_7 sky130_fd_sc_hd__tap_1 + PLACED ( 920 1904 ) FS ; - - tapcell.cell1_8 sky130_fd_sc_hd__tap_1 + PLACED ( 920 2176 ) N ; - - tapcell.cell1_9 sky130_fd_sc_hd__tap_1 + PLACED ( 920 2448 ) FS ; - - tapcell.cell2_0 sky130_fd_sc_hd__tap_1 + PLACED ( 1840 0 ) N ; - - tapcell.cell2_1 sky130_fd_sc_hd__tap_1 + PLACED ( 1840 272 ) FS ; - - tapcell.cell2_2 sky130_fd_sc_hd__tap_1 + PLACED ( 1840 544 ) N ; - - tapcell.cell2_3 sky130_fd_sc_hd__tap_1 + PLACED ( 1840 816 ) FS ; - - tapcell.cell2_4 sky130_fd_sc_hd__tap_1 + PLACED ( 1840 1088 ) N ; - - tapcell.cell2_5 sky130_fd_sc_hd__tap_1 + PLACED ( 1840 1360 ) FS ; - - tapcell.cell2_6 sky130_fd_sc_hd__tap_1 + PLACED ( 1840 1632 ) N ; - - tapcell.cell2_7 sky130_fd_sc_hd__tap_1 + PLACED ( 1840 1904 ) FS ; - - tapcell.cell2_8 sky130_fd_sc_hd__tap_1 + PLACED ( 1840 2176 ) N ; - - tapcell.cell2_9 sky130_fd_sc_hd__tap_1 + PLACED ( 1840 2448 ) FS ; - - tapcell.cell3_0 sky130_fd_sc_hd__tap_1 + PLACED ( 2760 0 ) N ; - - tapcell.cell3_1 sky130_fd_sc_hd__tap_1 + PLACED ( 2760 272 ) FS ; - - tapcell.cell3_2 sky130_fd_sc_hd__tap_1 + PLACED ( 2760 544 ) N ; - - tapcell.cell3_3 sky130_fd_sc_hd__tap_1 + PLACED ( 2760 816 ) FS ; - - tapcell.cell3_4 sky130_fd_sc_hd__tap_1 + PLACED ( 2760 1088 ) N ; - - tapcell.cell3_5 sky130_fd_sc_hd__tap_1 + PLACED ( 2760 1360 ) FS ; - - tapcell.cell3_6 sky130_fd_sc_hd__tap_1 + PLACED ( 2760 1632 ) N ; - - tapcell.cell3_7 sky130_fd_sc_hd__tap_1 + PLACED ( 2760 1904 ) FS ; - - tapcell.cell3_8 sky130_fd_sc_hd__tap_1 + PLACED ( 2760 2176 ) N ; - - tapcell.cell3_9 sky130_fd_sc_hd__tap_1 + PLACED ( 2760 2448 ) FS ; - - tapcell.cell4_0 sky130_fd_sc_hd__tap_1 + PLACED ( 3680 0 ) N ; - - tapcell.cell4_1 sky130_fd_sc_hd__tap_1 + PLACED ( 3680 272 ) FS ; - - tapcell.cell4_2 sky130_fd_sc_hd__tap_1 + PLACED ( 3680 544 ) N ; - - tapcell.cell4_3 sky130_fd_sc_hd__tap_1 + PLACED ( 3680 816 ) FS ; - - tapcell.cell4_4 sky130_fd_sc_hd__tap_1 + PLACED ( 3680 1088 ) N ; - - tapcell.cell4_5 sky130_fd_sc_hd__tap_1 + PLACED ( 3680 1360 ) FS ; - - tapcell.cell4_6 sky130_fd_sc_hd__tap_1 + PLACED ( 3680 1632 ) N ; - - tapcell.cell4_7 sky130_fd_sc_hd__tap_1 + PLACED ( 3680 1904 ) FS ; - - tapcell.cell4_8 sky130_fd_sc_hd__tap_1 + PLACED ( 3680 2176 ) N ; - - tapcell.cell4_9 sky130_fd_sc_hd__tap_1 + PLACED ( 3680 2448 ) FS ; - - tapcell.cell5_0 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 0 ) N ; - - tapcell.cell5_1 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 272 ) FS ; - - tapcell.cell5_2 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 544 ) N ; - - tapcell.cell5_3 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 816 ) FS ; - - tapcell.cell5_4 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 1088 ) N ; - - tapcell.cell5_5 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 1360 ) FS ; - - tapcell.cell5_6 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 1632 ) N ; - - tapcell.cell5_7 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 1904 ) FS ; - - tapcell.cell5_8 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 2176 ) N ; - - tapcell.cell5_9 sky130_fd_sc_hd__tap_1 + PLACED ( 4600 2448 ) FS ; - - tapcell.cell6_0 sky130_fd_sc_hd__tap_1 + PLACED ( 5520 0 ) N ; - - tapcell.cell6_1 sky130_fd_sc_hd__tap_1 + PLACED ( 5520 272 ) FS ; - - tapcell.cell6_2 sky130_fd_sc_hd__tap_1 + PLACED ( 5520 544 ) N ; - - tapcell.cell6_3 sky130_fd_sc_hd__tap_1 + PLACED ( 5520 816 ) FS ; - - tapcell.cell6_4 sky130_fd_sc_hd__tap_1 + PLACED ( 5520 1088 ) N ; - - tapcell.cell6_5 sky130_fd_sc_hd__tap_1 + PLACED ( 5520 1360 ) FS ; - - tapcell.cell6_6 sky130_fd_sc_hd__tap_1 + PLACED ( 5520 1632 ) N ; - - tapcell.cell6_7 sky130_fd_sc_hd__tap_1 + PLACED ( 5520 1904 ) FS ; - - tapcell.cell6_8 sky130_fd_sc_hd__tap_1 + PLACED ( 5520 2176 ) N ; - - tapcell.cell6_9 sky130_fd_sc_hd__tap_1 + PLACED ( 5520 2448 ) FS ; - - tapcell.cell7_0 sky130_fd_sc_hd__tap_1 + PLACED ( 6440 0 ) N ; - - tapcell.cell7_1 sky130_fd_sc_hd__tap_1 + PLACED ( 6440 272 ) FS ; - - tapcell.cell7_2 sky130_fd_sc_hd__tap_1 + PLACED ( 6440 544 ) N ; - - tapcell.cell7_3 sky130_fd_sc_hd__tap_1 + PLACED ( 6440 816 ) FS ; - - tapcell.cell7_4 sky130_fd_sc_hd__tap_1 + PLACED ( 6440 1088 ) N ; - - tapcell.cell7_5 sky130_fd_sc_hd__tap_1 + PLACED ( 6440 1360 ) FS ; - - tapcell.cell7_6 sky130_fd_sc_hd__tap_1 + PLACED ( 6440 1632 ) N ; - - tapcell.cell7_7 sky130_fd_sc_hd__tap_1 + PLACED ( 6440 1904 ) FS ; - - tapcell.cell7_8 sky130_fd_sc_hd__tap_1 + PLACED ( 6440 2176 ) N ; - - tapcell.cell7_9 sky130_fd_sc_hd__tap_1 + PLACED ( 6440 2448 ) FS ; - - tapcell.cell8_0 sky130_fd_sc_hd__tap_1 + PLACED ( 7360 0 ) N ; - - tapcell.cell8_1 sky130_fd_sc_hd__tap_1 + PLACED ( 7360 272 ) FS ; - - tapcell.cell8_2 sky130_fd_sc_hd__tap_1 + PLACED ( 7360 544 ) N ; - - tapcell.cell8_3 sky130_fd_sc_hd__tap_1 + PLACED ( 7360 816 ) FS ; - - tapcell.cell8_4 sky130_fd_sc_hd__tap_1 + PLACED ( 7360 1088 ) N ; - - tapcell.cell8_5 sky130_fd_sc_hd__tap_1 + PLACED ( 7360 1360 ) FS ; - - tapcell.cell8_6 sky130_fd_sc_hd__tap_1 + PLACED ( 7360 1632 ) N ; - - tapcell.cell8_7 sky130_fd_sc_hd__tap_1 + PLACED ( 7360 1904 ) FS ; - - tapcell.cell8_8 sky130_fd_sc_hd__tap_1 + PLACED ( 7360 2176 ) N ; - - tapcell.cell8_9 sky130_fd_sc_hd__tap_1 + PLACED ( 7360 2448 ) FS ; - - tapcell.cell9_0 sky130_fd_sc_hd__tap_1 + PLACED ( 8556 0 ) N ; - - tapcell.cell9_1 sky130_fd_sc_hd__tap_1 + PLACED ( 8556 272 ) FS ; - - tapcell.cell9_2 sky130_fd_sc_hd__tap_1 + PLACED ( 8556 544 ) N ; - - tapcell.cell9_3 sky130_fd_sc_hd__tap_1 + PLACED ( 8556 816 ) FS ; - - tapcell.cell9_4 sky130_fd_sc_hd__tap_1 + PLACED ( 8556 1088 ) N ; - - tapcell.cell9_5 sky130_fd_sc_hd__tap_1 + PLACED ( 8556 1360 ) FS ; - - tapcell.cell9_6 sky130_fd_sc_hd__tap_1 + PLACED ( 8556 1632 ) N ; - - tapcell.cell9_7 sky130_fd_sc_hd__tap_1 + PLACED ( 8556 1904 ) FS ; - - tapcell.cell9_8 sky130_fd_sc_hd__tap_1 + PLACED ( 8556 2176 ) N ; - - tapcell.cell9_9 sky130_fd_sc_hd__tap_1 + PLACED ( 8556 2448 ) FS ; + - tapcell.cell1_0 sky130_fd_sc_hd__tap_1 + PLACED ( 966 0 ) N ; + - tapcell.cell1_1 sky130_fd_sc_hd__tap_1 + PLACED ( 966 272 ) FS ; + - tapcell.cell1_2 sky130_fd_sc_hd__tap_1 + PLACED ( 966 544 ) N ; + - tapcell.cell1_3 sky130_fd_sc_hd__tap_1 + PLACED ( 966 816 ) FS ; + - tapcell.cell1_4 sky130_fd_sc_hd__tap_1 + PLACED ( 966 1088 ) N ; + - tapcell.cell1_5 sky130_fd_sc_hd__tap_1 + PLACED ( 966 1360 ) FS ; + - tapcell.cell1_6 sky130_fd_sc_hd__tap_1 + PLACED ( 966 1632 ) N ; + - tapcell.cell1_7 sky130_fd_sc_hd__tap_1 + PLACED ( 966 1904 ) FS ; + - tapcell.cell1_8 sky130_fd_sc_hd__tap_1 + PLACED ( 966 2176 ) N ; + - tapcell.cell1_9 sky130_fd_sc_hd__tap_1 + PLACED ( 966 2448 ) FS ; + - tapcell.cell2_0 sky130_fd_sc_hd__tap_1 + PLACED ( 1932 0 ) N ; + - tapcell.cell2_1 sky130_fd_sc_hd__tap_1 + PLACED ( 1932 272 ) FS ; + - tapcell.cell2_2 sky130_fd_sc_hd__tap_1 + PLACED ( 1932 544 ) N ; + - tapcell.cell2_3 sky130_fd_sc_hd__tap_1 + PLACED ( 1932 816 ) FS ; + - tapcell.cell2_4 sky130_fd_sc_hd__tap_1 + PLACED ( 1932 1088 ) N ; + - tapcell.cell2_5 sky130_fd_sc_hd__tap_1 + PLACED ( 1932 1360 ) FS ; + - tapcell.cell2_6 sky130_fd_sc_hd__tap_1 + PLACED ( 1932 1632 ) N ; + - tapcell.cell2_7 sky130_fd_sc_hd__tap_1 + PLACED ( 1932 1904 ) FS ; + - tapcell.cell2_8 sky130_fd_sc_hd__tap_1 + PLACED ( 1932 2176 ) N ; + - tapcell.cell2_9 sky130_fd_sc_hd__tap_1 + PLACED ( 1932 2448 ) FS ; + - tapcell.cell3_0 sky130_fd_sc_hd__tap_1 + PLACED ( 2898 0 ) N ; + - tapcell.cell3_1 sky130_fd_sc_hd__tap_1 + PLACED ( 2898 272 ) FS ; + - tapcell.cell3_2 sky130_fd_sc_hd__tap_1 + PLACED ( 2898 544 ) N ; + - tapcell.cell3_3 sky130_fd_sc_hd__tap_1 + PLACED ( 2898 816 ) FS ; + - tapcell.cell3_4 sky130_fd_sc_hd__tap_1 + PLACED ( 2898 1088 ) N ; + - tapcell.cell3_5 sky130_fd_sc_hd__tap_1 + PLACED ( 2898 1360 ) FS ; + - tapcell.cell3_6 sky130_fd_sc_hd__tap_1 + PLACED ( 2898 1632 ) N ; + - tapcell.cell3_7 sky130_fd_sc_hd__tap_1 + PLACED ( 2898 1904 ) FS ; + - tapcell.cell3_8 sky130_fd_sc_hd__tap_1 + PLACED ( 2898 2176 ) N ; + - tapcell.cell3_9 sky130_fd_sc_hd__tap_1 + PLACED ( 2898 2448 ) FS ; + - tapcell.cell4_0 sky130_fd_sc_hd__tap_1 + PLACED ( 3864 0 ) N ; + - tapcell.cell4_1 sky130_fd_sc_hd__tap_1 + PLACED ( 3864 272 ) FS ; + - tapcell.cell4_2 sky130_fd_sc_hd__tap_1 + PLACED ( 3864 544 ) N ; + - tapcell.cell4_3 sky130_fd_sc_hd__tap_1 + PLACED ( 3864 816 ) FS ; + - tapcell.cell4_4 sky130_fd_sc_hd__tap_1 + PLACED ( 3864 1088 ) N ; + - tapcell.cell4_5 sky130_fd_sc_hd__tap_1 + PLACED ( 3864 1360 ) FS ; + - tapcell.cell4_6 sky130_fd_sc_hd__tap_1 + PLACED ( 3864 1632 ) N ; + - tapcell.cell4_7 sky130_fd_sc_hd__tap_1 + PLACED ( 3864 1904 ) FS ; + - tapcell.cell4_8 sky130_fd_sc_hd__tap_1 + PLACED ( 3864 2176 ) N ; + - tapcell.cell4_9 sky130_fd_sc_hd__tap_1 + PLACED ( 3864 2448 ) FS ; + - tapcell.cell5_0 sky130_fd_sc_hd__tap_1 + PLACED ( 4830 0 ) N ; + - tapcell.cell5_1 sky130_fd_sc_hd__tap_1 + PLACED ( 4830 272 ) FS ; + - tapcell.cell5_2 sky130_fd_sc_hd__tap_1 + PLACED ( 4830 544 ) N ; + - tapcell.cell5_3 sky130_fd_sc_hd__tap_1 + PLACED ( 4830 816 ) FS ; + - tapcell.cell5_4 sky130_fd_sc_hd__tap_1 + PLACED ( 4830 1088 ) N ; + - tapcell.cell5_5 sky130_fd_sc_hd__tap_1 + PLACED ( 4830 1360 ) FS ; + - tapcell.cell5_6 sky130_fd_sc_hd__tap_1 + PLACED ( 4830 1632 ) N ; + - tapcell.cell5_7 sky130_fd_sc_hd__tap_1 + PLACED ( 4830 1904 ) FS ; + - tapcell.cell5_8 sky130_fd_sc_hd__tap_1 + PLACED ( 4830 2176 ) N ; + - tapcell.cell5_9 sky130_fd_sc_hd__tap_1 + PLACED ( 4830 2448 ) FS ; + - tapcell.cell6_0 sky130_fd_sc_hd__tap_1 + PLACED ( 5796 0 ) N ; + - tapcell.cell6_1 sky130_fd_sc_hd__tap_1 + PLACED ( 5796 272 ) FS ; + - tapcell.cell6_2 sky130_fd_sc_hd__tap_1 + PLACED ( 5796 544 ) N ; + - tapcell.cell6_3 sky130_fd_sc_hd__tap_1 + PLACED ( 5796 816 ) FS ; + - tapcell.cell6_4 sky130_fd_sc_hd__tap_1 + PLACED ( 5796 1088 ) N ; + - tapcell.cell6_5 sky130_fd_sc_hd__tap_1 + PLACED ( 5796 1360 ) FS ; + - tapcell.cell6_6 sky130_fd_sc_hd__tap_1 + PLACED ( 5796 1632 ) N ; + - tapcell.cell6_7 sky130_fd_sc_hd__tap_1 + PLACED ( 5796 1904 ) FS ; + - tapcell.cell6_8 sky130_fd_sc_hd__tap_1 + PLACED ( 5796 2176 ) N ; + - tapcell.cell6_9 sky130_fd_sc_hd__tap_1 + PLACED ( 5796 2448 ) FS ; + - tapcell.cell7_0 sky130_fd_sc_hd__tap_1 + PLACED ( 6762 0 ) N ; + - tapcell.cell7_1 sky130_fd_sc_hd__tap_1 + PLACED ( 6762 272 ) FS ; + - tapcell.cell7_2 sky130_fd_sc_hd__tap_1 + PLACED ( 6762 544 ) N ; + - tapcell.cell7_3 sky130_fd_sc_hd__tap_1 + PLACED ( 6762 816 ) FS ; + - tapcell.cell7_4 sky130_fd_sc_hd__tap_1 + PLACED ( 6762 1088 ) N ; + - tapcell.cell7_5 sky130_fd_sc_hd__tap_1 + PLACED ( 6762 1360 ) FS ; + - tapcell.cell7_6 sky130_fd_sc_hd__tap_1 + PLACED ( 6762 1632 ) N ; + - tapcell.cell7_7 sky130_fd_sc_hd__tap_1 + PLACED ( 6762 1904 ) FS ; + - tapcell.cell7_8 sky130_fd_sc_hd__tap_1 + PLACED ( 6762 2176 ) N ; + - tapcell.cell7_9 sky130_fd_sc_hd__tap_1 + PLACED ( 6762 2448 ) FS ; + - tapcell.cell8_0 sky130_fd_sc_hd__tap_1 + PLACED ( 7728 0 ) N ; + - tapcell.cell8_1 sky130_fd_sc_hd__tap_1 + PLACED ( 7728 272 ) FS ; + - tapcell.cell8_2 sky130_fd_sc_hd__tap_1 + PLACED ( 7728 544 ) N ; + - tapcell.cell8_3 sky130_fd_sc_hd__tap_1 + PLACED ( 7728 816 ) FS ; + - tapcell.cell8_4 sky130_fd_sc_hd__tap_1 + PLACED ( 7728 1088 ) N ; + - tapcell.cell8_5 sky130_fd_sc_hd__tap_1 + PLACED ( 7728 1360 ) FS ; + - tapcell.cell8_6 sky130_fd_sc_hd__tap_1 + PLACED ( 7728 1632 ) N ; + - tapcell.cell8_7 sky130_fd_sc_hd__tap_1 + PLACED ( 7728 1904 ) FS ; + - tapcell.cell8_8 sky130_fd_sc_hd__tap_1 + PLACED ( 7728 2176 ) N ; + - tapcell.cell8_9 sky130_fd_sc_hd__tap_1 + PLACED ( 7728 2448 ) FS ; + - tapcell.cell9_0 sky130_fd_sc_hd__tap_1 + PLACED ( 8924 0 ) N ; + - tapcell.cell9_1 sky130_fd_sc_hd__tap_1 + PLACED ( 8924 272 ) FS ; + - tapcell.cell9_2 sky130_fd_sc_hd__tap_1 + PLACED ( 8924 544 ) N ; + - tapcell.cell9_3 sky130_fd_sc_hd__tap_1 + PLACED ( 8924 816 ) FS ; + - tapcell.cell9_4 sky130_fd_sc_hd__tap_1 + PLACED ( 8924 1088 ) N ; + - tapcell.cell9_5 sky130_fd_sc_hd__tap_1 + PLACED ( 8924 1360 ) FS ; + - tapcell.cell9_6 sky130_fd_sc_hd__tap_1 + PLACED ( 8924 1632 ) N ; + - tapcell.cell9_7 sky130_fd_sc_hd__tap_1 + PLACED ( 8924 1904 ) FS ; + - tapcell.cell9_8 sky130_fd_sc_hd__tap_1 + PLACED ( 8924 2176 ) N ; + - tapcell.cell9_9 sky130_fd_sc_hd__tap_1 + PLACED ( 8924 2448 ) FS ; END COMPONENTS PINS 23 ; - D[0] + NET D[0] + DIRECTION INPUT + USE SIGNAL @@ -390,119 +398,119 @@ PINS 23 ; - D[2] + NET D[2] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 1955 2695 ) N ; + + PLACED ( 2047 2695 ) N ; - D[3] + NET D[3] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 2875 2695 ) N ; + + PLACED ( 2967 2695 ) N ; - D[4] + NET D[4] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 3795 2695 ) N ; + + PLACED ( 3887 2695 ) N ; - D[5] + NET D[5] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 4715 2695 ) N ; + + PLACED ( 4899 2695 ) N ; - D[6] + NET D[6] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 5635 2695 ) N ; + + PLACED ( 5911 2695 ) N ; - D[7] + NET D[7] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 6555 2695 ) N ; + + PLACED ( 6831 2695 ) N ; - Q[0] + NET Q[0] + DIRECTION OUTPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 851 2695 ) N ; + + PLACED ( 943 2695 ) N ; - Q[1] + NET Q[1] + DIRECTION OUTPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 1771 2695 ) N ; + + PLACED ( 1863 2695 ) N ; - Q[2] + NET Q[2] + DIRECTION OUTPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 2691 2695 ) N ; + + PLACED ( 2875 2695 ) N ; - Q[3] + NET Q[3] + DIRECTION OUTPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 3611 2695 ) N ; + + PLACED ( 3795 2695 ) N ; - Q[4] + NET Q[4] + DIRECTION OUTPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 4531 2695 ) N ; + + PLACED ( 4807 2695 ) N ; - Q[5] + NET Q[5] + DIRECTION OUTPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 5451 2695 ) N ; + + PLACED ( 5727 2695 ) N ; - Q[6] + NET Q[6] + DIRECTION OUTPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 6371 2695 ) N ; + + PLACED ( 6739 2695 ) N ; - Q[7] + NET Q[7] + DIRECTION OUTPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 7291 2695 ) N ; + + PLACED ( 7659 2695 ) N ; - VDD + NET VDD + SPECIAL + DIRECTION INOUT + USE POWER + PORT + LAYER met3 ( -15 -24 ) ( 15 24 ) - + LAYER met3 ( -9185 -24 ) ( -9155 24 ) - + LAYER met2 ( -3209 1706 ) ( -3161 1720 ) - + LAYER met2 ( -3209 -1000 ) ( -3161 -986 ) - + LAYER met2 ( -7209 1706 ) ( -7161 1720 ) - + LAYER met2 ( -7209 -1000 ) ( -7161 -986 ) + + LAYER met3 ( -9553 -24 ) ( -9523 24 ) + + LAYER met2 ( -3577 1706 ) ( -3529 1720 ) + + LAYER met2 ( -3577 -1000 ) ( -3529 -986 ) + + LAYER met2 ( -7577 1706 ) ( -7529 1720 ) + + LAYER met2 ( -7577 -1000 ) ( -7529 -986 ) + LAYER met1 ( 1 1424 ) ( 15 1472 ) - + LAYER met1 ( -9185 1424 ) ( -9171 1472 ) + + LAYER met1 ( -9553 1424 ) ( -9539 1472 ) + LAYER met1 ( 1 880 ) ( 15 928 ) - + LAYER met1 ( -9185 880 ) ( -9171 928 ) + + LAYER met1 ( -9553 880 ) ( -9539 928 ) + LAYER met1 ( 1 336 ) ( 15 384 ) - + LAYER met1 ( -9185 336 ) ( -9171 384 ) + + LAYER met1 ( -9553 336 ) ( -9539 384 ) + LAYER met1 ( 1 -208 ) ( 15 -160 ) - + LAYER met1 ( -9185 -208 ) ( -9171 -160 ) + + LAYER met1 ( -9553 -208 ) ( -9539 -160 ) + LAYER met1 ( 1 -752 ) ( 15 -704 ) - + LAYER met1 ( -9185 -752 ) ( -9171 -704 ) - + FIXED ( 9185 1000 ) N ; + + LAYER met1 ( -9553 -752 ) ( -9539 -704 ) + + FIXED ( 9553 1000 ) N ; - VSS + NET VSS + SPECIAL + DIRECTION INOUT + USE GROUND + PORT + LAYER met3 ( -15 -24 ) ( 15 24 ) - + LAYER met3 ( -9185 -24 ) ( -9155 24 ) - + LAYER met2 ( -1209 706 ) ( -1161 720 ) - + LAYER met2 ( -1209 -2000 ) ( -1161 -1986 ) - + LAYER met2 ( -5209 706 ) ( -5161 720 ) - + LAYER met2 ( -5209 -2000 ) ( -5161 -1986 ) + + LAYER met3 ( -9553 -24 ) ( -9523 24 ) + + LAYER met2 ( -1577 706 ) ( -1529 720 ) + + LAYER met2 ( -1577 -2000 ) ( -1529 -1986 ) + + LAYER met2 ( -5577 706 ) ( -5529 720 ) + + LAYER met2 ( -5577 -2000 ) ( -5529 -1986 ) + LAYER met1 ( 1 696 ) ( 15 744 ) - + LAYER met1 ( -9185 696 ) ( -9171 744 ) + + LAYER met1 ( -9553 696 ) ( -9539 744 ) + LAYER met1 ( 1 152 ) ( 15 200 ) - + LAYER met1 ( -9185 152 ) ( -9171 200 ) + + LAYER met1 ( -9553 152 ) ( -9539 200 ) + LAYER met1 ( 1 -392 ) ( 15 -344 ) - + LAYER met1 ( -9185 -392 ) ( -9171 -344 ) + + LAYER met1 ( -9553 -392 ) ( -9539 -344 ) + LAYER met1 ( 1 -936 ) ( 15 -888 ) - + LAYER met1 ( -9185 -936 ) ( -9171 -888 ) + + LAYER met1 ( -9553 -936 ) ( -9539 -888 ) + LAYER met1 ( 1 -1480 ) ( 15 -1432 ) - + LAYER met1 ( -9185 -1480 ) ( -9171 -1432 ) + + LAYER met1 ( -9553 -1480 ) ( -9539 -1432 ) + LAYER met1 ( 1 -2024 ) ( 15 -1976 ) - + LAYER met1 ( -9185 -2024 ) ( -9171 -1976 ) - + FIXED ( 9185 2000 ) N ; + + LAYER met1 ( -9553 -2024 ) ( -9539 -1976 ) + + FIXED ( 9553 2000 ) N ; - addr_rw[0] + NET addr_rw[0] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met3 ( -40 -15 ) ( 40 15 ) - + PLACED ( 9160 442 ) N ; + + PLACED ( 9528 442 ) N ; - addr_rw[1] + NET addr_rw[1] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met3 ( -40 -15 ) ( 40 15 ) - + PLACED ( 9160 714 ) N ; + + PLACED ( 9528 714 ) N ; - addr_rw[2] + NET addr_rw[2] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met3 ( -40 -15 ) ( 40 15 ) - + PLACED ( 9160 170 ) N ; + + PLACED ( 9528 170 ) N ; - clk + NET clk + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 7659 2695 ) N ; + + PLACED ( 8027 2695 ) N ; - we[0] + NET we[0] + DIRECTION INPUT + USE SIGNAL + PORT + LAYER met2 ( -7 -24 ) ( 7 25 ) - + PLACED ( 8119 2695 ) N ; + + PLACED ( 8487 2695 ) N ; END PINS SPECIALNETS 2 ; - VDD ( PIN VDD ) ( tapcell.cell9_9 VPWR ) ( tapcell.cell9_8 VPWR ) ( tapcell.cell9_7 VPWR ) ( tapcell.cell9_6 VPWR ) ( tapcell.cell9_5 VPWR ) ( tapcell.cell9_4 VPWR ) @@ -543,14 +551,14 @@ SPECIALNETS 2 ; ( storage_0_0_0.gcand VPWR ) ( storage_0_0_0.cg VPWR ) ( storage_0_0_0.bit7.obuf0 VPWR ) ( storage_0_0_0.bit7.bit VPWR ) ( storage_0_0_0.bit6.obuf0 VPWR ) ( storage_0_0_0.bit6.bit VPWR ) ( storage_0_0_0.bit5.obuf0 VPWR ) ( storage_0_0_0.bit5.bit VPWR ) ( storage_0_0_0.bit4.obuf0 VPWR ) ( storage_0_0_0.bit4.bit VPWR ) ( storage_0_0_0.bit3.obuf0 VPWR ) ( storage_0_0_0.bit3.bit VPWR ) ( storage_0_0_0.bit2.obuf0 VPWR ) ( storage_0_0_0.bit2.bit VPWR ) ( storage_0_0_0.bit1.obuf0 VPWR ) ( storage_0_0_0.bit1.bit VPWR ) ( storage_0_0_0.bit0.obuf0 VPWR ) ( storage_0_0_0.bit0.bit VPWR ) + USE POWER - + ROUTED met3 48 + SHAPE STRIPE ( 0 1000 ) ( 9200 1000 ) + + ROUTED met3 48 + SHAPE STRIPE ( 0 1000 ) ( 9568 1000 ) NEW met2 48 + SHAPE STRIPE ( 6000 0 ) ( 6000 2720 ) NEW met2 48 + SHAPE STRIPE ( 2000 0 ) ( 2000 2720 ) - NEW met1 48 + SHAPE FOLLOWPIN ( 0 2448 ) ( 9200 2448 ) - NEW met1 48 + SHAPE FOLLOWPIN ( 0 1904 ) ( 9200 1904 ) - NEW met1 48 + SHAPE FOLLOWPIN ( 0 1360 ) ( 9200 1360 ) - NEW met1 48 + SHAPE FOLLOWPIN ( 0 816 ) ( 9200 816 ) - NEW met1 48 + SHAPE FOLLOWPIN ( 0 272 ) ( 9200 272 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 2448 ) ( 9568 2448 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 1904 ) ( 9568 1904 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 1360 ) ( 9568 1360 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 816 ) ( 9568 816 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 272 ) ( 9568 272 ) NEW met2 0 + SHAPE STRIPE ( 6000 1000 ) via3_4_480_480_1_1_400_400 NEW met2 0 + SHAPE STRIPE ( 2000 1000 ) via3_4_480_480_1_1_400_400 NEW met1 0 + SHAPE STRIPE ( 6000 2448 ) via2_3_480_480_1_1_320_320 @@ -601,15 +609,15 @@ SPECIALNETS 2 ; ( storage_0_0_0.gcand VGND ) ( storage_0_0_0.cg VGND ) ( storage_0_0_0.bit7.obuf0 VGND ) ( storage_0_0_0.bit7.bit VGND ) ( storage_0_0_0.bit6.obuf0 VGND ) ( storage_0_0_0.bit6.bit VGND ) ( storage_0_0_0.bit5.obuf0 VGND ) ( storage_0_0_0.bit5.bit VGND ) ( storage_0_0_0.bit4.obuf0 VGND ) ( storage_0_0_0.bit4.bit VGND ) ( storage_0_0_0.bit3.obuf0 VGND ) ( storage_0_0_0.bit3.bit VGND ) ( storage_0_0_0.bit2.obuf0 VGND ) ( storage_0_0_0.bit2.bit VGND ) ( storage_0_0_0.bit1.obuf0 VGND ) ( storage_0_0_0.bit1.bit VGND ) ( storage_0_0_0.bit0.obuf0 VGND ) ( storage_0_0_0.bit0.bit VGND ) + USE GROUND - + ROUTED met3 48 + SHAPE STRIPE ( 0 2000 ) ( 9200 2000 ) + + ROUTED met3 48 + SHAPE STRIPE ( 0 2000 ) ( 9568 2000 ) NEW met2 48 + SHAPE STRIPE ( 8000 -24 ) ( 8000 2744 ) NEW met2 48 + SHAPE STRIPE ( 4000 -24 ) ( 4000 2744 ) - NEW met1 48 + SHAPE FOLLOWPIN ( 0 2720 ) ( 9200 2720 ) - NEW met1 48 + SHAPE FOLLOWPIN ( 0 2176 ) ( 9200 2176 ) - NEW met1 48 + SHAPE FOLLOWPIN ( 0 1632 ) ( 9200 1632 ) - NEW met1 48 + SHAPE FOLLOWPIN ( 0 1088 ) ( 9200 1088 ) - NEW met1 48 + SHAPE FOLLOWPIN ( 0 544 ) ( 9200 544 ) - NEW met1 48 + SHAPE FOLLOWPIN ( 0 0 ) ( 9200 0 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 2720 ) ( 9568 2720 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 2176 ) ( 9568 2176 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 1632 ) ( 9568 1632 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 1088 ) ( 9568 1088 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 544 ) ( 9568 544 ) + NEW met1 48 + SHAPE FOLLOWPIN ( 0 0 ) ( 9568 0 ) NEW met2 0 + SHAPE STRIPE ( 8000 2000 ) via3_4_480_480_1_1_400_400 NEW met2 0 + SHAPE STRIPE ( 4000 2000 ) via3_4_480_480_1_1_400_400 NEW met1 0 + SHAPE STRIPE ( 8000 2720 ) via2_3_480_480_1_1_320_320 @@ -633,1832 +641,1816 @@ NETS 153 ; NEW li1 ( 69 2601 ) L1M1_PR_MR ; - D[1] ( PIN D[1] ) ( buffer.in[1] A ) + USE SIGNAL + ROUTED met2 ( 1035 2601 ) ( * 2686 0 ) - NEW met1 ( 989 2601 ) ( 1035 * ) - NEW met1 ( 1035 2601 ) M1M2_PR - NEW li1 ( 989 2601 ) L1M1_PR_MR ; + NEW li1 ( 1035 2601 ) L1M1_PR_MR + NEW met1 ( 1035 2601 ) M1M2_PR ; - D[2] ( PIN D[2] ) ( buffer.in[2] A ) + USE SIGNAL - + ROUTED met2 ( 1955 2618 ) ( * 2686 0 ) - NEW met2 ( 1909 2618 ) ( 1955 * ) - NEW met2 ( 1909 2601 ) ( * 2618 ) - NEW li1 ( 1909 2601 ) L1M1_PR_MR - NEW met1 ( 1909 2601 ) M1M2_PR ; + + ROUTED met2 ( 2047 2618 ) ( * 2686 0 ) + NEW met2 ( 2047 2618 ) ( 2093 * ) + NEW met2 ( 2093 2601 ) ( * 2618 ) + NEW met1 ( 2001 2601 ) ( 2093 * ) + NEW met1 ( 2093 2601 ) M1M2_PR + NEW li1 ( 2001 2601 ) L1M1_PR_MR ; - D[3] ( PIN D[3] ) ( buffer.in[3] A ) + USE SIGNAL - + ROUTED met2 ( 2875 2601 ) ( * 2686 0 ) - NEW met1 ( 2829 2601 ) ( 2875 * ) - NEW met1 ( 2875 2601 ) M1M2_PR - NEW li1 ( 2829 2601 ) L1M1_PR_MR ; + + ROUTED met2 ( 2967 2601 ) ( * 2686 0 ) + NEW li1 ( 2967 2601 ) L1M1_PR_MR + NEW met1 ( 2967 2601 ) M1M2_PR ; - D[4] ( PIN D[4] ) ( buffer.in[4] A ) + USE SIGNAL - + ROUTED met2 ( 3795 2601 ) ( * 2686 0 ) - NEW met1 ( 3749 2601 ) ( 3795 * ) - NEW met1 ( 3795 2601 ) M1M2_PR - NEW li1 ( 3749 2601 ) L1M1_PR_MR ; + + ROUTED met2 ( 3887 2601 ) ( * 2686 0 ) + NEW met1 ( 3887 2601 ) ( 3933 * ) + NEW met1 ( 3887 2601 ) M1M2_PR + NEW li1 ( 3933 2601 ) L1M1_PR_MR ; - D[5] ( PIN D[5] ) ( buffer.in[5] A ) + USE SIGNAL - + ROUTED met2 ( 4715 2601 ) ( * 2686 0 ) - NEW met1 ( 4669 2601 ) ( 4715 * ) - NEW met1 ( 4715 2601 ) M1M2_PR - NEW li1 ( 4669 2601 ) L1M1_PR_MR ; + + ROUTED met2 ( 4899 2601 ) ( * 2686 0 ) + NEW li1 ( 4899 2601 ) L1M1_PR_MR + NEW met1 ( 4899 2601 ) M1M2_PR ; - D[6] ( PIN D[6] ) ( buffer.in[6] A ) + USE SIGNAL - + ROUTED met2 ( 5635 2601 ) ( * 2686 0 ) - NEW met1 ( 5589 2601 ) ( 5635 * ) - NEW met1 ( 5635 2601 ) M1M2_PR - NEW li1 ( 5589 2601 ) L1M1_PR_MR ; + + ROUTED met2 ( 5911 2601 ) ( * 2686 0 ) + NEW met1 ( 5865 2601 ) ( 5911 * ) + NEW met1 ( 5911 2601 ) M1M2_PR + NEW li1 ( 5865 2601 ) L1M1_PR_MR ; - D[7] ( PIN D[7] ) ( buffer.in[7] A ) + USE SIGNAL - + ROUTED met2 ( 6555 2601 ) ( * 2686 0 ) - NEW met1 ( 6509 2601 ) ( 6555 * ) - NEW met1 ( 6555 2601 ) M1M2_PR - NEW li1 ( 6509 2601 ) L1M1_PR_MR ; + + ROUTED met2 ( 6831 2601 ) ( * 2686 0 ) + NEW li1 ( 6831 2601 ) L1M1_PR_MR + NEW met1 ( 6831 2601 ) M1M2_PR ; - D_nets.b0 ( buffer.in[0] X ) ( neg_lat_b0.nlat D ) + USE SIGNAL - + ROUTED met1 ( 161 2261 ) ( 229 * ) - NEW met2 ( 161 2261 ) ( * 2499 ) - NEW li1 ( 229 2261 ) L1M1_PR_MR - NEW met1 ( 161 2261 ) M1M2_PR - NEW li1 ( 161 2499 ) L1M1_PR_MR - NEW met1 ( 161 2499 ) M1M2_PR ; + + ROUTED met2 ( 207 2295 ) ( * 2499 ) + NEW met1 ( 161 2499 ) ( 207 * ) + NEW li1 ( 207 2295 ) L1M1_PR_MR + NEW met1 ( 207 2295 ) M1M2_PR + NEW met1 ( 207 2499 ) M1M2_PR + NEW li1 ( 161 2499 ) L1M1_PR_MR ; - D_nets.b1 ( buffer.in[1] X ) ( neg_lat_b1.nlat D ) + USE SIGNAL - + ROUTED met1 ( 1081 2261 ) ( 1149 * ) - NEW met2 ( 1081 2261 ) ( * 2499 ) - NEW li1 ( 1149 2261 ) L1M1_PR_MR - NEW met1 ( 1081 2261 ) M1M2_PR - NEW li1 ( 1081 2499 ) L1M1_PR_MR - NEW met1 ( 1081 2499 ) M1M2_PR ; + + ROUTED met2 ( 1173 2295 ) ( * 2499 ) + NEW met1 ( 1127 2499 ) ( 1173 * ) + NEW li1 ( 1173 2295 ) L1M1_PR_MR + NEW met1 ( 1173 2295 ) M1M2_PR + NEW met1 ( 1173 2499 ) M1M2_PR + NEW li1 ( 1127 2499 ) L1M1_PR_MR ; - D_nets.b2 ( buffer.in[2] X ) ( neg_lat_b2.nlat D ) + USE SIGNAL - + ROUTED met1 ( 2090 2261 ) ( 2093 * ) - NEW met2 ( 2093 2261 ) ( * 2499 ) - NEW met1 ( 2001 2499 ) ( 2093 * ) - NEW li1 ( 2090 2261 ) L1M1_PR_MR - NEW met1 ( 2093 2261 ) M1M2_PR - NEW met1 ( 2093 2499 ) M1M2_PR - NEW li1 ( 2001 2499 ) L1M1_PR_MR - NEW met1 ( 2090 2261 ) RECT ( -32 -7 0 7 ) ; + + ROUTED met2 ( 2139 2295 ) ( * 2499 ) + NEW met1 ( 2093 2499 ) ( 2139 * ) + NEW li1 ( 2139 2295 ) L1M1_PR_MR + NEW met1 ( 2139 2295 ) M1M2_PR + NEW met1 ( 2139 2499 ) M1M2_PR + NEW li1 ( 2093 2499 ) L1M1_PR_MR ; - D_nets.b3 ( buffer.in[3] X ) ( neg_lat_b3.nlat D ) + USE SIGNAL - + ROUTED met1 ( 2921 2261 ) ( 2989 * ) - NEW met2 ( 2921 2261 ) ( * 2499 ) - NEW li1 ( 2989 2261 ) L1M1_PR_MR - NEW met1 ( 2921 2261 ) M1M2_PR - NEW li1 ( 2921 2499 ) L1M1_PR_MR - NEW met1 ( 2921 2499 ) M1M2_PR ; + + ROUTED met2 ( 3105 2295 ) ( * 2499 ) + NEW met1 ( 3059 2499 ) ( 3105 * ) + NEW li1 ( 3105 2295 ) L1M1_PR_MR + NEW met1 ( 3105 2295 ) M1M2_PR + NEW met1 ( 3105 2499 ) M1M2_PR + NEW li1 ( 3059 2499 ) L1M1_PR_MR ; - D_nets.b4 ( buffer.in[4] X ) ( neg_lat_b4.nlat D ) + USE SIGNAL - + ROUTED met1 ( 3841 2261 ) ( 3909 * ) - NEW met2 ( 3841 2261 ) ( * 2499 ) - NEW li1 ( 3909 2261 ) L1M1_PR_MR - NEW met1 ( 3841 2261 ) M1M2_PR - NEW li1 ( 3841 2499 ) L1M1_PR_MR - NEW met1 ( 3841 2499 ) M1M2_PR ; + + ROUTED met2 ( 4071 2295 ) ( * 2499 ) + NEW met1 ( 4025 2499 ) ( 4071 * ) + NEW li1 ( 4071 2295 ) L1M1_PR_MR + NEW met1 ( 4071 2295 ) M1M2_PR + NEW met1 ( 4071 2499 ) M1M2_PR + NEW li1 ( 4025 2499 ) L1M1_PR_MR ; - D_nets.b5 ( buffer.in[5] X ) ( neg_lat_b5.nlat D ) + USE SIGNAL - + ROUTED met1 ( 4761 2261 ) ( 4829 * ) - NEW met2 ( 4761 2261 ) ( * 2499 ) - NEW li1 ( 4829 2261 ) L1M1_PR_MR - NEW met1 ( 4761 2261 ) M1M2_PR - NEW li1 ( 4761 2499 ) L1M1_PR_MR - NEW met1 ( 4761 2499 ) M1M2_PR ; + + ROUTED met2 ( 5037 2295 ) ( * 2499 ) + NEW met1 ( 4991 2499 ) ( 5037 * ) + NEW li1 ( 5037 2295 ) L1M1_PR_MR + NEW met1 ( 5037 2295 ) M1M2_PR + NEW met1 ( 5037 2499 ) M1M2_PR + NEW li1 ( 4991 2499 ) L1M1_PR_MR ; - D_nets.b6 ( buffer.in[6] X ) ( neg_lat_b6.nlat D ) + USE SIGNAL - + ROUTED met1 ( 5681 2261 ) ( 5749 * ) - NEW met2 ( 5681 2261 ) ( * 2499 ) - NEW li1 ( 5749 2261 ) L1M1_PR_MR - NEW met1 ( 5681 2261 ) M1M2_PR - NEW li1 ( 5681 2499 ) L1M1_PR_MR - NEW met1 ( 5681 2499 ) M1M2_PR ; + + ROUTED met1 ( 5911 2295 ) ( 6003 * ) + NEW met1 ( 5911 2261 ) ( * 2295 ) + NEW met2 ( 5911 2261 ) ( * 2499 ) + NEW met1 ( 5911 2499 ) ( 5957 * ) + NEW li1 ( 6003 2295 ) L1M1_PR_MR + NEW met1 ( 5911 2261 ) M1M2_PR + NEW met1 ( 5911 2499 ) M1M2_PR + NEW li1 ( 5957 2499 ) L1M1_PR_MR ; - D_nets.b7 ( buffer.in[7] X ) ( neg_lat_b7.nlat D ) + USE SIGNAL - + ROUTED met1 ( 6601 2261 ) ( 6669 * ) - NEW met2 ( 6601 2261 ) ( * 2499 ) - NEW li1 ( 6669 2261 ) L1M1_PR_MR - NEW met1 ( 6601 2261 ) M1M2_PR - NEW li1 ( 6601 2499 ) L1M1_PR_MR - NEW met1 ( 6601 2499 ) M1M2_PR ; + + ROUTED met2 ( 6969 2295 ) ( * 2499 ) + NEW met1 ( 6923 2499 ) ( 6969 * ) + NEW li1 ( 6969 2295 ) L1M1_PR_MR + NEW met1 ( 6969 2295 ) M1M2_PR + NEW met1 ( 6969 2499 ) M1M2_PR + NEW li1 ( 6923 2499 ) L1M1_PR_MR ; - Q[0] ( PIN Q[0] ) ( storage_7_0_0.bit0.obuf0 Z ) ( storage_6_0_0.bit0.obuf0 Z ) ( storage_5_0_0.bit0.obuf0 Z ) ( storage_4_0_0.bit0.obuf0 Z ) ( storage_3_0_0.bit0.obuf0 Z ) ( storage_2_0_0.bit0.obuf0 Z ) ( storage_1_0_0.bit0.obuf0 Z ) ( storage_0_0_0.bit0.obuf0 Z ) + USE SIGNAL - + ROUTED met1 ( 851 2125 ) ( 897 * ) - NEW met2 ( 851 2125 ) ( * 2686 0 ) - NEW met2 ( 851 1853 ) ( * 2125 ) - NEW met1 ( 851 1581 ) ( 897 * ) - NEW met2 ( 851 1581 ) ( * 1853 ) - NEW met2 ( 851 1309 ) ( * 1581 ) - NEW met1 ( 851 1037 ) ( 897 * ) - NEW met2 ( 851 1037 ) ( * 1309 ) - NEW met2 ( 851 765 ) ( * 1037 ) - NEW met1 ( 851 493 ) ( 897 * ) - NEW met2 ( 851 493 ) ( * 765 ) - NEW met2 ( 851 221 ) ( * 493 ) - NEW li1 ( 897 2125 ) L1M1_PR_MR - NEW met1 ( 851 2125 ) M1M2_PR - NEW li1 ( 851 1853 ) L1M1_PR_MR - NEW met1 ( 851 1853 ) M1M2_PR - NEW li1 ( 897 1581 ) L1M1_PR_MR - NEW met1 ( 851 1581 ) M1M2_PR - NEW li1 ( 851 1309 ) L1M1_PR_MR - NEW met1 ( 851 1309 ) M1M2_PR - NEW li1 ( 897 1037 ) L1M1_PR_MR - NEW met1 ( 851 1037 ) M1M2_PR - NEW li1 ( 851 765 ) L1M1_PR_MR - NEW met1 ( 851 765 ) M1M2_PR - NEW li1 ( 897 493 ) L1M1_PR_MR - NEW met1 ( 851 493 ) M1M2_PR - NEW li1 ( 851 221 ) L1M1_PR_MR - NEW met1 ( 851 221 ) M1M2_PR ; + + ROUTED met2 ( 943 2125 ) ( * 2686 0 ) + NEW met2 ( 943 1853 ) ( * 2125 ) + NEW met2 ( 943 1581 ) ( * 1853 ) + NEW met2 ( 943 1309 ) ( * 1581 ) + NEW met2 ( 943 1037 ) ( * 1309 ) + NEW met2 ( 943 765 ) ( * 1037 ) + NEW met2 ( 943 493 ) ( * 765 ) + NEW met2 ( 943 221 ) ( * 493 ) + NEW li1 ( 943 2125 ) L1M1_PR_MR + NEW met1 ( 943 2125 ) M1M2_PR + NEW li1 ( 943 1853 ) L1M1_PR_MR + NEW met1 ( 943 1853 ) M1M2_PR + NEW li1 ( 943 1581 ) L1M1_PR_MR + NEW met1 ( 943 1581 ) M1M2_PR + NEW li1 ( 943 1309 ) L1M1_PR_MR + NEW met1 ( 943 1309 ) M1M2_PR + NEW li1 ( 943 1037 ) L1M1_PR_MR + NEW met1 ( 943 1037 ) M1M2_PR + NEW li1 ( 943 765 ) L1M1_PR_MR + NEW met1 ( 943 765 ) M1M2_PR + NEW li1 ( 943 493 ) L1M1_PR_MR + NEW met1 ( 943 493 ) M1M2_PR + NEW li1 ( 943 221 ) L1M1_PR_MR + NEW met1 ( 943 221 ) M1M2_PR ; - Q[1] ( PIN Q[1] ) ( storage_7_0_0.bit1.obuf0 Z ) ( storage_6_0_0.bit1.obuf0 Z ) ( storage_5_0_0.bit1.obuf0 Z ) ( storage_4_0_0.bit1.obuf0 Z ) ( storage_3_0_0.bit1.obuf0 Z ) ( storage_2_0_0.bit1.obuf0 Z ) ( storage_1_0_0.bit1.obuf0 Z ) ( storage_0_0_0.bit1.obuf0 Z ) + USE SIGNAL - + ROUTED met1 ( 1771 1037 ) ( 1817 * ) - NEW met2 ( 1771 1037 ) ( * 1309 ) - NEW met2 ( 1771 765 ) ( * 1037 ) - NEW met1 ( 1771 493 ) ( 1817 * ) - NEW met2 ( 1771 493 ) ( * 765 ) - NEW met2 ( 1771 221 ) ( * 493 ) - NEW met1 ( 1771 2125 ) ( 1817 * ) - NEW met2 ( 1771 2125 ) ( * 2686 0 ) - NEW met2 ( 1771 1853 ) ( * 2125 ) - NEW met1 ( 1771 1581 ) ( 1817 * ) - NEW met2 ( 1771 1581 ) ( * 1853 ) - NEW met2 ( 1771 1309 ) ( * 1581 ) - NEW li1 ( 1771 1309 ) L1M1_PR_MR - NEW met1 ( 1771 1309 ) M1M2_PR - NEW li1 ( 1817 1037 ) L1M1_PR_MR - NEW met1 ( 1771 1037 ) M1M2_PR - NEW li1 ( 1771 765 ) L1M1_PR_MR - NEW met1 ( 1771 765 ) M1M2_PR - NEW li1 ( 1817 493 ) L1M1_PR_MR - NEW met1 ( 1771 493 ) M1M2_PR - NEW li1 ( 1771 221 ) L1M1_PR_MR - NEW met1 ( 1771 221 ) M1M2_PR - NEW li1 ( 1817 2125 ) L1M1_PR_MR - NEW met1 ( 1771 2125 ) M1M2_PR - NEW li1 ( 1771 1853 ) L1M1_PR_MR - NEW met1 ( 1771 1853 ) M1M2_PR - NEW li1 ( 1817 1581 ) L1M1_PR_MR - NEW met1 ( 1771 1581 ) M1M2_PR ; + + ROUTED met1 ( 1863 1037 ) ( 1909 * ) + NEW met2 ( 1863 1037 ) ( * 1309 ) + NEW met2 ( 1863 765 ) ( * 1037 ) + NEW met1 ( 1863 493 ) ( 1909 * ) + NEW met2 ( 1863 493 ) ( * 765 ) + NEW met2 ( 1863 221 ) ( * 493 ) + NEW met1 ( 1863 2125 ) ( 1909 * ) + NEW met2 ( 1863 2125 ) ( * 2686 0 ) + NEW met2 ( 1863 1853 ) ( * 2125 ) + NEW met1 ( 1863 1581 ) ( 1909 * ) + NEW met2 ( 1863 1581 ) ( * 1853 ) + NEW met2 ( 1863 1309 ) ( * 1581 ) + NEW li1 ( 1863 1309 ) L1M1_PR_MR + NEW met1 ( 1863 1309 ) M1M2_PR + NEW li1 ( 1909 1037 ) L1M1_PR_MR + NEW met1 ( 1863 1037 ) M1M2_PR + NEW li1 ( 1863 765 ) L1M1_PR_MR + NEW met1 ( 1863 765 ) M1M2_PR + NEW li1 ( 1909 493 ) L1M1_PR_MR + NEW met1 ( 1863 493 ) M1M2_PR + NEW li1 ( 1863 221 ) L1M1_PR_MR + NEW met1 ( 1863 221 ) M1M2_PR + NEW li1 ( 1909 2125 ) L1M1_PR_MR + NEW met1 ( 1863 2125 ) M1M2_PR + NEW li1 ( 1863 1853 ) L1M1_PR_MR + NEW met1 ( 1863 1853 ) M1M2_PR + NEW li1 ( 1909 1581 ) L1M1_PR_MR + NEW met1 ( 1863 1581 ) M1M2_PR ; - Q[2] ( PIN Q[2] ) ( storage_7_0_0.bit2.obuf0 Z ) ( storage_6_0_0.bit2.obuf0 Z ) ( storage_5_0_0.bit2.obuf0 Z ) ( storage_4_0_0.bit2.obuf0 Z ) ( storage_3_0_0.bit2.obuf0 Z ) ( storage_2_0_0.bit2.obuf0 Z ) ( storage_1_0_0.bit2.obuf0 Z ) ( storage_0_0_0.bit2.obuf0 Z ) + USE SIGNAL - + ROUTED met1 ( 2691 1037 ) ( 2737 * ) - NEW met2 ( 2691 1037 ) ( * 1309 ) - NEW met2 ( 2691 765 ) ( * 1037 ) - NEW met1 ( 2691 493 ) ( 2737 * ) - NEW met2 ( 2691 493 ) ( * 765 ) - NEW met2 ( 2691 221 ) ( * 493 ) - NEW met1 ( 2691 2125 ) ( 2737 * ) - NEW met2 ( 2691 2125 ) ( * 2686 0 ) - NEW met2 ( 2691 1853 ) ( * 2125 ) - NEW met1 ( 2691 1581 ) ( 2737 * ) - NEW met2 ( 2691 1581 ) ( * 1853 ) - NEW met2 ( 2691 1309 ) ( * 1581 ) - NEW li1 ( 2691 1309 ) L1M1_PR_MR - NEW met1 ( 2691 1309 ) M1M2_PR - NEW li1 ( 2737 1037 ) L1M1_PR_MR - NEW met1 ( 2691 1037 ) M1M2_PR - NEW li1 ( 2691 765 ) L1M1_PR_MR - NEW met1 ( 2691 765 ) M1M2_PR - NEW li1 ( 2737 493 ) L1M1_PR_MR - NEW met1 ( 2691 493 ) M1M2_PR - NEW li1 ( 2691 221 ) L1M1_PR_MR - NEW met1 ( 2691 221 ) M1M2_PR - NEW li1 ( 2737 2125 ) L1M1_PR_MR - NEW met1 ( 2691 2125 ) M1M2_PR - NEW li1 ( 2691 1853 ) L1M1_PR_MR - NEW met1 ( 2691 1853 ) M1M2_PR - NEW li1 ( 2737 1581 ) L1M1_PR_MR - NEW met1 ( 2691 1581 ) M1M2_PR ; + + ROUTED met2 ( 2875 1037 ) ( * 1309 ) + NEW met2 ( 2875 765 ) ( * 1037 ) + NEW met2 ( 2875 493 ) ( * 765 ) + NEW met2 ( 2875 221 ) ( * 493 ) + NEW met2 ( 2875 2125 ) ( * 2686 0 ) + NEW met2 ( 2875 1853 ) ( * 2125 ) + NEW met2 ( 2875 1581 ) ( * 1853 ) + NEW met2 ( 2875 1309 ) ( * 1581 ) + NEW li1 ( 2875 1309 ) L1M1_PR_MR + NEW met1 ( 2875 1309 ) M1M2_PR + NEW li1 ( 2875 1037 ) L1M1_PR_MR + NEW met1 ( 2875 1037 ) M1M2_PR + NEW li1 ( 2875 765 ) L1M1_PR_MR + NEW met1 ( 2875 765 ) M1M2_PR + NEW li1 ( 2875 493 ) L1M1_PR_MR + NEW met1 ( 2875 493 ) M1M2_PR + NEW li1 ( 2875 221 ) L1M1_PR_MR + NEW met1 ( 2875 221 ) M1M2_PR + NEW li1 ( 2875 2125 ) L1M1_PR_MR + NEW met1 ( 2875 2125 ) M1M2_PR + NEW li1 ( 2875 1853 ) L1M1_PR_MR + NEW met1 ( 2875 1853 ) M1M2_PR + NEW li1 ( 2875 1581 ) L1M1_PR_MR + NEW met1 ( 2875 1581 ) M1M2_PR ; - Q[3] ( PIN Q[3] ) ( storage_7_0_0.bit3.obuf0 Z ) ( storage_6_0_0.bit3.obuf0 Z ) ( storage_5_0_0.bit3.obuf0 Z ) ( storage_4_0_0.bit3.obuf0 Z ) ( storage_3_0_0.bit3.obuf0 Z ) ( storage_2_0_0.bit3.obuf0 Z ) ( storage_1_0_0.bit3.obuf0 Z ) ( storage_0_0_0.bit3.obuf0 Z ) + USE SIGNAL - + ROUTED met1 ( 3611 1037 ) ( 3657 * ) - NEW met2 ( 3611 1037 ) ( * 1309 ) - NEW met2 ( 3611 765 ) ( * 1037 ) - NEW met1 ( 3611 493 ) ( 3657 * ) - NEW met2 ( 3611 493 ) ( * 765 ) - NEW met2 ( 3611 221 ) ( * 493 ) - NEW met1 ( 3611 2125 ) ( 3657 * ) - NEW met2 ( 3611 2125 ) ( * 2686 0 ) - NEW met2 ( 3611 1853 ) ( * 2125 ) - NEW met1 ( 3611 1581 ) ( 3657 * ) - NEW met2 ( 3611 1581 ) ( * 1853 ) - NEW met2 ( 3611 1309 ) ( * 1581 ) - NEW li1 ( 3611 1309 ) L1M1_PR_MR - NEW met1 ( 3611 1309 ) M1M2_PR - NEW li1 ( 3657 1037 ) L1M1_PR_MR - NEW met1 ( 3611 1037 ) M1M2_PR - NEW li1 ( 3611 765 ) L1M1_PR_MR - NEW met1 ( 3611 765 ) M1M2_PR - NEW li1 ( 3657 493 ) L1M1_PR_MR - NEW met1 ( 3611 493 ) M1M2_PR - NEW li1 ( 3611 221 ) L1M1_PR_MR - NEW met1 ( 3611 221 ) M1M2_PR - NEW li1 ( 3657 2125 ) L1M1_PR_MR - NEW met1 ( 3611 2125 ) M1M2_PR - NEW li1 ( 3611 1853 ) L1M1_PR_MR - NEW met1 ( 3611 1853 ) M1M2_PR - NEW li1 ( 3657 1581 ) L1M1_PR_MR - NEW met1 ( 3611 1581 ) M1M2_PR ; + + ROUTED met1 ( 3795 1037 ) ( 3841 * ) + NEW met2 ( 3795 1037 ) ( * 1309 ) + NEW met2 ( 3795 765 ) ( * 1037 ) + NEW met1 ( 3795 493 ) ( 3841 * ) + NEW met2 ( 3795 493 ) ( * 765 ) + NEW met2 ( 3795 221 ) ( * 493 ) + NEW met1 ( 3795 2125 ) ( 3841 * ) + NEW met2 ( 3795 2125 ) ( * 2686 0 ) + NEW met2 ( 3795 1853 ) ( * 2125 ) + NEW met1 ( 3795 1581 ) ( 3841 * ) + NEW met2 ( 3795 1581 ) ( * 1853 ) + NEW met2 ( 3795 1309 ) ( * 1581 ) + NEW li1 ( 3795 1309 ) L1M1_PR_MR + NEW met1 ( 3795 1309 ) M1M2_PR + NEW li1 ( 3841 1037 ) L1M1_PR_MR + NEW met1 ( 3795 1037 ) M1M2_PR + NEW li1 ( 3795 765 ) L1M1_PR_MR + NEW met1 ( 3795 765 ) M1M2_PR + NEW li1 ( 3841 493 ) L1M1_PR_MR + NEW met1 ( 3795 493 ) M1M2_PR + NEW li1 ( 3795 221 ) L1M1_PR_MR + NEW met1 ( 3795 221 ) M1M2_PR + NEW li1 ( 3841 2125 ) L1M1_PR_MR + NEW met1 ( 3795 2125 ) M1M2_PR + NEW li1 ( 3795 1853 ) L1M1_PR_MR + NEW met1 ( 3795 1853 ) M1M2_PR + NEW li1 ( 3841 1581 ) L1M1_PR_MR + NEW met1 ( 3795 1581 ) M1M2_PR ; - Q[4] ( PIN Q[4] ) ( storage_7_0_0.bit4.obuf0 Z ) ( storage_6_0_0.bit4.obuf0 Z ) ( storage_5_0_0.bit4.obuf0 Z ) ( storage_4_0_0.bit4.obuf0 Z ) ( storage_3_0_0.bit4.obuf0 Z ) ( storage_2_0_0.bit4.obuf0 Z ) ( storage_1_0_0.bit4.obuf0 Z ) ( storage_0_0_0.bit4.obuf0 Z ) + USE SIGNAL - + ROUTED met1 ( 4531 1037 ) ( 4577 * ) - NEW met2 ( 4531 1037 ) ( * 1309 ) - NEW met2 ( 4531 765 ) ( * 1037 ) - NEW met1 ( 4531 493 ) ( 4577 * ) - NEW met2 ( 4531 493 ) ( * 765 ) - NEW met2 ( 4531 221 ) ( * 493 ) - NEW met1 ( 4531 2125 ) ( 4577 * ) - NEW met2 ( 4531 2125 ) ( * 2686 0 ) - NEW met2 ( 4531 1853 ) ( * 2125 ) - NEW met1 ( 4531 1581 ) ( 4577 * ) - NEW met2 ( 4531 1581 ) ( * 1853 ) - NEW met2 ( 4531 1309 ) ( * 1581 ) - NEW li1 ( 4531 1309 ) L1M1_PR_MR - NEW met1 ( 4531 1309 ) M1M2_PR - NEW li1 ( 4577 1037 ) L1M1_PR_MR - NEW met1 ( 4531 1037 ) M1M2_PR - NEW li1 ( 4531 765 ) L1M1_PR_MR - NEW met1 ( 4531 765 ) M1M2_PR - NEW li1 ( 4577 493 ) L1M1_PR_MR - NEW met1 ( 4531 493 ) M1M2_PR - NEW li1 ( 4531 221 ) L1M1_PR_MR - NEW met1 ( 4531 221 ) M1M2_PR - NEW li1 ( 4577 2125 ) L1M1_PR_MR - NEW met1 ( 4531 2125 ) M1M2_PR - NEW li1 ( 4531 1853 ) L1M1_PR_MR - NEW met1 ( 4531 1853 ) M1M2_PR - NEW li1 ( 4577 1581 ) L1M1_PR_MR - NEW met1 ( 4531 1581 ) M1M2_PR ; + + ROUTED met2 ( 4807 1037 ) ( * 1309 ) + NEW met2 ( 4807 765 ) ( * 1037 ) + NEW met2 ( 4807 493 ) ( * 765 ) + NEW met2 ( 4807 221 ) ( * 493 ) + NEW met2 ( 4807 2125 ) ( * 2686 0 ) + NEW met2 ( 4807 1853 ) ( * 2125 ) + NEW met2 ( 4807 1581 ) ( * 1853 ) + NEW met2 ( 4807 1309 ) ( * 1581 ) + NEW li1 ( 4807 1309 ) L1M1_PR_MR + NEW met1 ( 4807 1309 ) M1M2_PR + NEW li1 ( 4807 1037 ) L1M1_PR_MR + NEW met1 ( 4807 1037 ) M1M2_PR + NEW li1 ( 4807 765 ) L1M1_PR_MR + NEW met1 ( 4807 765 ) M1M2_PR + NEW li1 ( 4807 493 ) L1M1_PR_MR + NEW met1 ( 4807 493 ) M1M2_PR + NEW li1 ( 4807 221 ) L1M1_PR_MR + NEW met1 ( 4807 221 ) M1M2_PR + NEW li1 ( 4807 2125 ) L1M1_PR_MR + NEW met1 ( 4807 2125 ) M1M2_PR + NEW li1 ( 4807 1853 ) L1M1_PR_MR + NEW met1 ( 4807 1853 ) M1M2_PR + NEW li1 ( 4807 1581 ) L1M1_PR_MR + NEW met1 ( 4807 1581 ) M1M2_PR ; - Q[5] ( PIN Q[5] ) ( storage_7_0_0.bit5.obuf0 Z ) ( storage_6_0_0.bit5.obuf0 Z ) ( storage_5_0_0.bit5.obuf0 Z ) ( storage_4_0_0.bit5.obuf0 Z ) ( storage_3_0_0.bit5.obuf0 Z ) ( storage_2_0_0.bit5.obuf0 Z ) ( storage_1_0_0.bit5.obuf0 Z ) ( storage_0_0_0.bit5.obuf0 Z ) + USE SIGNAL - + ROUTED met1 ( 5451 1037 ) ( 5497 * ) - NEW met2 ( 5451 1037 ) ( * 1309 ) - NEW met2 ( 5451 765 ) ( * 1037 ) - NEW met1 ( 5451 493 ) ( 5497 * ) - NEW met2 ( 5451 493 ) ( * 765 ) - NEW met2 ( 5451 221 ) ( * 493 ) - NEW met1 ( 5451 2125 ) ( 5497 * ) - NEW met2 ( 5451 2125 ) ( * 2686 0 ) - NEW met2 ( 5451 1853 ) ( * 2125 ) - NEW met1 ( 5451 1581 ) ( 5497 * ) - NEW met2 ( 5451 1581 ) ( * 1853 ) - NEW met2 ( 5451 1309 ) ( * 1581 ) - NEW li1 ( 5451 1309 ) L1M1_PR_MR - NEW met1 ( 5451 1309 ) M1M2_PR - NEW li1 ( 5497 1037 ) L1M1_PR_MR - NEW met1 ( 5451 1037 ) M1M2_PR - NEW li1 ( 5451 765 ) L1M1_PR_MR - NEW met1 ( 5451 765 ) M1M2_PR - NEW li1 ( 5497 493 ) L1M1_PR_MR - NEW met1 ( 5451 493 ) M1M2_PR - NEW li1 ( 5451 221 ) L1M1_PR_MR - NEW met1 ( 5451 221 ) M1M2_PR - NEW li1 ( 5497 2125 ) L1M1_PR_MR - NEW met1 ( 5451 2125 ) M1M2_PR - NEW li1 ( 5451 1853 ) L1M1_PR_MR - NEW met1 ( 5451 1853 ) M1M2_PR - NEW li1 ( 5497 1581 ) L1M1_PR_MR - NEW met1 ( 5451 1581 ) M1M2_PR ; + + ROUTED met1 ( 5727 1037 ) ( 5773 * ) + NEW met2 ( 5727 1037 ) ( * 1309 ) + NEW met2 ( 5727 765 ) ( * 1037 ) + NEW met1 ( 5727 493 ) ( 5773 * ) + NEW met2 ( 5727 493 ) ( * 765 ) + NEW met2 ( 5727 221 ) ( * 493 ) + NEW met1 ( 5727 2125 ) ( 5773 * ) + NEW met2 ( 5727 2125 ) ( * 2686 0 ) + NEW met2 ( 5727 1853 ) ( * 2125 ) + NEW met1 ( 5727 1581 ) ( 5773 * ) + NEW met2 ( 5727 1581 ) ( * 1853 ) + NEW met2 ( 5727 1309 ) ( * 1581 ) + NEW li1 ( 5727 1309 ) L1M1_PR_MR + NEW met1 ( 5727 1309 ) M1M2_PR + NEW li1 ( 5773 1037 ) L1M1_PR_MR + NEW met1 ( 5727 1037 ) M1M2_PR + NEW li1 ( 5727 765 ) L1M1_PR_MR + NEW met1 ( 5727 765 ) M1M2_PR + NEW li1 ( 5773 493 ) L1M1_PR_MR + NEW met1 ( 5727 493 ) M1M2_PR + NEW li1 ( 5727 221 ) L1M1_PR_MR + NEW met1 ( 5727 221 ) M1M2_PR + NEW li1 ( 5773 2125 ) L1M1_PR_MR + NEW met1 ( 5727 2125 ) M1M2_PR + NEW li1 ( 5727 1853 ) L1M1_PR_MR + NEW met1 ( 5727 1853 ) M1M2_PR + NEW li1 ( 5773 1581 ) L1M1_PR_MR + NEW met1 ( 5727 1581 ) M1M2_PR ; - Q[6] ( PIN Q[6] ) ( storage_7_0_0.bit6.obuf0 Z ) ( storage_6_0_0.bit6.obuf0 Z ) ( storage_5_0_0.bit6.obuf0 Z ) ( storage_4_0_0.bit6.obuf0 Z ) ( storage_3_0_0.bit6.obuf0 Z ) ( storage_2_0_0.bit6.obuf0 Z ) ( storage_1_0_0.bit6.obuf0 Z ) ( storage_0_0_0.bit6.obuf0 Z ) + USE SIGNAL - + ROUTED met1 ( 6371 1037 ) ( 6417 * ) - NEW met2 ( 6371 1037 ) ( * 1309 ) - NEW met2 ( 6371 765 ) ( * 1037 ) - NEW met1 ( 6371 493 ) ( 6417 * ) - NEW met2 ( 6371 493 ) ( * 765 ) - NEW met2 ( 6371 221 ) ( * 493 ) - NEW met1 ( 6371 2125 ) ( 6417 * ) - NEW met2 ( 6371 2125 ) ( * 2686 0 ) - NEW met2 ( 6371 1853 ) ( * 2125 ) - NEW met1 ( 6371 1581 ) ( 6417 * ) - NEW met2 ( 6371 1581 ) ( * 1853 ) - NEW met2 ( 6371 1309 ) ( * 1581 ) - NEW li1 ( 6371 1309 ) L1M1_PR_MR - NEW met1 ( 6371 1309 ) M1M2_PR - NEW li1 ( 6417 1037 ) L1M1_PR_MR - NEW met1 ( 6371 1037 ) M1M2_PR - NEW li1 ( 6371 765 ) L1M1_PR_MR - NEW met1 ( 6371 765 ) M1M2_PR - NEW li1 ( 6417 493 ) L1M1_PR_MR - NEW met1 ( 6371 493 ) M1M2_PR - NEW li1 ( 6371 221 ) L1M1_PR_MR - NEW met1 ( 6371 221 ) M1M2_PR - NEW li1 ( 6417 2125 ) L1M1_PR_MR - NEW met1 ( 6371 2125 ) M1M2_PR - NEW li1 ( 6371 1853 ) L1M1_PR_MR - NEW met1 ( 6371 1853 ) M1M2_PR - NEW li1 ( 6417 1581 ) L1M1_PR_MR - NEW met1 ( 6371 1581 ) M1M2_PR ; + + ROUTED met2 ( 6739 1037 ) ( * 1309 ) + NEW met2 ( 6739 765 ) ( * 1037 ) + NEW met2 ( 6739 493 ) ( * 765 ) + NEW met2 ( 6739 221 ) ( * 493 ) + NEW met2 ( 6739 2125 ) ( * 2686 0 ) + NEW met2 ( 6739 1853 ) ( * 2125 ) + NEW met2 ( 6739 1581 ) ( * 1853 ) + NEW met2 ( 6739 1309 ) ( * 1581 ) + NEW li1 ( 6739 1309 ) L1M1_PR_MR + NEW met1 ( 6739 1309 ) M1M2_PR + NEW li1 ( 6739 1037 ) L1M1_PR_MR + NEW met1 ( 6739 1037 ) M1M2_PR + NEW li1 ( 6739 765 ) L1M1_PR_MR + NEW met1 ( 6739 765 ) M1M2_PR + NEW li1 ( 6739 493 ) L1M1_PR_MR + NEW met1 ( 6739 493 ) M1M2_PR + NEW li1 ( 6739 221 ) L1M1_PR_MR + NEW met1 ( 6739 221 ) M1M2_PR + NEW li1 ( 6739 2125 ) L1M1_PR_MR + NEW met1 ( 6739 2125 ) M1M2_PR + NEW li1 ( 6739 1853 ) L1M1_PR_MR + NEW met1 ( 6739 1853 ) M1M2_PR + NEW li1 ( 6739 1581 ) L1M1_PR_MR + NEW met1 ( 6739 1581 ) M1M2_PR ; - Q[7] ( PIN Q[7] ) ( storage_7_0_0.bit7.obuf0 Z ) ( storage_6_0_0.bit7.obuf0 Z ) ( storage_5_0_0.bit7.obuf0 Z ) ( storage_4_0_0.bit7.obuf0 Z ) ( storage_3_0_0.bit7.obuf0 Z ) ( storage_2_0_0.bit7.obuf0 Z ) ( storage_1_0_0.bit7.obuf0 Z ) ( storage_0_0_0.bit7.obuf0 Z ) + USE SIGNAL - + ROUTED met1 ( 7291 1037 ) ( 7337 * ) - NEW met2 ( 7291 1037 ) ( * 1309 ) - NEW met2 ( 7291 765 ) ( * 1037 ) - NEW met1 ( 7291 493 ) ( 7337 * ) - NEW met2 ( 7291 493 ) ( * 765 ) - NEW met2 ( 7291 221 ) ( * 493 ) - NEW met1 ( 7291 2125 ) ( 7337 * ) - NEW met2 ( 7291 2125 ) ( * 2686 0 ) - NEW met1 ( 7291 1785 ) ( 7337 * ) - NEW met2 ( 7291 1785 ) ( * 2125 ) - NEW met1 ( 7291 1581 ) ( 7337 * ) - NEW met2 ( 7291 1581 ) ( * 1785 ) - NEW met2 ( 7291 1309 ) ( * 1581 ) - NEW li1 ( 7291 1309 ) L1M1_PR_MR - NEW met1 ( 7291 1309 ) M1M2_PR - NEW li1 ( 7337 1037 ) L1M1_PR_MR - NEW met1 ( 7291 1037 ) M1M2_PR - NEW li1 ( 7291 765 ) L1M1_PR_MR - NEW met1 ( 7291 765 ) M1M2_PR - NEW li1 ( 7337 493 ) L1M1_PR_MR - NEW met1 ( 7291 493 ) M1M2_PR - NEW li1 ( 7291 221 ) L1M1_PR_MR - NEW met1 ( 7291 221 ) M1M2_PR - NEW li1 ( 7337 2125 ) L1M1_PR_MR - NEW met1 ( 7291 2125 ) M1M2_PR - NEW li1 ( 7337 1785 ) L1M1_PR_MR - NEW met1 ( 7291 1785 ) M1M2_PR - NEW li1 ( 7337 1581 ) L1M1_PR_MR - NEW met1 ( 7291 1581 ) M1M2_PR ; + + ROUTED met1 ( 7659 2125 ) ( 7705 * ) + NEW met2 ( 7659 2125 ) ( * 2686 0 ) + NEW met2 ( 7705 1785 ) ( * 1802 ) + NEW met2 ( 7659 1802 ) ( 7705 * ) + NEW met2 ( 7659 1802 ) ( * 2125 ) + NEW met2 ( 7705 1581 ) ( * 1785 ) + NEW met2 ( 7705 1241 ) ( * 1581 ) + NEW met2 ( 7705 1037 ) ( * 1241 ) + NEW met2 ( 7705 765 ) ( * 1037 ) + NEW met2 ( 7705 493 ) ( * 765 ) + NEW met2 ( 7705 153 ) ( * 493 ) + NEW li1 ( 7705 2125 ) L1M1_PR_MR + NEW met1 ( 7659 2125 ) M1M2_PR + NEW li1 ( 7705 1785 ) L1M1_PR_MR + NEW met1 ( 7705 1785 ) M1M2_PR + NEW li1 ( 7705 1581 ) L1M1_PR_MR + NEW met1 ( 7705 1581 ) M1M2_PR + NEW li1 ( 7705 1241 ) L1M1_PR_MR + NEW met1 ( 7705 1241 ) M1M2_PR + NEW li1 ( 7705 1037 ) L1M1_PR_MR + NEW met1 ( 7705 1037 ) M1M2_PR + NEW li1 ( 7705 765 ) L1M1_PR_MR + NEW met1 ( 7705 765 ) M1M2_PR + NEW li1 ( 7705 493 ) L1M1_PR_MR + NEW met1 ( 7705 493 ) M1M2_PR + NEW li1 ( 7705 153 ) L1M1_PR_MR + NEW met1 ( 7705 153 ) M1M2_PR ; - addr_rw.inv_addr[0] ( decoder_p0.inv_p0_a0 Y ) ( decoder_p0.and_layer0_word6 A ) ( decoder_p0.and_layer0_word4 A ) ( decoder_p0.and_layer0_word2 A ) ( decoder_p0.and_layer0_word0 A ) + USE SIGNAL - + ROUTED met2 ( 8625 187 ) ( * 697 ) - NEW met2 ( 8625 697 ) ( * 1241 ) - NEW met1 ( 8625 1275 ) ( 9131 * ) - NEW met1 ( 8625 1241 ) ( * 1275 ) - NEW met2 ( 8625 1241 ) ( * 1785 ) - NEW li1 ( 8625 697 ) L1M1_PR_MR - NEW met1 ( 8625 697 ) M1M2_PR - NEW li1 ( 8625 187 ) L1M1_PR_MR - NEW met1 ( 8625 187 ) M1M2_PR - NEW li1 ( 8625 1241 ) L1M1_PR_MR - NEW met1 ( 8625 1241 ) M1M2_PR - NEW li1 ( 9131 1275 ) L1M1_PR_MR - NEW li1 ( 8625 1785 ) L1M1_PR_MR - NEW met1 ( 8625 1785 ) M1M2_PR ; + + ROUTED met2 ( 8993 187 ) ( * 697 ) + NEW met2 ( 8993 697 ) ( * 1241 ) + NEW met1 ( 8993 1275 ) ( 9499 * ) + NEW met1 ( 8993 1241 ) ( * 1275 ) + NEW met2 ( 8993 1241 ) ( * 1785 ) + NEW li1 ( 8993 697 ) L1M1_PR_MR + NEW met1 ( 8993 697 ) M1M2_PR + NEW li1 ( 8993 187 ) L1M1_PR_MR + NEW met1 ( 8993 187 ) M1M2_PR + NEW li1 ( 8993 1241 ) L1M1_PR_MR + NEW met1 ( 8993 1241 ) M1M2_PR + NEW li1 ( 9499 1275 ) L1M1_PR_MR + NEW li1 ( 8993 1785 ) L1M1_PR_MR + NEW met1 ( 8993 1785 ) M1M2_PR ; - addr_rw.inv_addr[1] ( decoder_p0.inv_p0_a1 Y ) ( decoder_p0.and_layer1_word5 A ) ( decoder_p0.and_layer1_word4 A ) ( decoder_p0.and_layer1_word1 A ) ( decoder_p0.and_layer1_word0 A ) + USE SIGNAL - + ROUTED met1 ( 8855 765 ) ( 9131 * ) - NEW met2 ( 8855 765 ) ( * 1241 ) - NEW met2 ( 8855 391 ) ( * 765 ) - NEW met2 ( 8855 187 ) ( * 391 ) - NEW met2 ( 8855 1241 ) ( * 1445 ) - NEW li1 ( 8855 1241 ) L1M1_PR_MR - NEW met1 ( 8855 1241 ) M1M2_PR - NEW li1 ( 9131 765 ) L1M1_PR_MR - NEW met1 ( 8855 765 ) M1M2_PR - NEW li1 ( 8855 391 ) L1M1_PR_MR - NEW met1 ( 8855 391 ) M1M2_PR - NEW li1 ( 8855 187 ) L1M1_PR_MR - NEW met1 ( 8855 187 ) M1M2_PR - NEW li1 ( 8855 1445 ) L1M1_PR_MR - NEW met1 ( 8855 1445 ) M1M2_PR ; + + ROUTED met2 ( 9223 1241 ) ( * 1445 ) + NEW met1 ( 9223 765 ) ( 9499 * ) + NEW met2 ( 9223 765 ) ( * 1241 ) + NEW met2 ( 9223 391 ) ( * 765 ) + NEW met2 ( 9223 187 ) ( * 391 ) + NEW li1 ( 9223 1241 ) L1M1_PR_MR + NEW met1 ( 9223 1241 ) M1M2_PR + NEW li1 ( 9223 1445 ) L1M1_PR_MR + NEW met1 ( 9223 1445 ) M1M2_PR + NEW li1 ( 9499 765 ) L1M1_PR_MR + NEW met1 ( 9223 765 ) M1M2_PR + NEW li1 ( 9223 391 ) L1M1_PR_MR + NEW met1 ( 9223 391 ) M1M2_PR + NEW li1 ( 9223 187 ) L1M1_PR_MR + NEW met1 ( 9223 187 ) M1M2_PR ; - addr_rw.inv_addr[2] ( decoder_p0.inv_p0_a2 Y ) ( decoder_p0.and_layer1_word3 B ) ( decoder_p0.and_layer1_word2 B ) ( decoder_p0.and_layer1_word1 B ) ( decoder_p0.and_layer1_word0 B ) + USE SIGNAL - + ROUTED met2 ( 8947 697 ) ( * 935 ) - NEW met2 ( 8947 425 ) ( * 697 ) - NEW met2 ( 8947 153 ) ( * 425 ) - NEW met1 ( 8947 153 ) ( 9131 * ) - NEW li1 ( 8947 697 ) L1M1_PR_MR - NEW met1 ( 8947 697 ) M1M2_PR - NEW li1 ( 8947 935 ) L1M1_PR_MR - NEW met1 ( 8947 935 ) M1M2_PR - NEW li1 ( 8947 425 ) L1M1_PR_MR - NEW met1 ( 8947 425 ) M1M2_PR - NEW li1 ( 8947 153 ) L1M1_PR_MR - NEW met1 ( 8947 153 ) M1M2_PR - NEW li1 ( 9131 153 ) L1M1_PR_MR ; + + ROUTED met2 ( 9315 697 ) ( * 935 ) + NEW met2 ( 9315 425 ) ( * 697 ) + NEW met2 ( 9315 153 ) ( * 425 ) + NEW met1 ( 9315 153 ) ( 9499 * ) + NEW li1 ( 9315 697 ) L1M1_PR_MR + NEW met1 ( 9315 697 ) M1M2_PR + NEW li1 ( 9315 935 ) L1M1_PR_MR + NEW met1 ( 9315 935 ) M1M2_PR + NEW li1 ( 9315 425 ) L1M1_PR_MR + NEW met1 ( 9315 425 ) M1M2_PR + NEW li1 ( 9315 153 ) L1M1_PR_MR + NEW met1 ( 9315 153 ) M1M2_PR + NEW li1 ( 9499 153 ) L1M1_PR_MR ; - addr_rw[0] ( PIN addr_rw[0] ) ( decoder_p0.inv_p0_a0 A ) ( decoder_p0.and_layer0_word7 A ) ( decoder_p0.and_layer0_word5 A ) ( decoder_p0.and_layer0_word3 A ) ( decoder_p0.and_layer0_word1 A ) + USE SIGNAL - + ROUTED met1 ( 8625 391 ) ( 8671 * ) - NEW met2 ( 8671 391 ) ( * 442 ) - NEW met3 ( 8671 442 ) ( 9154 * 0 ) - NEW met1 ( 8625 901 ) ( 8671 * ) - NEW met2 ( 8671 442 ) ( * 901 ) - NEW met1 ( 8671 1173 ) ( 9085 * ) - NEW met2 ( 8671 901 ) ( * 1173 ) - NEW met1 ( 8625 1479 ) ( 8671 * ) - NEW met2 ( 8671 1479 ) ( * 1989 ) - NEW met1 ( 8625 1989 ) ( 8671 * ) - NEW met2 ( 8671 1173 ) ( * 1479 ) - NEW li1 ( 8625 391 ) L1M1_PR_MR - NEW met1 ( 8671 391 ) M1M2_PR - NEW met2 ( 8671 442 ) M2M3_PR - NEW li1 ( 8625 901 ) L1M1_PR_MR - NEW met1 ( 8671 901 ) M1M2_PR - NEW li1 ( 9085 1173 ) L1M1_PR_MR - NEW met1 ( 8671 1173 ) M1M2_PR - NEW li1 ( 8625 1479 ) L1M1_PR_MR - NEW met1 ( 8671 1479 ) M1M2_PR - NEW met1 ( 8671 1989 ) M1M2_PR - NEW li1 ( 8625 1989 ) L1M1_PR_MR ; + + ROUTED met1 ( 8993 391 ) ( 9039 * ) + NEW met2 ( 9039 391 ) ( * 442 ) + NEW met3 ( 9039 442 ) ( 9522 * 0 ) + NEW met1 ( 8993 901 ) ( 9039 * ) + NEW met2 ( 9039 442 ) ( * 901 ) + NEW met1 ( 9039 1173 ) ( 9453 * ) + NEW met2 ( 9039 901 ) ( * 1173 ) + NEW met1 ( 8993 1445 ) ( 9039 * ) + NEW met2 ( 9039 1173 ) ( * 1445 ) + NEW met1 ( 8993 1989 ) ( 9039 * ) + NEW met2 ( 9039 1445 ) ( * 1989 ) + NEW li1 ( 8993 391 ) L1M1_PR_MR + NEW met1 ( 9039 391 ) M1M2_PR + NEW met2 ( 9039 442 ) M2M3_PR + NEW li1 ( 8993 901 ) L1M1_PR_MR + NEW met1 ( 9039 901 ) M1M2_PR + NEW li1 ( 9453 1173 ) L1M1_PR_MR + NEW met1 ( 9039 1173 ) M1M2_PR + NEW li1 ( 8993 1445 ) L1M1_PR_MR + NEW met1 ( 9039 1445 ) M1M2_PR + NEW li1 ( 8993 1989 ) L1M1_PR_MR + NEW met1 ( 9039 1989 ) M1M2_PR ; - addr_rw[1] ( PIN addr_rw[1] ) ( decoder_p0.inv_p0_a1 A ) ( decoder_p0.and_layer1_word7 A ) ( decoder_p0.and_layer1_word6 A ) ( decoder_p0.and_layer1_word3 A ) ( decoder_p0.and_layer1_word2 A ) + USE SIGNAL - + ROUTED met2 ( 9085 663 ) ( * 714 ) - NEW met3 ( 9085 714 ) ( 9154 * 0 ) - NEW met1 ( 8855 663 ) ( * 697 ) - NEW met1 ( 8855 663 ) ( 9085 * ) - NEW met1 ( 8855 901 ) ( 9085 * ) - NEW met2 ( 9085 714 ) ( * 901 ) - NEW met1 ( 8855 1785 ) ( 9085 * ) - NEW met2 ( 8855 1785 ) ( * 1989 ) - NEW met2 ( 9085 901 ) ( * 1785 ) - NEW li1 ( 9085 663 ) L1M1_PR_MR - NEW met1 ( 9085 663 ) M1M2_PR - NEW met2 ( 9085 714 ) M2M3_PR - NEW li1 ( 8855 697 ) L1M1_PR_MR - NEW li1 ( 8855 901 ) L1M1_PR_MR - NEW met1 ( 9085 901 ) M1M2_PR - NEW li1 ( 8855 1785 ) L1M1_PR_MR - NEW met1 ( 9085 1785 ) M1M2_PR - NEW li1 ( 8855 1989 ) L1M1_PR_MR - NEW met1 ( 8855 1989 ) M1M2_PR - NEW met1 ( 8855 1785 ) M1M2_PR ; + + ROUTED met2 ( 9453 663 ) ( * 714 ) + NEW met3 ( 9453 714 ) ( 9522 * 0 ) + NEW met1 ( 9223 663 ) ( * 697 ) + NEW met1 ( 9223 663 ) ( 9453 * ) + NEW met1 ( 9223 901 ) ( 9453 * ) + NEW met2 ( 9453 714 ) ( * 901 ) + NEW met1 ( 9223 1785 ) ( 9453 * ) + NEW met2 ( 9453 901 ) ( * 1785 ) + NEW met2 ( 9223 1785 ) ( * 1989 ) + NEW li1 ( 9453 663 ) L1M1_PR_MR + NEW met1 ( 9453 663 ) M1M2_PR + NEW met2 ( 9453 714 ) M2M3_PR + NEW li1 ( 9223 697 ) L1M1_PR_MR + NEW li1 ( 9223 901 ) L1M1_PR_MR + NEW met1 ( 9453 901 ) M1M2_PR + NEW li1 ( 9223 1785 ) L1M1_PR_MR + NEW met1 ( 9453 1785 ) M1M2_PR + NEW li1 ( 9223 1989 ) L1M1_PR_MR + NEW met1 ( 9223 1989 ) M1M2_PR + NEW met1 ( 9223 1785 ) M1M2_PR ; - addr_rw[2] ( PIN addr_rw[2] ) ( decoder_p0.inv_p0_a2 A ) ( decoder_p0.and_layer1_word7 B ) ( decoder_p0.and_layer1_word6 B ) ( decoder_p0.and_layer1_word5 B ) ( decoder_p0.and_layer1_word4 B ) + USE SIGNAL - + ROUTED met2 ( 9085 119 ) ( * 170 ) - NEW met3 ( 9085 170 ) ( 9154 * 0 ) - NEW met1 ( 8947 1207 ) ( 9039 * ) - NEW met2 ( 9039 170 ) ( * 1207 ) - NEW met2 ( 9039 170 ) ( 9085 * ) - NEW met1 ( 8947 1479 ) ( 9039 * ) - NEW met1 ( 8947 1751 ) ( 9039 * ) - NEW met2 ( 9039 1479 ) ( * 1751 ) - NEW met1 ( 8947 2023 ) ( 9039 * ) - NEW met2 ( 9039 1751 ) ( * 2023 ) - NEW met2 ( 9039 1207 ) ( * 1479 ) - NEW li1 ( 9085 119 ) L1M1_PR_MR - NEW met1 ( 9085 119 ) M1M2_PR - NEW met2 ( 9085 170 ) M2M3_PR - NEW li1 ( 8947 1207 ) L1M1_PR_MR - NEW met1 ( 9039 1207 ) M1M2_PR - NEW li1 ( 8947 1479 ) L1M1_PR_MR - NEW met1 ( 9039 1479 ) M1M2_PR - NEW li1 ( 8947 1751 ) L1M1_PR_MR - NEW met1 ( 9039 1751 ) M1M2_PR - NEW li1 ( 8947 2023 ) L1M1_PR_MR - NEW met1 ( 9039 2023 ) M1M2_PR ; + + ROUTED met2 ( 9453 119 ) ( * 170 ) + NEW met3 ( 9453 170 ) ( 9522 * 0 ) + NEW met1 ( 9315 1207 ) ( 9407 * ) + NEW met2 ( 9407 170 ) ( * 1207 ) + NEW met2 ( 9407 170 ) ( 9453 * ) + NEW met1 ( 9315 1479 ) ( 9407 * ) + NEW met2 ( 9407 1207 ) ( * 1479 ) + NEW met1 ( 9315 1751 ) ( 9407 * ) + NEW met2 ( 9407 1479 ) ( * 1751 ) + NEW met1 ( 9315 2023 ) ( 9407 * ) + NEW met2 ( 9407 1751 ) ( * 2023 ) + NEW li1 ( 9453 119 ) L1M1_PR_MR + NEW met1 ( 9453 119 ) M1M2_PR + NEW met2 ( 9453 170 ) M2M3_PR + NEW li1 ( 9315 1207 ) L1M1_PR_MR + NEW met1 ( 9407 1207 ) M1M2_PR + NEW li1 ( 9315 1479 ) L1M1_PR_MR + NEW met1 ( 9407 1479 ) M1M2_PR + NEW li1 ( 9315 1751 ) L1M1_PR_MR + NEW met1 ( 9407 1751 ) M1M2_PR + NEW li1 ( 9315 2023 ) L1M1_PR_MR + NEW met1 ( 9407 2023 ) M1M2_PR ; - clk ( PIN clk ) ( neg_row.clk_inv A ) ( storage_7_0_0.cg CLK ) ( storage_6_0_0.cg CLK ) ( storage_5_0_0.cg CLK ) ( storage_4_0_0.cg CLK ) ( storage_3_0_0.cg CLK ) ( storage_2_0_0.cg CLK ) ( storage_1_0_0.cg CLK ) ( storage_0_0_0.cg CLK ) + USE SIGNAL - + ROUTED met2 ( 7659 119 ) ( * 425 ) - NEW met2 ( 7659 425 ) ( * 663 ) - NEW met2 ( 7659 663 ) ( * 969 ) - NEW met2 ( 7659 969 ) ( * 1207 ) - NEW met2 ( 7659 2057 ) ( * 2686 0 ) - NEW met2 ( 7659 1751 ) ( * 2057 ) - NEW met2 ( 7659 1513 ) ( * 1751 ) - NEW met1 ( 7429 2261 ) ( 7659 * ) - NEW met2 ( 7659 1207 ) ( * 1513 ) - NEW met1 ( 7659 425 ) M1M2_PR - NEW met1 ( 7659 119 ) M1M2_PR - NEW met1 ( 7659 663 ) M1M2_PR - NEW met1 ( 7659 969 ) M1M2_PR - NEW met1 ( 7659 1207 ) M1M2_PR - NEW met1 ( 7659 2057 ) M1M2_PR - NEW met1 ( 7659 1751 ) M1M2_PR - NEW met1 ( 7659 1513 ) M1M2_PR - NEW li1 ( 7429 2261 ) L1M1_PR_MR - NEW met1 ( 7659 2261 ) M1M2_PR ; + + ROUTED met2 ( 8073 2057 ) ( * 2686 ) + NEW met2 ( 8027 2686 0 ) ( 8073 * ) + NEW met2 ( 8073 1751 ) ( * 2057 ) + NEW met2 ( 8073 1513 ) ( * 1751 ) + NEW met2 ( 8073 1207 ) ( * 1513 ) + NEW met2 ( 8073 969 ) ( * 1207 ) + NEW met2 ( 8073 663 ) ( * 969 ) + NEW met2 ( 8073 425 ) ( * 663 ) + NEW met2 ( 8073 119 ) ( * 425 ) + NEW met1 ( 7797 2227 ) ( 8073 * ) + NEW met1 ( 8073 2057 ) M1M2_PR + NEW met1 ( 8073 1751 ) M1M2_PR + NEW met1 ( 8073 1513 ) M1M2_PR + NEW met1 ( 8073 1207 ) M1M2_PR + NEW met1 ( 8073 969 ) M1M2_PR + NEW met1 ( 8073 663 ) M1M2_PR + NEW met1 ( 8073 425 ) M1M2_PR + NEW met1 ( 8073 119 ) M1M2_PR + NEW li1 ( 7797 2227 ) L1M1_PR_MR + NEW met1 ( 8073 2227 ) M1M2_PR ; - decoder_p0.layer_in0_word0 ( decoder_p0.and_layer1_word0 X ) ( decoder_p0.and_layer0_word0 B ) + USE SIGNAL - + ROUTED met1 ( 8717 119 ) ( 9039 * ) - NEW li1 ( 8717 119 ) L1M1_PR_MR - NEW li1 ( 9039 119 ) L1M1_PR_MR ; + + ROUTED met1 ( 9085 119 ) ( 9407 * ) + NEW li1 ( 9085 119 ) L1M1_PR_MR + NEW li1 ( 9407 119 ) L1M1_PR_MR ; - decoder_p0.layer_in0_word1 ( decoder_p0.and_layer1_word1 X ) ( decoder_p0.and_layer0_word1 B ) + USE SIGNAL - + ROUTED met1 ( 8717 357 ) ( * 391 ) - NEW met1 ( 8717 357 ) ( 9039 * ) - NEW li1 ( 8717 391 ) L1M1_PR_MR - NEW li1 ( 9039 357 ) L1M1_PR_MR ; + + ROUTED met1 ( 9085 357 ) ( * 391 ) + NEW met1 ( 9085 357 ) ( 9407 * ) + NEW li1 ( 9085 391 ) L1M1_PR_MR + NEW li1 ( 9407 357 ) L1M1_PR_MR ; - decoder_p0.layer_in0_word2 ( decoder_p0.and_layer1_word2 X ) ( decoder_p0.and_layer0_word2 B ) + USE SIGNAL - + ROUTED met1 ( 8717 629 ) ( * 663 ) - NEW met1 ( 8717 629 ) ( 9039 * ) - NEW li1 ( 8717 663 ) L1M1_PR_MR - NEW li1 ( 9039 629 ) L1M1_PR_MR ; + + ROUTED met1 ( 9085 629 ) ( * 663 ) + NEW met1 ( 9085 629 ) ( 9407 * ) + NEW li1 ( 9085 663 ) L1M1_PR_MR + NEW li1 ( 9407 629 ) L1M1_PR_MR ; - decoder_p0.layer_in0_word3 ( decoder_p0.and_layer1_word3 X ) ( decoder_p0.and_layer0_word3 B ) + USE SIGNAL - + ROUTED met1 ( 8717 969 ) ( 9039 * ) - NEW li1 ( 8717 969 ) L1M1_PR_MR - NEW li1 ( 9039 969 ) L1M1_PR_MR ; + + ROUTED met1 ( 9085 969 ) ( 9407 * ) + NEW li1 ( 9085 969 ) L1M1_PR_MR + NEW li1 ( 9407 969 ) L1M1_PR_MR ; - decoder_p0.layer_in0_word4 ( decoder_p0.and_layer1_word4 X ) ( decoder_p0.and_layer0_word4 B ) + USE SIGNAL - + ROUTED met1 ( 8579 1207 ) ( 8717 * ) - NEW met1 ( 8579 1207 ) ( * 1309 ) - NEW met1 ( 8579 1309 ) ( 9039 * ) - NEW li1 ( 8717 1207 ) L1M1_PR_MR - NEW li1 ( 9039 1309 ) L1M1_PR_MR ; + + ROUTED met2 ( 9085 1241 ) ( * 1309 ) + NEW met1 ( 9085 1309 ) ( 9407 * ) + NEW li1 ( 9085 1241 ) L1M1_PR_MR + NEW met1 ( 9085 1241 ) M1M2_PR + NEW met1 ( 9085 1309 ) M1M2_PR + NEW li1 ( 9407 1309 ) L1M1_PR_MR ; - decoder_p0.layer_in0_word5 ( decoder_p0.and_layer1_word5 X ) ( decoder_p0.and_layer0_word5 B ) + USE SIGNAL - + ROUTED met1 ( 8717 1513 ) ( * 1547 ) - NEW met1 ( 8717 1547 ) ( 9039 * ) - NEW li1 ( 8717 1513 ) L1M1_PR_MR - NEW li1 ( 9039 1547 ) L1M1_PR_MR ; + + ROUTED met1 ( 9085 1513 ) ( * 1547 ) + NEW met1 ( 9085 1547 ) ( 9407 * ) + NEW li1 ( 9085 1513 ) L1M1_PR_MR + NEW li1 ( 9407 1547 ) L1M1_PR_MR ; - decoder_p0.layer_in0_word6 ( decoder_p0.and_layer1_word6 X ) ( decoder_p0.and_layer0_word6 B ) + USE SIGNAL - + ROUTED met1 ( 8717 1785 ) ( * 1819 ) - NEW met1 ( 8717 1819 ) ( 9039 * ) - NEW li1 ( 8717 1785 ) L1M1_PR_MR - NEW li1 ( 9039 1819 ) L1M1_PR_MR ; + + ROUTED met1 ( 9085 1785 ) ( * 1819 ) + NEW met1 ( 9085 1819 ) ( 9407 * ) + NEW li1 ( 9085 1785 ) L1M1_PR_MR + NEW li1 ( 9407 1819 ) L1M1_PR_MR ; - decoder_p0.layer_in0_word7 ( decoder_p0.and_layer1_word7 X ) ( decoder_p0.and_layer0_word7 B ) + USE SIGNAL - + ROUTED met1 ( 8717 2057 ) ( * 2091 ) - NEW met1 ( 8717 2091 ) ( 9039 * ) - NEW li1 ( 8717 2057 ) L1M1_PR_MR - NEW li1 ( 9039 2091 ) L1M1_PR_MR ; + + ROUTED met1 ( 9085 2057 ) ( * 2091 ) + NEW met1 ( 9085 2091 ) ( 9407 * ) + NEW li1 ( 9085 2057 ) L1M1_PR_MR + NEW li1 ( 9407 2091 ) L1M1_PR_MR ; - decoder_p0.word0 ( decoder_p0.and_layer0_word0 X ) ( sel_buf_rw_p0.sel_buf_0 A ) + USE SIGNAL - + ROUTED met1 ( 8441 119 ) ( * 153 ) - NEW met1 ( 8441 153 ) ( 8809 * ) - NEW li1 ( 8441 119 ) L1M1_PR_MR - NEW li1 ( 8809 153 ) L1M1_PR_MR ; + + ROUTED met1 ( 8809 119 ) ( * 153 ) + NEW met1 ( 8809 153 ) ( 9177 * ) + NEW li1 ( 8809 119 ) L1M1_PR_MR + NEW li1 ( 9177 153 ) L1M1_PR_MR ; - decoder_p0.word1 ( decoder_p0.and_layer0_word1 X ) ( sel_buf_rw_p0.sel_buf_1 A ) + USE SIGNAL - + ROUTED met1 ( 8441 425 ) ( 8809 * ) - NEW li1 ( 8441 425 ) L1M1_PR_MR - NEW li1 ( 8809 425 ) L1M1_PR_MR ; + + ROUTED met1 ( 8809 425 ) ( 9177 * ) + NEW li1 ( 8809 425 ) L1M1_PR_MR + NEW li1 ( 9177 425 ) L1M1_PR_MR ; - decoder_p0.word2 ( decoder_p0.and_layer0_word2 X ) ( sel_buf_rw_p0.sel_buf_2 A ) + USE SIGNAL - + ROUTED met1 ( 8441 663 ) ( 8579 * ) - NEW met1 ( 8579 595 ) ( * 663 ) - NEW met1 ( 8579 595 ) ( 8809 * ) - NEW li1 ( 8441 663 ) L1M1_PR_MR - NEW li1 ( 8809 595 ) L1M1_PR_MR ; + + ROUTED met1 ( 8809 663 ) ( 9039 * ) + NEW met1 ( 9039 663 ) ( * 697 ) + NEW met1 ( 9039 697 ) ( 9177 * ) + NEW li1 ( 8809 663 ) L1M1_PR_MR + NEW li1 ( 9177 697 ) L1M1_PR_MR ; - decoder_p0.word3 ( decoder_p0.and_layer0_word3 X ) ( sel_buf_rw_p0.sel_buf_3 A ) + USE SIGNAL - + ROUTED met1 ( 8441 969 ) ( * 1003 ) - NEW met1 ( 8441 1003 ) ( 8809 * ) - NEW li1 ( 8441 969 ) L1M1_PR_MR - NEW li1 ( 8809 1003 ) L1M1_PR_MR ; + + ROUTED met1 ( 8809 969 ) ( * 1003 ) + NEW met1 ( 8809 1003 ) ( 9177 * ) + NEW li1 ( 8809 969 ) L1M1_PR_MR + NEW li1 ( 9177 1003 ) L1M1_PR_MR ; - decoder_p0.word4 ( decoder_p0.and_layer0_word4 X ) ( sel_buf_rw_p0.sel_buf_4 A ) + USE SIGNAL - + ROUTED met1 ( 8441 1173 ) ( * 1207 ) - NEW met1 ( 8441 1173 ) ( 8579 * ) - NEW met1 ( 8579 1139 ) ( * 1173 ) - NEW met1 ( 8579 1139 ) ( 8809 * ) - NEW li1 ( 8441 1207 ) L1M1_PR_MR - NEW li1 ( 8809 1139 ) L1M1_PR_MR ; + + ROUTED met1 ( 8809 1207 ) ( 9177 * ) + NEW li1 ( 8809 1207 ) L1M1_PR_MR + NEW li1 ( 9177 1207 ) L1M1_PR_MR ; - decoder_p0.word5 ( decoder_p0.and_layer0_word5 X ) ( sel_buf_rw_p0.sel_buf_5 A ) + USE SIGNAL - + ROUTED met1 ( 8441 1513 ) ( * 1581 ) - NEW met1 ( 8441 1581 ) ( 8809 * ) - NEW li1 ( 8441 1513 ) L1M1_PR_MR - NEW li1 ( 8809 1581 ) L1M1_PR_MR ; + + ROUTED met1 ( 8809 1479 ) ( * 1513 ) + NEW met1 ( 8809 1479 ) ( 9177 * ) + NEW li1 ( 8809 1513 ) L1M1_PR_MR + NEW li1 ( 9177 1479 ) L1M1_PR_MR ; - decoder_p0.word6 ( decoder_p0.and_layer0_word6 X ) ( sel_buf_rw_p0.sel_buf_6 A ) + USE SIGNAL - + ROUTED met1 ( 8441 1751 ) ( 8809 * ) - NEW li1 ( 8441 1751 ) L1M1_PR_MR - NEW li1 ( 8809 1751 ) L1M1_PR_MR ; + + ROUTED met1 ( 8809 1751 ) ( 9177 * ) + NEW li1 ( 8809 1751 ) L1M1_PR_MR + NEW li1 ( 9177 1751 ) L1M1_PR_MR ; - decoder_p0.word7 ( decoder_p0.and_layer0_word7 X ) ( sel_buf_rw_p0.sel_buf_7 A ) + USE SIGNAL - + ROUTED met1 ( 8441 2023 ) ( * 2057 ) - NEW met1 ( 8441 2023 ) ( 8809 * ) - NEW li1 ( 8441 2057 ) L1M1_PR_MR - NEW li1 ( 8809 2023 ) L1M1_PR_MR ; - - global.clk_b ( neg_lat_b7.nlat SLEEP_B ) ( neg_lat_b6.nlat SLEEP_B ) ( neg_lat_b5.nlat SLEEP_B ) ( neg_lat_b4.nlat SLEEP_B ) ( neg_lat_b3.nlat SLEEP_B ) ( neg_lat_b2.nlat SLEEP_B ) ( neg_lat_b1.nlat SLEEP_B ) - ( neg_lat_b0.nlat SLEEP_B ) ( neg_row.clk_inv Y ) + USE SIGNAL - + ROUTED met1 ( 69 2295 ) ( 989 * ) - NEW met1 ( 6509 2295 ) ( 7475 * ) - NEW met1 ( 4669 2295 ) ( 5589 * ) - NEW met1 ( 3749 2295 ) ( 4669 * ) - NEW met1 ( 2829 2295 ) ( 3749 * ) - NEW met1 ( 1909 2295 ) ( 2829 * ) - NEW met1 ( 989 2295 ) ( 1909 * ) - NEW met1 ( 5589 2295 ) ( 6509 * ) - NEW li1 ( 989 2295 ) L1M1_PR_MR + + ROUTED met1 ( 8809 2023 ) ( * 2057 ) + NEW met1 ( 8809 2023 ) ( 9177 * ) + NEW li1 ( 8809 2057 ) L1M1_PR_MR + NEW li1 ( 9177 2023 ) L1M1_PR_MR ; + - global.clk_b ( neg_lat_b7.nlat GATE ) ( neg_lat_b6.nlat GATE ) ( neg_lat_b5.nlat GATE ) ( neg_lat_b4.nlat GATE ) ( neg_lat_b3.nlat GATE ) ( neg_lat_b2.nlat GATE ) ( neg_lat_b1.nlat GATE ) + ( neg_lat_b0.nlat GATE ) ( neg_row.clk_inv Y ) + USE SIGNAL + + ROUTED met1 ( 1035 2261 ) ( * 2295 ) + NEW met1 ( 69 2261 ) ( 1035 * ) + NEW met1 ( 69 2261 ) ( * 2295 ) + NEW met1 ( 6831 2329 ) ( * 2397 ) + NEW met1 ( 1035 2261 ) ( 1380 * ) + NEW met1 ( 1380 2295 ) ( 2001 * ) + NEW met1 ( 1380 2261 ) ( * 2295 ) + NEW met1 ( 2967 2261 ) ( * 2295 ) + NEW met1 ( 2001 2261 ) ( 2967 * ) + NEW met1 ( 2001 2261 ) ( * 2295 ) + NEW met1 ( 3933 2261 ) ( * 2295 ) + NEW met1 ( 2967 2261 ) ( 3933 * ) + NEW met1 ( 4899 2261 ) ( * 2295 ) + NEW met1 ( 3933 2261 ) ( 4899 * ) + NEW met1 ( 5865 2261 ) ( * 2295 ) + NEW met1 ( 4899 2261 ) ( 5865 * ) + NEW met1 ( 5865 2295 ) ( * 2397 ) + NEW met1 ( 5865 2397 ) ( 6831 * ) + NEW met1 ( 6831 2397 ) ( 7843 * ) + NEW li1 ( 1035 2295 ) L1M1_PR_MR NEW li1 ( 69 2295 ) L1M1_PR_MR - NEW li1 ( 6509 2295 ) L1M1_PR_MR - NEW li1 ( 7475 2295 ) L1M1_PR_MR - NEW li1 ( 5589 2295 ) L1M1_PR_MR - NEW li1 ( 4669 2295 ) L1M1_PR_MR - NEW li1 ( 3749 2295 ) L1M1_PR_MR - NEW li1 ( 2829 2295 ) L1M1_PR_MR - NEW li1 ( 1909 2295 ) L1M1_PR_MR ; + NEW li1 ( 6831 2329 ) L1M1_PR_MR + NEW li1 ( 2001 2295 ) L1M1_PR_MR + NEW li1 ( 2967 2295 ) L1M1_PR_MR + NEW li1 ( 3933 2295 ) L1M1_PR_MR + NEW li1 ( 4899 2295 ) L1M1_PR_MR + NEW li1 ( 5865 2295 ) L1M1_PR_MR + NEW li1 ( 7843 2397 ) L1M1_PR_MR ; - mid.b0 ( neg_lat_b0.nlat Q ) ( storage_7_0_0.bit0.bit D ) ( storage_6_0_0.bit0.bit D ) ( storage_5_0_0.bit0.bit D ) ( storage_4_0_0.bit0.bit D ) ( storage_3_0_0.bit0.bit D ) ( storage_2_0_0.bit0.bit D ) ( storage_1_0_0.bit0.bit D ) ( storage_0_0_0.bit0.bit D ) + USE SIGNAL - + ROUTED met1 ( 250 2091 ) ( 529 * ) - NEW met2 ( 529 2091 ) ( * 2227 ) - NEW met1 ( 250 1717 ) ( 253 * ) - NEW met2 ( 253 1717 ) ( * 2091 ) - NEW met1 ( 250 1547 ) ( 253 * ) - NEW met2 ( 253 1547 ) ( * 1717 ) - NEW met1 ( 250 1173 ) ( 253 * ) - NEW met2 ( 253 1173 ) ( * 1547 ) - NEW met1 ( 250 1003 ) ( 253 * ) - NEW met2 ( 253 1003 ) ( * 1173 ) - NEW met1 ( 250 629 ) ( 253 * ) - NEW met2 ( 253 629 ) ( * 1003 ) - NEW met1 ( 250 459 ) ( 253 * ) - NEW met2 ( 253 459 ) ( * 629 ) - NEW met1 ( 250 85 ) ( 253 * ) - NEW met2 ( 253 85 ) ( * 459 ) - NEW li1 ( 250 2091 ) L1M1_PR_MR - NEW met1 ( 529 2091 ) M1M2_PR - NEW li1 ( 529 2227 ) L1M1_PR_MR - NEW met1 ( 529 2227 ) M1M2_PR - NEW li1 ( 250 1717 ) L1M1_PR_MR - NEW met1 ( 253 1717 ) M1M2_PR - NEW met1 ( 253 2091 ) M1M2_PR - NEW li1 ( 250 1547 ) L1M1_PR_MR - NEW met1 ( 253 1547 ) M1M2_PR - NEW li1 ( 250 1173 ) L1M1_PR_MR - NEW met1 ( 253 1173 ) M1M2_PR - NEW li1 ( 250 1003 ) L1M1_PR_MR - NEW met1 ( 253 1003 ) M1M2_PR - NEW li1 ( 250 629 ) L1M1_PR_MR - NEW met1 ( 253 629 ) M1M2_PR - NEW li1 ( 250 459 ) L1M1_PR_MR - NEW met1 ( 253 459 ) M1M2_PR - NEW li1 ( 250 85 ) L1M1_PR_MR - NEW met1 ( 253 85 ) M1M2_PR - NEW met1 ( 250 1717 ) RECT ( -32 -7 0 7 ) - NEW met1 ( 250 1547 ) RECT ( -32 -7 0 7 ) - NEW met1 ( 250 1173 ) RECT ( -32 -7 0 7 ) - NEW met1 ( 250 1003 ) RECT ( -32 -7 0 7 ) - NEW met1 ( 250 629 ) RECT ( -32 -7 0 7 ) - NEW met1 ( 250 459 ) RECT ( -32 -7 0 7 ) - NEW met1 ( 250 85 ) RECT ( -32 -7 0 7 ) ; + + ROUTED met2 ( 207 2057 ) ( * 2227 ) + NEW met1 ( 207 2227 ) ( 575 * ) + NEW met2 ( 207 1751 ) ( * 2057 ) + NEW met2 ( 207 1513 ) ( * 1751 ) + NEW met2 ( 207 1207 ) ( * 1513 ) + NEW met2 ( 207 969 ) ( * 1207 ) + NEW met2 ( 207 663 ) ( * 969 ) + NEW met2 ( 207 425 ) ( * 663 ) + NEW met2 ( 207 119 ) ( * 425 ) + NEW li1 ( 207 2057 ) L1M1_PR_MR + NEW met1 ( 207 2057 ) M1M2_PR + NEW met1 ( 207 2227 ) M1M2_PR + NEW li1 ( 575 2227 ) L1M1_PR_MR + NEW li1 ( 207 1751 ) L1M1_PR_MR + NEW met1 ( 207 1751 ) M1M2_PR + NEW li1 ( 207 1513 ) L1M1_PR_MR + NEW met1 ( 207 1513 ) M1M2_PR + NEW li1 ( 207 1207 ) L1M1_PR_MR + NEW met1 ( 207 1207 ) M1M2_PR + NEW li1 ( 207 969 ) L1M1_PR_MR + NEW met1 ( 207 969 ) M1M2_PR + NEW li1 ( 207 663 ) L1M1_PR_MR + NEW met1 ( 207 663 ) M1M2_PR + NEW li1 ( 207 425 ) L1M1_PR_MR + NEW met1 ( 207 425 ) M1M2_PR + NEW li1 ( 207 119 ) L1M1_PR_MR + NEW met1 ( 207 119 ) M1M2_PR ; - mid.b1 ( neg_lat_b1.nlat Q ) ( storage_7_0_0.bit1.bit D ) ( storage_6_0_0.bit1.bit D ) ( storage_5_0_0.bit1.bit D ) ( storage_4_0_0.bit1.bit D ) ( storage_3_0_0.bit1.bit D ) ( storage_2_0_0.bit1.bit D ) ( storage_1_0_0.bit1.bit D ) ( storage_0_0_0.bit1.bit D ) + USE SIGNAL - + ROUTED met1 ( 1170 2091 ) ( 1219 * ) - NEW met2 ( 1219 2091 ) ( * 2227 ) - NEW met1 ( 1170 1717 ) ( 1219 * ) - NEW met2 ( 1219 1717 ) ( * 2091 ) - NEW met1 ( 1170 1547 ) ( 1219 * ) - NEW met2 ( 1219 1547 ) ( * 1717 ) - NEW met1 ( 1170 1173 ) ( 1219 * ) - NEW met2 ( 1219 1173 ) ( * 1547 ) - NEW met1 ( 1170 1003 ) ( 1219 * ) - NEW met2 ( 1219 1003 ) ( * 1173 ) - NEW met1 ( 1170 629 ) ( 1219 * ) - NEW met2 ( 1219 629 ) ( * 1003 ) - NEW met1 ( 1170 459 ) ( 1219 * ) - NEW met2 ( 1219 459 ) ( * 629 ) - NEW met1 ( 1170 85 ) ( 1219 * ) - NEW met2 ( 1219 85 ) ( * 459 ) - NEW met1 ( 1219 2227 ) ( 1449 * ) - NEW li1 ( 1170 2091 ) L1M1_PR_MR - NEW met1 ( 1219 2091 ) M1M2_PR - NEW met1 ( 1219 2227 ) M1M2_PR - NEW li1 ( 1170 1717 ) L1M1_PR_MR - NEW met1 ( 1219 1717 ) M1M2_PR - NEW li1 ( 1170 1547 ) L1M1_PR_MR - NEW met1 ( 1219 1547 ) M1M2_PR - NEW li1 ( 1170 1173 ) L1M1_PR_MR - NEW met1 ( 1219 1173 ) M1M2_PR - NEW li1 ( 1170 1003 ) L1M1_PR_MR - NEW met1 ( 1219 1003 ) M1M2_PR - NEW li1 ( 1170 629 ) L1M1_PR_MR - NEW met1 ( 1219 629 ) M1M2_PR - NEW li1 ( 1170 459 ) L1M1_PR_MR - NEW met1 ( 1219 459 ) M1M2_PR - NEW li1 ( 1170 85 ) L1M1_PR_MR - NEW met1 ( 1219 85 ) M1M2_PR - NEW li1 ( 1449 2227 ) L1M1_PR_MR ; + + ROUTED met2 ( 1173 2057 ) ( * 2227 ) + NEW met2 ( 1173 1751 ) ( * 2057 ) + NEW met2 ( 1173 1513 ) ( * 1751 ) + NEW met2 ( 1173 1207 ) ( * 1513 ) + NEW met2 ( 1173 969 ) ( * 1207 ) + NEW met2 ( 1173 663 ) ( * 969 ) + NEW met2 ( 1173 425 ) ( * 663 ) + NEW met2 ( 1173 119 ) ( * 425 ) + NEW met1 ( 1173 2227 ) ( 1541 * ) + NEW li1 ( 1173 2057 ) L1M1_PR_MR + NEW met1 ( 1173 2057 ) M1M2_PR + NEW met1 ( 1173 2227 ) M1M2_PR + NEW li1 ( 1173 1751 ) L1M1_PR_MR + NEW met1 ( 1173 1751 ) M1M2_PR + NEW li1 ( 1173 1513 ) L1M1_PR_MR + NEW met1 ( 1173 1513 ) M1M2_PR + NEW li1 ( 1173 1207 ) L1M1_PR_MR + NEW met1 ( 1173 1207 ) M1M2_PR + NEW li1 ( 1173 969 ) L1M1_PR_MR + NEW met1 ( 1173 969 ) M1M2_PR + NEW li1 ( 1173 663 ) L1M1_PR_MR + NEW met1 ( 1173 663 ) M1M2_PR + NEW li1 ( 1173 425 ) L1M1_PR_MR + NEW met1 ( 1173 425 ) M1M2_PR + NEW li1 ( 1173 119 ) L1M1_PR_MR + NEW met1 ( 1173 119 ) M1M2_PR + NEW li1 ( 1541 2227 ) L1M1_PR_MR ; - mid.b2 ( neg_lat_b2.nlat Q ) ( storage_7_0_0.bit2.bit D ) ( storage_6_0_0.bit2.bit D ) ( storage_5_0_0.bit2.bit D ) ( storage_4_0_0.bit2.bit D ) ( storage_3_0_0.bit2.bit D ) ( storage_2_0_0.bit2.bit D ) ( storage_1_0_0.bit2.bit D ) ( storage_0_0_0.bit2.bit D ) + USE SIGNAL - + ROUTED met1 ( 2090 1173 ) ( 2093 * ) - NEW met1 ( 2090 1003 ) ( 2093 * ) - NEW met2 ( 2093 1003 ) ( * 1173 ) - NEW met1 ( 2090 629 ) ( 2093 * ) - NEW met2 ( 2093 629 ) ( * 1003 ) - NEW met1 ( 2090 459 ) ( 2093 * ) - NEW met2 ( 2093 459 ) ( * 629 ) - NEW met1 ( 2090 85 ) ( 2093 * ) - NEW met2 ( 2093 85 ) ( * 459 ) - NEW met1 ( 2090 2091 ) ( 2369 * ) - NEW met2 ( 2369 2091 ) ( * 2227 ) - NEW met1 ( 2090 1717 ) ( 2093 * ) - NEW met2 ( 2093 1717 ) ( * 2091 ) - NEW met1 ( 2090 1547 ) ( 2093 * ) - NEW met2 ( 2093 1547 ) ( * 1717 ) - NEW met2 ( 2093 1173 ) ( * 1547 ) - NEW li1 ( 2090 1173 ) L1M1_PR_MR - NEW met1 ( 2093 1173 ) M1M2_PR - NEW li1 ( 2090 1003 ) L1M1_PR_MR - NEW met1 ( 2093 1003 ) M1M2_PR - NEW li1 ( 2090 629 ) L1M1_PR_MR - NEW met1 ( 2093 629 ) M1M2_PR - NEW li1 ( 2090 459 ) L1M1_PR_MR - NEW met1 ( 2093 459 ) M1M2_PR - NEW li1 ( 2090 85 ) L1M1_PR_MR - NEW met1 ( 2093 85 ) M1M2_PR - NEW li1 ( 2090 2091 ) L1M1_PR_MR - NEW met1 ( 2369 2091 ) M1M2_PR - NEW li1 ( 2369 2227 ) L1M1_PR_MR - NEW met1 ( 2369 2227 ) M1M2_PR - NEW li1 ( 2090 1717 ) L1M1_PR_MR - NEW met1 ( 2093 1717 ) M1M2_PR - NEW met1 ( 2093 2091 ) M1M2_PR - NEW li1 ( 2090 1547 ) L1M1_PR_MR - NEW met1 ( 2093 1547 ) M1M2_PR - NEW met1 ( 2090 1173 ) RECT ( -32 -7 0 7 ) - NEW met1 ( 2090 1003 ) RECT ( -32 -7 0 7 ) - NEW met1 ( 2090 629 ) RECT ( -32 -7 0 7 ) - NEW met1 ( 2090 459 ) RECT ( -32 -7 0 7 ) - NEW met1 ( 2090 85 ) RECT ( -32 -7 0 7 ) - NEW met1 ( 2090 1717 ) RECT ( -32 -7 0 7 ) - NEW met1 ( 2090 1547 ) RECT ( -32 -7 0 7 ) ; + + ROUTED met2 ( 2139 969 ) ( * 1207 ) + NEW met2 ( 2139 663 ) ( * 969 ) + NEW met2 ( 2139 425 ) ( * 663 ) + NEW met2 ( 2139 119 ) ( * 425 ) + NEW met2 ( 2139 2057 ) ( * 2227 ) + NEW met1 ( 2139 2227 ) ( 2507 * ) + NEW met2 ( 2139 1751 ) ( * 2057 ) + NEW met2 ( 2139 1513 ) ( * 1751 ) + NEW met2 ( 2139 1207 ) ( * 1513 ) + NEW li1 ( 2139 1207 ) L1M1_PR_MR + NEW met1 ( 2139 1207 ) M1M2_PR + NEW li1 ( 2139 969 ) L1M1_PR_MR + NEW met1 ( 2139 969 ) M1M2_PR + NEW li1 ( 2139 663 ) L1M1_PR_MR + NEW met1 ( 2139 663 ) M1M2_PR + NEW li1 ( 2139 425 ) L1M1_PR_MR + NEW met1 ( 2139 425 ) M1M2_PR + NEW li1 ( 2139 119 ) L1M1_PR_MR + NEW met1 ( 2139 119 ) M1M2_PR + NEW li1 ( 2139 2057 ) L1M1_PR_MR + NEW met1 ( 2139 2057 ) M1M2_PR + NEW met1 ( 2139 2227 ) M1M2_PR + NEW li1 ( 2507 2227 ) L1M1_PR_MR + NEW li1 ( 2139 1751 ) L1M1_PR_MR + NEW met1 ( 2139 1751 ) M1M2_PR + NEW li1 ( 2139 1513 ) L1M1_PR_MR + NEW met1 ( 2139 1513 ) M1M2_PR ; - mid.b3 ( neg_lat_b3.nlat Q ) ( storage_7_0_0.bit3.bit D ) ( storage_6_0_0.bit3.bit D ) ( storage_5_0_0.bit3.bit D ) ( storage_4_0_0.bit3.bit D ) ( storage_3_0_0.bit3.bit D ) ( storage_2_0_0.bit3.bit D ) ( storage_1_0_0.bit3.bit D ) ( storage_0_0_0.bit3.bit D ) + USE SIGNAL - + ROUTED met1 ( 3010 1173 ) ( 3013 * ) - NEW met1 ( 3010 1003 ) ( 3013 * ) - NEW met2 ( 3013 1003 ) ( * 1173 ) - NEW met1 ( 3010 629 ) ( 3013 * ) - NEW met2 ( 3013 629 ) ( * 1003 ) - NEW met1 ( 3010 459 ) ( 3013 * ) - NEW met2 ( 3013 459 ) ( * 629 ) - NEW met1 ( 3010 85 ) ( 3013 * ) - NEW met2 ( 3013 85 ) ( * 459 ) - NEW met1 ( 3010 2091 ) ( 3289 * ) - NEW met2 ( 3289 2091 ) ( * 2227 ) - NEW met1 ( 3010 1717 ) ( 3013 * ) - NEW met2 ( 3013 1717 ) ( * 2091 ) - NEW met1 ( 3010 1547 ) ( 3013 * ) - NEW met2 ( 3013 1547 ) ( * 1717 ) - NEW met2 ( 3013 1173 ) ( * 1547 ) - NEW li1 ( 3010 1173 ) L1M1_PR_MR - NEW met1 ( 3013 1173 ) M1M2_PR - NEW li1 ( 3010 1003 ) L1M1_PR_MR - NEW met1 ( 3013 1003 ) M1M2_PR - NEW li1 ( 3010 629 ) L1M1_PR_MR - NEW met1 ( 3013 629 ) M1M2_PR - NEW li1 ( 3010 459 ) L1M1_PR_MR - NEW met1 ( 3013 459 ) M1M2_PR - NEW li1 ( 3010 85 ) L1M1_PR_MR - NEW met1 ( 3013 85 ) M1M2_PR - NEW li1 ( 3010 2091 ) L1M1_PR_MR - NEW met1 ( 3289 2091 ) M1M2_PR - NEW li1 ( 3289 2227 ) L1M1_PR_MR - NEW met1 ( 3289 2227 ) M1M2_PR - NEW li1 ( 3010 1717 ) L1M1_PR_MR - NEW met1 ( 3013 1717 ) M1M2_PR - NEW met1 ( 3013 2091 ) M1M2_PR - NEW li1 ( 3010 1547 ) L1M1_PR_MR - NEW met1 ( 3013 1547 ) M1M2_PR - NEW met1 ( 3010 1173 ) RECT ( -32 -7 0 7 ) - NEW met1 ( 3010 1003 ) RECT ( -32 -7 0 7 ) - NEW met1 ( 3010 629 ) RECT ( -32 -7 0 7 ) - NEW met1 ( 3010 459 ) RECT ( -32 -7 0 7 ) - NEW met1 ( 3010 85 ) RECT ( -32 -7 0 7 ) - NEW met1 ( 3010 1717 ) RECT ( -32 -7 0 7 ) - NEW met1 ( 3010 1547 ) RECT ( -32 -7 0 7 ) ; + + ROUTED met2 ( 3105 969 ) ( * 1207 ) + NEW met2 ( 3105 663 ) ( * 969 ) + NEW met2 ( 3105 425 ) ( * 663 ) + NEW met2 ( 3105 119 ) ( * 425 ) + NEW met2 ( 3105 2057 ) ( * 2227 ) + NEW met1 ( 3105 2227 ) ( 3473 * ) + NEW met2 ( 3105 1751 ) ( * 2057 ) + NEW met2 ( 3105 1513 ) ( * 1751 ) + NEW met2 ( 3105 1207 ) ( * 1513 ) + NEW li1 ( 3105 1207 ) L1M1_PR_MR + NEW met1 ( 3105 1207 ) M1M2_PR + NEW li1 ( 3105 969 ) L1M1_PR_MR + NEW met1 ( 3105 969 ) M1M2_PR + NEW li1 ( 3105 663 ) L1M1_PR_MR + NEW met1 ( 3105 663 ) M1M2_PR + NEW li1 ( 3105 425 ) L1M1_PR_MR + NEW met1 ( 3105 425 ) M1M2_PR + NEW li1 ( 3105 119 ) L1M1_PR_MR + NEW met1 ( 3105 119 ) M1M2_PR + NEW li1 ( 3105 2057 ) L1M1_PR_MR + NEW met1 ( 3105 2057 ) M1M2_PR + NEW met1 ( 3105 2227 ) M1M2_PR + NEW li1 ( 3473 2227 ) L1M1_PR_MR + NEW li1 ( 3105 1751 ) L1M1_PR_MR + NEW met1 ( 3105 1751 ) M1M2_PR + NEW li1 ( 3105 1513 ) L1M1_PR_MR + NEW met1 ( 3105 1513 ) M1M2_PR ; - mid.b4 ( neg_lat_b4.nlat Q ) ( storage_7_0_0.bit4.bit D ) ( storage_6_0_0.bit4.bit D ) ( storage_5_0_0.bit4.bit D ) ( storage_4_0_0.bit4.bit D ) ( storage_3_0_0.bit4.bit D ) ( storage_2_0_0.bit4.bit D ) ( storage_1_0_0.bit4.bit D ) ( storage_0_0_0.bit4.bit D ) + USE SIGNAL - + ROUTED met1 ( 3930 1173 ) ( 4071 * ) - NEW met1 ( 3930 1003 ) ( 4071 * ) - NEW met2 ( 4071 1003 ) ( * 1173 ) - NEW met1 ( 3930 629 ) ( 4071 * ) - NEW met2 ( 4071 629 ) ( * 1003 ) - NEW met1 ( 3930 459 ) ( 4071 * ) - NEW met2 ( 4071 459 ) ( * 629 ) - NEW met1 ( 3930 85 ) ( 4071 * ) - NEW met2 ( 4071 85 ) ( * 459 ) - NEW met1 ( 3930 2091 ) ( 4071 * ) - NEW met2 ( 4071 2091 ) ( * 2227 ) - NEW met1 ( 4071 2227 ) ( 4209 * ) - NEW met1 ( 3930 1717 ) ( 4071 * ) - NEW met2 ( 4071 1717 ) ( * 2091 ) - NEW met1 ( 3930 1547 ) ( 4071 * ) - NEW met2 ( 4071 1547 ) ( * 1717 ) - NEW met2 ( 4071 1173 ) ( * 1547 ) - NEW li1 ( 3930 1173 ) L1M1_PR_MR - NEW met1 ( 4071 1173 ) M1M2_PR - NEW li1 ( 3930 1003 ) L1M1_PR_MR - NEW met1 ( 4071 1003 ) M1M2_PR - NEW li1 ( 3930 629 ) L1M1_PR_MR - NEW met1 ( 4071 629 ) M1M2_PR - NEW li1 ( 3930 459 ) L1M1_PR_MR - NEW met1 ( 4071 459 ) M1M2_PR - NEW li1 ( 3930 85 ) L1M1_PR_MR - NEW met1 ( 4071 85 ) M1M2_PR - NEW li1 ( 3930 2091 ) L1M1_PR_MR - NEW met1 ( 4071 2091 ) M1M2_PR + + ROUTED met2 ( 4071 969 ) ( * 1207 ) + NEW met2 ( 4071 663 ) ( * 969 ) + NEW met2 ( 4071 425 ) ( * 663 ) + NEW met2 ( 4071 119 ) ( * 425 ) + NEW met2 ( 4071 2057 ) ( * 2227 ) + NEW met1 ( 4071 2227 ) ( 4439 * ) + NEW met2 ( 4071 1751 ) ( * 2057 ) + NEW met2 ( 4071 1513 ) ( * 1751 ) + NEW met2 ( 4071 1207 ) ( * 1513 ) + NEW li1 ( 4071 1207 ) L1M1_PR_MR + NEW met1 ( 4071 1207 ) M1M2_PR + NEW li1 ( 4071 969 ) L1M1_PR_MR + NEW met1 ( 4071 969 ) M1M2_PR + NEW li1 ( 4071 663 ) L1M1_PR_MR + NEW met1 ( 4071 663 ) M1M2_PR + NEW li1 ( 4071 425 ) L1M1_PR_MR + NEW met1 ( 4071 425 ) M1M2_PR + NEW li1 ( 4071 119 ) L1M1_PR_MR + NEW met1 ( 4071 119 ) M1M2_PR + NEW li1 ( 4071 2057 ) L1M1_PR_MR + NEW met1 ( 4071 2057 ) M1M2_PR NEW met1 ( 4071 2227 ) M1M2_PR - NEW li1 ( 4209 2227 ) L1M1_PR_MR - NEW li1 ( 3930 1717 ) L1M1_PR_MR - NEW met1 ( 4071 1717 ) M1M2_PR - NEW li1 ( 3930 1547 ) L1M1_PR_MR - NEW met1 ( 4071 1547 ) M1M2_PR ; + NEW li1 ( 4439 2227 ) L1M1_PR_MR + NEW li1 ( 4071 1751 ) L1M1_PR_MR + NEW met1 ( 4071 1751 ) M1M2_PR + NEW li1 ( 4071 1513 ) L1M1_PR_MR + NEW met1 ( 4071 1513 ) M1M2_PR ; - mid.b5 ( neg_lat_b5.nlat Q ) ( storage_7_0_0.bit5.bit D ) ( storage_6_0_0.bit5.bit D ) ( storage_5_0_0.bit5.bit D ) ( storage_4_0_0.bit5.bit D ) ( storage_3_0_0.bit5.bit D ) ( storage_2_0_0.bit5.bit D ) ( storage_1_0_0.bit5.bit D ) ( storage_0_0_0.bit5.bit D ) + USE SIGNAL - + ROUTED met1 ( 4850 1173 ) ( 4853 * ) - NEW met1 ( 4850 1003 ) ( 4853 * ) - NEW met2 ( 4853 1003 ) ( * 1173 ) - NEW met1 ( 4850 629 ) ( 4853 * ) - NEW met2 ( 4853 629 ) ( * 1003 ) - NEW met1 ( 4850 459 ) ( 4853 * ) - NEW met2 ( 4853 459 ) ( * 629 ) - NEW met1 ( 4850 85 ) ( 4853 * ) - NEW met2 ( 4853 85 ) ( * 459 ) - NEW met1 ( 4850 2091 ) ( 5129 * ) - NEW met2 ( 5129 2091 ) ( * 2227 ) - NEW met1 ( 4850 1717 ) ( 4853 * ) - NEW met2 ( 4853 1717 ) ( * 2091 ) - NEW met1 ( 4850 1547 ) ( 4853 * ) - NEW met2 ( 4853 1547 ) ( * 1717 ) - NEW met2 ( 4853 1173 ) ( * 1547 ) - NEW li1 ( 4850 1173 ) L1M1_PR_MR - NEW met1 ( 4853 1173 ) M1M2_PR - NEW li1 ( 4850 1003 ) L1M1_PR_MR - NEW met1 ( 4853 1003 ) M1M2_PR - NEW li1 ( 4850 629 ) L1M1_PR_MR - NEW met1 ( 4853 629 ) M1M2_PR - NEW li1 ( 4850 459 ) L1M1_PR_MR - NEW met1 ( 4853 459 ) M1M2_PR - NEW li1 ( 4850 85 ) L1M1_PR_MR - NEW met1 ( 4853 85 ) M1M2_PR - NEW li1 ( 4850 2091 ) L1M1_PR_MR - NEW met1 ( 5129 2091 ) M1M2_PR - NEW li1 ( 5129 2227 ) L1M1_PR_MR - NEW met1 ( 5129 2227 ) M1M2_PR - NEW li1 ( 4850 1717 ) L1M1_PR_MR - NEW met1 ( 4853 1717 ) M1M2_PR - NEW met1 ( 4853 2091 ) M1M2_PR - NEW li1 ( 4850 1547 ) L1M1_PR_MR - NEW met1 ( 4853 1547 ) M1M2_PR - NEW met1 ( 4850 1173 ) RECT ( -32 -7 0 7 ) - NEW met1 ( 4850 1003 ) RECT ( -32 -7 0 7 ) - NEW met1 ( 4850 629 ) RECT ( -32 -7 0 7 ) - NEW met1 ( 4850 459 ) RECT ( -32 -7 0 7 ) - NEW met1 ( 4850 85 ) RECT ( -32 -7 0 7 ) - NEW met1 ( 4850 1717 ) RECT ( -32 -7 0 7 ) - NEW met1 ( 4850 1547 ) RECT ( -32 -7 0 7 ) ; + + ROUTED met2 ( 5037 969 ) ( * 1207 ) + NEW met2 ( 5037 663 ) ( * 969 ) + NEW met2 ( 5037 425 ) ( * 663 ) + NEW met2 ( 5037 119 ) ( * 425 ) + NEW met2 ( 5037 2057 ) ( * 2227 ) + NEW met1 ( 5037 2227 ) ( 5405 * ) + NEW met2 ( 5037 1751 ) ( * 2057 ) + NEW met2 ( 5037 1513 ) ( * 1751 ) + NEW met2 ( 5037 1207 ) ( * 1513 ) + NEW li1 ( 5037 1207 ) L1M1_PR_MR + NEW met1 ( 5037 1207 ) M1M2_PR + NEW li1 ( 5037 969 ) L1M1_PR_MR + NEW met1 ( 5037 969 ) M1M2_PR + NEW li1 ( 5037 663 ) L1M1_PR_MR + NEW met1 ( 5037 663 ) M1M2_PR + NEW li1 ( 5037 425 ) L1M1_PR_MR + NEW met1 ( 5037 425 ) M1M2_PR + NEW li1 ( 5037 119 ) L1M1_PR_MR + NEW met1 ( 5037 119 ) M1M2_PR + NEW li1 ( 5037 2057 ) L1M1_PR_MR + NEW met1 ( 5037 2057 ) M1M2_PR + NEW met1 ( 5037 2227 ) M1M2_PR + NEW li1 ( 5405 2227 ) L1M1_PR_MR + NEW li1 ( 5037 1751 ) L1M1_PR_MR + NEW met1 ( 5037 1751 ) M1M2_PR + NEW li1 ( 5037 1513 ) L1M1_PR_MR + NEW met1 ( 5037 1513 ) M1M2_PR ; - mid.b6 ( neg_lat_b6.nlat Q ) ( storage_7_0_0.bit6.bit D ) ( storage_6_0_0.bit6.bit D ) ( storage_5_0_0.bit6.bit D ) ( storage_4_0_0.bit6.bit D ) ( storage_3_0_0.bit6.bit D ) ( storage_2_0_0.bit6.bit D ) ( storage_1_0_0.bit6.bit D ) ( storage_0_0_0.bit6.bit D ) + USE SIGNAL - + ROUTED met1 ( 5770 1173 ) ( 5819 * ) - NEW met1 ( 5770 1003 ) ( 5819 * ) - NEW met2 ( 5819 1003 ) ( * 1173 ) - NEW met1 ( 5770 629 ) ( 5819 * ) - NEW met2 ( 5819 629 ) ( * 1003 ) - NEW met1 ( 5770 459 ) ( 5819 * ) - NEW met2 ( 5819 459 ) ( * 629 ) - NEW met1 ( 5770 85 ) ( 5819 * ) - NEW met2 ( 5819 85 ) ( * 459 ) - NEW met1 ( 5770 2091 ) ( 5819 * ) - NEW met2 ( 5819 2091 ) ( * 2227 ) - NEW met1 ( 5819 2227 ) ( 6049 * ) - NEW met1 ( 5770 1717 ) ( 5819 * ) - NEW met2 ( 5819 1717 ) ( * 2091 ) - NEW met1 ( 5770 1547 ) ( 5819 * ) - NEW met2 ( 5819 1547 ) ( * 1717 ) - NEW met2 ( 5819 1173 ) ( * 1547 ) - NEW li1 ( 5770 1173 ) L1M1_PR_MR - NEW met1 ( 5819 1173 ) M1M2_PR - NEW li1 ( 5770 1003 ) L1M1_PR_MR - NEW met1 ( 5819 1003 ) M1M2_PR - NEW li1 ( 5770 629 ) L1M1_PR_MR - NEW met1 ( 5819 629 ) M1M2_PR - NEW li1 ( 5770 459 ) L1M1_PR_MR - NEW met1 ( 5819 459 ) M1M2_PR - NEW li1 ( 5770 85 ) L1M1_PR_MR - NEW met1 ( 5819 85 ) M1M2_PR - NEW li1 ( 5770 2091 ) L1M1_PR_MR - NEW met1 ( 5819 2091 ) M1M2_PR - NEW met1 ( 5819 2227 ) M1M2_PR - NEW li1 ( 6049 2227 ) L1M1_PR_MR - NEW li1 ( 5770 1717 ) L1M1_PR_MR - NEW met1 ( 5819 1717 ) M1M2_PR - NEW li1 ( 5770 1547 ) L1M1_PR_MR - NEW met1 ( 5819 1547 ) M1M2_PR ; + + ROUTED met1 ( 6003 1207 ) ( 6141 * ) + NEW met1 ( 6003 969 ) ( 6141 * ) + NEW met2 ( 6141 969 ) ( * 1207 ) + NEW met1 ( 6003 663 ) ( 6141 * ) + NEW met2 ( 6141 663 ) ( * 969 ) + NEW met1 ( 6003 425 ) ( 6141 * ) + NEW met2 ( 6141 425 ) ( * 663 ) + NEW met1 ( 6003 119 ) ( 6141 * ) + NEW met2 ( 6141 119 ) ( * 425 ) + NEW met1 ( 6003 1513 ) ( 6141 * ) + NEW met1 ( 6003 1751 ) ( 6141 * ) + NEW met2 ( 6141 1513 ) ( * 1751 ) + NEW met1 ( 6003 2057 ) ( 6141 * ) + NEW met2 ( 6141 1751 ) ( * 2057 ) + NEW met2 ( 6141 2057 ) ( * 2227 ) + NEW met2 ( 6141 1207 ) ( * 1513 ) + NEW met1 ( 6141 2227 ) ( 6371 * ) + NEW li1 ( 6371 2227 ) L1M1_PR_MR + NEW li1 ( 6003 1207 ) L1M1_PR_MR + NEW met1 ( 6141 1207 ) M1M2_PR + NEW li1 ( 6003 969 ) L1M1_PR_MR + NEW met1 ( 6141 969 ) M1M2_PR + NEW li1 ( 6003 663 ) L1M1_PR_MR + NEW met1 ( 6141 663 ) M1M2_PR + NEW li1 ( 6003 425 ) L1M1_PR_MR + NEW met1 ( 6141 425 ) M1M2_PR + NEW li1 ( 6003 119 ) L1M1_PR_MR + NEW met1 ( 6141 119 ) M1M2_PR + NEW li1 ( 6003 1513 ) L1M1_PR_MR + NEW met1 ( 6141 1513 ) M1M2_PR + NEW li1 ( 6003 1751 ) L1M1_PR_MR + NEW met1 ( 6141 1751 ) M1M2_PR + NEW li1 ( 6003 2057 ) L1M1_PR_MR + NEW met1 ( 6141 2057 ) M1M2_PR + NEW met1 ( 6141 2227 ) M1M2_PR ; - mid.b7 ( neg_lat_b7.nlat Q ) ( storage_7_0_0.bit7.bit D ) ( storage_6_0_0.bit7.bit D ) ( storage_5_0_0.bit7.bit D ) ( storage_4_0_0.bit7.bit D ) ( storage_3_0_0.bit7.bit D ) ( storage_2_0_0.bit7.bit D ) ( storage_1_0_0.bit7.bit D ) ( storage_0_0_0.bit7.bit D ) + USE SIGNAL - + ROUTED met1 ( 6690 1173 ) ( 6739 * ) - NEW met1 ( 6690 1003 ) ( 6739 * ) - NEW met2 ( 6739 1003 ) ( * 1173 ) - NEW met1 ( 6690 629 ) ( 6739 * ) - NEW met2 ( 6739 629 ) ( * 1003 ) - NEW met1 ( 6690 459 ) ( 6739 * ) - NEW met2 ( 6739 459 ) ( * 629 ) - NEW met1 ( 6690 85 ) ( 6739 * ) - NEW met2 ( 6739 85 ) ( * 459 ) - NEW met1 ( 6690 2091 ) ( 6739 * ) - NEW met2 ( 6739 2091 ) ( * 2227 ) - NEW met1 ( 6739 2227 ) ( 6969 * ) - NEW met1 ( 6690 1717 ) ( 6739 * ) - NEW met2 ( 6739 1717 ) ( * 2091 ) - NEW met1 ( 6690 1547 ) ( 6739 * ) - NEW met2 ( 6739 1547 ) ( * 1717 ) - NEW met2 ( 6739 1173 ) ( * 1547 ) - NEW li1 ( 6690 1173 ) L1M1_PR_MR - NEW met1 ( 6739 1173 ) M1M2_PR - NEW li1 ( 6690 1003 ) L1M1_PR_MR - NEW met1 ( 6739 1003 ) M1M2_PR - NEW li1 ( 6690 629 ) L1M1_PR_MR - NEW met1 ( 6739 629 ) M1M2_PR - NEW li1 ( 6690 459 ) L1M1_PR_MR - NEW met1 ( 6739 459 ) M1M2_PR - NEW li1 ( 6690 85 ) L1M1_PR_MR - NEW met1 ( 6739 85 ) M1M2_PR - NEW li1 ( 6690 2091 ) L1M1_PR_MR - NEW met1 ( 6739 2091 ) M1M2_PR - NEW met1 ( 6739 2227 ) M1M2_PR - NEW li1 ( 6969 2227 ) L1M1_PR_MR - NEW li1 ( 6690 1717 ) L1M1_PR_MR - NEW met1 ( 6739 1717 ) M1M2_PR - NEW li1 ( 6690 1547 ) L1M1_PR_MR - NEW met1 ( 6739 1547 ) M1M2_PR ; + + ROUTED met2 ( 6969 969 ) ( * 1207 ) + NEW met2 ( 6969 425 ) ( * 969 ) + NEW met2 ( 6969 119 ) ( * 425 ) + NEW met2 ( 6969 2057 ) ( * 2227 ) + NEW met1 ( 6969 2227 ) ( 7337 * ) + NEW met2 ( 6969 1751 ) ( * 2057 ) + NEW met2 ( 6969 1513 ) ( * 1751 ) + NEW met2 ( 6969 1207 ) ( * 1513 ) + NEW li1 ( 6969 1207 ) L1M1_PR_MR + NEW met1 ( 6969 1207 ) M1M2_PR + NEW li1 ( 6969 969 ) L1M1_PR_MR + NEW met1 ( 6969 969 ) M1M2_PR + NEW li1 ( 6969 425 ) L1M1_PR_MR + NEW met1 ( 6969 425 ) M1M2_PR + NEW li1 ( 6969 119 ) L1M1_PR_MR + NEW met1 ( 6969 119 ) M1M2_PR + NEW li1 ( 6969 658 ) L1M1_PR_MR + NEW met1 ( 6969 658 ) M1M2_PR + NEW li1 ( 6969 2057 ) L1M1_PR_MR + NEW met1 ( 6969 2057 ) M1M2_PR + NEW met1 ( 6969 2227 ) M1M2_PR + NEW li1 ( 7337 2227 ) L1M1_PR_MR + NEW li1 ( 6969 1751 ) L1M1_PR_MR + NEW met1 ( 6969 1751 ) M1M2_PR + NEW li1 ( 6969 1513 ) L1M1_PR_MR + NEW met1 ( 6969 1513 ) M1M2_PR ; - rw_sel_p0.select_wr0 ( sel_buf_rw_p0.sel_buf_0 X ) ( storage_0_0_0.select_inv_0 A ) ( storage_0_0_0.gcand A ) + USE SIGNAL - + ROUTED met1 ( 8303 119 ) ( * 153 ) - NEW met1 ( 8280 187 ) ( 8533 * ) - NEW met1 ( 8280 153 ) ( 8303 * ) - NEW met1 ( 8073 153 ) ( 8280 * ) - NEW met1 ( 8280 153 ) ( * 187 ) - NEW li1 ( 8533 187 ) L1M1_PR_MR - NEW li1 ( 8303 119 ) L1M1_PR_MR - NEW li1 ( 8073 153 ) L1M1_PR_MR ; + + ROUTED met1 ( 8671 85 ) ( 8901 * ) + NEW met1 ( 8901 51 ) ( * 85 ) + NEW met1 ( 8441 153 ) ( 8671 * ) + NEW met1 ( 8671 85 ) ( * 153 ) + NEW li1 ( 8671 85 ) L1M1_PR_MR + NEW li1 ( 8901 51 ) L1M1_PR_MR + NEW li1 ( 8441 153 ) L1M1_PR_MR ; - rw_sel_p0.select_wr1 ( sel_buf_rw_p0.sel_buf_1 X ) ( storage_1_0_0.select_inv_0 A ) ( storage_1_0_0.gcand A ) + USE SIGNAL - + ROUTED met1 ( 8303 493 ) ( 8533 * ) - NEW met1 ( 8073 391 ) ( * 425 ) - NEW met1 ( 8073 425 ) ( 8303 * ) - NEW li1 ( 8303 493 ) L1M1_PR_MR - NEW li1 ( 8533 493 ) L1M1_PR_MR - NEW li1 ( 8303 425 ) L1M1_PR_MR - NEW li1 ( 8073 391 ) L1M1_PR_MR ; + + ROUTED met1 ( 8671 493 ) ( 8901 * ) + NEW met1 ( 8441 391 ) ( * 425 ) + NEW met1 ( 8441 425 ) ( 8671 * ) + NEW li1 ( 8671 493 ) L1M1_PR_MR + NEW li1 ( 8901 493 ) L1M1_PR_MR + NEW li1 ( 8441 391 ) L1M1_PR_MR + NEW li1 ( 8671 425 ) L1M1_PR_MR ; - rw_sel_p0.select_wr2 ( sel_buf_rw_p0.sel_buf_2 X ) ( storage_2_0_0.select_inv_0 A ) ( storage_2_0_0.gcand A ) + USE SIGNAL - + ROUTED met1 ( 8303 663 ) ( * 697 ) - NEW met1 ( 8280 697 ) ( 8303 * ) - NEW met1 ( 8280 731 ) ( 8533 * ) - NEW met1 ( 8073 697 ) ( 8280 * ) - NEW met1 ( 8280 697 ) ( * 731 ) - NEW li1 ( 8533 731 ) L1M1_PR_MR - NEW li1 ( 8303 663 ) L1M1_PR_MR - NEW li1 ( 8073 697 ) L1M1_PR_MR ; + + ROUTED met1 ( 8671 629 ) ( 8901 * ) + NEW met1 ( 8901 595 ) ( * 629 ) + NEW met1 ( 8441 697 ) ( 8671 * ) + NEW met1 ( 8671 629 ) ( * 697 ) + NEW li1 ( 8671 629 ) L1M1_PR_MR + NEW li1 ( 8901 595 ) L1M1_PR_MR + NEW li1 ( 8441 697 ) L1M1_PR_MR ; - rw_sel_p0.select_wr3 ( sel_buf_rw_p0.sel_buf_3 X ) ( storage_3_0_0.select_inv_0 A ) ( storage_3_0_0.gcand A ) + USE SIGNAL - + ROUTED met1 ( 8303 1037 ) ( 8533 * ) - NEW met1 ( 8073 935 ) ( * 969 ) - NEW met1 ( 8073 969 ) ( 8303 * ) - NEW li1 ( 8303 1037 ) L1M1_PR_MR - NEW li1 ( 8533 1037 ) L1M1_PR_MR - NEW li1 ( 8303 969 ) L1M1_PR_MR - NEW li1 ( 8073 935 ) L1M1_PR_MR ; + + ROUTED met1 ( 8671 1037 ) ( 8901 * ) + NEW met1 ( 8441 935 ) ( * 969 ) + NEW met1 ( 8441 969 ) ( 8671 * ) + NEW li1 ( 8671 1037 ) L1M1_PR_MR + NEW li1 ( 8901 1037 ) L1M1_PR_MR + NEW li1 ( 8441 935 ) L1M1_PR_MR + NEW li1 ( 8671 969 ) L1M1_PR_MR ; - rw_sel_p0.select_wr4 ( sel_buf_rw_p0.sel_buf_4 X ) ( storage_4_0_0.select_inv_0 A ) ( storage_4_0_0.gcand A ) + USE SIGNAL - + ROUTED met1 ( 8303 1207 ) ( * 1241 ) - NEW met1 ( 8280 1275 ) ( 8533 * ) - NEW met1 ( 8280 1241 ) ( 8303 * ) - NEW met1 ( 8073 1241 ) ( 8280 * ) - NEW met1 ( 8280 1241 ) ( * 1275 ) - NEW li1 ( 8533 1275 ) L1M1_PR_MR - NEW li1 ( 8303 1207 ) L1M1_PR_MR - NEW li1 ( 8073 1241 ) L1M1_PR_MR ; + + ROUTED met1 ( 8671 1173 ) ( 8901 * ) + NEW met1 ( 8901 1139 ) ( * 1173 ) + NEW met1 ( 8441 1241 ) ( 8671 * ) + NEW met1 ( 8671 1173 ) ( * 1241 ) + NEW li1 ( 8671 1173 ) L1M1_PR_MR + NEW li1 ( 8901 1139 ) L1M1_PR_MR + NEW li1 ( 8441 1241 ) L1M1_PR_MR ; - rw_sel_p0.select_wr5 ( sel_buf_rw_p0.sel_buf_5 X ) ( storage_5_0_0.select_inv_0 A ) ( storage_5_0_0.gcand A ) + USE SIGNAL - + ROUTED met1 ( 8303 1445 ) ( * 1513 ) - NEW met1 ( 8303 1445 ) ( 8533 * ) - NEW met1 ( 8073 1445 ) ( 8303 * ) - NEW li1 ( 8303 1513 ) L1M1_PR_MR - NEW li1 ( 8533 1445 ) L1M1_PR_MR - NEW li1 ( 8073 1445 ) L1M1_PR_MR ; + + ROUTED met1 ( 8671 1581 ) ( 8901 * ) + NEW met1 ( 8441 1479 ) ( * 1513 ) + NEW met1 ( 8441 1513 ) ( 8671 * ) + NEW li1 ( 8671 1581 ) L1M1_PR_MR + NEW li1 ( 8901 1581 ) L1M1_PR_MR + NEW li1 ( 8441 1479 ) L1M1_PR_MR + NEW li1 ( 8671 1513 ) L1M1_PR_MR ; - rw_sel_p0.select_wr6 ( sel_buf_rw_p0.sel_buf_6 X ) ( storage_6_0_0.select_inv_0 A ) ( storage_6_0_0.gcand A ) + USE SIGNAL - + ROUTED met1 ( 8303 1717 ) ( 8533 * ) - NEW met1 ( 8533 1683 ) ( * 1717 ) - NEW met1 ( 8073 1785 ) ( 8303 * ) - NEW met1 ( 8303 1717 ) ( * 1785 ) - NEW li1 ( 8303 1717 ) L1M1_PR_MR - NEW li1 ( 8533 1683 ) L1M1_PR_MR - NEW li1 ( 8073 1785 ) L1M1_PR_MR ; + + ROUTED met1 ( 8671 1717 ) ( 8901 * ) + NEW met1 ( 8901 1683 ) ( * 1717 ) + NEW met1 ( 8441 1785 ) ( 8671 * ) + NEW met1 ( 8671 1717 ) ( * 1785 ) + NEW li1 ( 8671 1717 ) L1M1_PR_MR + NEW li1 ( 8901 1683 ) L1M1_PR_MR + NEW li1 ( 8441 1785 ) L1M1_PR_MR ; - rw_sel_p0.select_wr7 ( sel_buf_rw_p0.sel_buf_7 X ) ( storage_7_0_0.select_inv_0 A ) ( storage_7_0_0.gcand A ) + USE SIGNAL - + ROUTED met1 ( 8303 2125 ) ( 8533 * ) - NEW met1 ( 8073 2023 ) ( * 2057 ) - NEW met1 ( 8073 2057 ) ( 8303 * ) - NEW li1 ( 8303 2125 ) L1M1_PR_MR - NEW li1 ( 8533 2125 ) L1M1_PR_MR - NEW li1 ( 8073 2023 ) L1M1_PR_MR - NEW li1 ( 8303 2057 ) L1M1_PR_MR ; + + ROUTED met1 ( 8671 2125 ) ( 8901 * ) + NEW met1 ( 8441 2023 ) ( * 2057 ) + NEW met1 ( 8441 2057 ) ( 8671 * ) + NEW li1 ( 8671 2125 ) L1M1_PR_MR + NEW li1 ( 8901 2125 ) L1M1_PR_MR + NEW li1 ( 8441 2023 ) L1M1_PR_MR + NEW li1 ( 8671 2057 ) L1M1_PR_MR ; - storage_0_0_0.bit0.storage ( storage_0_0_0.bit0.obuf0 A ) ( storage_0_0_0.bit0.bit Q ) + USE SIGNAL - + ROUTED met1 ( 529 119 ) ( 575 * ) - NEW li1 ( 575 119 ) L1M1_PR_MR - NEW li1 ( 529 119 ) L1M1_PR_MR ; + + ROUTED met1 ( 621 153 ) ( * 187 ) + NEW met1 ( 575 187 ) ( 621 * ) + NEW li1 ( 621 153 ) L1M1_PR_MR + NEW li1 ( 575 187 ) L1M1_PR_MR ; - storage_0_0_0.bit1.storage ( storage_0_0_0.bit1.obuf0 A ) ( storage_0_0_0.bit1.bit Q ) + USE SIGNAL - + ROUTED met1 ( 1449 119 ) ( 1495 * ) - NEW li1 ( 1495 119 ) L1M1_PR_MR - NEW li1 ( 1449 119 ) L1M1_PR_MR ; + + ROUTED met1 ( 1587 153 ) ( * 187 ) + NEW met1 ( 1541 187 ) ( 1587 * ) + NEW li1 ( 1587 153 ) L1M1_PR_MR + NEW li1 ( 1541 187 ) L1M1_PR_MR ; - storage_0_0_0.bit2.storage ( storage_0_0_0.bit2.obuf0 A ) ( storage_0_0_0.bit2.bit Q ) + USE SIGNAL - + ROUTED met1 ( 2369 119 ) ( 2415 * ) - NEW li1 ( 2415 119 ) L1M1_PR_MR - NEW li1 ( 2369 119 ) L1M1_PR_MR ; + + ROUTED met1 ( 2553 153 ) ( * 187 ) + NEW met1 ( 2507 187 ) ( 2553 * ) + NEW li1 ( 2553 153 ) L1M1_PR_MR + NEW li1 ( 2507 187 ) L1M1_PR_MR ; - storage_0_0_0.bit3.storage ( storage_0_0_0.bit3.obuf0 A ) ( storage_0_0_0.bit3.bit Q ) + USE SIGNAL - + ROUTED met1 ( 3289 119 ) ( 3335 * ) - NEW li1 ( 3335 119 ) L1M1_PR_MR - NEW li1 ( 3289 119 ) L1M1_PR_MR ; + + ROUTED met1 ( 3519 153 ) ( * 187 ) + NEW met1 ( 3473 187 ) ( 3519 * ) + NEW li1 ( 3519 153 ) L1M1_PR_MR + NEW li1 ( 3473 187 ) L1M1_PR_MR ; - storage_0_0_0.bit4.storage ( storage_0_0_0.bit4.obuf0 A ) ( storage_0_0_0.bit4.bit Q ) + USE SIGNAL - + ROUTED met1 ( 4209 119 ) ( 4255 * ) - NEW li1 ( 4255 119 ) L1M1_PR_MR - NEW li1 ( 4209 119 ) L1M1_PR_MR ; + + ROUTED met1 ( 4485 153 ) ( * 187 ) + NEW met1 ( 4439 187 ) ( 4485 * ) + NEW li1 ( 4485 153 ) L1M1_PR_MR + NEW li1 ( 4439 187 ) L1M1_PR_MR ; - storage_0_0_0.bit5.storage ( storage_0_0_0.bit5.obuf0 A ) ( storage_0_0_0.bit5.bit Q ) + USE SIGNAL - + ROUTED met1 ( 5129 119 ) ( 5175 * ) - NEW li1 ( 5175 119 ) L1M1_PR_MR - NEW li1 ( 5129 119 ) L1M1_PR_MR ; + + ROUTED met1 ( 5451 153 ) ( * 187 ) + NEW met1 ( 5405 187 ) ( 5451 * ) + NEW li1 ( 5451 153 ) L1M1_PR_MR + NEW li1 ( 5405 187 ) L1M1_PR_MR ; - storage_0_0_0.bit6.storage ( storage_0_0_0.bit6.obuf0 A ) ( storage_0_0_0.bit6.bit Q ) + USE SIGNAL - + ROUTED met1 ( 6049 119 ) ( 6095 * ) - NEW li1 ( 6095 119 ) L1M1_PR_MR - NEW li1 ( 6049 119 ) L1M1_PR_MR ; + + ROUTED met1 ( 6417 153 ) ( * 187 ) + NEW met1 ( 6371 187 ) ( 6417 * ) + NEW li1 ( 6417 153 ) L1M1_PR_MR + NEW li1 ( 6371 187 ) L1M1_PR_MR ; - storage_0_0_0.bit7.storage ( storage_0_0_0.bit7.obuf0 A ) ( storage_0_0_0.bit7.bit Q ) + USE SIGNAL - + ROUTED met1 ( 6969 119 ) ( 7015 * ) - NEW li1 ( 7015 119 ) L1M1_PR_MR - NEW li1 ( 6969 119 ) L1M1_PR_MR ; - - storage_0_0_0.gclock ( storage_0_0_0.cg GCLK ) ( storage_0_0_0.bit7.bit SLEEP_B ) ( storage_0_0_0.bit6.bit SLEEP_B ) ( storage_0_0_0.bit5.bit SLEEP_B ) ( storage_0_0_0.bit4.bit SLEEP_B ) ( storage_0_0_0.bit3.bit SLEEP_B ) ( storage_0_0_0.bit2.bit SLEEP_B ) - ( storage_0_0_0.bit1.bit SLEEP_B ) ( storage_0_0_0.bit0.bit SLEEP_B ) + USE SIGNAL - + ROUTED met1 ( 69 153 ) ( 989 * ) - NEW met1 ( 6509 153 ) ( 8027 * ) - NEW met1 ( 4669 153 ) ( 5589 * ) - NEW met1 ( 3749 153 ) ( 4669 * ) - NEW met1 ( 2829 153 ) ( 3749 * ) - NEW met1 ( 1909 153 ) ( 2829 * ) - NEW met1 ( 989 153 ) ( 1909 * ) - NEW met1 ( 5589 153 ) ( 6509 * ) - NEW li1 ( 989 153 ) L1M1_PR_MR - NEW li1 ( 69 153 ) L1M1_PR_MR - NEW li1 ( 6509 153 ) L1M1_PR_MR - NEW li1 ( 8027 153 ) L1M1_PR_MR - NEW li1 ( 5589 153 ) L1M1_PR_MR - NEW li1 ( 4669 153 ) L1M1_PR_MR - NEW li1 ( 3749 153 ) L1M1_PR_MR - NEW li1 ( 2829 153 ) L1M1_PR_MR - NEW li1 ( 1909 153 ) L1M1_PR_MR ; + + ROUTED met1 ( 7383 153 ) ( * 187 ) + NEW met1 ( 7337 187 ) ( 7383 * ) + NEW li1 ( 7383 153 ) L1M1_PR_MR + NEW li1 ( 7337 187 ) L1M1_PR_MR ; + - storage_0_0_0.gclock ( storage_0_0_0.cg GCLK ) ( storage_0_0_0.bit7.bit GATE ) ( storage_0_0_0.bit6.bit GATE ) ( storage_0_0_0.bit5.bit GATE ) ( storage_0_0_0.bit4.bit GATE ) ( storage_0_0_0.bit3.bit GATE ) ( storage_0_0_0.bit2.bit GATE ) + ( storage_0_0_0.bit1.bit GATE ) ( storage_0_0_0.bit0.bit GATE ) + USE SIGNAL + + ROUTED met1 ( 1035 85 ) ( * 119 ) + NEW met1 ( 69 85 ) ( 1035 * ) + NEW met1 ( 69 85 ) ( * 119 ) + NEW met1 ( 6831 85 ) ( * 119 ) + NEW met1 ( 2001 85 ) ( * 119 ) + NEW met1 ( 2967 85 ) ( * 119 ) + NEW met1 ( 2001 85 ) ( 2967 * ) + NEW met1 ( 3933 85 ) ( * 119 ) + NEW met1 ( 2967 85 ) ( 3933 * ) + NEW met1 ( 4899 85 ) ( * 119 ) + NEW met1 ( 3933 85 ) ( 4899 * ) + NEW met1 ( 5865 85 ) ( * 119 ) + NEW met1 ( 4899 85 ) ( 5865 * ) + NEW met1 ( 1035 85 ) ( 2001 * ) + NEW met1 ( 5865 85 ) ( 6831 * ) + NEW met1 ( 7659 85 ) ( * 187 ) + NEW met1 ( 7659 187 ) ( 8395 * ) + NEW met1 ( 6831 85 ) ( 7659 * ) + NEW li1 ( 1035 119 ) L1M1_PR_MR + NEW li1 ( 69 119 ) L1M1_PR_MR + NEW li1 ( 6831 119 ) L1M1_PR_MR + NEW li1 ( 2001 119 ) L1M1_PR_MR + NEW li1 ( 2967 119 ) L1M1_PR_MR + NEW li1 ( 3933 119 ) L1M1_PR_MR + NEW li1 ( 4899 119 ) L1M1_PR_MR + NEW li1 ( 5865 119 ) L1M1_PR_MR + NEW li1 ( 8395 187 ) L1M1_PR_MR ; - storage_0_0_0.select0_b ( storage_0_0_0.select_inv_0 Y ) ( storage_0_0_0.bit7.obuf0 TE_B ) ( storage_0_0_0.bit6.obuf0 TE_B ) ( storage_0_0_0.bit5.obuf0 TE_B ) ( storage_0_0_0.bit4.obuf0 TE_B ) ( storage_0_0_0.bit3.obuf0 TE_B ) ( storage_0_0_0.bit2.obuf0 TE_B ) ( storage_0_0_0.bit1.obuf0 TE_B ) ( storage_0_0_0.bit0.obuf0 TE_B ) + USE SIGNAL - + ROUTED met1 ( 7107 85 ) ( * 119 ) - NEW met1 ( 6785 85 ) ( * 119 ) - NEW met1 ( 6785 85 ) ( 7107 * ) - NEW met1 ( 7107 85 ) ( 8349 * ) - NEW met1 ( 667 119 ) ( 1380 * ) - NEW met1 ( 1587 85 ) ( * 119 ) - NEW met1 ( 1380 85 ) ( 1587 * ) - NEW met1 ( 1380 85 ) ( * 119 ) - NEW met1 ( 2507 85 ) ( * 119 ) - NEW met1 ( 2323 85 ) ( 2507 * ) - NEW met1 ( 2323 85 ) ( * 119 ) - NEW met1 ( 1587 119 ) ( 2323 * ) - NEW met1 ( 3427 85 ) ( * 119 ) - NEW met1 ( 3243 85 ) ( 3427 * ) - NEW met1 ( 3243 85 ) ( * 119 ) - NEW met1 ( 2507 119 ) ( 3243 * ) - NEW met1 ( 4347 85 ) ( * 119 ) - NEW met1 ( 4163 85 ) ( 4347 * ) - NEW met1 ( 4163 85 ) ( * 119 ) - NEW met1 ( 3427 119 ) ( 4163 * ) - NEW met1 ( 5267 85 ) ( * 119 ) - NEW met1 ( 5083 85 ) ( 5267 * ) - NEW met1 ( 5083 85 ) ( * 119 ) - NEW met1 ( 4347 119 ) ( 5083 * ) - NEW met1 ( 6187 85 ) ( * 119 ) - NEW met1 ( 6003 85 ) ( 6187 * ) - NEW met1 ( 6003 85 ) ( * 119 ) - NEW met1 ( 5267 119 ) ( 6003 * ) - NEW met1 ( 6187 119 ) ( 6785 * ) - NEW li1 ( 667 119 ) L1M1_PR_MR - NEW li1 ( 8349 85 ) L1M1_PR_MR - NEW li1 ( 7107 119 ) L1M1_PR_MR - NEW li1 ( 1587 119 ) L1M1_PR_MR - NEW li1 ( 2507 119 ) L1M1_PR_MR - NEW li1 ( 3427 119 ) L1M1_PR_MR - NEW li1 ( 4347 119 ) L1M1_PR_MR - NEW li1 ( 5267 119 ) L1M1_PR_MR - NEW li1 ( 6187 119 ) L1M1_PR_MR ; + + ROUTED met1 ( 713 153 ) ( 989 * ) + NEW met1 ( 989 153 ) ( * 221 ) + NEW met1 ( 7475 153 ) ( * 187 ) + NEW met1 ( 6509 153 ) ( 6785 * ) + NEW met1 ( 6785 153 ) ( * 221 ) + NEW met1 ( 6785 221 ) ( 7475 * ) + NEW met1 ( 7475 187 ) ( * 221 ) + NEW met1 ( 6509 153 ) ( * 221 ) + NEW met1 ( 5543 153 ) ( 5773 * ) + NEW met1 ( 5773 153 ) ( * 221 ) + NEW met1 ( 4577 153 ) ( 4853 * ) + NEW met1 ( 4853 153 ) ( * 221 ) + NEW met1 ( 4853 221 ) ( 5543 * ) + NEW met1 ( 5543 153 ) ( * 221 ) + NEW met1 ( 3611 153 ) ( 3841 * ) + NEW met1 ( 3841 153 ) ( * 221 ) + NEW met1 ( 3841 221 ) ( 4577 * ) + NEW met1 ( 4577 153 ) ( * 221 ) + NEW met1 ( 2645 153 ) ( 2921 * ) + NEW met1 ( 2921 153 ) ( * 221 ) + NEW met1 ( 2921 221 ) ( 3611 * ) + NEW met1 ( 3611 153 ) ( * 221 ) + NEW met1 ( 1679 153 ) ( 1909 * ) + NEW met1 ( 1909 153 ) ( * 221 ) + NEW met1 ( 1909 221 ) ( 2645 * ) + NEW met1 ( 2645 153 ) ( * 221 ) + NEW met1 ( 1679 153 ) ( * 221 ) + NEW met1 ( 989 221 ) ( 1679 * ) + NEW met1 ( 5773 221 ) ( 6509 * ) + NEW met1 ( 7475 187 ) ( 7590 * ) + NEW met1 ( 7590 187 ) ( * 221 ) + NEW met1 ( 7590 221 ) ( 8717 * ) + NEW li1 ( 713 153 ) L1M1_PR_MR + NEW li1 ( 7475 153 ) L1M1_PR_MR + NEW li1 ( 6509 153 ) L1M1_PR_MR + NEW li1 ( 5543 153 ) L1M1_PR_MR + NEW li1 ( 4577 153 ) L1M1_PR_MR + NEW li1 ( 3611 153 ) L1M1_PR_MR + NEW li1 ( 2645 153 ) L1M1_PR_MR + NEW li1 ( 1679 153 ) L1M1_PR_MR + NEW li1 ( 8717 221 ) L1M1_PR_MR ; - storage_0_0_0.we ( storage_0_0_0.gcand X ) ( storage_0_0_0.cg GATE ) + USE SIGNAL - + ROUTED met1 ( 7613 51 ) ( 8257 * ) - NEW li1 ( 7613 51 ) L1M1_PR_MR - NEW li1 ( 8257 51 ) L1M1_PR_MR ; + + ROUTED met1 ( 7981 51 ) ( 8625 * ) + NEW li1 ( 7981 51 ) L1M1_PR_MR + NEW li1 ( 8625 51 ) L1M1_PR_MR ; - storage_1_0_0.bit0.storage ( storage_1_0_0.bit0.obuf0 A ) ( storage_1_0_0.bit0.bit Q ) + USE SIGNAL - + ROUTED met1 ( 529 425 ) ( 575 * ) - NEW li1 ( 575 425 ) L1M1_PR_MR - NEW li1 ( 529 425 ) L1M1_PR_MR ; + + ROUTED met1 ( 575 391 ) ( 621 * ) + NEW met1 ( 575 357 ) ( * 391 ) + NEW li1 ( 621 391 ) L1M1_PR_MR + NEW li1 ( 575 357 ) L1M1_PR_MR ; - storage_1_0_0.bit1.storage ( storage_1_0_0.bit1.obuf0 A ) ( storage_1_0_0.bit1.bit Q ) + USE SIGNAL - + ROUTED met1 ( 1449 425 ) ( 1495 * ) - NEW li1 ( 1495 425 ) L1M1_PR_MR - NEW li1 ( 1449 425 ) L1M1_PR_MR ; + + ROUTED met1 ( 1541 391 ) ( 1587 * ) + NEW met1 ( 1541 357 ) ( * 391 ) + NEW li1 ( 1587 391 ) L1M1_PR_MR + NEW li1 ( 1541 357 ) L1M1_PR_MR ; - storage_1_0_0.bit2.storage ( storage_1_0_0.bit2.obuf0 A ) ( storage_1_0_0.bit2.bit Q ) + USE SIGNAL - + ROUTED met1 ( 2369 425 ) ( 2415 * ) - NEW li1 ( 2415 425 ) L1M1_PR_MR - NEW li1 ( 2369 425 ) L1M1_PR_MR ; + + ROUTED met1 ( 2507 391 ) ( 2553 * ) + NEW met1 ( 2507 357 ) ( * 391 ) + NEW li1 ( 2553 391 ) L1M1_PR_MR + NEW li1 ( 2507 357 ) L1M1_PR_MR ; - storage_1_0_0.bit3.storage ( storage_1_0_0.bit3.obuf0 A ) ( storage_1_0_0.bit3.bit Q ) + USE SIGNAL - + ROUTED met1 ( 3289 425 ) ( 3335 * ) - NEW li1 ( 3335 425 ) L1M1_PR_MR - NEW li1 ( 3289 425 ) L1M1_PR_MR ; + + ROUTED met1 ( 3473 391 ) ( 3519 * ) + NEW met1 ( 3473 357 ) ( * 391 ) + NEW li1 ( 3519 391 ) L1M1_PR_MR + NEW li1 ( 3473 357 ) L1M1_PR_MR ; - storage_1_0_0.bit4.storage ( storage_1_0_0.bit4.obuf0 A ) ( storage_1_0_0.bit4.bit Q ) + USE SIGNAL - + ROUTED met1 ( 4209 425 ) ( 4255 * ) - NEW li1 ( 4255 425 ) L1M1_PR_MR - NEW li1 ( 4209 425 ) L1M1_PR_MR ; + + ROUTED met1 ( 4439 391 ) ( 4485 * ) + NEW met1 ( 4439 357 ) ( * 391 ) + NEW li1 ( 4485 391 ) L1M1_PR_MR + NEW li1 ( 4439 357 ) L1M1_PR_MR ; - storage_1_0_0.bit5.storage ( storage_1_0_0.bit5.obuf0 A ) ( storage_1_0_0.bit5.bit Q ) + USE SIGNAL - + ROUTED met1 ( 5129 425 ) ( 5175 * ) - NEW li1 ( 5175 425 ) L1M1_PR_MR - NEW li1 ( 5129 425 ) L1M1_PR_MR ; + + ROUTED met1 ( 5405 391 ) ( 5451 * ) + NEW met1 ( 5405 357 ) ( * 391 ) + NEW li1 ( 5451 391 ) L1M1_PR_MR + NEW li1 ( 5405 357 ) L1M1_PR_MR ; - storage_1_0_0.bit6.storage ( storage_1_0_0.bit6.obuf0 A ) ( storage_1_0_0.bit6.bit Q ) + USE SIGNAL - + ROUTED met1 ( 6049 425 ) ( 6095 * ) - NEW li1 ( 6095 425 ) L1M1_PR_MR - NEW li1 ( 6049 425 ) L1M1_PR_MR ; + + ROUTED met1 ( 6371 391 ) ( 6417 * ) + NEW met1 ( 6371 357 ) ( * 391 ) + NEW li1 ( 6417 391 ) L1M1_PR_MR + NEW li1 ( 6371 357 ) L1M1_PR_MR ; - storage_1_0_0.bit7.storage ( storage_1_0_0.bit7.obuf0 A ) ( storage_1_0_0.bit7.bit Q ) + USE SIGNAL - + ROUTED met1 ( 6969 425 ) ( 7015 * ) - NEW li1 ( 7015 425 ) L1M1_PR_MR - NEW li1 ( 6969 425 ) L1M1_PR_MR ; - - storage_1_0_0.gclock ( storage_1_0_0.cg GCLK ) ( storage_1_0_0.bit7.bit SLEEP_B ) ( storage_1_0_0.bit6.bit SLEEP_B ) ( storage_1_0_0.bit5.bit SLEEP_B ) ( storage_1_0_0.bit4.bit SLEEP_B ) ( storage_1_0_0.bit3.bit SLEEP_B ) ( storage_1_0_0.bit2.bit SLEEP_B ) - ( storage_1_0_0.bit1.bit SLEEP_B ) ( storage_1_0_0.bit0.bit SLEEP_B ) + USE SIGNAL - + ROUTED met1 ( 6509 391 ) ( 8027 * ) - NEW met1 ( 6509 357 ) ( * 391 ) - NEW met1 ( 5589 357 ) ( * 391 ) - NEW met1 ( 4669 357 ) ( * 391 ) - NEW met1 ( 4669 357 ) ( 5589 * ) - NEW met1 ( 3749 357 ) ( * 391 ) - NEW met1 ( 3749 357 ) ( 4669 * ) - NEW met1 ( 5589 357 ) ( 6509 * ) - NEW met1 ( 621 425 ) ( 989 * ) - NEW met1 ( 621 391 ) ( * 425 ) - NEW met1 ( 69 391 ) ( 621 * ) - NEW met1 ( 1909 357 ) ( * 391 ) - NEW met1 ( 989 357 ) ( 1909 * ) - NEW met2 ( 989 357 ) ( * 425 ) - NEW met1 ( 1909 391 ) ( 2829 * ) - NEW met1 ( 2829 357 ) ( * 391 ) - NEW met1 ( 2829 357 ) ( 3749 * ) - NEW li1 ( 6509 391 ) L1M1_PR_MR - NEW li1 ( 8027 391 ) L1M1_PR_MR - NEW li1 ( 5589 391 ) L1M1_PR_MR - NEW li1 ( 4669 391 ) L1M1_PR_MR - NEW li1 ( 3749 391 ) L1M1_PR_MR - NEW li1 ( 989 425 ) L1M1_PR_MR - NEW li1 ( 69 391 ) L1M1_PR_MR - NEW li1 ( 1909 391 ) L1M1_PR_MR - NEW met1 ( 989 357 ) M1M2_PR - NEW met1 ( 989 425 ) M1M2_PR - NEW li1 ( 2829 391 ) L1M1_PR_MR ; + + ROUTED met1 ( 7337 391 ) ( 7383 * ) + NEW met1 ( 7337 357 ) ( * 391 ) + NEW li1 ( 7383 391 ) L1M1_PR_MR + NEW li1 ( 7337 357 ) L1M1_PR_MR ; + - storage_1_0_0.gclock ( storage_1_0_0.cg GCLK ) ( storage_1_0_0.bit7.bit GATE ) ( storage_1_0_0.bit6.bit GATE ) ( storage_1_0_0.bit5.bit GATE ) ( storage_1_0_0.bit4.bit GATE ) ( storage_1_0_0.bit3.bit GATE ) ( storage_1_0_0.bit2.bit GATE ) + ( storage_1_0_0.bit1.bit GATE ) ( storage_1_0_0.bit0.bit GATE ) + USE SIGNAL + + ROUTED met1 ( 1035 425 ) ( * 459 ) + NEW met1 ( 69 459 ) ( 1035 * ) + NEW met1 ( 69 425 ) ( * 459 ) + NEW met1 ( 6831 323 ) ( * 391 ) + NEW met1 ( 2001 425 ) ( * 459 ) + NEW met1 ( 2967 425 ) ( * 459 ) + NEW met1 ( 2001 459 ) ( 2967 * ) + NEW met1 ( 3933 425 ) ( * 459 ) + NEW met1 ( 2967 459 ) ( 3933 * ) + NEW met1 ( 4899 425 ) ( * 459 ) + NEW met1 ( 3933 459 ) ( 4899 * ) + NEW met1 ( 5773 391 ) ( 5865 * ) + NEW met1 ( 5773 391 ) ( * 459 ) + NEW met1 ( 4899 459 ) ( 5773 * ) + NEW met1 ( 5865 323 ) ( * 391 ) + NEW met1 ( 1035 459 ) ( 2001 * ) + NEW met1 ( 5865 323 ) ( 6831 * ) + NEW met1 ( 6831 323 ) ( 8395 * ) + NEW li1 ( 1035 425 ) L1M1_PR_MR + NEW li1 ( 69 425 ) L1M1_PR_MR + NEW li1 ( 6831 391 ) L1M1_PR_MR + NEW li1 ( 2001 425 ) L1M1_PR_MR + NEW li1 ( 2967 425 ) L1M1_PR_MR + NEW li1 ( 3933 425 ) L1M1_PR_MR + NEW li1 ( 4899 425 ) L1M1_PR_MR + NEW li1 ( 5865 391 ) L1M1_PR_MR + NEW li1 ( 8395 323 ) L1M1_PR_MR ; - storage_1_0_0.select0_b ( storage_1_0_0.select_inv_0 Y ) ( storage_1_0_0.bit7.obuf0 TE_B ) ( storage_1_0_0.bit6.obuf0 TE_B ) ( storage_1_0_0.bit5.obuf0 TE_B ) ( storage_1_0_0.bit4.obuf0 TE_B ) ( storage_1_0_0.bit3.obuf0 TE_B ) ( storage_1_0_0.bit2.obuf0 TE_B ) ( storage_1_0_0.bit1.obuf0 TE_B ) ( storage_1_0_0.bit0.obuf0 TE_B ) + USE SIGNAL - + ROUTED met1 ( 7107 425 ) ( * 459 ) - NEW met1 ( 6785 425 ) ( * 459 ) - NEW met1 ( 6785 459 ) ( 7107 * ) - NEW met1 ( 7107 459 ) ( 8349 * ) - NEW met1 ( 4163 391 ) ( 4347 * ) - NEW met1 ( 4163 391 ) ( * 425 ) - NEW met1 ( 5083 391 ) ( 5267 * ) - NEW met1 ( 5083 391 ) ( * 425 ) - NEW met1 ( 4347 425 ) ( 5083 * ) - NEW met1 ( 4347 391 ) ( * 425 ) - NEW met1 ( 6003 391 ) ( 6187 * ) - NEW met1 ( 6003 391 ) ( * 425 ) - NEW met1 ( 5267 425 ) ( 6003 * ) - NEW met1 ( 5267 391 ) ( * 425 ) - NEW met1 ( 6187 391 ) ( * 425 ) - NEW met1 ( 6187 425 ) ( 6785 * ) - NEW met1 ( 1587 425 ) ( * 459 ) - NEW met1 ( 1311 459 ) ( 1587 * ) - NEW met1 ( 1311 391 ) ( * 459 ) - NEW met1 ( 667 391 ) ( 1311 * ) - NEW met1 ( 2507 425 ) ( * 459 ) - NEW met1 ( 2323 459 ) ( 2507 * ) - NEW met1 ( 2323 425 ) ( * 459 ) - NEW met1 ( 1587 425 ) ( 2323 * ) - NEW met1 ( 3243 391 ) ( 3427 * ) - NEW met1 ( 3243 391 ) ( * 425 ) - NEW met1 ( 2507 425 ) ( 3243 * ) - NEW met1 ( 3427 391 ) ( * 425 ) - NEW met1 ( 3427 425 ) ( 4163 * ) - NEW li1 ( 8349 459 ) L1M1_PR_MR - NEW li1 ( 7107 425 ) L1M1_PR_MR - NEW li1 ( 4347 391 ) L1M1_PR_MR - NEW li1 ( 5267 391 ) L1M1_PR_MR - NEW li1 ( 6187 391 ) L1M1_PR_MR - NEW li1 ( 1587 425 ) L1M1_PR_MR - NEW li1 ( 667 391 ) L1M1_PR_MR - NEW li1 ( 2507 425 ) L1M1_PR_MR - NEW li1 ( 3427 391 ) L1M1_PR_MR ; + + ROUTED met1 ( 713 323 ) ( * 391 ) + NEW met1 ( 7475 357 ) ( * 391 ) + NEW met1 ( 6509 425 ) ( * 459 ) + NEW met1 ( 6509 459 ) ( 7475 * ) + NEW met1 ( 7475 391 ) ( * 459 ) + NEW met1 ( 5543 357 ) ( * 391 ) + NEW met1 ( 5543 357 ) ( 5819 * ) + NEW met2 ( 5819 357 ) ( * 459 ) + NEW met1 ( 4577 323 ) ( * 391 ) + NEW met1 ( 4577 323 ) ( 5543 * ) + NEW met1 ( 5543 323 ) ( * 357 ) + NEW met1 ( 3611 323 ) ( * 391 ) + NEW met1 ( 3611 323 ) ( 4577 * ) + NEW met1 ( 2645 323 ) ( * 391 ) + NEW met1 ( 2645 323 ) ( 3611 * ) + NEW met1 ( 1679 323 ) ( * 391 ) + NEW met1 ( 1679 323 ) ( 2645 * ) + NEW met1 ( 713 323 ) ( 1679 * ) + NEW met1 ( 5819 459 ) ( 6509 * ) + NEW met1 ( 7475 357 ) ( 8717 * ) + NEW li1 ( 713 391 ) L1M1_PR_MR + NEW li1 ( 7475 391 ) L1M1_PR_MR + NEW li1 ( 6509 425 ) L1M1_PR_MR + NEW li1 ( 5543 391 ) L1M1_PR_MR + NEW met1 ( 5819 357 ) M1M2_PR + NEW met1 ( 5819 459 ) M1M2_PR + NEW li1 ( 4577 391 ) L1M1_PR_MR + NEW li1 ( 3611 391 ) L1M1_PR_MR + NEW li1 ( 2645 391 ) L1M1_PR_MR + NEW li1 ( 1679 391 ) L1M1_PR_MR + NEW li1 ( 8717 357 ) L1M1_PR_MR ; - storage_1_0_0.we ( storage_1_0_0.gcand X ) ( storage_1_0_0.cg GATE ) + USE SIGNAL - + ROUTED met1 ( 7613 493 ) ( 8257 * ) - NEW li1 ( 7613 493 ) L1M1_PR_MR - NEW li1 ( 8257 493 ) L1M1_PR_MR ; + + ROUTED met1 ( 7981 459 ) ( 8625 * ) + NEW li1 ( 7981 459 ) L1M1_PR_MR + NEW li1 ( 8625 459 ) L1M1_PR_MR ; - storage_2_0_0.bit0.storage ( storage_2_0_0.bit0.obuf0 A ) ( storage_2_0_0.bit0.bit Q ) + USE SIGNAL - + ROUTED met1 ( 529 663 ) ( 575 * ) - NEW li1 ( 575 663 ) L1M1_PR_MR - NEW li1 ( 529 663 ) L1M1_PR_MR ; + + ROUTED met1 ( 575 663 ) ( 621 * ) + NEW met1 ( 575 595 ) ( * 663 ) + NEW li1 ( 621 663 ) L1M1_PR_MR + NEW li1 ( 575 595 ) L1M1_PR_MR ; - storage_2_0_0.bit1.storage ( storage_2_0_0.bit1.obuf0 A ) ( storage_2_0_0.bit1.bit Q ) + USE SIGNAL - + ROUTED met1 ( 1449 663 ) ( 1495 * ) - NEW li1 ( 1495 663 ) L1M1_PR_MR - NEW li1 ( 1449 663 ) L1M1_PR_MR ; + + ROUTED met1 ( 1541 663 ) ( 1587 * ) + NEW met1 ( 1541 663 ) ( * 731 ) + NEW li1 ( 1587 663 ) L1M1_PR_MR + NEW li1 ( 1541 731 ) L1M1_PR_MR ; - storage_2_0_0.bit2.storage ( storage_2_0_0.bit2.obuf0 A ) ( storage_2_0_0.bit2.bit Q ) + USE SIGNAL - + ROUTED met1 ( 2369 663 ) ( 2415 * ) - NEW li1 ( 2415 663 ) L1M1_PR_MR - NEW li1 ( 2369 663 ) L1M1_PR_MR ; + + ROUTED met1 ( 2507 663 ) ( 2553 * ) + NEW met1 ( 2507 663 ) ( * 731 ) + NEW li1 ( 2553 663 ) L1M1_PR_MR + NEW li1 ( 2507 731 ) L1M1_PR_MR ; - storage_2_0_0.bit3.storage ( storage_2_0_0.bit3.obuf0 A ) ( storage_2_0_0.bit3.bit Q ) + USE SIGNAL - + ROUTED met1 ( 3289 663 ) ( 3335 * ) - NEW li1 ( 3335 663 ) L1M1_PR_MR - NEW li1 ( 3289 663 ) L1M1_PR_MR ; + + ROUTED met1 ( 3473 663 ) ( 3519 * ) + NEW met1 ( 3473 663 ) ( * 731 ) + NEW li1 ( 3519 663 ) L1M1_PR_MR + NEW li1 ( 3473 731 ) L1M1_PR_MR ; - storage_2_0_0.bit4.storage ( storage_2_0_0.bit4.obuf0 A ) ( storage_2_0_0.bit4.bit Q ) + USE SIGNAL - + ROUTED met1 ( 4209 663 ) ( 4255 * ) - NEW li1 ( 4255 663 ) L1M1_PR_MR - NEW li1 ( 4209 663 ) L1M1_PR_MR ; + + ROUTED met1 ( 4439 663 ) ( 4485 * ) + NEW met1 ( 4439 663 ) ( * 731 ) + NEW li1 ( 4485 663 ) L1M1_PR_MR + NEW li1 ( 4439 731 ) L1M1_PR_MR ; - storage_2_0_0.bit5.storage ( storage_2_0_0.bit5.obuf0 A ) ( storage_2_0_0.bit5.bit Q ) + USE SIGNAL - + ROUTED met1 ( 5129 663 ) ( 5175 * ) - NEW li1 ( 5175 663 ) L1M1_PR_MR - NEW li1 ( 5129 663 ) L1M1_PR_MR ; + + ROUTED met1 ( 5405 663 ) ( 5451 * ) + NEW met1 ( 5405 663 ) ( * 731 ) + NEW li1 ( 5451 663 ) L1M1_PR_MR + NEW li1 ( 5405 731 ) L1M1_PR_MR ; - storage_2_0_0.bit6.storage ( storage_2_0_0.bit6.obuf0 A ) ( storage_2_0_0.bit6.bit Q ) + USE SIGNAL - + ROUTED met1 ( 6049 663 ) ( 6095 * ) - NEW li1 ( 6095 663 ) L1M1_PR_MR - NEW li1 ( 6049 663 ) L1M1_PR_MR ; + + ROUTED met1 ( 6371 663 ) ( 6417 * ) + NEW met1 ( 6371 663 ) ( * 731 ) + NEW li1 ( 6417 663 ) L1M1_PR_MR + NEW li1 ( 6371 731 ) L1M1_PR_MR ; - storage_2_0_0.bit7.storage ( storage_2_0_0.bit7.obuf0 A ) ( storage_2_0_0.bit7.bit Q ) + USE SIGNAL - + ROUTED met1 ( 6969 663 ) ( 7015 * ) - NEW li1 ( 7015 663 ) L1M1_PR_MR - NEW li1 ( 6969 663 ) L1M1_PR_MR ; - - storage_2_0_0.gclock ( storage_2_0_0.cg GCLK ) ( storage_2_0_0.bit7.bit SLEEP_B ) ( storage_2_0_0.bit6.bit SLEEP_B ) ( storage_2_0_0.bit5.bit SLEEP_B ) ( storage_2_0_0.bit4.bit SLEEP_B ) ( storage_2_0_0.bit3.bit SLEEP_B ) ( storage_2_0_0.bit2.bit SLEEP_B ) - ( storage_2_0_0.bit1.bit SLEEP_B ) ( storage_2_0_0.bit0.bit SLEEP_B ) + USE SIGNAL - + ROUTED met1 ( 989 629 ) ( * 663 ) - NEW met1 ( 483 629 ) ( 989 * ) - NEW met1 ( 483 629 ) ( * 663 ) - NEW met1 ( 69 663 ) ( 483 * ) - NEW met1 ( 6509 663 ) ( 6785 * ) - NEW met1 ( 6785 629 ) ( * 663 ) - NEW met1 ( 6785 629 ) ( 7889 * ) - NEW met2 ( 7889 629 ) ( * 731 ) - NEW met1 ( 7889 731 ) ( 8027 * ) - NEW met1 ( 6509 629 ) ( * 663 ) - NEW met1 ( 989 663 ) ( 1380 * ) + + ROUTED met1 ( 7383 648 ) ( * 663 ) + NEW met1 ( 7337 648 ) ( 7383 * ) + NEW met1 ( 7337 595 ) ( * 648 ) + NEW li1 ( 7383 663 ) L1M1_PR_MR + NEW li1 ( 7337 595 ) L1M1_PR_MR ; + - storage_2_0_0.gclock ( storage_2_0_0.cg GCLK ) ( storage_2_0_0.bit7.bit GATE ) ( storage_2_0_0.bit6.bit GATE ) ( storage_2_0_0.bit5.bit GATE ) ( storage_2_0_0.bit4.bit GATE ) ( storage_2_0_0.bit3.bit GATE ) ( storage_2_0_0.bit2.bit GATE ) + ( storage_2_0_0.bit1.bit GATE ) ( storage_2_0_0.bit0.bit GATE ) + USE SIGNAL + + ROUTED met1 ( 759 663 ) ( 1035 * ) + NEW met1 ( 759 663 ) ( * 697 ) + NEW met1 ( 529 697 ) ( 759 * ) + NEW met1 ( 529 629 ) ( * 697 ) + NEW met1 ( 69 629 ) ( 529 * ) + NEW met1 ( 69 629 ) ( * 663 ) + NEW met1 ( 1035 629 ) ( * 663 ) + NEW met1 ( 6831 697 ) ( * 765 ) + NEW met1 ( 6831 765 ) ( 7153 * ) + NEW met1 ( 7153 731 ) ( * 765 ) + NEW met1 ( 6463 629 ) ( * 697 ) + NEW met1 ( 6463 697 ) ( 6831 * ) + NEW met1 ( 1725 663 ) ( 2001 * ) + NEW met1 ( 1725 663 ) ( * 697 ) + NEW met1 ( 1633 697 ) ( 1725 * ) + NEW met1 ( 1633 629 ) ( * 697 ) + NEW met1 ( 2691 663 ) ( 2967 * ) + NEW met1 ( 2691 663 ) ( * 697 ) + NEW met1 ( 2599 697 ) ( 2691 * ) + NEW met1 ( 2599 629 ) ( * 697 ) + NEW met1 ( 2001 629 ) ( 2599 * ) + NEW met1 ( 2001 629 ) ( * 663 ) + NEW met1 ( 3657 663 ) ( 3933 * ) + NEW met1 ( 3657 663 ) ( * 697 ) + NEW met1 ( 3565 697 ) ( 3657 * ) + NEW met1 ( 3565 629 ) ( * 697 ) + NEW met1 ( 2967 629 ) ( 3565 * ) + NEW met1 ( 2967 629 ) ( * 663 ) + NEW met1 ( 4623 663 ) ( 4899 * ) + NEW met1 ( 4623 663 ) ( * 697 ) + NEW met1 ( 4531 697 ) ( 4623 * ) + NEW met1 ( 4531 629 ) ( * 697 ) + NEW met1 ( 3933 629 ) ( 4531 * ) + NEW met1 ( 3933 629 ) ( * 663 ) NEW met1 ( 5589 663 ) ( 5865 * ) - NEW met1 ( 5865 629 ) ( * 663 ) - NEW met1 ( 4669 663 ) ( 4899 * ) + NEW met1 ( 5589 663 ) ( * 697 ) + NEW met1 ( 5497 697 ) ( 5589 * ) + NEW met1 ( 5497 629 ) ( * 697 ) + NEW met1 ( 4899 629 ) ( 5497 * ) NEW met1 ( 4899 629 ) ( * 663 ) - NEW met1 ( 4899 629 ) ( 5589 * ) - NEW met1 ( 5589 629 ) ( * 663 ) - NEW met1 ( 3749 663 ) ( 4117 * ) - NEW met1 ( 4117 629 ) ( * 663 ) - NEW met1 ( 4117 629 ) ( 4669 * ) - NEW met1 ( 4669 629 ) ( * 663 ) - NEW met1 ( 2829 663 ) ( 3059 * ) - NEW met1 ( 3059 629 ) ( * 663 ) - NEW met1 ( 3059 629 ) ( 3749 * ) - NEW met1 ( 3749 629 ) ( * 663 ) - NEW met1 ( 1909 663 ) ( 2139 * ) - NEW met1 ( 2139 629 ) ( * 663 ) - NEW met1 ( 2139 629 ) ( 2829 * ) - NEW met1 ( 2829 629 ) ( * 663 ) - NEW met1 ( 1380 629 ) ( * 663 ) - NEW met1 ( 1380 629 ) ( 1909 * ) - NEW met1 ( 1909 629 ) ( * 663 ) - NEW met1 ( 5865 629 ) ( 6509 * ) - NEW li1 ( 989 663 ) L1M1_PR_MR + NEW met1 ( 5865 629 ) ( * 663 ) + NEW met1 ( 1035 629 ) ( 1633 * ) + NEW met1 ( 5865 629 ) ( 6463 * ) + NEW met1 ( 7153 731 ) ( 8395 * ) + NEW li1 ( 1035 663 ) L1M1_PR_MR NEW li1 ( 69 663 ) L1M1_PR_MR - NEW li1 ( 6509 663 ) L1M1_PR_MR - NEW met1 ( 7889 629 ) M1M2_PR - NEW met1 ( 7889 731 ) M1M2_PR - NEW li1 ( 8027 731 ) L1M1_PR_MR - NEW li1 ( 5589 663 ) L1M1_PR_MR - NEW li1 ( 4669 663 ) L1M1_PR_MR - NEW li1 ( 3749 663 ) L1M1_PR_MR - NEW li1 ( 2829 663 ) L1M1_PR_MR - NEW li1 ( 1909 663 ) L1M1_PR_MR ; + NEW li1 ( 6831 697 ) L1M1_PR_MR + NEW li1 ( 2001 663 ) L1M1_PR_MR + NEW li1 ( 2967 663 ) L1M1_PR_MR + NEW li1 ( 3933 663 ) L1M1_PR_MR + NEW li1 ( 4899 663 ) L1M1_PR_MR + NEW li1 ( 5865 663 ) L1M1_PR_MR + NEW li1 ( 8395 731 ) L1M1_PR_MR ; - storage_2_0_0.select0_b ( storage_2_0_0.select_inv_0 Y ) ( storage_2_0_0.bit7.obuf0 TE_B ) ( storage_2_0_0.bit6.obuf0 TE_B ) ( storage_2_0_0.bit5.obuf0 TE_B ) ( storage_2_0_0.bit4.obuf0 TE_B ) ( storage_2_0_0.bit3.obuf0 TE_B ) ( storage_2_0_0.bit2.obuf0 TE_B ) ( storage_2_0_0.bit1.obuf0 TE_B ) ( storage_2_0_0.bit0.obuf0 TE_B ) + USE SIGNAL - + ROUTED met1 ( 943 663 ) ( * 697 ) - NEW met1 ( 667 663 ) ( 943 * ) - NEW met1 ( 7107 663 ) ( 7383 * ) - NEW met1 ( 7383 663 ) ( * 697 ) - NEW met1 ( 7383 697 ) ( 7981 * ) - NEW met1 ( 7981 629 ) ( * 697 ) - NEW met1 ( 6463 663 ) ( * 697 ) - NEW met1 ( 6463 697 ) ( 7061 * ) - NEW met1 ( 7061 663 ) ( * 697 ) - NEW met1 ( 7061 663 ) ( 7107 * ) - NEW met1 ( 7981 629 ) ( 8349 * ) - NEW met1 ( 1541 663 ) ( 1587 * ) - NEW met1 ( 1541 663 ) ( * 697 ) - NEW met1 ( 2461 663 ) ( 2507 * ) - NEW met1 ( 2461 663 ) ( * 697 ) - NEW met1 ( 1863 697 ) ( 2461 * ) - NEW met1 ( 1863 663 ) ( * 697 ) - NEW met1 ( 1587 663 ) ( 1863 * ) - NEW met1 ( 3381 663 ) ( 3427 * ) - NEW met1 ( 3381 663 ) ( * 697 ) - NEW met1 ( 2783 697 ) ( 3381 * ) - NEW met1 ( 2783 663 ) ( * 697 ) - NEW met1 ( 2507 663 ) ( 2783 * ) - NEW met1 ( 4301 663 ) ( 4347 * ) - NEW met1 ( 4301 663 ) ( * 697 ) - NEW met1 ( 3703 697 ) ( 4301 * ) - NEW met1 ( 3703 663 ) ( * 697 ) - NEW met1 ( 3427 663 ) ( 3703 * ) - NEW met1 ( 5221 663 ) ( 5267 * ) - NEW met1 ( 5221 663 ) ( * 697 ) - NEW met1 ( 4623 697 ) ( 5221 * ) - NEW met1 ( 4623 663 ) ( * 697 ) - NEW met1 ( 4347 663 ) ( 4623 * ) - NEW met1 ( 6141 663 ) ( 6187 * ) - NEW met1 ( 6141 663 ) ( * 697 ) - NEW met1 ( 5543 697 ) ( 6141 * ) - NEW met1 ( 5543 663 ) ( * 697 ) - NEW met1 ( 5267 663 ) ( 5543 * ) - NEW met1 ( 943 697 ) ( 1541 * ) - NEW met1 ( 6187 663 ) ( 6463 * ) - NEW li1 ( 667 663 ) L1M1_PR_MR - NEW li1 ( 8349 629 ) L1M1_PR_MR - NEW li1 ( 7107 663 ) L1M1_PR_MR - NEW li1 ( 1587 663 ) L1M1_PR_MR - NEW li1 ( 2507 663 ) L1M1_PR_MR - NEW li1 ( 3427 663 ) L1M1_PR_MR - NEW li1 ( 4347 663 ) L1M1_PR_MR - NEW li1 ( 5267 663 ) L1M1_PR_MR - NEW li1 ( 6187 663 ) L1M1_PR_MR ; + + ROUTED met1 ( 713 595 ) ( * 663 ) + NEW met1 ( 7475 629 ) ( * 663 ) + NEW met1 ( 6509 663 ) ( 6555 * ) + NEW met1 ( 6555 595 ) ( * 663 ) + NEW met1 ( 6555 595 ) ( 7291 * ) + NEW met1 ( 7291 595 ) ( * 697 ) + NEW met1 ( 7291 697 ) ( 7429 * ) + NEW met1 ( 7429 663 ) ( * 697 ) + NEW met1 ( 7429 663 ) ( 7475 * ) + NEW met1 ( 5543 629 ) ( * 663 ) + NEW met1 ( 5543 629 ) ( 5589 * ) + NEW met1 ( 5589 595 ) ( * 629 ) + NEW met1 ( 4577 595 ) ( * 663 ) + NEW met1 ( 4577 595 ) ( 5589 * ) + NEW met1 ( 3611 629 ) ( * 663 ) + NEW met1 ( 3611 629 ) ( 3657 * ) + NEW met1 ( 3657 595 ) ( * 629 ) + NEW met1 ( 3657 595 ) ( 4577 * ) + NEW met1 ( 2645 595 ) ( * 663 ) + NEW met1 ( 2645 595 ) ( 3657 * ) + NEW met1 ( 1679 629 ) ( * 663 ) + NEW met1 ( 1679 629 ) ( 1725 * ) + NEW met1 ( 1725 595 ) ( * 629 ) + NEW met1 ( 1725 595 ) ( 2645 * ) + NEW met1 ( 713 595 ) ( 1725 * ) + NEW met1 ( 5589 595 ) ( 6555 * ) + NEW met2 ( 7751 629 ) ( * 765 ) + NEW met1 ( 7751 765 ) ( 8717 * ) + NEW met1 ( 7475 629 ) ( 7751 * ) + NEW li1 ( 713 663 ) L1M1_PR_MR + NEW li1 ( 7475 663 ) L1M1_PR_MR + NEW li1 ( 6509 663 ) L1M1_PR_MR + NEW li1 ( 5543 663 ) L1M1_PR_MR + NEW li1 ( 4577 663 ) L1M1_PR_MR + NEW li1 ( 3611 663 ) L1M1_PR_MR + NEW li1 ( 2645 663 ) L1M1_PR_MR + NEW li1 ( 1679 663 ) L1M1_PR_MR + NEW met1 ( 7751 629 ) M1M2_PR + NEW met1 ( 7751 765 ) M1M2_PR + NEW li1 ( 8717 765 ) L1M1_PR_MR ; - storage_2_0_0.we ( storage_2_0_0.gcand X ) ( storage_2_0_0.cg GATE ) + USE SIGNAL - + ROUTED met1 ( 7613 595 ) ( 8257 * ) - NEW li1 ( 7613 595 ) L1M1_PR_MR - NEW li1 ( 8257 595 ) L1M1_PR_MR ; + + ROUTED met1 ( 7981 595 ) ( 8625 * ) + NEW li1 ( 7981 595 ) L1M1_PR_MR + NEW li1 ( 8625 595 ) L1M1_PR_MR ; - storage_3_0_0.bit0.storage ( storage_3_0_0.bit0.obuf0 A ) ( storage_3_0_0.bit0.bit Q ) + USE SIGNAL - + ROUTED met1 ( 529 969 ) ( 575 * ) - NEW li1 ( 575 969 ) L1M1_PR_MR - NEW li1 ( 529 969 ) L1M1_PR_MR ; + + ROUTED met1 ( 575 935 ) ( 621 * ) + NEW met1 ( 575 901 ) ( * 935 ) + NEW li1 ( 621 935 ) L1M1_PR_MR + NEW li1 ( 575 901 ) L1M1_PR_MR ; - storage_3_0_0.bit1.storage ( storage_3_0_0.bit1.obuf0 A ) ( storage_3_0_0.bit1.bit Q ) + USE SIGNAL - + ROUTED met1 ( 1449 969 ) ( 1495 * ) - NEW li1 ( 1495 969 ) L1M1_PR_MR - NEW li1 ( 1449 969 ) L1M1_PR_MR ; + + ROUTED met1 ( 1541 935 ) ( 1587 * ) + NEW met1 ( 1541 901 ) ( * 935 ) + NEW li1 ( 1587 935 ) L1M1_PR_MR + NEW li1 ( 1541 901 ) L1M1_PR_MR ; - storage_3_0_0.bit2.storage ( storage_3_0_0.bit2.obuf0 A ) ( storage_3_0_0.bit2.bit Q ) + USE SIGNAL - + ROUTED met1 ( 2369 969 ) ( 2415 * ) - NEW li1 ( 2415 969 ) L1M1_PR_MR - NEW li1 ( 2369 969 ) L1M1_PR_MR ; + + ROUTED met1 ( 2507 935 ) ( 2553 * ) + NEW met1 ( 2507 901 ) ( * 935 ) + NEW li1 ( 2553 935 ) L1M1_PR_MR + NEW li1 ( 2507 901 ) L1M1_PR_MR ; - storage_3_0_0.bit3.storage ( storage_3_0_0.bit3.obuf0 A ) ( storage_3_0_0.bit3.bit Q ) + USE SIGNAL - + ROUTED met1 ( 3289 969 ) ( 3335 * ) - NEW li1 ( 3335 969 ) L1M1_PR_MR - NEW li1 ( 3289 969 ) L1M1_PR_MR ; + + ROUTED met1 ( 3473 935 ) ( 3519 * ) + NEW met1 ( 3473 901 ) ( * 935 ) + NEW li1 ( 3519 935 ) L1M1_PR_MR + NEW li1 ( 3473 901 ) L1M1_PR_MR ; - storage_3_0_0.bit4.storage ( storage_3_0_0.bit4.obuf0 A ) ( storage_3_0_0.bit4.bit Q ) + USE SIGNAL - + ROUTED met1 ( 4209 969 ) ( 4255 * ) - NEW li1 ( 4255 969 ) L1M1_PR_MR - NEW li1 ( 4209 969 ) L1M1_PR_MR ; + + ROUTED met1 ( 4439 935 ) ( 4485 * ) + NEW met1 ( 4439 901 ) ( * 935 ) + NEW li1 ( 4485 935 ) L1M1_PR_MR + NEW li1 ( 4439 901 ) L1M1_PR_MR ; - storage_3_0_0.bit5.storage ( storage_3_0_0.bit5.obuf0 A ) ( storage_3_0_0.bit5.bit Q ) + USE SIGNAL - + ROUTED met1 ( 5129 969 ) ( 5175 * ) - NEW li1 ( 5175 969 ) L1M1_PR_MR - NEW li1 ( 5129 969 ) L1M1_PR_MR ; + + ROUTED met1 ( 5405 935 ) ( 5451 * ) + NEW met1 ( 5405 901 ) ( * 935 ) + NEW li1 ( 5451 935 ) L1M1_PR_MR + NEW li1 ( 5405 901 ) L1M1_PR_MR ; - storage_3_0_0.bit6.storage ( storage_3_0_0.bit6.obuf0 A ) ( storage_3_0_0.bit6.bit Q ) + USE SIGNAL - + ROUTED met1 ( 6049 969 ) ( 6095 * ) - NEW li1 ( 6095 969 ) L1M1_PR_MR - NEW li1 ( 6049 969 ) L1M1_PR_MR ; + + ROUTED met1 ( 6371 935 ) ( 6417 * ) + NEW met1 ( 6371 901 ) ( * 935 ) + NEW li1 ( 6417 935 ) L1M1_PR_MR + NEW li1 ( 6371 901 ) L1M1_PR_MR ; - storage_3_0_0.bit7.storage ( storage_3_0_0.bit7.obuf0 A ) ( storage_3_0_0.bit7.bit Q ) + USE SIGNAL - + ROUTED met1 ( 6969 969 ) ( 7015 * ) - NEW li1 ( 7015 969 ) L1M1_PR_MR - NEW li1 ( 6969 969 ) L1M1_PR_MR ; - - storage_3_0_0.gclock ( storage_3_0_0.cg GCLK ) ( storage_3_0_0.bit7.bit SLEEP_B ) ( storage_3_0_0.bit6.bit SLEEP_B ) ( storage_3_0_0.bit5.bit SLEEP_B ) ( storage_3_0_0.bit4.bit SLEEP_B ) ( storage_3_0_0.bit3.bit SLEEP_B ) ( storage_3_0_0.bit2.bit SLEEP_B ) - ( storage_3_0_0.bit1.bit SLEEP_B ) ( storage_3_0_0.bit0.bit SLEEP_B ) + USE SIGNAL - + ROUTED met1 ( 6509 935 ) ( 8027 * ) - NEW met1 ( 6509 901 ) ( * 935 ) - NEW met1 ( 5589 901 ) ( * 935 ) - NEW met1 ( 4669 901 ) ( * 935 ) - NEW met1 ( 4669 901 ) ( 5589 * ) - NEW met1 ( 3749 901 ) ( * 935 ) - NEW met1 ( 3749 901 ) ( 4669 * ) - NEW met1 ( 5589 901 ) ( 6509 * ) - NEW met1 ( 621 969 ) ( 989 * ) - NEW met1 ( 621 935 ) ( * 969 ) - NEW met1 ( 69 935 ) ( 621 * ) - NEW met1 ( 1909 901 ) ( * 935 ) - NEW met1 ( 989 901 ) ( 1909 * ) - NEW met2 ( 989 901 ) ( * 969 ) - NEW met1 ( 1909 935 ) ( 2829 * ) - NEW met1 ( 2829 901 ) ( * 935 ) - NEW met1 ( 2829 901 ) ( 3749 * ) - NEW li1 ( 6509 935 ) L1M1_PR_MR - NEW li1 ( 8027 935 ) L1M1_PR_MR - NEW li1 ( 5589 935 ) L1M1_PR_MR - NEW li1 ( 4669 935 ) L1M1_PR_MR - NEW li1 ( 3749 935 ) L1M1_PR_MR - NEW li1 ( 989 969 ) L1M1_PR_MR - NEW li1 ( 69 935 ) L1M1_PR_MR - NEW li1 ( 1909 935 ) L1M1_PR_MR - NEW met1 ( 989 901 ) M1M2_PR - NEW met1 ( 989 969 ) M1M2_PR - NEW li1 ( 2829 935 ) L1M1_PR_MR ; + + ROUTED met1 ( 7337 935 ) ( 7383 * ) + NEW met1 ( 7337 901 ) ( * 935 ) + NEW li1 ( 7383 935 ) L1M1_PR_MR + NEW li1 ( 7337 901 ) L1M1_PR_MR ; + - storage_3_0_0.gclock ( storage_3_0_0.cg GCLK ) ( storage_3_0_0.bit7.bit GATE ) ( storage_3_0_0.bit6.bit GATE ) ( storage_3_0_0.bit5.bit GATE ) ( storage_3_0_0.bit4.bit GATE ) ( storage_3_0_0.bit3.bit GATE ) ( storage_3_0_0.bit2.bit GATE ) + ( storage_3_0_0.bit1.bit GATE ) ( storage_3_0_0.bit0.bit GATE ) + USE SIGNAL + + ROUTED met1 ( 1035 969 ) ( * 1003 ) + NEW met1 ( 69 1003 ) ( 1035 * ) + NEW met1 ( 69 969 ) ( * 1003 ) + NEW met1 ( 2001 969 ) ( * 1003 ) + NEW met1 ( 2967 969 ) ( * 1003 ) + NEW met1 ( 2001 1003 ) ( 2967 * ) + NEW met1 ( 3933 969 ) ( * 1003 ) + NEW met1 ( 2967 1003 ) ( 3933 * ) + NEW met1 ( 1035 1003 ) ( 2001 * ) + NEW met1 ( 4899 969 ) ( * 1003 ) + NEW met1 ( 5681 935 ) ( 5865 * ) + NEW met2 ( 5681 935 ) ( * 1003 ) + NEW met1 ( 4899 1003 ) ( 5681 * ) + NEW met1 ( 6831 867 ) ( * 935 ) + NEW met1 ( 5865 867 ) ( 6831 * ) + NEW met1 ( 5865 867 ) ( * 935 ) + NEW met1 ( 3933 1003 ) ( 4899 * ) + NEW met1 ( 6831 867 ) ( 8395 * ) + NEW li1 ( 1035 969 ) L1M1_PR_MR + NEW li1 ( 69 969 ) L1M1_PR_MR + NEW li1 ( 2001 969 ) L1M1_PR_MR + NEW li1 ( 2967 969 ) L1M1_PR_MR + NEW li1 ( 3933 969 ) L1M1_PR_MR + NEW li1 ( 4899 969 ) L1M1_PR_MR + NEW li1 ( 5865 935 ) L1M1_PR_MR + NEW met1 ( 5681 935 ) M1M2_PR + NEW met1 ( 5681 1003 ) M1M2_PR + NEW li1 ( 6831 935 ) L1M1_PR_MR + NEW li1 ( 8395 867 ) L1M1_PR_MR ; - storage_3_0_0.select0_b ( storage_3_0_0.select_inv_0 Y ) ( storage_3_0_0.bit7.obuf0 TE_B ) ( storage_3_0_0.bit6.obuf0 TE_B ) ( storage_3_0_0.bit5.obuf0 TE_B ) ( storage_3_0_0.bit4.obuf0 TE_B ) ( storage_3_0_0.bit3.obuf0 TE_B ) ( storage_3_0_0.bit2.obuf0 TE_B ) ( storage_3_0_0.bit1.obuf0 TE_B ) ( storage_3_0_0.bit0.obuf0 TE_B ) + USE SIGNAL - + ROUTED met1 ( 7107 969 ) ( * 1003 ) - NEW met1 ( 6785 969 ) ( * 1003 ) - NEW met1 ( 6785 1003 ) ( 7107 * ) - NEW met1 ( 7107 1003 ) ( 8349 * ) - NEW met1 ( 4163 935 ) ( 4347 * ) - NEW met1 ( 4163 935 ) ( * 969 ) - NEW met1 ( 5083 935 ) ( 5267 * ) - NEW met1 ( 5083 935 ) ( * 969 ) - NEW met1 ( 4347 969 ) ( 5083 * ) - NEW met1 ( 4347 935 ) ( * 969 ) - NEW met1 ( 6003 935 ) ( 6187 * ) - NEW met1 ( 6003 935 ) ( * 969 ) - NEW met1 ( 5267 969 ) ( 6003 * ) - NEW met1 ( 5267 935 ) ( * 969 ) - NEW met1 ( 6187 935 ) ( * 969 ) - NEW met1 ( 6187 969 ) ( 6785 * ) - NEW met1 ( 1587 969 ) ( * 1003 ) - NEW met1 ( 1311 1003 ) ( 1587 * ) - NEW met1 ( 1311 935 ) ( * 1003 ) - NEW met1 ( 667 935 ) ( 1311 * ) - NEW met1 ( 2507 969 ) ( * 1003 ) - NEW met1 ( 2323 1003 ) ( 2507 * ) - NEW met1 ( 2323 969 ) ( * 1003 ) - NEW met1 ( 1587 969 ) ( 2323 * ) - NEW met1 ( 3243 935 ) ( 3427 * ) - NEW met1 ( 3243 935 ) ( * 969 ) - NEW met1 ( 2507 969 ) ( 3243 * ) - NEW met1 ( 3427 935 ) ( * 969 ) - NEW met1 ( 3427 969 ) ( 4163 * ) - NEW li1 ( 8349 1003 ) L1M1_PR_MR - NEW li1 ( 7107 969 ) L1M1_PR_MR - NEW li1 ( 4347 935 ) L1M1_PR_MR - NEW li1 ( 5267 935 ) L1M1_PR_MR - NEW li1 ( 6187 935 ) L1M1_PR_MR - NEW li1 ( 1587 969 ) L1M1_PR_MR - NEW li1 ( 667 935 ) L1M1_PR_MR - NEW li1 ( 2507 969 ) L1M1_PR_MR - NEW li1 ( 3427 935 ) L1M1_PR_MR ; + + ROUTED met1 ( 713 867 ) ( * 935 ) + NEW met1 ( 7475 901 ) ( * 935 ) + NEW met1 ( 7475 935 ) ( * 1003 ) + NEW met1 ( 3611 867 ) ( * 935 ) + NEW met1 ( 2645 867 ) ( * 935 ) + NEW met1 ( 2645 867 ) ( 3611 * ) + NEW met1 ( 1679 867 ) ( * 935 ) + NEW met1 ( 1679 867 ) ( 2645 * ) + NEW met1 ( 713 867 ) ( 1679 * ) + NEW met1 ( 4577 867 ) ( * 935 ) + NEW met1 ( 5543 867 ) ( * 935 ) + NEW met1 ( 4577 867 ) ( 5543 * ) + NEW met1 ( 6509 969 ) ( * 1003 ) + NEW met1 ( 5819 1003 ) ( 6509 * ) + NEW met2 ( 5819 901 ) ( * 1003 ) + NEW met1 ( 5543 901 ) ( 5819 * ) + NEW met1 ( 3611 867 ) ( 4577 * ) + NEW met1 ( 6509 1003 ) ( 7475 * ) + NEW met1 ( 7475 901 ) ( 8717 * ) + NEW li1 ( 713 935 ) L1M1_PR_MR + NEW li1 ( 7475 935 ) L1M1_PR_MR + NEW li1 ( 3611 935 ) L1M1_PR_MR + NEW li1 ( 2645 935 ) L1M1_PR_MR + NEW li1 ( 1679 935 ) L1M1_PR_MR + NEW li1 ( 4577 935 ) L1M1_PR_MR + NEW li1 ( 5543 935 ) L1M1_PR_MR + NEW li1 ( 6509 969 ) L1M1_PR_MR + NEW met1 ( 5819 1003 ) M1M2_PR + NEW met1 ( 5819 901 ) M1M2_PR + NEW li1 ( 8717 901 ) L1M1_PR_MR ; - storage_3_0_0.we ( storage_3_0_0.gcand X ) ( storage_3_0_0.cg GATE ) + USE SIGNAL - + ROUTED met1 ( 7613 1037 ) ( 8257 * ) - NEW li1 ( 7613 1037 ) L1M1_PR_MR - NEW li1 ( 8257 1037 ) L1M1_PR_MR ; + + ROUTED met1 ( 7981 1003 ) ( 8625 * ) + NEW li1 ( 7981 1003 ) L1M1_PR_MR + NEW li1 ( 8625 1003 ) L1M1_PR_MR ; - storage_4_0_0.bit0.storage ( storage_4_0_0.bit0.obuf0 A ) ( storage_4_0_0.bit0.bit Q ) + USE SIGNAL - + ROUTED met1 ( 529 1207 ) ( 575 * ) - NEW li1 ( 575 1207 ) L1M1_PR_MR - NEW li1 ( 529 1207 ) L1M1_PR_MR ; + + ROUTED met1 ( 621 1241 ) ( * 1275 ) + NEW met1 ( 575 1275 ) ( 621 * ) + NEW li1 ( 621 1241 ) L1M1_PR_MR + NEW li1 ( 575 1275 ) L1M1_PR_MR ; - storage_4_0_0.bit1.storage ( storage_4_0_0.bit1.obuf0 A ) ( storage_4_0_0.bit1.bit Q ) + USE SIGNAL - + ROUTED met1 ( 1449 1207 ) ( 1495 * ) - NEW li1 ( 1495 1207 ) L1M1_PR_MR - NEW li1 ( 1449 1207 ) L1M1_PR_MR ; + + ROUTED met1 ( 1587 1241 ) ( * 1275 ) + NEW met1 ( 1541 1275 ) ( 1587 * ) + NEW li1 ( 1587 1241 ) L1M1_PR_MR + NEW li1 ( 1541 1275 ) L1M1_PR_MR ; - storage_4_0_0.bit2.storage ( storage_4_0_0.bit2.obuf0 A ) ( storage_4_0_0.bit2.bit Q ) + USE SIGNAL - + ROUTED met1 ( 2369 1207 ) ( 2415 * ) - NEW li1 ( 2415 1207 ) L1M1_PR_MR - NEW li1 ( 2369 1207 ) L1M1_PR_MR ; + + ROUTED met1 ( 2553 1241 ) ( * 1275 ) + NEW met1 ( 2507 1275 ) ( 2553 * ) + NEW li1 ( 2553 1241 ) L1M1_PR_MR + NEW li1 ( 2507 1275 ) L1M1_PR_MR ; - storage_4_0_0.bit3.storage ( storage_4_0_0.bit3.obuf0 A ) ( storage_4_0_0.bit3.bit Q ) + USE SIGNAL - + ROUTED met1 ( 3289 1207 ) ( 3335 * ) - NEW li1 ( 3335 1207 ) L1M1_PR_MR - NEW li1 ( 3289 1207 ) L1M1_PR_MR ; + + ROUTED met1 ( 3519 1241 ) ( * 1275 ) + NEW met1 ( 3473 1275 ) ( 3519 * ) + NEW li1 ( 3519 1241 ) L1M1_PR_MR + NEW li1 ( 3473 1275 ) L1M1_PR_MR ; - storage_4_0_0.bit4.storage ( storage_4_0_0.bit4.obuf0 A ) ( storage_4_0_0.bit4.bit Q ) + USE SIGNAL - + ROUTED met1 ( 4209 1207 ) ( 4255 * ) - NEW li1 ( 4255 1207 ) L1M1_PR_MR - NEW li1 ( 4209 1207 ) L1M1_PR_MR ; + + ROUTED met1 ( 4485 1241 ) ( * 1275 ) + NEW met1 ( 4439 1275 ) ( 4485 * ) + NEW li1 ( 4485 1241 ) L1M1_PR_MR + NEW li1 ( 4439 1275 ) L1M1_PR_MR ; - storage_4_0_0.bit5.storage ( storage_4_0_0.bit5.obuf0 A ) ( storage_4_0_0.bit5.bit Q ) + USE SIGNAL - + ROUTED met1 ( 5129 1207 ) ( 5175 * ) - NEW li1 ( 5175 1207 ) L1M1_PR_MR - NEW li1 ( 5129 1207 ) L1M1_PR_MR ; + + ROUTED met1 ( 5451 1241 ) ( * 1275 ) + NEW met1 ( 5405 1275 ) ( 5451 * ) + NEW li1 ( 5451 1241 ) L1M1_PR_MR + NEW li1 ( 5405 1275 ) L1M1_PR_MR ; - storage_4_0_0.bit6.storage ( storage_4_0_0.bit6.obuf0 A ) ( storage_4_0_0.bit6.bit Q ) + USE SIGNAL - + ROUTED met1 ( 6049 1207 ) ( 6095 * ) - NEW li1 ( 6095 1207 ) L1M1_PR_MR - NEW li1 ( 6049 1207 ) L1M1_PR_MR ; + + ROUTED met1 ( 6417 1241 ) ( * 1275 ) + NEW met1 ( 6371 1275 ) ( 6417 * ) + NEW li1 ( 6417 1241 ) L1M1_PR_MR + NEW li1 ( 6371 1275 ) L1M1_PR_MR ; - storage_4_0_0.bit7.storage ( storage_4_0_0.bit7.obuf0 A ) ( storage_4_0_0.bit7.bit Q ) + USE SIGNAL - + ROUTED met1 ( 6969 1207 ) ( 7015 * ) - NEW li1 ( 7015 1207 ) L1M1_PR_MR - NEW li1 ( 6969 1207 ) L1M1_PR_MR ; - - storage_4_0_0.gclock ( storage_4_0_0.cg GCLK ) ( storage_4_0_0.bit7.bit SLEEP_B ) ( storage_4_0_0.bit6.bit SLEEP_B ) ( storage_4_0_0.bit5.bit SLEEP_B ) ( storage_4_0_0.bit4.bit SLEEP_B ) ( storage_4_0_0.bit3.bit SLEEP_B ) ( storage_4_0_0.bit2.bit SLEEP_B ) - ( storage_4_0_0.bit1.bit SLEEP_B ) ( storage_4_0_0.bit0.bit SLEEP_B ) + USE SIGNAL - + ROUTED met1 ( 69 1241 ) ( 989 * ) - NEW met1 ( 6509 1241 ) ( 8027 * ) - NEW met1 ( 4669 1241 ) ( 5589 * ) - NEW met1 ( 3749 1241 ) ( 4669 * ) - NEW met1 ( 2829 1241 ) ( 3749 * ) - NEW met1 ( 1909 1241 ) ( 2829 * ) - NEW met1 ( 989 1241 ) ( 1909 * ) - NEW met1 ( 5589 1241 ) ( 6509 * ) - NEW li1 ( 989 1241 ) L1M1_PR_MR - NEW li1 ( 69 1241 ) L1M1_PR_MR - NEW li1 ( 6509 1241 ) L1M1_PR_MR - NEW li1 ( 8027 1241 ) L1M1_PR_MR - NEW li1 ( 5589 1241 ) L1M1_PR_MR - NEW li1 ( 4669 1241 ) L1M1_PR_MR - NEW li1 ( 3749 1241 ) L1M1_PR_MR - NEW li1 ( 2829 1241 ) L1M1_PR_MR - NEW li1 ( 1909 1241 ) L1M1_PR_MR ; + + ROUTED met1 ( 7383 1241 ) ( * 1275 ) + NEW met1 ( 7337 1275 ) ( 7383 * ) + NEW li1 ( 7383 1241 ) L1M1_PR_MR + NEW li1 ( 7337 1275 ) L1M1_PR_MR ; + - storage_4_0_0.gclock ( storage_4_0_0.cg GCLK ) ( storage_4_0_0.bit7.bit GATE ) ( storage_4_0_0.bit6.bit GATE ) ( storage_4_0_0.bit5.bit GATE ) ( storage_4_0_0.bit4.bit GATE ) ( storage_4_0_0.bit3.bit GATE ) ( storage_4_0_0.bit2.bit GATE ) + ( storage_4_0_0.bit1.bit GATE ) ( storage_4_0_0.bit0.bit GATE ) + USE SIGNAL + + ROUTED met1 ( 1035 1173 ) ( * 1207 ) + NEW met1 ( 69 1173 ) ( 1035 * ) + NEW met1 ( 69 1173 ) ( * 1207 ) + NEW met1 ( 6831 1173 ) ( * 1207 ) + NEW met1 ( 2001 1173 ) ( * 1207 ) + NEW met1 ( 2967 1173 ) ( * 1207 ) + NEW met1 ( 2001 1173 ) ( 2967 * ) + NEW met1 ( 3933 1173 ) ( * 1207 ) + NEW met1 ( 2967 1173 ) ( 3933 * ) + NEW met1 ( 4899 1173 ) ( * 1207 ) + NEW met1 ( 3933 1173 ) ( 4899 * ) + NEW met1 ( 5865 1173 ) ( * 1207 ) + NEW met1 ( 4899 1173 ) ( 5865 * ) + NEW met1 ( 1035 1173 ) ( 2001 * ) + NEW met1 ( 5865 1173 ) ( 6831 * ) + NEW met1 ( 7659 1173 ) ( * 1275 ) + NEW met1 ( 7659 1275 ) ( 8395 * ) + NEW met1 ( 6831 1173 ) ( 7659 * ) + NEW li1 ( 1035 1207 ) L1M1_PR_MR + NEW li1 ( 69 1207 ) L1M1_PR_MR + NEW li1 ( 6831 1207 ) L1M1_PR_MR + NEW li1 ( 2001 1207 ) L1M1_PR_MR + NEW li1 ( 2967 1207 ) L1M1_PR_MR + NEW li1 ( 3933 1207 ) L1M1_PR_MR + NEW li1 ( 4899 1207 ) L1M1_PR_MR + NEW li1 ( 5865 1207 ) L1M1_PR_MR + NEW li1 ( 8395 1275 ) L1M1_PR_MR ; - storage_4_0_0.select0_b ( storage_4_0_0.select_inv_0 Y ) ( storage_4_0_0.bit7.obuf0 TE_B ) ( storage_4_0_0.bit6.obuf0 TE_B ) ( storage_4_0_0.bit5.obuf0 TE_B ) ( storage_4_0_0.bit4.obuf0 TE_B ) ( storage_4_0_0.bit3.obuf0 TE_B ) ( storage_4_0_0.bit2.obuf0 TE_B ) ( storage_4_0_0.bit1.obuf0 TE_B ) ( storage_4_0_0.bit0.obuf0 TE_B ) + USE SIGNAL - + ROUTED met1 ( 7107 1173 ) ( * 1207 ) - NEW met1 ( 6785 1173 ) ( * 1207 ) - NEW met1 ( 6785 1173 ) ( 7107 * ) - NEW met1 ( 7107 1173 ) ( 8349 * ) - NEW met1 ( 667 1207 ) ( 1380 * ) - NEW met1 ( 1587 1173 ) ( * 1207 ) - NEW met1 ( 1380 1173 ) ( 1587 * ) - NEW met1 ( 1380 1173 ) ( * 1207 ) - NEW met1 ( 2507 1173 ) ( * 1207 ) - NEW met1 ( 2323 1173 ) ( 2507 * ) - NEW met1 ( 2323 1173 ) ( * 1207 ) - NEW met1 ( 1587 1207 ) ( 2323 * ) - NEW met1 ( 3427 1173 ) ( * 1207 ) - NEW met1 ( 3243 1173 ) ( 3427 * ) - NEW met1 ( 3243 1173 ) ( * 1207 ) - NEW met1 ( 2507 1207 ) ( 3243 * ) - NEW met1 ( 4347 1173 ) ( * 1207 ) - NEW met1 ( 4163 1173 ) ( 4347 * ) - NEW met1 ( 4163 1173 ) ( * 1207 ) - NEW met1 ( 3427 1207 ) ( 4163 * ) - NEW met1 ( 5267 1173 ) ( * 1207 ) - NEW met1 ( 5083 1173 ) ( 5267 * ) - NEW met1 ( 5083 1173 ) ( * 1207 ) - NEW met1 ( 4347 1207 ) ( 5083 * ) - NEW met1 ( 6187 1173 ) ( * 1207 ) - NEW met1 ( 6003 1173 ) ( 6187 * ) - NEW met1 ( 6003 1173 ) ( * 1207 ) - NEW met1 ( 5267 1207 ) ( 6003 * ) - NEW met1 ( 6187 1207 ) ( 6785 * ) - NEW li1 ( 667 1207 ) L1M1_PR_MR - NEW li1 ( 8349 1173 ) L1M1_PR_MR - NEW li1 ( 7107 1207 ) L1M1_PR_MR - NEW li1 ( 1587 1207 ) L1M1_PR_MR - NEW li1 ( 2507 1207 ) L1M1_PR_MR - NEW li1 ( 3427 1207 ) L1M1_PR_MR - NEW li1 ( 4347 1207 ) L1M1_PR_MR - NEW li1 ( 5267 1207 ) L1M1_PR_MR - NEW li1 ( 6187 1207 ) L1M1_PR_MR ; + + ROUTED met1 ( 713 1241 ) ( 989 * ) + NEW met1 ( 989 1241 ) ( * 1309 ) + NEW met1 ( 7475 1241 ) ( * 1275 ) + NEW met1 ( 6509 1241 ) ( 6785 * ) + NEW met1 ( 6785 1241 ) ( * 1309 ) + NEW met1 ( 6785 1309 ) ( 7475 * ) + NEW met1 ( 7475 1275 ) ( * 1309 ) + NEW met1 ( 6509 1241 ) ( * 1309 ) + NEW met1 ( 5543 1241 ) ( 5773 * ) + NEW met1 ( 5773 1241 ) ( * 1309 ) + NEW met1 ( 4577 1241 ) ( 4853 * ) + NEW met1 ( 4853 1241 ) ( * 1309 ) + NEW met1 ( 4853 1309 ) ( 5543 * ) + NEW met1 ( 5543 1241 ) ( * 1309 ) + NEW met1 ( 3611 1241 ) ( 3841 * ) + NEW met1 ( 3841 1241 ) ( * 1309 ) + NEW met1 ( 3841 1309 ) ( 4577 * ) + NEW met1 ( 4577 1241 ) ( * 1309 ) + NEW met1 ( 2645 1241 ) ( 2921 * ) + NEW met1 ( 2921 1241 ) ( * 1309 ) + NEW met1 ( 2921 1309 ) ( 3611 * ) + NEW met1 ( 3611 1241 ) ( * 1309 ) + NEW met1 ( 1679 1241 ) ( 1909 * ) + NEW met1 ( 1909 1241 ) ( * 1309 ) + NEW met1 ( 1909 1309 ) ( 2645 * ) + NEW met1 ( 2645 1241 ) ( * 1309 ) + NEW met1 ( 1679 1241 ) ( * 1309 ) + NEW met1 ( 989 1309 ) ( 1679 * ) + NEW met1 ( 5773 1309 ) ( 6509 * ) + NEW met1 ( 7475 1275 ) ( 7590 * ) + NEW met1 ( 7590 1275 ) ( * 1309 ) + NEW met1 ( 7590 1309 ) ( 8717 * ) + NEW li1 ( 713 1241 ) L1M1_PR_MR + NEW li1 ( 7475 1241 ) L1M1_PR_MR + NEW li1 ( 6509 1241 ) L1M1_PR_MR + NEW li1 ( 5543 1241 ) L1M1_PR_MR + NEW li1 ( 4577 1241 ) L1M1_PR_MR + NEW li1 ( 3611 1241 ) L1M1_PR_MR + NEW li1 ( 2645 1241 ) L1M1_PR_MR + NEW li1 ( 1679 1241 ) L1M1_PR_MR + NEW li1 ( 8717 1309 ) L1M1_PR_MR ; - storage_4_0_0.we ( storage_4_0_0.gcand X ) ( storage_4_0_0.cg GATE ) + USE SIGNAL - + ROUTED met1 ( 7613 1139 ) ( 8257 * ) - NEW li1 ( 7613 1139 ) L1M1_PR_MR - NEW li1 ( 8257 1139 ) L1M1_PR_MR ; + + ROUTED met1 ( 7981 1139 ) ( 8625 * ) + NEW li1 ( 7981 1139 ) L1M1_PR_MR + NEW li1 ( 8625 1139 ) L1M1_PR_MR ; - storage_5_0_0.bit0.storage ( storage_5_0_0.bit0.obuf0 A ) ( storage_5_0_0.bit0.bit Q ) + USE SIGNAL - + ROUTED met1 ( 529 1513 ) ( 575 * ) - NEW li1 ( 575 1513 ) L1M1_PR_MR - NEW li1 ( 529 1513 ) L1M1_PR_MR ; + + ROUTED met1 ( 575 1479 ) ( 621 * ) + NEW met1 ( 575 1445 ) ( * 1479 ) + NEW li1 ( 621 1479 ) L1M1_PR_MR + NEW li1 ( 575 1445 ) L1M1_PR_MR ; - storage_5_0_0.bit1.storage ( storage_5_0_0.bit1.obuf0 A ) ( storage_5_0_0.bit1.bit Q ) + USE SIGNAL - + ROUTED met1 ( 1449 1513 ) ( 1495 * ) - NEW li1 ( 1495 1513 ) L1M1_PR_MR - NEW li1 ( 1449 1513 ) L1M1_PR_MR ; + + ROUTED met1 ( 1541 1479 ) ( 1587 * ) + NEW met1 ( 1541 1445 ) ( * 1479 ) + NEW li1 ( 1587 1479 ) L1M1_PR_MR + NEW li1 ( 1541 1445 ) L1M1_PR_MR ; - storage_5_0_0.bit2.storage ( storage_5_0_0.bit2.obuf0 A ) ( storage_5_0_0.bit2.bit Q ) + USE SIGNAL - + ROUTED met1 ( 2369 1513 ) ( 2415 * ) - NEW li1 ( 2415 1513 ) L1M1_PR_MR - NEW li1 ( 2369 1513 ) L1M1_PR_MR ; + + ROUTED met1 ( 2507 1479 ) ( 2553 * ) + NEW met1 ( 2507 1445 ) ( * 1479 ) + NEW li1 ( 2553 1479 ) L1M1_PR_MR + NEW li1 ( 2507 1445 ) L1M1_PR_MR ; - storage_5_0_0.bit3.storage ( storage_5_0_0.bit3.obuf0 A ) ( storage_5_0_0.bit3.bit Q ) + USE SIGNAL - + ROUTED met1 ( 3289 1513 ) ( 3335 * ) - NEW li1 ( 3335 1513 ) L1M1_PR_MR - NEW li1 ( 3289 1513 ) L1M1_PR_MR ; + + ROUTED met1 ( 3473 1479 ) ( 3519 * ) + NEW met1 ( 3473 1445 ) ( * 1479 ) + NEW li1 ( 3519 1479 ) L1M1_PR_MR + NEW li1 ( 3473 1445 ) L1M1_PR_MR ; - storage_5_0_0.bit4.storage ( storage_5_0_0.bit4.obuf0 A ) ( storage_5_0_0.bit4.bit Q ) + USE SIGNAL - + ROUTED met1 ( 4209 1513 ) ( 4255 * ) - NEW li1 ( 4255 1513 ) L1M1_PR_MR - NEW li1 ( 4209 1513 ) L1M1_PR_MR ; + + ROUTED met1 ( 4439 1479 ) ( 4485 * ) + NEW met1 ( 4439 1445 ) ( * 1479 ) + NEW li1 ( 4485 1479 ) L1M1_PR_MR + NEW li1 ( 4439 1445 ) L1M1_PR_MR ; - storage_5_0_0.bit5.storage ( storage_5_0_0.bit5.obuf0 A ) ( storage_5_0_0.bit5.bit Q ) + USE SIGNAL - + ROUTED met1 ( 5129 1513 ) ( 5175 * ) - NEW li1 ( 5175 1513 ) L1M1_PR_MR - NEW li1 ( 5129 1513 ) L1M1_PR_MR ; + + ROUTED met1 ( 5405 1479 ) ( 5451 * ) + NEW met1 ( 5405 1445 ) ( * 1479 ) + NEW li1 ( 5451 1479 ) L1M1_PR_MR + NEW li1 ( 5405 1445 ) L1M1_PR_MR ; - storage_5_0_0.bit6.storage ( storage_5_0_0.bit6.obuf0 A ) ( storage_5_0_0.bit6.bit Q ) + USE SIGNAL - + ROUTED met1 ( 6049 1513 ) ( 6095 * ) - NEW li1 ( 6095 1513 ) L1M1_PR_MR - NEW li1 ( 6049 1513 ) L1M1_PR_MR ; + + ROUTED met1 ( 6371 1479 ) ( 6417 * ) + NEW met1 ( 6371 1445 ) ( * 1479 ) + NEW li1 ( 6417 1479 ) L1M1_PR_MR + NEW li1 ( 6371 1445 ) L1M1_PR_MR ; - storage_5_0_0.bit7.storage ( storage_5_0_0.bit7.obuf0 A ) ( storage_5_0_0.bit7.bit Q ) + USE SIGNAL - + ROUTED met1 ( 6969 1513 ) ( 7015 * ) - NEW li1 ( 7015 1513 ) L1M1_PR_MR - NEW li1 ( 6969 1513 ) L1M1_PR_MR ; - - storage_5_0_0.gclock ( storage_5_0_0.cg GCLK ) ( storage_5_0_0.bit7.bit SLEEP_B ) ( storage_5_0_0.bit6.bit SLEEP_B ) ( storage_5_0_0.bit5.bit SLEEP_B ) ( storage_5_0_0.bit4.bit SLEEP_B ) ( storage_5_0_0.bit3.bit SLEEP_B ) ( storage_5_0_0.bit2.bit SLEEP_B ) - ( storage_5_0_0.bit1.bit SLEEP_B ) ( storage_5_0_0.bit0.bit SLEEP_B ) + USE SIGNAL - + ROUTED met1 ( 6509 1445 ) ( * 1479 ) - NEW met1 ( 6509 1445 ) ( 8027 * ) - NEW met1 ( 5589 1445 ) ( * 1479 ) - NEW met1 ( 4669 1445 ) ( * 1479 ) - NEW met1 ( 4669 1445 ) ( 5589 * ) - NEW met1 ( 3749 1445 ) ( * 1479 ) - NEW met1 ( 3749 1445 ) ( 4669 * ) - NEW met1 ( 5589 1445 ) ( 6509 * ) - NEW met1 ( 621 1513 ) ( 989 * ) - NEW met1 ( 621 1479 ) ( * 1513 ) - NEW met1 ( 69 1479 ) ( 621 * ) - NEW met1 ( 1909 1445 ) ( * 1479 ) - NEW met1 ( 989 1445 ) ( 1909 * ) - NEW met2 ( 989 1445 ) ( * 1513 ) - NEW met1 ( 1909 1479 ) ( 2829 * ) - NEW met1 ( 2829 1445 ) ( * 1479 ) - NEW met1 ( 2829 1445 ) ( 3749 * ) - NEW li1 ( 6509 1479 ) L1M1_PR_MR - NEW li1 ( 8027 1445 ) L1M1_PR_MR - NEW li1 ( 5589 1479 ) L1M1_PR_MR - NEW li1 ( 4669 1479 ) L1M1_PR_MR - NEW li1 ( 3749 1479 ) L1M1_PR_MR - NEW li1 ( 989 1513 ) L1M1_PR_MR - NEW li1 ( 69 1479 ) L1M1_PR_MR - NEW li1 ( 1909 1479 ) L1M1_PR_MR - NEW met1 ( 989 1445 ) M1M2_PR - NEW met1 ( 989 1513 ) M1M2_PR - NEW li1 ( 2829 1479 ) L1M1_PR_MR ; + + ROUTED met1 ( 7337 1479 ) ( 7383 * ) + NEW met1 ( 7337 1445 ) ( * 1479 ) + NEW li1 ( 7383 1479 ) L1M1_PR_MR + NEW li1 ( 7337 1445 ) L1M1_PR_MR ; + - storage_5_0_0.gclock ( storage_5_0_0.cg GCLK ) ( storage_5_0_0.bit7.bit GATE ) ( storage_5_0_0.bit6.bit GATE ) ( storage_5_0_0.bit5.bit GATE ) ( storage_5_0_0.bit4.bit GATE ) ( storage_5_0_0.bit3.bit GATE ) ( storage_5_0_0.bit2.bit GATE ) + ( storage_5_0_0.bit1.bit GATE ) ( storage_5_0_0.bit0.bit GATE ) + USE SIGNAL + + ROUTED met1 ( 1035 1513 ) ( * 1547 ) + NEW met1 ( 69 1547 ) ( 1035 * ) + NEW met1 ( 69 1513 ) ( * 1547 ) + NEW met1 ( 2001 1513 ) ( * 1547 ) + NEW met1 ( 2967 1513 ) ( * 1547 ) + NEW met1 ( 2001 1547 ) ( 2967 * ) + NEW met1 ( 3933 1513 ) ( * 1547 ) + NEW met1 ( 2967 1547 ) ( 3933 * ) + NEW met1 ( 1035 1547 ) ( 2001 * ) + NEW met1 ( 4899 1513 ) ( * 1547 ) + NEW met1 ( 5681 1479 ) ( 5865 * ) + NEW met2 ( 5681 1479 ) ( * 1547 ) + NEW met1 ( 4899 1547 ) ( 5681 * ) + NEW met1 ( 6831 1411 ) ( * 1479 ) + NEW met1 ( 5865 1411 ) ( 6831 * ) + NEW met1 ( 5865 1411 ) ( * 1479 ) + NEW met1 ( 3933 1547 ) ( 4899 * ) + NEW met1 ( 6831 1411 ) ( 8395 * ) + NEW li1 ( 1035 1513 ) L1M1_PR_MR + NEW li1 ( 69 1513 ) L1M1_PR_MR + NEW li1 ( 2001 1513 ) L1M1_PR_MR + NEW li1 ( 2967 1513 ) L1M1_PR_MR + NEW li1 ( 3933 1513 ) L1M1_PR_MR + NEW li1 ( 4899 1513 ) L1M1_PR_MR + NEW li1 ( 5865 1479 ) L1M1_PR_MR + NEW met1 ( 5681 1479 ) M1M2_PR + NEW met1 ( 5681 1547 ) M1M2_PR + NEW li1 ( 6831 1479 ) L1M1_PR_MR + NEW li1 ( 8395 1411 ) L1M1_PR_MR ; - storage_5_0_0.select0_b ( storage_5_0_0.select_inv_0 Y ) ( storage_5_0_0.bit7.obuf0 TE_B ) ( storage_5_0_0.bit6.obuf0 TE_B ) ( storage_5_0_0.bit5.obuf0 TE_B ) ( storage_5_0_0.bit4.obuf0 TE_B ) ( storage_5_0_0.bit3.obuf0 TE_B ) ( storage_5_0_0.bit2.obuf0 TE_B ) ( storage_5_0_0.bit1.obuf0 TE_B ) ( storage_5_0_0.bit0.obuf0 TE_B ) + USE SIGNAL - + ROUTED met1 ( 7107 1513 ) ( * 1547 ) - NEW met1 ( 7107 1547 ) ( 8349 * ) - NEW met1 ( 6785 1513 ) ( * 1547 ) - NEW met1 ( 6785 1547 ) ( 7107 * ) - NEW met1 ( 4163 1479 ) ( 4347 * ) - NEW met1 ( 4163 1479 ) ( * 1513 ) - NEW met1 ( 5083 1479 ) ( 5267 * ) - NEW met1 ( 5083 1479 ) ( * 1513 ) - NEW met1 ( 4347 1513 ) ( 5083 * ) - NEW met1 ( 4347 1479 ) ( * 1513 ) - NEW met1 ( 6003 1479 ) ( 6187 * ) - NEW met1 ( 6003 1479 ) ( * 1513 ) - NEW met1 ( 5267 1513 ) ( 6003 * ) - NEW met1 ( 5267 1479 ) ( * 1513 ) - NEW met1 ( 6187 1479 ) ( * 1513 ) - NEW met1 ( 6187 1513 ) ( 6785 * ) - NEW met1 ( 1587 1513 ) ( * 1547 ) - NEW met1 ( 1311 1547 ) ( 1587 * ) - NEW met1 ( 1311 1479 ) ( * 1547 ) - NEW met1 ( 667 1479 ) ( 1311 * ) - NEW met1 ( 2507 1513 ) ( * 1547 ) - NEW met1 ( 2323 1547 ) ( 2507 * ) - NEW met1 ( 2323 1513 ) ( * 1547 ) - NEW met1 ( 1587 1513 ) ( 2323 * ) - NEW met1 ( 3243 1479 ) ( 3427 * ) - NEW met1 ( 3243 1479 ) ( * 1513 ) - NEW met1 ( 2507 1513 ) ( 3243 * ) - NEW met1 ( 3427 1479 ) ( * 1513 ) - NEW met1 ( 3427 1513 ) ( 4163 * ) - NEW li1 ( 7107 1513 ) L1M1_PR_MR - NEW li1 ( 8349 1547 ) L1M1_PR_MR - NEW li1 ( 4347 1479 ) L1M1_PR_MR - NEW li1 ( 5267 1479 ) L1M1_PR_MR - NEW li1 ( 6187 1479 ) L1M1_PR_MR - NEW li1 ( 1587 1513 ) L1M1_PR_MR - NEW li1 ( 667 1479 ) L1M1_PR_MR - NEW li1 ( 2507 1513 ) L1M1_PR_MR - NEW li1 ( 3427 1479 ) L1M1_PR_MR ; + + ROUTED met1 ( 713 1411 ) ( * 1479 ) + NEW met1 ( 7475 1513 ) ( * 1547 ) + NEW met1 ( 3611 1411 ) ( * 1479 ) + NEW met1 ( 2645 1411 ) ( * 1479 ) + NEW met1 ( 2645 1411 ) ( 3611 * ) + NEW met1 ( 1679 1411 ) ( * 1479 ) + NEW met1 ( 1679 1411 ) ( 2645 * ) + NEW met1 ( 713 1411 ) ( 1679 * ) + NEW met1 ( 4577 1411 ) ( * 1479 ) + NEW met1 ( 5543 1411 ) ( * 1479 ) + NEW met1 ( 4577 1411 ) ( 5543 * ) + NEW met1 ( 6509 1513 ) ( * 1547 ) + NEW met1 ( 5819 1547 ) ( 6509 * ) + NEW met2 ( 5819 1445 ) ( * 1547 ) + NEW met1 ( 5543 1445 ) ( 5819 * ) + NEW met1 ( 3611 1411 ) ( 4577 * ) + NEW met1 ( 6509 1547 ) ( 7475 * ) + NEW met1 ( 7751 1547 ) ( * 1581 ) + NEW met1 ( 7751 1581 ) ( 7843 * ) + NEW met1 ( 7843 1547 ) ( * 1581 ) + NEW met1 ( 7843 1547 ) ( 8717 * ) + NEW met1 ( 7475 1547 ) ( 7751 * ) + NEW li1 ( 713 1479 ) L1M1_PR_MR + NEW li1 ( 7475 1513 ) L1M1_PR_MR + NEW li1 ( 3611 1479 ) L1M1_PR_MR + NEW li1 ( 2645 1479 ) L1M1_PR_MR + NEW li1 ( 1679 1479 ) L1M1_PR_MR + NEW li1 ( 4577 1479 ) L1M1_PR_MR + NEW li1 ( 5543 1479 ) L1M1_PR_MR + NEW li1 ( 6509 1513 ) L1M1_PR_MR + NEW met1 ( 5819 1547 ) M1M2_PR + NEW met1 ( 5819 1445 ) M1M2_PR + NEW li1 ( 8717 1547 ) L1M1_PR_MR ; - storage_5_0_0.we ( storage_5_0_0.gcand X ) ( storage_5_0_0.cg GATE ) + USE SIGNAL - + ROUTED met1 ( 7613 1581 ) ( 8257 * ) - NEW li1 ( 7613 1581 ) L1M1_PR_MR - NEW li1 ( 8257 1581 ) L1M1_PR_MR ; + + ROUTED met1 ( 7981 1581 ) ( 8625 * ) + NEW li1 ( 7981 1581 ) L1M1_PR_MR + NEW li1 ( 8625 1581 ) L1M1_PR_MR ; - storage_6_0_0.bit0.storage ( storage_6_0_0.bit0.obuf0 A ) ( storage_6_0_0.bit0.bit Q ) + USE SIGNAL - + ROUTED met1 ( 529 1751 ) ( 575 * ) - NEW li1 ( 575 1751 ) L1M1_PR_MR - NEW li1 ( 529 1751 ) L1M1_PR_MR ; + + ROUTED met1 ( 621 1785 ) ( * 1819 ) + NEW met1 ( 575 1819 ) ( 621 * ) + NEW li1 ( 621 1785 ) L1M1_PR_MR + NEW li1 ( 575 1819 ) L1M1_PR_MR ; - storage_6_0_0.bit1.storage ( storage_6_0_0.bit1.obuf0 A ) ( storage_6_0_0.bit1.bit Q ) + USE SIGNAL - + ROUTED met1 ( 1449 1751 ) ( 1495 * ) - NEW li1 ( 1495 1751 ) L1M1_PR_MR - NEW li1 ( 1449 1751 ) L1M1_PR_MR ; + + ROUTED met1 ( 1587 1785 ) ( * 1819 ) + NEW met1 ( 1541 1819 ) ( 1587 * ) + NEW li1 ( 1587 1785 ) L1M1_PR_MR + NEW li1 ( 1541 1819 ) L1M1_PR_MR ; - storage_6_0_0.bit2.storage ( storage_6_0_0.bit2.obuf0 A ) ( storage_6_0_0.bit2.bit Q ) + USE SIGNAL - + ROUTED met1 ( 2369 1751 ) ( 2415 * ) - NEW li1 ( 2415 1751 ) L1M1_PR_MR - NEW li1 ( 2369 1751 ) L1M1_PR_MR ; + + ROUTED met1 ( 2553 1785 ) ( * 1819 ) + NEW met1 ( 2507 1819 ) ( 2553 * ) + NEW li1 ( 2553 1785 ) L1M1_PR_MR + NEW li1 ( 2507 1819 ) L1M1_PR_MR ; - storage_6_0_0.bit3.storage ( storage_6_0_0.bit3.obuf0 A ) ( storage_6_0_0.bit3.bit Q ) + USE SIGNAL - + ROUTED met1 ( 3289 1751 ) ( 3335 * ) - NEW li1 ( 3335 1751 ) L1M1_PR_MR - NEW li1 ( 3289 1751 ) L1M1_PR_MR ; + + ROUTED met1 ( 3519 1785 ) ( * 1819 ) + NEW met1 ( 3473 1819 ) ( 3519 * ) + NEW li1 ( 3519 1785 ) L1M1_PR_MR + NEW li1 ( 3473 1819 ) L1M1_PR_MR ; - storage_6_0_0.bit4.storage ( storage_6_0_0.bit4.obuf0 A ) ( storage_6_0_0.bit4.bit Q ) + USE SIGNAL - + ROUTED met1 ( 4209 1751 ) ( 4255 * ) - NEW li1 ( 4255 1751 ) L1M1_PR_MR - NEW li1 ( 4209 1751 ) L1M1_PR_MR ; + + ROUTED met1 ( 4485 1785 ) ( * 1819 ) + NEW met1 ( 4439 1819 ) ( 4485 * ) + NEW li1 ( 4485 1785 ) L1M1_PR_MR + NEW li1 ( 4439 1819 ) L1M1_PR_MR ; - storage_6_0_0.bit5.storage ( storage_6_0_0.bit5.obuf0 A ) ( storage_6_0_0.bit5.bit Q ) + USE SIGNAL - + ROUTED met1 ( 5129 1751 ) ( 5175 * ) - NEW li1 ( 5175 1751 ) L1M1_PR_MR - NEW li1 ( 5129 1751 ) L1M1_PR_MR ; + + ROUTED met1 ( 5451 1785 ) ( * 1819 ) + NEW met1 ( 5405 1819 ) ( 5451 * ) + NEW li1 ( 5451 1785 ) L1M1_PR_MR + NEW li1 ( 5405 1819 ) L1M1_PR_MR ; - storage_6_0_0.bit6.storage ( storage_6_0_0.bit6.obuf0 A ) ( storage_6_0_0.bit6.bit Q ) + USE SIGNAL - + ROUTED met1 ( 6049 1751 ) ( 6095 * ) - NEW li1 ( 6095 1751 ) L1M1_PR_MR - NEW li1 ( 6049 1751 ) L1M1_PR_MR ; + + ROUTED met1 ( 6417 1785 ) ( * 1819 ) + NEW met1 ( 6371 1819 ) ( 6417 * ) + NEW li1 ( 6417 1785 ) L1M1_PR_MR + NEW li1 ( 6371 1819 ) L1M1_PR_MR ; - storage_6_0_0.bit7.storage ( storage_6_0_0.bit7.obuf0 A ) ( storage_6_0_0.bit7.bit Q ) + USE SIGNAL - + ROUTED met1 ( 6969 1751 ) ( 7015 * ) - NEW li1 ( 7015 1751 ) L1M1_PR_MR - NEW li1 ( 6969 1751 ) L1M1_PR_MR ; - - storage_6_0_0.gclock ( storage_6_0_0.cg GCLK ) ( storage_6_0_0.bit7.bit SLEEP_B ) ( storage_6_0_0.bit6.bit SLEEP_B ) ( storage_6_0_0.bit5.bit SLEEP_B ) ( storage_6_0_0.bit4.bit SLEEP_B ) ( storage_6_0_0.bit3.bit SLEEP_B ) ( storage_6_0_0.bit2.bit SLEEP_B ) - ( storage_6_0_0.bit1.bit SLEEP_B ) ( storage_6_0_0.bit0.bit SLEEP_B ) + USE SIGNAL - + ROUTED met1 ( 69 1785 ) ( 989 * ) - NEW met1 ( 6509 1785 ) ( * 1853 ) - NEW met1 ( 6509 1853 ) ( 8027 * ) - NEW met1 ( 4669 1785 ) ( 5589 * ) - NEW met1 ( 3749 1785 ) ( 4669 * ) - NEW met1 ( 2829 1785 ) ( 3749 * ) - NEW met1 ( 1909 1785 ) ( 2829 * ) - NEW met1 ( 989 1785 ) ( 1909 * ) - NEW met1 ( 5589 1785 ) ( 6509 * ) - NEW li1 ( 989 1785 ) L1M1_PR_MR - NEW li1 ( 69 1785 ) L1M1_PR_MR - NEW li1 ( 6509 1785 ) L1M1_PR_MR - NEW li1 ( 8027 1853 ) L1M1_PR_MR - NEW li1 ( 5589 1785 ) L1M1_PR_MR - NEW li1 ( 4669 1785 ) L1M1_PR_MR - NEW li1 ( 3749 1785 ) L1M1_PR_MR - NEW li1 ( 2829 1785 ) L1M1_PR_MR - NEW li1 ( 1909 1785 ) L1M1_PR_MR ; + + ROUTED met1 ( 7383 1785 ) ( * 1819 ) + NEW met1 ( 7337 1819 ) ( 7383 * ) + NEW li1 ( 7383 1785 ) L1M1_PR_MR + NEW li1 ( 7337 1819 ) L1M1_PR_MR ; + - storage_6_0_0.gclock ( storage_6_0_0.cg GCLK ) ( storage_6_0_0.bit7.bit GATE ) ( storage_6_0_0.bit6.bit GATE ) ( storage_6_0_0.bit5.bit GATE ) ( storage_6_0_0.bit4.bit GATE ) ( storage_6_0_0.bit3.bit GATE ) ( storage_6_0_0.bit2.bit GATE ) + ( storage_6_0_0.bit1.bit GATE ) ( storage_6_0_0.bit0.bit GATE ) + USE SIGNAL + + ROUTED met1 ( 1035 1717 ) ( * 1751 ) + NEW met1 ( 69 1717 ) ( 1035 * ) + NEW met1 ( 69 1717 ) ( * 1751 ) + NEW met1 ( 6831 1717 ) ( * 1751 ) + NEW met1 ( 2001 1717 ) ( * 1751 ) + NEW met1 ( 2967 1717 ) ( * 1751 ) + NEW met1 ( 2001 1717 ) ( 2967 * ) + NEW met1 ( 3933 1717 ) ( * 1751 ) + NEW met1 ( 2967 1717 ) ( 3933 * ) + NEW met1 ( 4899 1717 ) ( * 1751 ) + NEW met1 ( 3933 1717 ) ( 4899 * ) + NEW met1 ( 5865 1717 ) ( * 1751 ) + NEW met1 ( 4899 1717 ) ( 5865 * ) + NEW met1 ( 1035 1717 ) ( 2001 * ) + NEW met1 ( 5865 1717 ) ( 6831 * ) + NEW met1 ( 7659 1717 ) ( * 1819 ) + NEW met1 ( 7659 1819 ) ( 8395 * ) + NEW met1 ( 6831 1717 ) ( 7659 * ) + NEW li1 ( 1035 1751 ) L1M1_PR_MR + NEW li1 ( 69 1751 ) L1M1_PR_MR + NEW li1 ( 6831 1751 ) L1M1_PR_MR + NEW li1 ( 2001 1751 ) L1M1_PR_MR + NEW li1 ( 2967 1751 ) L1M1_PR_MR + NEW li1 ( 3933 1751 ) L1M1_PR_MR + NEW li1 ( 4899 1751 ) L1M1_PR_MR + NEW li1 ( 5865 1751 ) L1M1_PR_MR + NEW li1 ( 8395 1819 ) L1M1_PR_MR ; - storage_6_0_0.select0_b ( storage_6_0_0.select_inv_0 Y ) ( storage_6_0_0.bit7.obuf0 TE_B ) ( storage_6_0_0.bit6.obuf0 TE_B ) ( storage_6_0_0.bit5.obuf0 TE_B ) ( storage_6_0_0.bit4.obuf0 TE_B ) ( storage_6_0_0.bit3.obuf0 TE_B ) ( storage_6_0_0.bit2.obuf0 TE_B ) ( storage_6_0_0.bit1.obuf0 TE_B ) ( storage_6_0_0.bit0.obuf0 TE_B ) + USE SIGNAL - + ROUTED met1 ( 7107 1751 ) ( * 1819 ) - NEW met1 ( 7107 1819 ) ( 8349 * ) - NEW met1 ( 6785 1717 ) ( * 1751 ) - NEW met1 ( 6785 1717 ) ( 7107 * ) - NEW met1 ( 7107 1717 ) ( * 1751 ) - NEW met1 ( 667 1751 ) ( 1380 * ) - NEW met1 ( 1587 1717 ) ( * 1751 ) - NEW met1 ( 1380 1717 ) ( 1587 * ) - NEW met1 ( 1380 1717 ) ( * 1751 ) - NEW met1 ( 2507 1717 ) ( * 1751 ) - NEW met1 ( 2323 1717 ) ( 2507 * ) - NEW met1 ( 2323 1717 ) ( * 1751 ) - NEW met1 ( 1587 1751 ) ( 2323 * ) - NEW met1 ( 3427 1717 ) ( * 1751 ) - NEW met1 ( 3243 1717 ) ( 3427 * ) - NEW met1 ( 3243 1717 ) ( * 1751 ) - NEW met1 ( 2507 1751 ) ( 3243 * ) - NEW met1 ( 4347 1717 ) ( * 1751 ) - NEW met1 ( 4163 1717 ) ( 4347 * ) - NEW met1 ( 4163 1717 ) ( * 1751 ) - NEW met1 ( 3427 1751 ) ( 4163 * ) - NEW met1 ( 5267 1717 ) ( * 1751 ) - NEW met1 ( 5083 1717 ) ( 5267 * ) - NEW met1 ( 5083 1717 ) ( * 1751 ) - NEW met1 ( 4347 1751 ) ( 5083 * ) - NEW met1 ( 6187 1717 ) ( * 1751 ) - NEW met1 ( 6003 1717 ) ( 6187 * ) - NEW met1 ( 6003 1717 ) ( * 1751 ) - NEW met1 ( 5267 1751 ) ( 6003 * ) - NEW met1 ( 6187 1751 ) ( 6785 * ) - NEW li1 ( 667 1751 ) L1M1_PR_MR - NEW li1 ( 7107 1751 ) L1M1_PR_MR - NEW li1 ( 8349 1819 ) L1M1_PR_MR - NEW li1 ( 1587 1751 ) L1M1_PR_MR - NEW li1 ( 2507 1751 ) L1M1_PR_MR - NEW li1 ( 3427 1751 ) L1M1_PR_MR - NEW li1 ( 4347 1751 ) L1M1_PR_MR - NEW li1 ( 5267 1751 ) L1M1_PR_MR - NEW li1 ( 6187 1751 ) L1M1_PR_MR ; + + ROUTED met1 ( 713 1785 ) ( 989 * ) + NEW met1 ( 989 1785 ) ( * 1853 ) + NEW met1 ( 7475 1785 ) ( * 1819 ) + NEW met1 ( 6509 1785 ) ( 6785 * ) + NEW met1 ( 6785 1785 ) ( * 1853 ) + NEW met1 ( 6785 1853 ) ( 7475 * ) + NEW met1 ( 7475 1819 ) ( * 1853 ) + NEW met1 ( 6509 1785 ) ( * 1853 ) + NEW met1 ( 5543 1785 ) ( 5773 * ) + NEW met1 ( 5773 1785 ) ( * 1853 ) + NEW met1 ( 4577 1785 ) ( 4853 * ) + NEW met1 ( 4853 1785 ) ( * 1853 ) + NEW met1 ( 4853 1853 ) ( 5543 * ) + NEW met1 ( 5543 1785 ) ( * 1853 ) + NEW met1 ( 3611 1785 ) ( 3841 * ) + NEW met1 ( 3841 1785 ) ( * 1853 ) + NEW met1 ( 3841 1853 ) ( 4577 * ) + NEW met1 ( 4577 1785 ) ( * 1853 ) + NEW met1 ( 2645 1785 ) ( 2921 * ) + NEW met1 ( 2921 1785 ) ( * 1853 ) + NEW met1 ( 2921 1853 ) ( 3611 * ) + NEW met1 ( 3611 1785 ) ( * 1853 ) + NEW met1 ( 1679 1785 ) ( 1909 * ) + NEW met1 ( 1909 1785 ) ( * 1853 ) + NEW met1 ( 1909 1853 ) ( 2645 * ) + NEW met1 ( 2645 1785 ) ( * 1853 ) + NEW met1 ( 1679 1785 ) ( * 1853 ) + NEW met1 ( 989 1853 ) ( 1679 * ) + NEW met1 ( 5773 1853 ) ( 6509 * ) + NEW met1 ( 7475 1819 ) ( 7590 * ) + NEW met1 ( 7590 1819 ) ( * 1853 ) + NEW met1 ( 7590 1853 ) ( 8717 * ) + NEW li1 ( 713 1785 ) L1M1_PR_MR + NEW li1 ( 7475 1785 ) L1M1_PR_MR + NEW li1 ( 6509 1785 ) L1M1_PR_MR + NEW li1 ( 5543 1785 ) L1M1_PR_MR + NEW li1 ( 4577 1785 ) L1M1_PR_MR + NEW li1 ( 3611 1785 ) L1M1_PR_MR + NEW li1 ( 2645 1785 ) L1M1_PR_MR + NEW li1 ( 1679 1785 ) L1M1_PR_MR + NEW li1 ( 8717 1853 ) L1M1_PR_MR ; - storage_6_0_0.we ( storage_6_0_0.gcand X ) ( storage_6_0_0.cg GATE ) + USE SIGNAL - + ROUTED met1 ( 7613 1683 ) ( 8211 * ) - NEW met1 ( 8211 1683 ) ( * 1751 ) - NEW met1 ( 8211 1751 ) ( 8257 * ) - NEW li1 ( 7613 1683 ) L1M1_PR_MR - NEW li1 ( 8257 1751 ) L1M1_PR_MR ; + + ROUTED met1 ( 7981 1683 ) ( 8625 * ) + NEW li1 ( 7981 1683 ) L1M1_PR_MR + NEW li1 ( 8625 1683 ) L1M1_PR_MR ; - storage_7_0_0.bit0.storage ( storage_7_0_0.bit0.obuf0 A ) ( storage_7_0_0.bit0.bit Q ) + USE SIGNAL - + ROUTED met1 ( 529 2023 ) ( 575 * ) - NEW met1 ( 529 1989 ) ( * 2023 ) - NEW li1 ( 575 2023 ) L1M1_PR_MR - NEW li1 ( 529 1989 ) L1M1_PR_MR ; + + ROUTED met1 ( 575 2023 ) ( 621 * ) + NEW met1 ( 575 1989 ) ( * 2023 ) + NEW li1 ( 621 2023 ) L1M1_PR_MR + NEW li1 ( 575 1989 ) L1M1_PR_MR ; - storage_7_0_0.bit1.storage ( storage_7_0_0.bit1.obuf0 A ) ( storage_7_0_0.bit1.bit Q ) + USE SIGNAL - + ROUTED met1 ( 1449 2057 ) ( 1495 * ) - NEW li1 ( 1495 2057 ) L1M1_PR_MR - NEW li1 ( 1449 2057 ) L1M1_PR_MR ; + + ROUTED met1 ( 1541 2023 ) ( 1587 * ) + NEW met1 ( 1541 1989 ) ( * 2023 ) + NEW li1 ( 1587 2023 ) L1M1_PR_MR + NEW li1 ( 1541 1989 ) L1M1_PR_MR ; - storage_7_0_0.bit2.storage ( storage_7_0_0.bit2.obuf0 A ) ( storage_7_0_0.bit2.bit Q ) + USE SIGNAL - + ROUTED met1 ( 2369 2023 ) ( 2415 * ) - NEW met1 ( 2369 1989 ) ( * 2023 ) - NEW li1 ( 2415 2023 ) L1M1_PR_MR - NEW li1 ( 2369 1989 ) L1M1_PR_MR ; + + ROUTED met1 ( 2507 2023 ) ( 2553 * ) + NEW met1 ( 2507 1989 ) ( * 2023 ) + NEW li1 ( 2553 2023 ) L1M1_PR_MR + NEW li1 ( 2507 1989 ) L1M1_PR_MR ; - storage_7_0_0.bit3.storage ( storage_7_0_0.bit3.obuf0 A ) ( storage_7_0_0.bit3.bit Q ) + USE SIGNAL - + ROUTED met1 ( 3289 2023 ) ( 3335 * ) - NEW met1 ( 3289 1989 ) ( * 2023 ) - NEW li1 ( 3335 2023 ) L1M1_PR_MR - NEW li1 ( 3289 1989 ) L1M1_PR_MR ; + + ROUTED met1 ( 3473 2023 ) ( 3519 * ) + NEW met1 ( 3473 1989 ) ( * 2023 ) + NEW li1 ( 3519 2023 ) L1M1_PR_MR + NEW li1 ( 3473 1989 ) L1M1_PR_MR ; - storage_7_0_0.bit4.storage ( storage_7_0_0.bit4.obuf0 A ) ( storage_7_0_0.bit4.bit Q ) + USE SIGNAL - + ROUTED met1 ( 4209 2057 ) ( 4255 * ) - NEW li1 ( 4255 2057 ) L1M1_PR_MR - NEW li1 ( 4209 2057 ) L1M1_PR_MR ; + + ROUTED met1 ( 4439 2023 ) ( 4485 * ) + NEW met1 ( 4439 1989 ) ( * 2023 ) + NEW li1 ( 4485 2023 ) L1M1_PR_MR + NEW li1 ( 4439 1989 ) L1M1_PR_MR ; - storage_7_0_0.bit5.storage ( storage_7_0_0.bit5.obuf0 A ) ( storage_7_0_0.bit5.bit Q ) + USE SIGNAL - + ROUTED met1 ( 5129 2023 ) ( 5175 * ) - NEW met1 ( 5129 1989 ) ( * 2023 ) - NEW li1 ( 5175 2023 ) L1M1_PR_MR - NEW li1 ( 5129 1989 ) L1M1_PR_MR ; + + ROUTED met1 ( 5405 2023 ) ( 5451 * ) + NEW met1 ( 5405 1989 ) ( * 2023 ) + NEW li1 ( 5451 2023 ) L1M1_PR_MR + NEW li1 ( 5405 1989 ) L1M1_PR_MR ; - storage_7_0_0.bit6.storage ( storage_7_0_0.bit6.obuf0 A ) ( storage_7_0_0.bit6.bit Q ) + USE SIGNAL - + ROUTED met1 ( 6049 2057 ) ( 6095 * ) - NEW li1 ( 6095 2057 ) L1M1_PR_MR - NEW li1 ( 6049 2057 ) L1M1_PR_MR ; + + ROUTED met1 ( 6371 2023 ) ( 6417 * ) + NEW met1 ( 6371 1989 ) ( * 2023 ) + NEW li1 ( 6417 2023 ) L1M1_PR_MR + NEW li1 ( 6371 1989 ) L1M1_PR_MR ; - storage_7_0_0.bit7.storage ( storage_7_0_0.bit7.obuf0 A ) ( storage_7_0_0.bit7.bit Q ) + USE SIGNAL - + ROUTED met1 ( 6969 2057 ) ( 7015 * ) - NEW li1 ( 7015 2057 ) L1M1_PR_MR - NEW li1 ( 6969 2057 ) L1M1_PR_MR ; - - storage_7_0_0.gclock ( storage_7_0_0.cg GCLK ) ( storage_7_0_0.bit7.bit SLEEP_B ) ( storage_7_0_0.bit6.bit SLEEP_B ) ( storage_7_0_0.bit5.bit SLEEP_B ) ( storage_7_0_0.bit4.bit SLEEP_B ) ( storage_7_0_0.bit3.bit SLEEP_B ) ( storage_7_0_0.bit2.bit SLEEP_B ) - ( storage_7_0_0.bit1.bit SLEEP_B ) ( storage_7_0_0.bit0.bit SLEEP_B ) + USE SIGNAL - + ROUTED met1 ( 69 2057 ) ( 989 * ) - NEW met1 ( 989 2057 ) ( 1380 * ) - NEW met1 ( 2829 2057 ) ( 3749 * ) - NEW met1 ( 3749 2023 ) ( * 2057 ) - NEW met1 ( 1909 2057 ) ( 2829 * ) - NEW met1 ( 1380 2057 ) ( * 2091 ) - NEW met1 ( 1380 2091 ) ( 1909 * ) - NEW met1 ( 1909 2057 ) ( * 2091 ) - NEW met1 ( 6509 2023 ) ( 8027 * ) - NEW met2 ( 5589 1989 ) ( * 2057 ) - NEW met1 ( 5589 1989 ) ( 6509 * ) - NEW met1 ( 6509 1989 ) ( * 2023 ) - NEW met1 ( 4669 2057 ) ( 5589 * ) - NEW met1 ( 4301 2023 ) ( * 2057 ) - NEW met1 ( 4301 2057 ) ( 4669 * ) - NEW met1 ( 3749 2023 ) ( 4301 * ) - NEW li1 ( 989 2057 ) L1M1_PR_MR + + ROUTED met1 ( 7337 2023 ) ( 7383 * ) + NEW met1 ( 7337 1989 ) ( * 2023 ) + NEW li1 ( 7383 2023 ) L1M1_PR_MR + NEW li1 ( 7337 1989 ) L1M1_PR_MR ; + - storage_7_0_0.gclock ( storage_7_0_0.cg GCLK ) ( storage_7_0_0.bit7.bit GATE ) ( storage_7_0_0.bit6.bit GATE ) ( storage_7_0_0.bit5.bit GATE ) ( storage_7_0_0.bit4.bit GATE ) ( storage_7_0_0.bit3.bit GATE ) ( storage_7_0_0.bit2.bit GATE ) + ( storage_7_0_0.bit1.bit GATE ) ( storage_7_0_0.bit0.bit GATE ) + USE SIGNAL + + ROUTED met1 ( 1035 2057 ) ( * 2091 ) + NEW met1 ( 69 2091 ) ( 1035 * ) + NEW met1 ( 69 2057 ) ( * 2091 ) + NEW met1 ( 2001 2057 ) ( * 2091 ) + NEW met1 ( 2967 2057 ) ( * 2091 ) + NEW met1 ( 2001 2091 ) ( 2967 * ) + NEW met1 ( 3933 2057 ) ( * 2091 ) + NEW met1 ( 2967 2091 ) ( 3933 * ) + NEW met1 ( 1035 2091 ) ( 2001 * ) + NEW met1 ( 4899 2057 ) ( * 2091 ) + NEW met1 ( 5681 2023 ) ( 5865 * ) + NEW met2 ( 5681 2023 ) ( * 2091 ) + NEW met1 ( 4899 2091 ) ( 5681 * ) + NEW met1 ( 6831 1955 ) ( * 2023 ) + NEW met1 ( 5865 1955 ) ( 6831 * ) + NEW met1 ( 5865 1955 ) ( * 2023 ) + NEW met1 ( 3933 2091 ) ( 4899 * ) + NEW met1 ( 6831 1955 ) ( 8395 * ) + NEW li1 ( 1035 2057 ) L1M1_PR_MR NEW li1 ( 69 2057 ) L1M1_PR_MR - NEW li1 ( 3749 2023 ) L1M1_PR_MR - NEW li1 ( 2829 2057 ) L1M1_PR_MR - NEW li1 ( 1909 2057 ) L1M1_PR_MR - NEW li1 ( 6509 2023 ) L1M1_PR_MR - NEW li1 ( 8027 2023 ) L1M1_PR_MR - NEW li1 ( 5589 2057 ) L1M1_PR_MR - NEW met1 ( 5589 2057 ) M1M2_PR - NEW met1 ( 5589 1989 ) M1M2_PR - NEW li1 ( 4669 2057 ) L1M1_PR_MR ; + NEW li1 ( 2001 2057 ) L1M1_PR_MR + NEW li1 ( 2967 2057 ) L1M1_PR_MR + NEW li1 ( 3933 2057 ) L1M1_PR_MR + NEW li1 ( 4899 2057 ) L1M1_PR_MR + NEW li1 ( 5865 2023 ) L1M1_PR_MR + NEW met1 ( 5681 2023 ) M1M2_PR + NEW met1 ( 5681 2091 ) M1M2_PR + NEW li1 ( 6831 2023 ) L1M1_PR_MR + NEW li1 ( 8395 1955 ) L1M1_PR_MR ; - storage_7_0_0.select0_b ( storage_7_0_0.select_inv_0 Y ) ( storage_7_0_0.bit7.obuf0 TE_B ) ( storage_7_0_0.bit6.obuf0 TE_B ) ( storage_7_0_0.bit5.obuf0 TE_B ) ( storage_7_0_0.bit4.obuf0 TE_B ) ( storage_7_0_0.bit3.obuf0 TE_B ) ( storage_7_0_0.bit2.obuf0 TE_B ) ( storage_7_0_0.bit1.obuf0 TE_B ) ( storage_7_0_0.bit0.obuf0 TE_B ) + USE SIGNAL - + ROUTED met1 ( 2507 1955 ) ( * 2023 ) - NEW met1 ( 1587 1955 ) ( 2507 * ) - NEW met1 ( 1587 1955 ) ( * 2023 ) - NEW met1 ( 3427 1955 ) ( * 2023 ) - NEW met1 ( 2507 1955 ) ( 3427 * ) - NEW met1 ( 667 2023 ) ( 1587 * ) - NEW met1 ( 7107 2057 ) ( * 2091 ) - NEW met1 ( 6187 2023 ) ( 6279 * ) - NEW met1 ( 6279 2023 ) ( * 2057 ) - NEW met1 ( 6279 2057 ) ( 6785 * ) - NEW met1 ( 6785 2057 ) ( * 2091 ) - NEW met1 ( 6785 2091 ) ( 7107 * ) - NEW met1 ( 5267 2023 ) ( 6187 * ) - NEW met1 ( 4347 1955 ) ( * 2023 ) - NEW met1 ( 4347 1955 ) ( 5267 * ) - NEW met1 ( 5267 1955 ) ( * 2023 ) - NEW met1 ( 3427 1989 ) ( 4347 * ) - NEW met1 ( 7107 2091 ) ( 8349 * ) - NEW li1 ( 667 2023 ) L1M1_PR_MR - NEW li1 ( 8349 2091 ) L1M1_PR_MR - NEW li1 ( 1587 2023 ) L1M1_PR_MR - NEW li1 ( 2507 2023 ) L1M1_PR_MR - NEW li1 ( 3427 2023 ) L1M1_PR_MR - NEW li1 ( 7107 2057 ) L1M1_PR_MR - NEW li1 ( 6187 2023 ) L1M1_PR_MR - NEW li1 ( 5267 2023 ) L1M1_PR_MR - NEW li1 ( 4347 2023 ) L1M1_PR_MR ; + + ROUTED met1 ( 713 1955 ) ( * 2023 ) + NEW met1 ( 7475 1989 ) ( * 2023 ) + NEW met1 ( 7475 2023 ) ( * 2091 ) + NEW met1 ( 3611 1955 ) ( * 2023 ) + NEW met1 ( 2645 1955 ) ( * 2023 ) + NEW met1 ( 2645 1955 ) ( 3611 * ) + NEW met1 ( 1679 1955 ) ( * 2023 ) + NEW met1 ( 1679 1955 ) ( 2645 * ) + NEW met1 ( 713 1955 ) ( 1679 * ) + NEW met1 ( 4577 1955 ) ( * 2023 ) + NEW met1 ( 5543 1955 ) ( * 2023 ) + NEW met1 ( 4577 1955 ) ( 5543 * ) + NEW met1 ( 6509 2057 ) ( * 2091 ) + NEW met1 ( 5819 2091 ) ( 6509 * ) + NEW met2 ( 5819 1989 ) ( * 2091 ) + NEW met1 ( 5543 1989 ) ( 5819 * ) + NEW met1 ( 3611 1955 ) ( 4577 * ) + NEW met1 ( 6509 2091 ) ( 7475 * ) + NEW met1 ( 7475 1989 ) ( 8717 * ) + NEW li1 ( 713 2023 ) L1M1_PR_MR + NEW li1 ( 7475 2023 ) L1M1_PR_MR + NEW li1 ( 3611 2023 ) L1M1_PR_MR + NEW li1 ( 2645 2023 ) L1M1_PR_MR + NEW li1 ( 1679 2023 ) L1M1_PR_MR + NEW li1 ( 4577 2023 ) L1M1_PR_MR + NEW li1 ( 5543 2023 ) L1M1_PR_MR + NEW li1 ( 6509 2057 ) L1M1_PR_MR + NEW met1 ( 5819 2091 ) M1M2_PR + NEW met1 ( 5819 1989 ) M1M2_PR + NEW li1 ( 8717 1989 ) L1M1_PR_MR ; - storage_7_0_0.we ( storage_7_0_0.gcand X ) ( storage_7_0_0.cg GATE ) + USE SIGNAL - + ROUTED met1 ( 7613 2125 ) ( 8257 * ) - NEW li1 ( 7613 2125 ) L1M1_PR_MR - NEW li1 ( 8257 2125 ) L1M1_PR_MR ; + + ROUTED met1 ( 7981 2091 ) ( 8625 * ) + NEW li1 ( 7981 2091 ) L1M1_PR_MR + NEW li1 ( 8625 2091 ) L1M1_PR_MR ; - we[0] ( PIN we[0] ) ( storage_7_0_0.gcand B ) ( storage_6_0_0.gcand B ) ( storage_5_0_0.gcand B ) ( storage_4_0_0.gcand B ) ( storage_3_0_0.gcand B ) ( storage_2_0_0.gcand B ) ( storage_1_0_0.gcand B ) ( storage_0_0_0.gcand B ) + USE SIGNAL - + ROUTED met1 ( 8119 1207 ) ( 8165 * ) - NEW met1 ( 8119 935 ) ( 8165 * ) - NEW met2 ( 8119 935 ) ( * 1207 ) - NEW met1 ( 8119 663 ) ( 8165 * ) - NEW met2 ( 8119 663 ) ( * 935 ) - NEW met1 ( 8119 391 ) ( 8165 * ) - NEW met2 ( 8119 391 ) ( * 663 ) - NEW met1 ( 8119 119 ) ( 8165 * ) - NEW met2 ( 8119 119 ) ( * 391 ) - NEW met1 ( 8119 2023 ) ( 8165 * ) - NEW met2 ( 8119 2023 ) ( * 2686 0 ) - NEW met1 ( 8119 1751 ) ( 8165 * ) - NEW met2 ( 8119 1751 ) ( * 2023 ) - NEW met1 ( 8119 1513 ) ( 8165 * ) - NEW met2 ( 8119 1513 ) ( * 1751 ) - NEW met2 ( 8119 1207 ) ( * 1513 ) - NEW li1 ( 8165 1207 ) L1M1_PR_MR - NEW met1 ( 8119 1207 ) M1M2_PR - NEW li1 ( 8165 935 ) L1M1_PR_MR - NEW met1 ( 8119 935 ) M1M2_PR - NEW li1 ( 8165 663 ) L1M1_PR_MR - NEW met1 ( 8119 663 ) M1M2_PR - NEW li1 ( 8165 391 ) L1M1_PR_MR - NEW met1 ( 8119 391 ) M1M2_PR - NEW li1 ( 8165 119 ) L1M1_PR_MR - NEW met1 ( 8119 119 ) M1M2_PR - NEW li1 ( 8165 2023 ) L1M1_PR_MR - NEW met1 ( 8119 2023 ) M1M2_PR - NEW li1 ( 8165 1751 ) L1M1_PR_MR - NEW met1 ( 8119 1751 ) M1M2_PR - NEW li1 ( 8165 1513 ) L1M1_PR_MR - NEW met1 ( 8119 1513 ) M1M2_PR ; + + ROUTED met1 ( 8487 2023 ) ( 8533 * ) + NEW met2 ( 8487 2023 ) ( * 2686 0 ) + NEW met1 ( 8487 1751 ) ( 8533 * ) + NEW met2 ( 8487 1751 ) ( * 2023 ) + NEW met1 ( 8487 1479 ) ( 8533 * ) + NEW met2 ( 8487 1479 ) ( * 1751 ) + NEW met1 ( 8487 1207 ) ( 8533 * ) + NEW met2 ( 8487 1207 ) ( * 1479 ) + NEW met1 ( 8487 935 ) ( 8533 * ) + NEW met2 ( 8487 935 ) ( * 1207 ) + NEW met1 ( 8487 663 ) ( 8533 * ) + NEW met2 ( 8487 663 ) ( * 935 ) + NEW met1 ( 8487 391 ) ( 8533 * ) + NEW met2 ( 8487 391 ) ( * 663 ) + NEW met1 ( 8487 119 ) ( 8533 * ) + NEW met2 ( 8487 119 ) ( * 391 ) + NEW li1 ( 8533 2023 ) L1M1_PR_MR + NEW met1 ( 8487 2023 ) M1M2_PR + NEW li1 ( 8533 1751 ) L1M1_PR_MR + NEW met1 ( 8487 1751 ) M1M2_PR + NEW li1 ( 8533 1479 ) L1M1_PR_MR + NEW met1 ( 8487 1479 ) M1M2_PR + NEW li1 ( 8533 1207 ) L1M1_PR_MR + NEW met1 ( 8487 1207 ) M1M2_PR + NEW li1 ( 8533 935 ) L1M1_PR_MR + NEW met1 ( 8487 935 ) M1M2_PR + NEW li1 ( 8533 663 ) L1M1_PR_MR + NEW met1 ( 8487 663 ) M1M2_PR + NEW li1 ( 8533 391 ) L1M1_PR_MR + NEW met1 ( 8487 391 ) M1M2_PR + NEW li1 ( 8533 119 ) L1M1_PR_MR + NEW met1 ( 8487 119 ) M1M2_PR ; END NETS END DESIGN diff --git a/src/ram/test/make_8x8_latch_sky130.lefok b/src/ram/test/make_8x8_latch_sky130.lefok index 6b2ca7e5b0f..462ef400a58 100644 --- a/src/ram/test/make_8x8_latch_sky130.lefok +++ b/src/ram/test/make_8x8_latch_sky130.lefok @@ -8,13 +8,13 @@ END UNITS MACRO RAM8x8 FOREIGN RAM8x8 0 0 ; CLASS BLOCK ; - SIZE 92 BY 27.2 ; + SIZE 95.68 BY 27.2 ; PIN clk DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 76.52 26.715 76.66 27.2 ; + RECT 80.2 26.715 80.34 27.2 ; END END clk PIN we[0] @@ -22,7 +22,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 81.12 26.715 81.26 27.2 ; + RECT 84.8 26.715 84.94 27.2 ; END END we[0] PIN addr_rw[0] @@ -30,7 +30,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met3 ; - RECT 91.2 4.27 92 4.57 ; + RECT 94.88 4.27 95.68 4.57 ; END END addr_rw[0] PIN addr_rw[1] @@ -38,7 +38,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met3 ; - RECT 91.2 6.99 92 7.29 ; + RECT 94.88 6.99 95.68 7.29 ; END END addr_rw[1] PIN addr_rw[2] @@ -46,7 +46,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met3 ; - RECT 91.2 1.55 92 1.85 ; + RECT 94.88 1.55 95.68 1.85 ; END END addr_rw[2] PIN D[0] @@ -62,7 +62,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 8.44 26.715 8.58 27.2 ; + RECT 9.36 26.715 9.5 27.2 ; END END Q[0] PIN D[1] @@ -78,7 +78,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 17.64 26.715 17.78 27.2 ; + RECT 18.56 26.715 18.7 27.2 ; END END Q[1] PIN D[2] @@ -86,7 +86,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 19.48 26.715 19.62 27.2 ; + RECT 20.4 26.715 20.54 27.2 ; END END D[2] PIN Q[2] @@ -94,7 +94,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 26.84 26.715 26.98 27.2 ; + RECT 28.68 26.715 28.82 27.2 ; END END Q[2] PIN D[3] @@ -102,7 +102,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 28.68 26.715 28.82 27.2 ; + RECT 29.6 26.715 29.74 27.2 ; END END D[3] PIN Q[3] @@ -110,7 +110,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 36.04 26.715 36.18 27.2 ; + RECT 37.88 26.715 38.02 27.2 ; END END Q[3] PIN D[4] @@ -118,7 +118,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 37.88 26.715 38.02 27.2 ; + RECT 38.8 26.715 38.94 27.2 ; END END D[4] PIN Q[4] @@ -126,7 +126,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 45.24 26.715 45.38 27.2 ; + RECT 48 26.715 48.14 27.2 ; END END Q[4] PIN D[5] @@ -134,7 +134,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 47.08 26.715 47.22 27.2 ; + RECT 48.92 26.715 49.06 27.2 ; END END D[5] PIN Q[5] @@ -142,7 +142,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 54.44 26.715 54.58 27.2 ; + RECT 57.2 26.715 57.34 27.2 ; END END Q[5] PIN D[6] @@ -150,7 +150,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 56.28 26.715 56.42 27.2 ; + RECT 59.04 26.715 59.18 27.2 ; END END D[6] PIN Q[6] @@ -158,7 +158,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 63.64 26.715 63.78 27.2 ; + RECT 67.32 26.715 67.46 27.2 ; END END Q[6] PIN D[7] @@ -166,7 +166,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 65.48 26.715 65.62 27.2 ; + RECT 68.24 26.715 68.38 27.2 ; END END D[7] PIN Q[7] @@ -174,7 +174,7 @@ MACRO RAM8x8 USE SIGNAL ; PORT LAYER met2 ; - RECT 72.84 26.715 72.98 27.2 ; + RECT 76.52 26.715 76.66 27.2 ; END END Q[7] PIN VDD @@ -182,7 +182,7 @@ MACRO RAM8x8 USE POWER ; PORT LAYER met3 ; - RECT 91.7 9.76 92 10.24 ; + RECT 95.38 9.76 95.68 10.24 ; RECT 0 9.76 0.3 10.24 ; LAYER met2 ; RECT 59.76 27.06 60.24 27.2 ; @@ -190,15 +190,15 @@ MACRO RAM8x8 RECT 19.76 27.06 20.24 27.2 ; RECT 19.76 0 20.24 0.14 ; LAYER met1 ; - RECT 91.86 24.24 92 24.72 ; + RECT 95.54 24.24 95.68 24.72 ; RECT 0 24.24 0.14 24.72 ; - RECT 91.86 18.8 92 19.28 ; + RECT 95.54 18.8 95.68 19.28 ; RECT 0 18.8 0.14 19.28 ; - RECT 91.86 13.36 92 13.84 ; + RECT 95.54 13.36 95.68 13.84 ; RECT 0 13.36 0.14 13.84 ; - RECT 91.86 7.92 92 8.4 ; + RECT 95.54 7.92 95.68 8.4 ; RECT 0 7.92 0.14 8.4 ; - RECT 91.86 2.48 92 2.96 ; + RECT 95.54 2.48 95.68 2.96 ; RECT 0 2.48 0.14 2.96 ; END END VDD @@ -207,7 +207,7 @@ MACRO RAM8x8 USE GROUND ; PORT LAYER met3 ; - RECT 91.7 19.76 92 20.24 ; + RECT 95.38 19.76 95.68 20.24 ; RECT 0 19.76 0.3 20.24 ; LAYER met2 ; RECT 79.76 27.06 80.24 27.2 ; @@ -215,55 +215,56 @@ MACRO RAM8x8 RECT 39.76 27.06 40.24 27.2 ; RECT 39.76 0 40.24 0.14 ; LAYER met1 ; - RECT 91.86 26.96 92 27.44 ; + RECT 95.54 26.96 95.68 27.44 ; RECT 0 26.96 0.14 27.44 ; - RECT 91.86 21.52 92 22 ; + RECT 95.54 21.52 95.68 22 ; RECT 0 21.52 0.14 22 ; - RECT 91.86 16.08 92 16.56 ; + RECT 95.54 16.08 95.68 16.56 ; RECT 0 16.08 0.14 16.56 ; - RECT 91.86 10.64 92 11.12 ; + RECT 95.54 10.64 95.68 11.12 ; RECT 0 10.64 0.14 11.12 ; - RECT 91.86 5.2 92 5.68 ; + RECT 95.54 5.2 95.68 5.68 ; RECT 0 5.2 0.14 5.68 ; - RECT 91.86 -0.24 92 0.24 ; + RECT 95.54 -0.24 95.68 0.24 ; RECT 0 -0.24 0.14 0.24 ; END END VSS OBS LAYER li1 ; - RECT 0 -0.085 92 27.285 ; + RECT 0 -0.085 95.68 27.285 ; LAYER met1 ; - RECT 0 -0.24 92 27.44 ; + RECT 0 -0.24 95.68 27.44 ; LAYER met2 ; - RECT 19.76 0 20.24 0.69 ; - RECT 39.76 -0.24 40.24 0.69 ; - RECT 59.76 0 60.24 0.69 ; - RECT 58.06 0.69 67.52 1.03 ; + RECT 19.76 0 20.24 1.03 ; + RECT 39.76 -0.24 40.24 1.03 ; + RECT 59.76 0 60.24 1.03 ; RECT 79.76 -0.24 80.24 1.03 ; - RECT 58.06 1.03 81.32 1.37 ; - RECT 90.72 1.03 90.98 1.37 ; - RECT 58.06 1.37 90.98 1.515 ; - RECT 2.4 0.69 2.66 2.05 ; - RECT 12.06 0.69 30.26 2.05 ; - RECT 39.76 0.69 48.66 2.05 ; - RECT 58.06 1.515 90.99 2.05 ; - RECT 2.4 2.05 90.99 7.325 ; - RECT 2.4 7.325 90.98 18.01 ; - RECT 2.4 18.01 90.52 20.39 ; - RECT 2.4 20.39 81.26 22.45 ; - RECT 1.48 22.45 81.26 25.85 ; - RECT 1.02 25.85 81.26 26.17 ; - RECT 1.08 26.17 81.26 26.86 ; + RECT 59.76 1.03 69.82 1.37 ; + RECT 79.76 1.03 85 1.37 ; + RECT 94.4 1.03 94.66 1.37 ; + RECT 59.76 1.37 94.66 1.515 ; + RECT 1.94 1.03 2.2 2.05 ; + RECT 11.6 1.03 21.52 2.05 ; + RECT 30.92 1.03 40.84 2.05 ; + RECT 50.24 1.03 50.5 2.05 ; + RECT 59.76 1.515 94.67 2.05 ; + RECT 1.94 2.05 94.67 7.325 ; + RECT 1.94 7.325 94.66 18.01 ; + RECT 1.94 18.01 94.2 20.39 ; + RECT 1.94 20.39 84.94 25.85 ; + RECT 1.02 25.85 84.94 26.17 ; + RECT 1.08 26.17 84.94 26.86 ; + RECT 79.76 26.86 80.8 26.93 ; RECT 19.76 26.86 20.24 27.2 ; RECT 59.76 26.86 60.24 27.2 ; RECT 39.76 26.86 40.24 27.44 ; - RECT 79.76 26.86 80.24 27.44 ; + RECT 79.76 26.93 80.24 27.44 ; LAYER met3 ; - RECT 0 9.76 86.545 20.24 ; - RECT 86.545 4.255 90.685 20.24 ; - RECT 90.685 1.535 91.015 20.24 ; - RECT 91.015 1.55 91.54 20.24 ; - RECT 91.54 9.76 92 20.24 ; + RECT 0 9.76 90.225 20.24 ; + RECT 90.225 4.255 94.365 20.24 ; + RECT 94.365 1.535 94.695 20.24 ; + RECT 94.695 1.55 95.22 20.24 ; + RECT 95.22 9.76 95.68 20.24 ; END END RAM8x8 END LIBRARY diff --git a/src/ram/test/make_8x8_latch_sky130.ok b/src/ram/test/make_8x8_latch_sky130.ok index 4df4eb2b222..ae3cde7a3d7 100644 --- a/src/ram/test/make_8x8_latch_sky130.ok +++ b/src/ram/test/make_8x8_latch_sky130.ok @@ -6,23 +6,22 @@ [INFO RAM-0016] Selected and2 cell sky130_fd_sc_hd__and2_0 [INFO RAM-0016] Selected clock gate cell sky130_fd_sc_hd__dlclkp_1 [INFO RAM-0016] Selected buffer cell sky130_fd_sc_hd__buf_1 -[INFO RAM-0016] Selected latch cell sky130_fd_sc_hd__lpflow_inputisolatch_1 [INFO RAM-0016] Selected aoi22 cell sky130_fd_sc_hd__a22oi_1 [INFO RAM-0024] Behavioral Verilog written for RAM8x8 -[INFO RAM-0044] RAM worst setup path delay: 0.879054 ns -[INFO RAM-0045] RAM worst hold path delay: 0.000000 ns -[INFO RAM-0046] RAM total power (no activity): 0.000158 W +[INFO RAM-0044] RAM maximum path delay: 0.879 ns +[INFO RAM-0045] RAM minimum path delay: 0.000 ns +[INFO RAM-0046] RAM estimated power: 181922.922 nW [INFO PDN-0001] Inserting grid: ram_grid -[INFO PPL-0067] Restrict pins [ clk we[0] D[0] Q[0] D[1] ... ] to region 0.00u-92.00u at the TOP edge. +[INFO PPL-0067] Restrict pins [ clk we[0] D[0] Q[0] D[1] ... ] to region 0.00u-95.68u at the TOP edge. [INFO PPL-0067] Restrict pins [ addr_rw[0] addr_rw[1] addr_rw[2] ] to region 0.00u-27.20u at the RIGHT edge. -[INFO PPL-0001] Number of available slots 234 +[INFO PPL-0001] Number of available slots 242 [INFO PPL-0002] Number of I/O 21 [INFO PPL-0003] Number of I/O w/sink 21 [INFO PPL-0004] Number of I/O w/o sink 0 [INFO PPL-0005] Slots per section 200 [INFO PPL-0008] Successfully assigned pins to sections. -[INFO PPL-0012] I/O nets HPWL: 338.39 um. -[INFO DPL-0001] Placed 48 filler instances. +[INFO PPL-0012] I/O nets HPWL: 337.24 um. +[INFO DPL-0001] Placed 56 filler instances. [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via @@ -45,9 +44,9 @@ [INFO DRT-0168] Init region query. [INFO DRT-0033] FR_MASTERSLICE shape region query size = 0. [INFO DRT-0033] FR_VIA shape region query size = 0. -[INFO DRT-0033] li1 shape region query size = 6908. -[INFO DRT-0033] mcon shape region query size = 200. -[INFO DRT-0033] met1 shape region query size = 783. +[INFO DRT-0033] li1 shape region query size = 6924. +[INFO DRT-0033] mcon shape region query size = 488. +[INFO DRT-0033] met1 shape region query size = 1231. [INFO DRT-0033] via shape region query size = 22. [INFO DRT-0033] met2 shape region query size = 56. [INFO DRT-0033] via2 shape region query size = 4. @@ -59,7 +58,7 @@ [INFO DRT-0178] Init guide query. [INFO DRT-0036] FR_MASTERSLICE guide region query size = 0. [INFO DRT-0036] FR_VIA guide region query size = 0. -[INFO DRT-0036] li1 guide region query size = 345. +[INFO DRT-0036] li1 guide region query size = 347. [INFO DRT-0036] mcon guide region query size = 0. [INFO DRT-0036] met1 guide region query size = 212. [INFO DRT-0036] via guide region query size = 0. diff --git a/src/ram/test/make_8x8_latch_sky130.tcl b/src/ram/test/make_8x8_latch_sky130.tcl index c37a8b581e4..7407bc083ab 100644 --- a/src/ram/test/make_8x8_latch_sky130.tcl +++ b/src/ram/test/make_8x8_latch_sky130.tcl @@ -15,6 +15,7 @@ generate_ram \ -num_words 8 \ -rw_ports 1 \ -use_latch 1 \ + -storage_cell sky130_fd_sc_hd__dlxtp_1 \ -routing_layer {met1 0.48} \ -ver_layer {met2 0.48 40} \ -hor_layer {met3 0.48 20} \ diff --git a/src/ram/test/make_8x8_mux2_sky130.ok b/src/ram/test/make_8x8_mux2_sky130.ok index 7d68a2b9210..8585d41d6c1 100644 --- a/src/ram/test/make_8x8_mux2_sky130.ok +++ b/src/ram/test/make_8x8_mux2_sky130.ok @@ -8,9 +8,9 @@ [INFO RAM-0016] Selected buffer cell sky130_fd_sc_hd__buf_1 [INFO RAM-0016] Selected aoi22 cell sky130_fd_sc_hd__a22oi_1 [INFO RAM-0024] Behavioral Verilog written for RAM8x8 -[INFO RAM-0044] RAM worst setup path delay: 1.045793 ns -[INFO RAM-0045] RAM worst hold path delay: 0.000000 ns -[INFO RAM-0046] RAM total power (no activity): 0.000237 W +[INFO RAM-0044] RAM maximum path delay: 1.046 ns +[INFO RAM-0045] RAM minimum path delay: 0.000 ns +[INFO RAM-0046] RAM estimated power: 237089.828 nW [INFO PDN-0001] Inserting grid: ram_grid [INFO PPL-0067] Restrict pins [ clk we[0] D[0] Q[0] D[1] ... ] to region 0.00u-213.90u at the TOP edge. [INFO PPL-0067] Restrict pins [ addr_rw[0] addr_rw[1] addr_rw[2] ] to region 0.00u-13.60u at the RIGHT edge. diff --git a/src/ram/test/make_8x8_mux4_sky130.ok b/src/ram/test/make_8x8_mux4_sky130.ok index 296225ac6a0..c1259df2115 100644 --- a/src/ram/test/make_8x8_mux4_sky130.ok +++ b/src/ram/test/make_8x8_mux4_sky130.ok @@ -8,9 +8,9 @@ [INFO RAM-0016] Selected buffer cell sky130_fd_sc_hd__buf_1 [INFO RAM-0016] Selected aoi22 cell sky130_fd_sc_hd__a22oi_1 [INFO RAM-0024] Behavioral Verilog written for RAM8x8 -[INFO RAM-0044] RAM worst setup path delay: 1.423589 ns -[INFO RAM-0045] RAM worst hold path delay: 0.000000 ns -[INFO RAM-0046] RAM total power (no activity): 0.000253 W +[INFO RAM-0044] RAM maximum path delay: 1.424 ns +[INFO RAM-0045] RAM minimum path delay: 0.000 ns +[INFO RAM-0046] RAM estimated power: 253089.922 nW [INFO PDN-0001] Inserting grid: ram_grid [INFO PPL-0067] Restrict pins [ clk we[0] D[0] Q[0] D[1] ... ] to region 0.00u-419.98u at the TOP edge. [INFO PPL-0067] Restrict pins [ addr_rw[0] addr_rw[1] addr_rw[2] ] to region 0.00u-8.16u at the RIGHT edge. diff --git a/src/ram/test/make_8x8_sky130.ok b/src/ram/test/make_8x8_sky130.ok index d526f31e8ff..86dd6310a48 100644 --- a/src/ram/test/make_8x8_sky130.ok +++ b/src/ram/test/make_8x8_sky130.ok @@ -8,9 +8,9 @@ [INFO RAM-0016] Selected buffer cell sky130_fd_sc_hd__buf_1 [INFO RAM-0016] Selected aoi22 cell sky130_fd_sc_hd__a22oi_1 [INFO RAM-0024] Behavioral Verilog written for RAM8x8 -[INFO RAM-0044] RAM worst setup path delay: 0.879054 ns -[INFO RAM-0045] RAM worst hold path delay: 0.000000 ns -[INFO RAM-0046] RAM total power (no activity): 0.000233 W +[INFO RAM-0044] RAM maximum path delay: 0.879 ns +[INFO RAM-0045] RAM minimum path delay: 0.000 ns +[INFO RAM-0046] RAM estimated power: 232520.859 nW [INFO PDN-0001] Inserting grid: ram_grid [INFO PPL-0067] Restrict pins [ clk we[0] D[0] Q[0] D[1] ... ] to region 0.00u-110.40u at the TOP edge. [INFO PPL-0067] Restrict pins [ addr_rw[0] addr_rw[1] addr_rw[2] ] to region 0.00u-24.48u at the RIGHT edge. From 7f6271e12e2f0c3f8f03743b223572ab364c1038 Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Tue, 7 Jul 2026 18:24:13 -0400 Subject: [PATCH 10/19] ram: move reportTimingPower() to public method and add a tcl wrapper to call it at the end of generate_ram after filler insertion and routing Signed-off-by: Thinh Nguyen --- src/ram/include/ram/ram.h | 4 ++-- src/ram/src/ram.cpp | 1 - src/ram/src/ram.i | 6 ++++++ src/ram/src/ram.tcl | 2 ++ src/ram/test/make_7x7_2r1w_nangate45.ok | 6 +++--- src/ram/test/make_7x7_nangate45.ok | 6 +++--- src/ram/test/make_8x8_2r1w_sky130.ok | 6 +++--- src/ram/test/make_8x8_latch_sky130.ok | 6 +++--- src/ram/test/make_8x8_mux2_sky130.ok | 6 +++--- src/ram/test/make_8x8_mux4_sky130.ok | 6 +++--- src/ram/test/make_8x8_sky130.ok | 6 +++--- 11 files changed, 31 insertions(+), 24 deletions(-) diff --git a/src/ram/include/ram/ram.h b/src/ram/include/ram/ram.h index 6cd48a86aed..d3c60ed2c4e 100644 --- a/src/ram/include/ram/ram.h +++ b/src/ram/include/ram/ram.h @@ -133,6 +133,8 @@ class RamGen int rw_ports, int r_ports, int w_ports); + + void reportTimingAndPower(); private: void findMasters(); @@ -199,8 +201,6 @@ class RamGen const std::vector& decoder_output_nets, const std::vector& select_nets); - void reportTimingAndPower(); - std::unique_ptr makeInverterColumn( int num_rows, int num_row_bits, diff --git a/src/ram/src/ram.cpp b/src/ram/src/ram.cpp index e099343e8e2..ef80e0c241d 100644 --- a/src/ram/src/ram.cpp +++ b/src/ram/src/ram.cpp @@ -1921,7 +1921,6 @@ void RamGen::generate(const int mask_size, r_ports, w_ports); - reportTimingAndPower(); } void RamGen::setBehavioralVerilogFilename(const std::string& filename) diff --git a/src/ram/src/ram.i b/src/ram/src/ram.i index b40cb302d27..f01ade007bc 100644 --- a/src/ram/src/ram.i +++ b/src/ram/src/ram.i @@ -127,6 +127,12 @@ void ram_routing() ram_gen->ramRouting(thread_count); } +void ram_report_timing_power() +{ + RamGen* ram_gen = ord::getRamGen(); + ram_gen->reportTimingAndPower(); +} + void set_behavioral_verilog_filename(const char* filename) { RamGen* ram_gen = ord::getRamGen(); diff --git a/src/ram/src/ram.tcl b/src/ram/src/ram.tcl index 4e58c501636..618b7780e55 100644 --- a/src/ram/src/ram.tcl +++ b/src/ram/src/ram.tcl @@ -297,4 +297,6 @@ proc generate_ram { args } { ram::ram_filler $filler_cells ram::ram_routing + + ram::ram_report_timing_power } diff --git a/src/ram/test/make_7x7_2r1w_nangate45.ok b/src/ram/test/make_7x7_2r1w_nangate45.ok index 52e09b50ba4..3e33dd0dc6f 100644 --- a/src/ram/test/make_7x7_2r1w_nangate45.ok +++ b/src/ram/test/make_7x7_2r1w_nangate45.ok @@ -28,9 +28,6 @@ [INFO RAM-0016] Selected buffer cell BUF_X1 [INFO RAM-0016] Selected aoi22 cell AOI22_X1 [INFO RAM-0024] Behavioral Verilog written for RAM7x7 -[INFO RAM-0044] RAM maximum path delay: 0.265 ns -[INFO RAM-0045] RAM minimum path delay: 0.000 ns -[INFO RAM-0046] RAM estimated power: 79128.938 nW [INFO PDN-0001] Inserting grid: ram_grid [WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (4.5000 um, 4.0000 um) for VDD [WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (9.0000 um, 8.0000 um) for VSS @@ -116,6 +113,9 @@ [INFO DRT-0036] via9 guide region query size = 0. [INFO DRT-0036] metal10 guide region query size = 0. [INFO DRT-0179] Init gr pin query. +[INFO RAM-0044] RAM maximum path delay: 0.265 ns +[INFO RAM-0045] RAM minimum path delay: 0.000 ns +[INFO RAM-0046] RAM estimated power: 79128.938 nW No differences found. No differences found. No differences found. diff --git a/src/ram/test/make_7x7_nangate45.ok b/src/ram/test/make_7x7_nangate45.ok index e5373c81654..2b8a5758efc 100644 --- a/src/ram/test/make_7x7_nangate45.ok +++ b/src/ram/test/make_7x7_nangate45.ok @@ -28,9 +28,6 @@ [INFO RAM-0016] Selected buffer cell BUF_X1 [INFO RAM-0016] Selected aoi22 cell AOI22_X1 [INFO RAM-0024] Behavioral Verilog written for RAM7x7 -[INFO RAM-0044] RAM maximum path delay: 0.268 ns -[INFO RAM-0045] RAM minimum path delay: 0.000 ns -[INFO RAM-0046] RAM estimated power: 52755.473 nW [INFO PDN-0001] Inserting grid: ram_grid [WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (4.5000 um, 4.0000 um) for VDD [WARNING PDN-0195] Removing 1 via(s) between metal3 and metal4 at (9.0000 um, 8.0000 um) for VSS @@ -112,6 +109,9 @@ [INFO DRT-0036] via9 guide region query size = 0. [INFO DRT-0036] metal10 guide region query size = 0. [INFO DRT-0179] Init gr pin query. +[INFO RAM-0044] RAM maximum path delay: 0.268 ns +[INFO RAM-0045] RAM minimum path delay: 0.000 ns +[INFO RAM-0046] RAM estimated power: 52755.473 nW No differences found. No differences found. No differences found. diff --git a/src/ram/test/make_8x8_2r1w_sky130.ok b/src/ram/test/make_8x8_2r1w_sky130.ok index 05981fb0424..b8da039f221 100644 --- a/src/ram/test/make_8x8_2r1w_sky130.ok +++ b/src/ram/test/make_8x8_2r1w_sky130.ok @@ -8,9 +8,6 @@ [INFO RAM-0016] Selected buffer cell sky130_fd_sc_hd__buf_1 [INFO RAM-0016] Selected aoi22 cell sky130_fd_sc_hd__a22oi_1 [INFO RAM-0024] Behavioral Verilog written for RAM8x8 -[INFO RAM-0044] RAM maximum path delay: 0.859 ns -[INFO RAM-0045] RAM minimum path delay: 0.000 ns -[INFO RAM-0046] RAM estimated power: 360445.062 nW [INFO PDN-0001] Inserting grid: ram_grid [INFO PPL-0067] Restrict pins [ clk we[0] D[0] Q0[0] Q1[0] ... ] to region 0.00u-155.02u at the TOP edge. [INFO PPL-0067] Restrict pins [ addr_w[0] addr_w[1] addr_w[2] addr_r0[0] addr_r0[1] ... ] to region 0.00u-24.48u at the RIGHT edge. @@ -70,6 +67,9 @@ [INFO DRT-0036] via4 guide region query size = 0. [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. +[INFO RAM-0044] RAM maximum path delay: 0.859 ns +[INFO RAM-0045] RAM minimum path delay: 0.000 ns +[INFO RAM-0046] RAM estimated power: 360445.062 nW No differences found. No differences found. No differences found. diff --git a/src/ram/test/make_8x8_latch_sky130.ok b/src/ram/test/make_8x8_latch_sky130.ok index ae3cde7a3d7..de04fdf4607 100644 --- a/src/ram/test/make_8x8_latch_sky130.ok +++ b/src/ram/test/make_8x8_latch_sky130.ok @@ -8,9 +8,6 @@ [INFO RAM-0016] Selected buffer cell sky130_fd_sc_hd__buf_1 [INFO RAM-0016] Selected aoi22 cell sky130_fd_sc_hd__a22oi_1 [INFO RAM-0024] Behavioral Verilog written for RAM8x8 -[INFO RAM-0044] RAM maximum path delay: 0.879 ns -[INFO RAM-0045] RAM minimum path delay: 0.000 ns -[INFO RAM-0046] RAM estimated power: 181922.922 nW [INFO PDN-0001] Inserting grid: ram_grid [INFO PPL-0067] Restrict pins [ clk we[0] D[0] Q[0] D[1] ... ] to region 0.00u-95.68u at the TOP edge. [INFO PPL-0067] Restrict pins [ addr_rw[0] addr_rw[1] addr_rw[2] ] to region 0.00u-27.20u at the RIGHT edge. @@ -70,6 +67,9 @@ [INFO DRT-0036] via4 guide region query size = 0. [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. +[INFO RAM-0044] RAM maximum path delay: 0.879 ns +[INFO RAM-0045] RAM minimum path delay: 0.000 ns +[INFO RAM-0046] RAM estimated power: 181922.922 nW No differences found. No differences found. No differences found. diff --git a/src/ram/test/make_8x8_mux2_sky130.ok b/src/ram/test/make_8x8_mux2_sky130.ok index 8585d41d6c1..a79b50c4cac 100644 --- a/src/ram/test/make_8x8_mux2_sky130.ok +++ b/src/ram/test/make_8x8_mux2_sky130.ok @@ -8,9 +8,6 @@ [INFO RAM-0016] Selected buffer cell sky130_fd_sc_hd__buf_1 [INFO RAM-0016] Selected aoi22 cell sky130_fd_sc_hd__a22oi_1 [INFO RAM-0024] Behavioral Verilog written for RAM8x8 -[INFO RAM-0044] RAM maximum path delay: 1.046 ns -[INFO RAM-0045] RAM minimum path delay: 0.000 ns -[INFO RAM-0046] RAM estimated power: 237089.828 nW [INFO PDN-0001] Inserting grid: ram_grid [INFO PPL-0067] Restrict pins [ clk we[0] D[0] Q[0] D[1] ... ] to region 0.00u-213.90u at the TOP edge. [INFO PPL-0067] Restrict pins [ addr_rw[0] addr_rw[1] addr_rw[2] ] to region 0.00u-13.60u at the RIGHT edge. @@ -70,6 +67,9 @@ [INFO DRT-0036] via4 guide region query size = 0. [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. +[INFO RAM-0044] RAM maximum path delay: 1.046 ns +[INFO RAM-0045] RAM minimum path delay: 0.000 ns +[INFO RAM-0046] RAM estimated power: 237089.828 nW No differences found. No differences found. No differences found. diff --git a/src/ram/test/make_8x8_mux4_sky130.ok b/src/ram/test/make_8x8_mux4_sky130.ok index c1259df2115..572d9494e1f 100644 --- a/src/ram/test/make_8x8_mux4_sky130.ok +++ b/src/ram/test/make_8x8_mux4_sky130.ok @@ -8,9 +8,6 @@ [INFO RAM-0016] Selected buffer cell sky130_fd_sc_hd__buf_1 [INFO RAM-0016] Selected aoi22 cell sky130_fd_sc_hd__a22oi_1 [INFO RAM-0024] Behavioral Verilog written for RAM8x8 -[INFO RAM-0044] RAM maximum path delay: 1.424 ns -[INFO RAM-0045] RAM minimum path delay: 0.000 ns -[INFO RAM-0046] RAM estimated power: 253089.922 nW [INFO PDN-0001] Inserting grid: ram_grid [INFO PPL-0067] Restrict pins [ clk we[0] D[0] Q[0] D[1] ... ] to region 0.00u-419.98u at the TOP edge. [INFO PPL-0067] Restrict pins [ addr_rw[0] addr_rw[1] addr_rw[2] ] to region 0.00u-8.16u at the RIGHT edge. @@ -70,6 +67,9 @@ [INFO DRT-0036] via4 guide region query size = 0. [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. +[INFO RAM-0044] RAM maximum path delay: 1.424 ns +[INFO RAM-0045] RAM minimum path delay: 0.000 ns +[INFO RAM-0046] RAM estimated power: 253089.922 nW No differences found. No differences found. No differences found. diff --git a/src/ram/test/make_8x8_sky130.ok b/src/ram/test/make_8x8_sky130.ok index 86dd6310a48..6856e8f5f6e 100644 --- a/src/ram/test/make_8x8_sky130.ok +++ b/src/ram/test/make_8x8_sky130.ok @@ -8,9 +8,6 @@ [INFO RAM-0016] Selected buffer cell sky130_fd_sc_hd__buf_1 [INFO RAM-0016] Selected aoi22 cell sky130_fd_sc_hd__a22oi_1 [INFO RAM-0024] Behavioral Verilog written for RAM8x8 -[INFO RAM-0044] RAM maximum path delay: 0.879 ns -[INFO RAM-0045] RAM minimum path delay: 0.000 ns -[INFO RAM-0046] RAM estimated power: 232520.859 nW [INFO PDN-0001] Inserting grid: ram_grid [INFO PPL-0067] Restrict pins [ clk we[0] D[0] Q[0] D[1] ... ] to region 0.00u-110.40u at the TOP edge. [INFO PPL-0067] Restrict pins [ addr_rw[0] addr_rw[1] addr_rw[2] ] to region 0.00u-24.48u at the RIGHT edge. @@ -70,6 +67,9 @@ [INFO DRT-0036] via4 guide region query size = 0. [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. +[INFO RAM-0044] RAM maximum path delay: 0.879 ns +[INFO RAM-0045] RAM minimum path delay: 0.000 ns +[INFO RAM-0046] RAM estimated power: 232520.859 nW No differences found. No differences found. No differences found. From 28fbd8d4c379d6846a984b7a6cb16d298202c7ab Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Tue, 7 Jul 2026 18:37:58 -0400 Subject: [PATCH 11/19] ram: fix clang-format and tclfmt lint violations Signed-off-by: Thinh Nguyen --- src/ram/include/ram/ram.h | 2 +- src/ram/src/ram.cpp | 1 - src/ram/src/ram.tcl | 3 +-- 3 files changed, 2 insertions(+), 4 deletions(-) diff --git a/src/ram/include/ram/ram.h b/src/ram/include/ram/ram.h index d3c60ed2c4e..f944ce6dab9 100644 --- a/src/ram/include/ram/ram.h +++ b/src/ram/include/ram/ram.h @@ -133,7 +133,7 @@ class RamGen int rw_ports, int r_ports, int w_ports); - + void reportTimingAndPower(); private: diff --git a/src/ram/src/ram.cpp b/src/ram/src/ram.cpp index ef80e0c241d..7cc974239f6 100644 --- a/src/ram/src/ram.cpp +++ b/src/ram/src/ram.cpp @@ -1920,7 +1920,6 @@ void RamGen::generate(const int mask_size, rw_ports, r_ports, w_ports); - } void RamGen::setBehavioralVerilogFilename(const std::string& filename) diff --git a/src/ram/src/ram.tcl b/src/ram/src/ram.tcl index 618b7780e55..322c99dfaf9 100644 --- a/src/ram/src/ram.tcl +++ b/src/ram/src/ram.tcl @@ -297,6 +297,5 @@ proc generate_ram { args } { ram::ram_filler $filler_cells ram::ram_routing - - ram::ram_report_timing_power + ram::ram_report_timing_power } From c121752782cfaa8fcb92a92ea6410b5da5f1225f Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Tue, 7 Jul 2026 21:23:20 -0400 Subject: [PATCH 12/19] ram: restrict timing report to functional real data endpoints like storage/latch D pins and primary Q outputs Signed-off-by: Thinh Nguyen --- src/ram/src/ram.cpp | 46 +++++++++++++++++++++++-- src/ram/test/make_7x7_2r1w_nangate45.ok | 2 +- src/ram/test/make_7x7_nangate45.ok | 2 +- src/ram/test/make_8x8_2r1w_sky130.ok | 2 +- src/ram/test/make_8x8_latch_sky130.ok | 2 +- src/ram/test/make_8x8_mux2_sky130.ok | 2 +- src/ram/test/make_8x8_mux4_sky130.ok | 2 +- src/ram/test/make_8x8_sky130.ok | 2 +- 8 files changed, 51 insertions(+), 9 deletions(-) diff --git a/src/ram/src/ram.cpp b/src/ram/src/ram.cpp index 7cc974239f6..9c909fae0c7 100644 --- a/src/ram/src/ram.cpp +++ b/src/ram/src/ram.cpp @@ -32,6 +32,7 @@ #include "sta/FuncExpr.hh" #include "sta/Liberty.hh" #include "sta/MinMax.hh" +#include "sta/NetworkClass.hh" #include "sta/PathEnd.hh" #include "sta/PortDirection.hh" #include "sta/PowerClass.hh" @@ -39,6 +40,7 @@ #include "sta/SearchClass.hh" #include "sta/Sequential.hh" #include "sta/StringUtil.hh" +#include "sta/Transition.hh" #include "sta/Units.hh" #include "utl/Logger.h" @@ -2075,11 +2077,44 @@ void RamGen::reportTimingAndPower() sta::StringSeq group_names; + // restrict path searches to the RAM's data endpoints (storage/latch + // D pins and primary Q outputs) since unconstrained searches + // also land on register and clock-gate CLK pins, which will + // report a misleading zero value for min path delay + // since no clock is defined for this automated test + auto collect_data_endpoints = [&]() -> sta::PinSet* { + auto* pins = new sta::PinSet(network_); + odb::dbMaster* seq_cell = use_latch_ ? latch_cell_ : storage_cell_; + const auto& seq_ports = use_latch_ ? latch_ports_ : storage_ports_; + const std::string& data_in_mterm = seq_ports.at({PortRoleType::DataIn, 0}); + auto* mterm = seq_cell->findMTerm(data_in_mterm.c_str()); + for (auto* inst : block_->getInsts()) { + if (inst->getMaster() == seq_cell) { + auto* iterm = inst->getITerm(mterm); + pins->insert(network_->dbToSta(iterm)); + } + } + for (auto& port_outputs : q_outputs_) { + for (auto* bterm : port_outputs) { + pins->insert(network_->dbToSta(bterm)); + } + } + return pins; + }; + // Find worst unconstrained setup path delay/longest path + sta::ExceptionTo* setup_to + = sta_->makeExceptionTo(collect_data_endpoints(), + nullptr, + nullptr, + sta::RiseFallBoth::riseFall(), + sta::RiseFallBoth::riseFall(), + sta_->cmdSdc()); + sta::PathEndSeq setup_ends = sta_->findPathEnds(nullptr, /* from */ nullptr, /* thrus */ - nullptr, /* to */ + setup_to, /* to */ true, /* unconstrained */ scenes, /* scenes */ sta::MinMaxAll::max(), /* min_max */ @@ -2104,10 +2139,17 @@ void RamGen::reportTimingAndPower() : static_cast(setup_ends[0]->dataArrivalTime(sta_)); // Find worst unconstrained hold path delay/shortest path + sta::ExceptionTo* hold_to + = sta_->makeExceptionTo(collect_data_endpoints(), + nullptr, + nullptr, + sta::RiseFallBoth::riseFall(), + sta::RiseFallBoth::riseFall(), + sta_->cmdSdc()); sta::PathEndSeq hold_ends = sta_->findPathEnds(nullptr, /* from */ nullptr, /* thrus */ - nullptr, /* to */ + hold_to, /* to */ true, /* unconstrained */ scenes, /* scenes */ sta::MinMaxAll::min(), /* min_max */ diff --git a/src/ram/test/make_7x7_2r1w_nangate45.ok b/src/ram/test/make_7x7_2r1w_nangate45.ok index 3e33dd0dc6f..ee1d4344e2a 100644 --- a/src/ram/test/make_7x7_2r1w_nangate45.ok +++ b/src/ram/test/make_7x7_2r1w_nangate45.ok @@ -114,7 +114,7 @@ [INFO DRT-0036] metal10 guide region query size = 0. [INFO DRT-0179] Init gr pin query. [INFO RAM-0044] RAM maximum path delay: 0.265 ns -[INFO RAM-0045] RAM minimum path delay: 0.000 ns +[INFO RAM-0045] RAM minimum path delay: 0.032 ns [INFO RAM-0046] RAM estimated power: 79128.938 nW No differences found. No differences found. diff --git a/src/ram/test/make_7x7_nangate45.ok b/src/ram/test/make_7x7_nangate45.ok index 2b8a5758efc..6e3eb64222e 100644 --- a/src/ram/test/make_7x7_nangate45.ok +++ b/src/ram/test/make_7x7_nangate45.ok @@ -110,7 +110,7 @@ [INFO DRT-0036] metal10 guide region query size = 0. [INFO DRT-0179] Init gr pin query. [INFO RAM-0044] RAM maximum path delay: 0.268 ns -[INFO RAM-0045] RAM minimum path delay: 0.000 ns +[INFO RAM-0045] RAM minimum path delay: 0.032 ns [INFO RAM-0046] RAM estimated power: 52755.473 nW No differences found. No differences found. diff --git a/src/ram/test/make_8x8_2r1w_sky130.ok b/src/ram/test/make_8x8_2r1w_sky130.ok index b8da039f221..46f94e9c7ee 100644 --- a/src/ram/test/make_8x8_2r1w_sky130.ok +++ b/src/ram/test/make_8x8_2r1w_sky130.ok @@ -68,7 +68,7 @@ [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. [INFO RAM-0044] RAM maximum path delay: 0.859 ns -[INFO RAM-0045] RAM minimum path delay: 0.000 ns +[INFO RAM-0045] RAM minimum path delay: 0.116 ns [INFO RAM-0046] RAM estimated power: 360445.062 nW No differences found. No differences found. diff --git a/src/ram/test/make_8x8_latch_sky130.ok b/src/ram/test/make_8x8_latch_sky130.ok index de04fdf4607..33331fa6713 100644 --- a/src/ram/test/make_8x8_latch_sky130.ok +++ b/src/ram/test/make_8x8_latch_sky130.ok @@ -68,7 +68,7 @@ [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. [INFO RAM-0044] RAM maximum path delay: 0.879 ns -[INFO RAM-0045] RAM minimum path delay: 0.000 ns +[INFO RAM-0045] RAM minimum path delay: 0.057 ns [INFO RAM-0046] RAM estimated power: 181922.922 nW No differences found. No differences found. diff --git a/src/ram/test/make_8x8_mux2_sky130.ok b/src/ram/test/make_8x8_mux2_sky130.ok index a79b50c4cac..fbc24e55370 100644 --- a/src/ram/test/make_8x8_mux2_sky130.ok +++ b/src/ram/test/make_8x8_mux2_sky130.ok @@ -68,7 +68,7 @@ [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. [INFO RAM-0044] RAM maximum path delay: 1.046 ns -[INFO RAM-0045] RAM minimum path delay: 0.000 ns +[INFO RAM-0045] RAM minimum path delay: 0.069 ns [INFO RAM-0046] RAM estimated power: 237089.828 nW No differences found. No differences found. diff --git a/src/ram/test/make_8x8_mux4_sky130.ok b/src/ram/test/make_8x8_mux4_sky130.ok index 572d9494e1f..f9e6cf597ca 100644 --- a/src/ram/test/make_8x8_mux4_sky130.ok +++ b/src/ram/test/make_8x8_mux4_sky130.ok @@ -68,7 +68,7 @@ [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. [INFO RAM-0044] RAM maximum path delay: 1.424 ns -[INFO RAM-0045] RAM minimum path delay: 0.000 ns +[INFO RAM-0045] RAM minimum path delay: 0.025 ns [INFO RAM-0046] RAM estimated power: 253089.922 nW No differences found. No differences found. diff --git a/src/ram/test/make_8x8_sky130.ok b/src/ram/test/make_8x8_sky130.ok index 6856e8f5f6e..2e6e03b26cd 100644 --- a/src/ram/test/make_8x8_sky130.ok +++ b/src/ram/test/make_8x8_sky130.ok @@ -68,7 +68,7 @@ [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. [INFO RAM-0044] RAM maximum path delay: 0.879 ns -[INFO RAM-0045] RAM minimum path delay: 0.000 ns +[INFO RAM-0045] RAM minimum path delay: 0.116 ns [INFO RAM-0046] RAM estimated power: 232520.859 nW No differences found. No differences found. From af382e0daa1427bdbfb90273b7fc35b0c8caf3ac Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Tue, 7 Jul 2026 21:44:59 -0400 Subject: [PATCH 13/19] ram: add sta/SdcClass.hh include to fix clang tidy bazel Signed-off-by: Thinh Nguyen --- src/ram/src/ram.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/ram/src/ram.cpp b/src/ram/src/ram.cpp index 9c909fae0c7..06087928aab 100644 --- a/src/ram/src/ram.cpp +++ b/src/ram/src/ram.cpp @@ -37,6 +37,7 @@ #include "sta/PortDirection.hh" #include "sta/PowerClass.hh" #include "sta/Scene.hh" +#include "sta/SdcClass.hh" #include "sta/SearchClass.hh" #include "sta/Sequential.hh" #include "sta/StringUtil.hh" From 07a3ee1dbb53a9a0ef6294bdbe553da9d5e90796 Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Sat, 11 Jul 2026 14:34:51 -0400 Subject: [PATCH 14/19] ram: change reportTimingAndPower to include all non clock pins for analysis, run parasitic estimation before analysis Signed-off-by: Thinh Nguyen --- src/ram/src/ram.cpp | 64 +++++++++++++++---------- src/ram/src/ram.tcl | 1 + src/ram/test/make_7x7_2r1w_nangate45.ok | 6 +-- src/ram/test/make_7x7_nangate45.ok | 6 +-- src/ram/test/make_8x8_2r1w_sky130.ok | 6 +-- src/ram/test/make_8x8_latch_sky130.ok | 6 +-- src/ram/test/make_8x8_mux2_sky130.ok | 6 +-- src/ram/test/make_8x8_mux4_sky130.ok | 6 +-- src/ram/test/make_8x8_sky130.ok | 6 +-- 9 files changed, 62 insertions(+), 45 deletions(-) diff --git a/src/ram/src/ram.cpp b/src/ram/src/ram.cpp index 06087928aab..15b987f2ac4 100644 --- a/src/ram/src/ram.cpp +++ b/src/ram/src/ram.cpp @@ -2069,43 +2069,53 @@ endmodule logger_->info(RAM, 24, "Behavioral Verilog written for {}", module_name); } +static bool isClockPin(const sta::Pin* pin, sta::dbNetwork* network) +{ + sta::LibertyPort* lp = network->libertyPort(pin); + if (!lp) { + return false; + } + return lp->isClock() || lp->isRegClk() || lp->isClockGateClock(); +} + void RamGen::reportTimingAndPower() { network_->setBlock(block_); sta_->updateTiming(false); sta::SceneSeq scenes = sta_->makeSceneSeq(sta_->cmdScene()); - sta::StringSeq group_names; - // restrict path searches to the RAM's data endpoints (storage/latch - // D pins and primary Q outputs) since unconstrained searches - // also land on register and clock-gate CLK pins, which will - // report a misleading zero value for min path delay - // since no clock is defined for this automated test - auto collect_data_endpoints = [&]() -> sta::PinSet* { + // Exclude clock pins (register and latch CLK, clock-gate CLK). + // All other pins remain a valid start and end point for analysis + auto collect_non_clock_pins = [&]() -> sta::PinSet* { auto* pins = new sta::PinSet(network_); - odb::dbMaster* seq_cell = use_latch_ ? latch_cell_ : storage_cell_; - const auto& seq_ports = use_latch_ ? latch_ports_ : storage_ports_; - const std::string& data_in_mterm = seq_ports.at({PortRoleType::DataIn, 0}); - auto* mterm = seq_cell->findMTerm(data_in_mterm.c_str()); for (auto* inst : block_->getInsts()) { - if (inst->getMaster() == seq_cell) { - auto* iterm = inst->getITerm(mterm); - pins->insert(network_->dbToSta(iterm)); + for (auto* iterm : inst->getITerms()) { + auto* pin = network_->dbToSta(iterm); + if (pin && !isClockPin(pin, network_)) { + pins->insert(pin); + } } } - for (auto& port_outputs : q_outputs_) { - for (auto* bterm : port_outputs) { - pins->insert(network_->dbToSta(bterm)); + for (auto* bterm : block_->getBTerms()) { + auto* pin = network_->dbToSta(bterm); + if (pin && !isClockPin(pin, network_)) { + pins->insert(pin); } } return pins; }; // Find worst unconstrained setup path delay/longest path + sta::ExceptionFrom* setup_from + = sta_->makeExceptionFrom(collect_non_clock_pins(), + nullptr, + nullptr, + sta::RiseFallBoth::riseFall(), + sta_->cmdSdc()); sta::ExceptionTo* setup_to - = sta_->makeExceptionTo(collect_data_endpoints(), + = sta_->makeExceptionTo(collect_non_clock_pins(), nullptr, nullptr, sta::RiseFallBoth::riseFall(), @@ -2113,7 +2123,7 @@ void RamGen::reportTimingAndPower() sta_->cmdSdc()); sta::PathEndSeq setup_ends - = sta_->findPathEnds(nullptr, /* from */ + = sta_->findPathEnds(setup_from, /* from */ nullptr, /* thrus */ setup_to, /* to */ true, /* unconstrained */ @@ -2131,7 +2141,7 @@ void RamGen::reportTimingAndPower() false, /* hold */ false, /* recovery */ false, /* removal */ - false, /* clk_gating_setup */ + true, /* clk_gating_setup */ false); /* clk_gating_hold */ float setup_delay @@ -2140,15 +2150,22 @@ void RamGen::reportTimingAndPower() : static_cast(setup_ends[0]->dataArrivalTime(sta_)); // Find worst unconstrained hold path delay/shortest path + sta::ExceptionFrom* hold_from + = sta_->makeExceptionFrom(collect_non_clock_pins(), + nullptr, + nullptr, + sta::RiseFallBoth::riseFall(), + sta_->cmdSdc()); sta::ExceptionTo* hold_to - = sta_->makeExceptionTo(collect_data_endpoints(), + = sta_->makeExceptionTo(collect_non_clock_pins(), nullptr, nullptr, sta::RiseFallBoth::riseFall(), sta::RiseFallBoth::riseFall(), sta_->cmdSdc()); + sta::PathEndSeq hold_ends - = sta_->findPathEnds(nullptr, /* from */ + = sta_->findPathEnds(hold_from, /* from */ nullptr, /* thrus */ hold_to, /* to */ true, /* unconstrained */ @@ -2167,7 +2184,7 @@ void RamGen::reportTimingAndPower() false, /* recovery */ false, /* removal */ false, /* clk_gating_setup */ - false); /* clk_gating_hold */ + true); /* clk_gating_hold */ float hold_delay = hold_ends.empty() @@ -2186,7 +2203,6 @@ void RamGen::reportTimingAndPower() time_unit->asString(hold_delay), time_unit->scaleAbbrevSuffix()); - // Estimated power (STA applies a default activity when none is set) sta::PowerResult total, sequential, combinational, clock, macro, pad; sta_->power( sta_->cmdScene(), total, sequential, combinational, clock, macro, pad); diff --git a/src/ram/src/ram.tcl b/src/ram/src/ram.tcl index 322c99dfaf9..78b6d399fab 100644 --- a/src/ram/src/ram.tcl +++ b/src/ram/src/ram.tcl @@ -297,5 +297,6 @@ proc generate_ram { args } { ram::ram_filler $filler_cells ram::ram_routing + estimate_parasitics -global_routing ram::ram_report_timing_power } diff --git a/src/ram/test/make_7x7_2r1w_nangate45.ok b/src/ram/test/make_7x7_2r1w_nangate45.ok index ee1d4344e2a..8d682b98fb9 100644 --- a/src/ram/test/make_7x7_2r1w_nangate45.ok +++ b/src/ram/test/make_7x7_2r1w_nangate45.ok @@ -113,9 +113,9 @@ [INFO DRT-0036] via9 guide region query size = 0. [INFO DRT-0036] metal10 guide region query size = 0. [INFO DRT-0179] Init gr pin query. -[INFO RAM-0044] RAM maximum path delay: 0.265 ns -[INFO RAM-0045] RAM minimum path delay: 0.032 ns -[INFO RAM-0046] RAM estimated power: 79128.938 nW +[INFO RAM-0044] RAM maximum path delay: 0.284 ns +[INFO RAM-0045] RAM minimum path delay: 0.026 ns +[INFO RAM-0046] RAM estimated power: 84905.438 nW No differences found. No differences found. No differences found. diff --git a/src/ram/test/make_7x7_nangate45.ok b/src/ram/test/make_7x7_nangate45.ok index 6e3eb64222e..44ce76e04f4 100644 --- a/src/ram/test/make_7x7_nangate45.ok +++ b/src/ram/test/make_7x7_nangate45.ok @@ -109,9 +109,9 @@ [INFO DRT-0036] via9 guide region query size = 0. [INFO DRT-0036] metal10 guide region query size = 0. [INFO DRT-0179] Init gr pin query. -[INFO RAM-0044] RAM maximum path delay: 0.268 ns -[INFO RAM-0045] RAM minimum path delay: 0.032 ns -[INFO RAM-0046] RAM estimated power: 52755.473 nW +[INFO RAM-0044] RAM maximum path delay: 0.282 ns +[INFO RAM-0045] RAM minimum path delay: 0.026 ns +[INFO RAM-0046] RAM estimated power: 55594.766 nW No differences found. No differences found. No differences found. diff --git a/src/ram/test/make_8x8_2r1w_sky130.ok b/src/ram/test/make_8x8_2r1w_sky130.ok index 46f94e9c7ee..cfd18e41f13 100644 --- a/src/ram/test/make_8x8_2r1w_sky130.ok +++ b/src/ram/test/make_8x8_2r1w_sky130.ok @@ -67,9 +67,9 @@ [INFO DRT-0036] via4 guide region query size = 0. [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. -[INFO RAM-0044] RAM maximum path delay: 0.859 ns -[INFO RAM-0045] RAM minimum path delay: 0.116 ns -[INFO RAM-0046] RAM estimated power: 360445.062 nW +[INFO RAM-0044] RAM maximum path delay: 1.131 ns +[INFO RAM-0045] RAM minimum path delay: 0.103 ns +[INFO RAM-0046] RAM estimated power: 427698.656 nW No differences found. No differences found. No differences found. diff --git a/src/ram/test/make_8x8_latch_sky130.ok b/src/ram/test/make_8x8_latch_sky130.ok index 33331fa6713..f238a73b4c4 100644 --- a/src/ram/test/make_8x8_latch_sky130.ok +++ b/src/ram/test/make_8x8_latch_sky130.ok @@ -67,9 +67,9 @@ [INFO DRT-0036] via4 guide region query size = 0. [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. -[INFO RAM-0044] RAM maximum path delay: 0.879 ns -[INFO RAM-0045] RAM minimum path delay: 0.057 ns -[INFO RAM-0046] RAM estimated power: 181922.922 nW +[INFO RAM-0044] RAM maximum path delay: 1.118 ns +[INFO RAM-0045] RAM minimum path delay: 0.067 ns +[INFO RAM-0046] RAM estimated power: 208674.484 nW No differences found. No differences found. No differences found. diff --git a/src/ram/test/make_8x8_mux2_sky130.ok b/src/ram/test/make_8x8_mux2_sky130.ok index fbc24e55370..6c6ae48c6b2 100644 --- a/src/ram/test/make_8x8_mux2_sky130.ok +++ b/src/ram/test/make_8x8_mux2_sky130.ok @@ -67,9 +67,9 @@ [INFO DRT-0036] via4 guide region query size = 0. [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. -[INFO RAM-0044] RAM maximum path delay: 1.046 ns -[INFO RAM-0045] RAM minimum path delay: 0.069 ns -[INFO RAM-0046] RAM estimated power: 237089.828 nW +[INFO RAM-0044] RAM maximum path delay: 1.397 ns +[INFO RAM-0045] RAM minimum path delay: 0.091 ns +[INFO RAM-0046] RAM estimated power: 286239.875 nW No differences found. No differences found. No differences found. diff --git a/src/ram/test/make_8x8_mux4_sky130.ok b/src/ram/test/make_8x8_mux4_sky130.ok index f9e6cf597ca..0307c64aefd 100644 --- a/src/ram/test/make_8x8_mux4_sky130.ok +++ b/src/ram/test/make_8x8_mux4_sky130.ok @@ -67,9 +67,9 @@ [INFO DRT-0036] via4 guide region query size = 0. [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. -[INFO RAM-0044] RAM maximum path delay: 1.424 ns -[INFO RAM-0045] RAM minimum path delay: 0.025 ns -[INFO RAM-0046] RAM estimated power: 253089.922 nW +[INFO RAM-0044] RAM maximum path delay: 1.946 ns +[INFO RAM-0045] RAM minimum path delay: 0.032 ns +[INFO RAM-0046] RAM estimated power: 313878.781 nW No differences found. No differences found. No differences found. diff --git a/src/ram/test/make_8x8_sky130.ok b/src/ram/test/make_8x8_sky130.ok index 2e6e03b26cd..495fbbdf937 100644 --- a/src/ram/test/make_8x8_sky130.ok +++ b/src/ram/test/make_8x8_sky130.ok @@ -67,9 +67,9 @@ [INFO DRT-0036] via4 guide region query size = 0. [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. -[INFO RAM-0044] RAM maximum path delay: 0.879 ns -[INFO RAM-0045] RAM minimum path delay: 0.116 ns -[INFO RAM-0046] RAM estimated power: 232520.859 nW +[INFO RAM-0044] RAM maximum path delay: 1.114 ns +[INFO RAM-0045] RAM minimum path delay: 0.100 ns +[INFO RAM-0046] RAM estimated power: 265202.000 nW No differences found. No differences found. No differences found. From 06eb442f5b13990de3cd81c4891d2a64230aa178 Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Sun, 12 Jul 2026 10:55:54 -0400 Subject: [PATCH 15/19] ram: restrict reportTimingAndPower to non-clock inputs to all outputs Signed-off-by: Thinh Nguyen --- src/ram/include/ram/ram.h | 1 + src/ram/src/ram.cpp | 41 +++++++++++++++++++------ src/ram/test/make_7x7_2r1w_nangate45.ok | 2 +- src/ram/test/make_7x7_nangate45.ok | 2 +- src/ram/test/make_8x8_2r1w_sky130.ok | 2 +- src/ram/test/make_8x8_latch_sky130.ok | 2 +- src/ram/test/make_8x8_sky130.ok | 2 +- 7 files changed, 38 insertions(+), 14 deletions(-) diff --git a/src/ram/include/ram/ram.h b/src/ram/include/ram/ram.h index f944ce6dab9..6eae3c0046b 100644 --- a/src/ram/include/ram/ram.h +++ b/src/ram/include/ram/ram.h @@ -250,6 +250,7 @@ class RamGen std::vector> addr_inputs_; std::vector data_inputs_; + std::vector write_enable_; std::vector> q_outputs_; std::string behavioral_verilog_filename_; std::string aoi22_in_a1_, aoi22_in_a2_, aoi22_in_b1_, aoi22_in_b2_, diff --git a/src/ram/src/ram.cpp b/src/ram/src/ram.cpp index 15b987f2ac4..32b4b73be95 100644 --- a/src/ram/src/ram.cpp +++ b/src/ram/src/ram.cpp @@ -1288,6 +1288,7 @@ void RamGen::generate(const int mask_size, auto in_name = fmt::format("we[{}]", slice); write_enable[slice] = makeBTerm(in_name, dbIoType::INPUT); } + write_enable_ = write_enable; // When column_mux_ratio > 1: word_sel_nets[word_idx] is high/active when // word_idx is the addressed word within a physical row. Derived from the @@ -2086,21 +2087,41 @@ void RamGen::reportTimingAndPower() sta::SceneSeq scenes = sta_->makeSceneSeq(sta_->cmdScene()); sta::StringSeq group_names; - // Exclude clock pins (register and latch CLK, clock-gate CLK). - // All other pins remain a valid start and end point for analysis - auto collect_non_clock_pins = [&]() -> sta::PinSet* { + // Include non clock primary inputs: D, address, write enable pins + auto collect_primary_inputs = [&]() -> sta::PinSet* { + auto* pins = new sta::PinSet(network_); + for (auto* bterm : data_inputs_) { + pins->insert(network_->dbToSta(bterm)); + } + for (auto& port_addrs : addr_inputs_) { + for (auto* bterm : port_addrs) { + pins->insert(network_->dbToSta(bterm)); + } + } + for (auto* bterm : write_enable_) { + pins->insert(network_->dbToSta(bterm)); + } + return pins; + }; + + auto collect_all_outputs = [&]() -> sta::PinSet* { auto* pins = new sta::PinSet(network_); for (auto* inst : block_->getInsts()) { for (auto* iterm : inst->getITerms()) { auto* pin = network_->dbToSta(iterm); - if (pin && !isClockPin(pin, network_)) { + if (!pin || isClockPin(pin, network_)) { + continue; + } + auto* lp = network_->libertyPort(pin); + if (lp && lp->direction()->isAnyOutput()) { pins->insert(pin); } } } for (auto* bterm : block_->getBTerms()) { auto* pin = network_->dbToSta(bterm); - if (pin && !isClockPin(pin, network_)) { + if (pin && !isClockPin(pin, network_) + && network_->direction(pin)->isOutput()) { pins->insert(pin); } } @@ -2109,13 +2130,14 @@ void RamGen::reportTimingAndPower() // Find worst unconstrained setup path delay/longest path sta::ExceptionFrom* setup_from - = sta_->makeExceptionFrom(collect_non_clock_pins(), + = sta_->makeExceptionFrom(collect_primary_inputs(), nullptr, nullptr, sta::RiseFallBoth::riseFall(), sta_->cmdSdc()); + sta::ExceptionTo* setup_to - = sta_->makeExceptionTo(collect_non_clock_pins(), + = sta_->makeExceptionTo(collect_all_outputs(), nullptr, nullptr, sta::RiseFallBoth::riseFall(), @@ -2151,13 +2173,14 @@ void RamGen::reportTimingAndPower() // Find worst unconstrained hold path delay/shortest path sta::ExceptionFrom* hold_from - = sta_->makeExceptionFrom(collect_non_clock_pins(), + = sta_->makeExceptionFrom(collect_primary_inputs(), nullptr, nullptr, sta::RiseFallBoth::riseFall(), sta_->cmdSdc()); + sta::ExceptionTo* hold_to - = sta_->makeExceptionTo(collect_non_clock_pins(), + = sta_->makeExceptionTo(collect_all_outputs(), nullptr, nullptr, sta::RiseFallBoth::riseFall(), diff --git a/src/ram/test/make_7x7_2r1w_nangate45.ok b/src/ram/test/make_7x7_2r1w_nangate45.ok index 8d682b98fb9..edd813fb266 100644 --- a/src/ram/test/make_7x7_2r1w_nangate45.ok +++ b/src/ram/test/make_7x7_2r1w_nangate45.ok @@ -114,7 +114,7 @@ [INFO DRT-0036] metal10 guide region query size = 0. [INFO DRT-0179] Init gr pin query. [INFO RAM-0044] RAM maximum path delay: 0.284 ns -[INFO RAM-0045] RAM minimum path delay: 0.026 ns +[INFO RAM-0045] RAM minimum path delay: 0.116 ns [INFO RAM-0046] RAM estimated power: 84905.438 nW No differences found. No differences found. diff --git a/src/ram/test/make_7x7_nangate45.ok b/src/ram/test/make_7x7_nangate45.ok index 44ce76e04f4..d9434fca27a 100644 --- a/src/ram/test/make_7x7_nangate45.ok +++ b/src/ram/test/make_7x7_nangate45.ok @@ -110,7 +110,7 @@ [INFO DRT-0036] metal10 guide region query size = 0. [INFO DRT-0179] Init gr pin query. [INFO RAM-0044] RAM maximum path delay: 0.282 ns -[INFO RAM-0045] RAM minimum path delay: 0.026 ns +[INFO RAM-0045] RAM minimum path delay: 0.118 ns [INFO RAM-0046] RAM estimated power: 55594.766 nW No differences found. No differences found. diff --git a/src/ram/test/make_8x8_2r1w_sky130.ok b/src/ram/test/make_8x8_2r1w_sky130.ok index cfd18e41f13..1c7bf4a324a 100644 --- a/src/ram/test/make_8x8_2r1w_sky130.ok +++ b/src/ram/test/make_8x8_2r1w_sky130.ok @@ -68,7 +68,7 @@ [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. [INFO RAM-0044] RAM maximum path delay: 1.131 ns -[INFO RAM-0045] RAM minimum path delay: 0.103 ns +[INFO RAM-0045] RAM minimum path delay: 0.395 ns [INFO RAM-0046] RAM estimated power: 427698.656 nW No differences found. No differences found. diff --git a/src/ram/test/make_8x8_latch_sky130.ok b/src/ram/test/make_8x8_latch_sky130.ok index f238a73b4c4..bebe22d959e 100644 --- a/src/ram/test/make_8x8_latch_sky130.ok +++ b/src/ram/test/make_8x8_latch_sky130.ok @@ -68,7 +68,7 @@ [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. [INFO RAM-0044] RAM maximum path delay: 1.118 ns -[INFO RAM-0045] RAM minimum path delay: 0.067 ns +[INFO RAM-0045] RAM minimum path delay: 0.388 ns [INFO RAM-0046] RAM estimated power: 208674.484 nW No differences found. No differences found. diff --git a/src/ram/test/make_8x8_sky130.ok b/src/ram/test/make_8x8_sky130.ok index 495fbbdf937..12d1da2303a 100644 --- a/src/ram/test/make_8x8_sky130.ok +++ b/src/ram/test/make_8x8_sky130.ok @@ -68,7 +68,7 @@ [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. [INFO RAM-0044] RAM maximum path delay: 1.114 ns -[INFO RAM-0045] RAM minimum path delay: 0.100 ns +[INFO RAM-0045] RAM minimum path delay: 0.399 ns [INFO RAM-0046] RAM estimated power: 265202.000 nW No differences found. No differences found. From ae83037156a2999c1acd2f73f4826907ed951686 Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Sun, 12 Jul 2026 11:11:52 -0400 Subject: [PATCH 16/19] ram: retrigger ci build Signed-off-by: Thinh Nguyen From ade748433795d7e09bd7e31dafe69662df7bb9f8 Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Thu, 1 Oct 2026 13:11:49 -0400 Subject: [PATCH 17/19] ram: remove stray local test files and restore upstream test files Signed-off-by: Thinh Nguyen --- src/ram/test/BUILD | 6 - src/ram/test/make_7x7_2r1w_nangate45.ok | 3 - src/ram/test/make_7x7_nangate45.ok | 3 - src/ram/test/make_8x8_2r1w_sky130.ok | 3 - src/ram/test/make_8x8_latch_sky130.lefok | 50 +++--- src/ram/test/make_8x8_latch_sky130.ok | 75 --------- src/ram/test/make_8x8_latch_sky130.tcl | 1 - src/ram/test/make_8x8_mux2_sky130.lefok | 74 ++++----- src/ram/test/make_8x8_mux2_sky130.ok | 21 ++- src/ram/test/make_8x8_mux4_sky130.lefok | 194 +++++++++++------------ src/ram/test/make_8x8_mux4_sky130.ok | 29 ++-- src/ram/test/make_8x8_sky130.ok | 3 - 12 files changed, 181 insertions(+), 281 deletions(-) delete mode 100644 src/ram/test/make_8x8_latch_sky130.ok diff --git a/src/ram/test/BUILD b/src/ram/test/BUILD index 89370ad8d1b..071fa2c0f0b 100644 --- a/src/ram/test/BUILD +++ b/src/ram/test/BUILD @@ -9,9 +9,6 @@ COMPULSORY_TESTS = [ "make_7x7_2r1w_nangate45", "make_7x7_nangate45", "make_8x8_2r1w_sky130", - "make_8x8_latch_sky130", - "make_8x8_mux2_sky130", - "make_8x8_mux4_sky130", "make_8x8_sky130", ] @@ -67,9 +64,6 @@ filegroup( "Nangate45/Nangate45_typ.lib", ], "make_8x8_2r1w_sky130": ["make_8x8_2r1w_sky130_behavioral.vok"], - "make_8x8_latch_sky130": ["make_8x8_behavioral.vok"], - "make_8x8_mux2_sky130": ["make_8x8_behavioral.vok"], - "make_8x8_mux4_sky130": ["make_8x8_behavioral.vok"], "make_8x8_sky130": ["make_8x8_sky130_behavioral.vok"], }.get(test_name, []), ) diff --git a/src/ram/test/make_7x7_2r1w_nangate45.ok b/src/ram/test/make_7x7_2r1w_nangate45.ok index cdeec32e1ba..e2b03632f05 100644 --- a/src/ram/test/make_7x7_2r1w_nangate45.ok +++ b/src/ram/test/make_7x7_2r1w_nangate45.ok @@ -113,9 +113,6 @@ [INFO DRT-0036] via9 guide region query size = 0. [INFO DRT-0036] metal10 guide region query size = 0. [INFO DRT-0179] Init gr pin query. -[INFO RAM-0044] RAM maximum path delay: 0.284 ns -[INFO RAM-0045] RAM minimum path delay: 0.116 ns -[INFO RAM-0046] RAM estimated power: 84905.438 nW No differences found. No differences found. No differences found. diff --git a/src/ram/test/make_7x7_nangate45.ok b/src/ram/test/make_7x7_nangate45.ok index 1c642822627..7c45868bbda 100644 --- a/src/ram/test/make_7x7_nangate45.ok +++ b/src/ram/test/make_7x7_nangate45.ok @@ -109,9 +109,6 @@ [INFO DRT-0036] via9 guide region query size = 0. [INFO DRT-0036] metal10 guide region query size = 0. [INFO DRT-0179] Init gr pin query. -[INFO RAM-0044] RAM maximum path delay: 0.282 ns -[INFO RAM-0045] RAM minimum path delay: 0.118 ns -[INFO RAM-0046] RAM estimated power: 55594.766 nW No differences found. No differences found. No differences found. diff --git a/src/ram/test/make_8x8_2r1w_sky130.ok b/src/ram/test/make_8x8_2r1w_sky130.ok index 21823e197c9..fc0abe7aa2f 100644 --- a/src/ram/test/make_8x8_2r1w_sky130.ok +++ b/src/ram/test/make_8x8_2r1w_sky130.ok @@ -67,9 +67,6 @@ [INFO DRT-0036] via4 guide region query size = 0. [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. -[INFO RAM-0044] RAM maximum path delay: 1.131 ns -[INFO RAM-0045] RAM minimum path delay: 0.395 ns -[INFO RAM-0046] RAM estimated power: 427698.656 nW No differences found. No differences found. No differences found. diff --git a/src/ram/test/make_8x8_latch_sky130.lefok b/src/ram/test/make_8x8_latch_sky130.lefok index 462ef400a58..115ed50af8d 100644 --- a/src/ram/test/make_8x8_latch_sky130.lefok +++ b/src/ram/test/make_8x8_latch_sky130.lefok @@ -177,31 +177,6 @@ MACRO RAM8x8 RECT 76.52 26.715 76.66 27.2 ; END END Q[7] - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER met3 ; - RECT 95.38 9.76 95.68 10.24 ; - RECT 0 9.76 0.3 10.24 ; - LAYER met2 ; - RECT 59.76 27.06 60.24 27.2 ; - RECT 59.76 0 60.24 0.14 ; - RECT 19.76 27.06 20.24 27.2 ; - RECT 19.76 0 20.24 0.14 ; - LAYER met1 ; - RECT 95.54 24.24 95.68 24.72 ; - RECT 0 24.24 0.14 24.72 ; - RECT 95.54 18.8 95.68 19.28 ; - RECT 0 18.8 0.14 19.28 ; - RECT 95.54 13.36 95.68 13.84 ; - RECT 0 13.36 0.14 13.84 ; - RECT 95.54 7.92 95.68 8.4 ; - RECT 0 7.92 0.14 8.4 ; - RECT 95.54 2.48 95.68 2.96 ; - RECT 0 2.48 0.14 2.96 ; - END - END VDD PIN VSS DIRECTION INOUT ; USE GROUND ; @@ -229,6 +204,31 @@ MACRO RAM8x8 RECT 0 -0.24 0.14 0.24 ; END END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER met3 ; + RECT 95.38 9.76 95.68 10.24 ; + RECT 0 9.76 0.3 10.24 ; + LAYER met2 ; + RECT 59.76 27.06 60.24 27.2 ; + RECT 59.76 0 60.24 0.14 ; + RECT 19.76 27.06 20.24 27.2 ; + RECT 19.76 0 20.24 0.14 ; + LAYER met1 ; + RECT 95.54 24.24 95.68 24.72 ; + RECT 0 24.24 0.14 24.72 ; + RECT 95.54 18.8 95.68 19.28 ; + RECT 0 18.8 0.14 19.28 ; + RECT 95.54 13.36 95.68 13.84 ; + RECT 0 13.36 0.14 13.84 ; + RECT 95.54 7.92 95.68 8.4 ; + RECT 0 7.92 0.14 8.4 ; + RECT 95.54 2.48 95.68 2.96 ; + RECT 0 2.48 0.14 2.96 ; + END + END VDD OBS LAYER li1 ; RECT 0 -0.085 95.68 27.285 ; diff --git a/src/ram/test/make_8x8_latch_sky130.ok b/src/ram/test/make_8x8_latch_sky130.ok deleted file mode 100644 index bebe22d959e..00000000000 --- a/src/ram/test/make_8x8_latch_sky130.ok +++ /dev/null @@ -1,75 +0,0 @@ -[INFO ODB-0227] LEF file: sky130hd/sky130hd.tlef, created 13 layers, 25 vias -[INFO ODB-0227] LEF file: sky130hd/sky130_fd_sc_hd_merged.lef, created 437 library cells -[INFO RAM-0003] Generating RAM8x8 -[INFO RAM-0016] Selected inverter cell sky130_fd_sc_hd__clkinv_1 -[INFO RAM-0016] Selected tristate cell sky130_fd_sc_hd__ebufn_1 -[INFO RAM-0016] Selected and2 cell sky130_fd_sc_hd__and2_0 -[INFO RAM-0016] Selected clock gate cell sky130_fd_sc_hd__dlclkp_1 -[INFO RAM-0016] Selected buffer cell sky130_fd_sc_hd__buf_1 -[INFO RAM-0016] Selected aoi22 cell sky130_fd_sc_hd__a22oi_1 -[INFO RAM-0024] Behavioral Verilog written for RAM8x8 -[INFO PDN-0001] Inserting grid: ram_grid -[INFO PPL-0067] Restrict pins [ clk we[0] D[0] Q[0] D[1] ... ] to region 0.00u-95.68u at the TOP edge. -[INFO PPL-0067] Restrict pins [ addr_rw[0] addr_rw[1] addr_rw[2] ] to region 0.00u-27.20u at the RIGHT edge. -[INFO PPL-0001] Number of available slots 242 -[INFO PPL-0002] Number of I/O 21 -[INFO PPL-0003] Number of I/O w/sink 21 -[INFO PPL-0004] Number of I/O w/o sink 0 -[INFO PPL-0005] Slots per section 200 -[INFO PPL-0008] Successfully assigned pins to sections. -[INFO PPL-0012] I/O nets HPWL: 337.24 um. -[INFO DPL-0001] Placed 56 filler instances. -[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon -[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon -[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via -[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via -[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2 -[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2 -[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3 -[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3 -[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4 -[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4 -[INFO DRT-0167] List of default vias: - Layer via - default via: M1M2_PR - Layer via2 - default via: M2M3_PR - Layer via3 - default via: M3M4_PR - Layer via4 - default via: M4M5_PR -[INFO DRT-0168] Init region query. -[INFO DRT-0033] FR_MASTERSLICE shape region query size = 0. -[INFO DRT-0033] FR_VIA shape region query size = 0. -[INFO DRT-0033] li1 shape region query size = 6924. -[INFO DRT-0033] mcon shape region query size = 488. -[INFO DRT-0033] met1 shape region query size = 1231. -[INFO DRT-0033] via shape region query size = 22. -[INFO DRT-0033] met2 shape region query size = 56. -[INFO DRT-0033] via2 shape region query size = 4. -[INFO DRT-0033] met3 shape region query size = 13. -[INFO DRT-0033] via3 shape region query size = 0. -[INFO DRT-0033] met4 shape region query size = 0. -[INFO DRT-0033] via4 shape region query size = 0. -[INFO DRT-0033] met5 shape region query size = 0. -[INFO DRT-0178] Init guide query. -[INFO DRT-0036] FR_MASTERSLICE guide region query size = 0. -[INFO DRT-0036] FR_VIA guide region query size = 0. -[INFO DRT-0036] li1 guide region query size = 347. -[INFO DRT-0036] mcon guide region query size = 0. -[INFO DRT-0036] met1 guide region query size = 212. -[INFO DRT-0036] via guide region query size = 0. -[INFO DRT-0036] met2 guide region query size = 56. -[INFO DRT-0036] via2 guide region query size = 0. -[INFO DRT-0036] met3 guide region query size = 3. -[INFO DRT-0036] via3 guide region query size = 0. -[INFO DRT-0036] met4 guide region query size = 0. -[INFO DRT-0036] via4 guide region query size = 0. -[INFO DRT-0036] met5 guide region query size = 0. -[INFO DRT-0179] Init gr pin query. -[INFO RAM-0044] RAM maximum path delay: 1.118 ns -[INFO RAM-0045] RAM minimum path delay: 0.388 ns -[INFO RAM-0046] RAM estimated power: 208674.484 nW -No differences found. -No differences found. -No differences found. diff --git a/src/ram/test/make_8x8_latch_sky130.tcl b/src/ram/test/make_8x8_latch_sky130.tcl index 7407bc083ab..c37a8b581e4 100644 --- a/src/ram/test/make_8x8_latch_sky130.tcl +++ b/src/ram/test/make_8x8_latch_sky130.tcl @@ -15,7 +15,6 @@ generate_ram \ -num_words 8 \ -rw_ports 1 \ -use_latch 1 \ - -storage_cell sky130_fd_sc_hd__dlxtp_1 \ -routing_layer {met1 0.48} \ -ver_layer {met2 0.48 40} \ -hor_layer {met3 0.48 20} \ diff --git a/src/ram/test/make_8x8_mux2_sky130.lefok b/src/ram/test/make_8x8_mux2_sky130.lefok index 2f8e0be0c5f..3458860b559 100644 --- a/src/ram/test/make_8x8_mux2_sky130.lefok +++ b/src/ram/test/make_8x8_mux2_sky130.lefok @@ -177,6 +177,43 @@ MACRO RAM8x8 RECT 176.8 13.115 176.94 13.6 ; END END Q[7] + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER met3 ; + RECT 213.6 9.76 213.9 10.24 ; + RECT 0 9.76 0.3 10.24 ; + LAYER met2 ; + RECT 199.76 13.46 200.24 13.6 ; + RECT 199.76 0 200.24 0.14 ; + RECT 179.76 13.46 180.24 13.6 ; + RECT 179.76 0 180.24 0.14 ; + RECT 159.76 13.46 160.24 13.6 ; + RECT 159.76 0 160.24 0.14 ; + RECT 139.76 13.46 140.24 13.6 ; + RECT 139.76 0 140.24 0.14 ; + RECT 119.76 13.46 120.24 13.6 ; + RECT 119.76 0 120.24 0.14 ; + RECT 99.76 13.46 100.24 13.6 ; + RECT 99.76 0 100.24 0.14 ; + RECT 79.76 13.46 80.24 13.6 ; + RECT 79.76 0 80.24 0.14 ; + RECT 59.76 13.46 60.24 13.6 ; + RECT 59.76 0 60.24 0.14 ; + RECT 39.76 13.46 40.24 13.6 ; + RECT 39.76 0 40.24 0.14 ; + RECT 19.76 13.46 20.24 13.6 ; + RECT 19.76 0 20.24 0.14 ; + LAYER met1 ; + RECT 213.76 10.64 213.9 11.12 ; + RECT 0 10.64 0.14 11.12 ; + RECT 213.76 5.2 213.9 5.68 ; + RECT 0 5.2 0.14 5.68 ; + RECT 213.76 -0.24 213.9 0.24 ; + RECT 0 -0.24 0.14 0.24 ; + END + END VSS PIN VDD DIRECTION INOUT ; USE POWER ; @@ -216,43 +253,6 @@ MACRO RAM8x8 RECT 0 2.48 0.14 2.96 ; END END VDD - PIN VSS - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER met3 ; - RECT 213.6 9.76 213.9 10.24 ; - RECT 0 9.76 0.3 10.24 ; - LAYER met2 ; - RECT 199.76 13.46 200.24 13.6 ; - RECT 199.76 0 200.24 0.14 ; - RECT 179.76 13.46 180.24 13.6 ; - RECT 179.76 0 180.24 0.14 ; - RECT 159.76 13.46 160.24 13.6 ; - RECT 159.76 0 160.24 0.14 ; - RECT 139.76 13.46 140.24 13.6 ; - RECT 139.76 0 140.24 0.14 ; - RECT 119.76 13.46 120.24 13.6 ; - RECT 119.76 0 120.24 0.14 ; - RECT 99.76 13.46 100.24 13.6 ; - RECT 99.76 0 100.24 0.14 ; - RECT 79.76 13.46 80.24 13.6 ; - RECT 79.76 0 80.24 0.14 ; - RECT 59.76 13.46 60.24 13.6 ; - RECT 59.76 0 60.24 0.14 ; - RECT 39.76 13.46 40.24 13.6 ; - RECT 39.76 0 40.24 0.14 ; - RECT 19.76 13.46 20.24 13.6 ; - RECT 19.76 0 20.24 0.14 ; - LAYER met1 ; - RECT 213.76 10.64 213.9 11.12 ; - RECT 0 10.64 0.14 11.12 ; - RECT 213.76 5.2 213.9 5.68 ; - RECT 0 5.2 0.14 5.68 ; - RECT 213.76 -0.24 213.9 0.24 ; - RECT 0 -0.24 0.14 0.24 ; - END - END VSS OBS LAYER li1 ; RECT 0 -0.24 213.9 13.84 ; diff --git a/src/ram/test/make_8x8_mux2_sky130.ok b/src/ram/test/make_8x8_mux2_sky130.ok index 6c6ae48c6b2..1ffe78cb495 100644 --- a/src/ram/test/make_8x8_mux2_sky130.ok +++ b/src/ram/test/make_8x8_mux2_sky130.ok @@ -9,16 +9,16 @@ [INFO RAM-0016] Selected aoi22 cell sky130_fd_sc_hd__a22oi_1 [INFO RAM-0024] Behavioral Verilog written for RAM8x8 [INFO PDN-0001] Inserting grid: ram_grid -[INFO PPL-0067] Restrict pins [ clk we[0] D[0] Q[0] D[1] ... ] to region 0.00u-213.90u at the TOP edge. -[INFO PPL-0067] Restrict pins [ addr_rw[0] addr_rw[1] addr_rw[2] ] to region 0.00u-13.60u at the RIGHT edge. +[INFO PPL-0067] Restrict pins [ D[0] Q[0] D[1] Q[1] D[2] ... ] to region 0.00u-213.90u at the TOP edge. +[INFO PPL-0067] Restrict pins [ clk we[0] addr_rw[0] addr_rw[1] addr_rw[2] ... ] to region 0.00u-13.60u at the RIGHT edge. [INFO PPL-0001] Number of available slots 464 [INFO PPL-0002] Number of I/O 21 [INFO PPL-0003] Number of I/O w/sink 21 [INFO PPL-0004] Number of I/O w/o sink 0 [INFO PPL-0005] Slots per section 200 [INFO PPL-0008] Successfully assigned pins to sections. -[INFO PPL-0012] I/O nets HPWL: 373.75 um. -[INFO DPL-0001] Placed 77 filler instances. +[INFO PPL-0012] I/O nets HPWL: 389.01 um. +[INFO DPL-0001] Placed 80 filler instances. [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via @@ -41,13 +41,13 @@ [INFO DRT-0168] Init region query. [INFO DRT-0033] FR_MASTERSLICE shape region query size = 0. [INFO DRT-0033] FR_VIA shape region query size = 0. -[INFO DRT-0033] li1 shape region query size = 7779. +[INFO DRT-0033] li1 shape region query size = 7785. [INFO DRT-0033] mcon shape region query size = 574. -[INFO DRT-0033] met1 shape region query size = 1359. +[INFO DRT-0033] met1 shape region query size = 1365. [INFO DRT-0033] via shape region query size = 63. -[INFO DRT-0033] met2 shape region query size = 165. +[INFO DRT-0033] met2 shape region query size = 163. [INFO DRT-0033] via2 shape region query size = 21. -[INFO DRT-0033] met3 shape region query size = 30. +[INFO DRT-0033] met3 shape region query size = 32. [INFO DRT-0033] via3 shape region query size = 0. [INFO DRT-0033] met4 shape region query size = 0. [INFO DRT-0033] via4 shape region query size = 0. @@ -61,15 +61,12 @@ [INFO DRT-0036] via guide region query size = 0. [INFO DRT-0036] met2 guide region query size = 21. [INFO DRT-0036] via2 guide region query size = 0. -[INFO DRT-0036] met3 guide region query size = 3. +[INFO DRT-0036] met3 guide region query size = 5. [INFO DRT-0036] via3 guide region query size = 0. [INFO DRT-0036] met4 guide region query size = 0. [INFO DRT-0036] via4 guide region query size = 0. [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. -[INFO RAM-0044] RAM maximum path delay: 1.397 ns -[INFO RAM-0045] RAM minimum path delay: 0.091 ns -[INFO RAM-0046] RAM estimated power: 286239.875 nW No differences found. No differences found. No differences found. diff --git a/src/ram/test/make_8x8_mux4_sky130.lefok b/src/ram/test/make_8x8_mux4_sky130.lefok index dc3fb381c1f..fce97e84ac7 100644 --- a/src/ram/test/make_8x8_mux4_sky130.lefok +++ b/src/ram/test/make_8x8_mux4_sky130.lefok @@ -177,6 +177,103 @@ MACRO RAM8x8 RECT 347 7.675 347.14 8.16 ; END END Q[7] + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER met3 ; + RECT 419.68 6.76 419.98 7.24 ; + RECT 0 6.76 0.3 7.24 ; + LAYER met2 ; + RECT 409.76 8.02 410.24 8.16 ; + RECT 409.76 0 410.24 0.14 ; + RECT 399.76 8.02 400.24 8.16 ; + RECT 399.76 0 400.24 0.14 ; + RECT 389.76 8.02 390.24 8.16 ; + RECT 389.76 0 390.24 0.14 ; + RECT 379.76 8.02 380.24 8.16 ; + RECT 379.76 0 380.24 0.14 ; + RECT 369.76 8.02 370.24 8.16 ; + RECT 369.76 0 370.24 0.14 ; + RECT 359.76 8.02 360.24 8.16 ; + RECT 359.76 0 360.24 0.14 ; + RECT 349.76 8.02 350.24 8.16 ; + RECT 349.76 0 350.24 0.14 ; + RECT 339.76 8.02 340.24 8.16 ; + RECT 339.76 0 340.24 0.14 ; + RECT 329.76 8.02 330.24 8.16 ; + RECT 329.76 0 330.24 0.14 ; + RECT 319.76 8.02 320.24 8.16 ; + RECT 319.76 0 320.24 0.14 ; + RECT 309.76 8.02 310.24 8.16 ; + RECT 309.76 0 310.24 0.14 ; + RECT 299.76 8.02 300.24 8.16 ; + RECT 299.76 0 300.24 0.14 ; + RECT 289.76 8.02 290.24 8.16 ; + RECT 289.76 0 290.24 0.14 ; + RECT 279.76 8.02 280.24 8.16 ; + RECT 279.76 0 280.24 0.14 ; + RECT 269.76 8.02 270.24 8.16 ; + RECT 269.76 0 270.24 0.14 ; + RECT 259.76 8.02 260.24 8.16 ; + RECT 259.76 0 260.24 0.14 ; + RECT 249.76 8.02 250.24 8.16 ; + RECT 249.76 0 250.24 0.14 ; + RECT 239.76 8.02 240.24 8.16 ; + RECT 239.76 0 240.24 0.14 ; + RECT 229.76 8.02 230.24 8.16 ; + RECT 229.76 0 230.24 0.14 ; + RECT 219.76 8.02 220.24 8.16 ; + RECT 219.76 0 220.24 0.14 ; + RECT 209.76 8.02 210.24 8.16 ; + RECT 209.76 0 210.24 0.14 ; + RECT 199.76 8.02 200.24 8.16 ; + RECT 199.76 0 200.24 0.14 ; + RECT 189.76 8.02 190.24 8.16 ; + RECT 189.76 0 190.24 0.14 ; + RECT 179.76 8.02 180.24 8.16 ; + RECT 179.76 0 180.24 0.14 ; + RECT 169.76 8.02 170.24 8.16 ; + RECT 169.76 0 170.24 0.14 ; + RECT 159.76 8.02 160.24 8.16 ; + RECT 159.76 0 160.24 0.14 ; + RECT 149.76 8.02 150.24 8.16 ; + RECT 149.76 0 150.24 0.14 ; + RECT 139.76 8.02 140.24 8.16 ; + RECT 139.76 0 140.24 0.14 ; + RECT 129.76 8.02 130.24 8.16 ; + RECT 129.76 0 130.24 0.14 ; + RECT 119.76 8.02 120.24 8.16 ; + RECT 119.76 0 120.24 0.14 ; + RECT 109.76 8.02 110.24 8.16 ; + RECT 109.76 0 110.24 0.14 ; + RECT 99.76 8.02 100.24 8.16 ; + RECT 99.76 0 100.24 0.14 ; + RECT 89.76 8.02 90.24 8.16 ; + RECT 89.76 0 90.24 0.14 ; + RECT 79.76 8.02 80.24 8.16 ; + RECT 79.76 0 80.24 0.14 ; + RECT 69.76 8.02 70.24 8.16 ; + RECT 69.76 0 70.24 0.14 ; + RECT 59.76 8.02 60.24 8.16 ; + RECT 59.76 0 60.24 0.14 ; + RECT 49.76 8.02 50.24 8.16 ; + RECT 49.76 0 50.24 0.14 ; + RECT 39.76 8.02 40.24 8.16 ; + RECT 39.76 0 40.24 0.14 ; + RECT 29.76 8.02 30.24 8.16 ; + RECT 29.76 0 30.24 0.14 ; + RECT 19.76 8.02 20.24 8.16 ; + RECT 19.76 0 20.24 0.14 ; + RECT 9.76 8.02 10.24 8.16 ; + RECT 9.76 0 10.24 0.14 ; + LAYER met1 ; + RECT 419.84 5.2 419.98 5.68 ; + RECT 0 5.2 0.14 5.68 ; + RECT 419.84 -0.24 419.98 0.24 ; + RECT 0 -0.24 0.14 0.24 ; + END + END VSS PIN VDD DIRECTION INOUT ; USE POWER ; @@ -276,103 +373,6 @@ MACRO RAM8x8 RECT 0 2.48 0.14 2.96 ; END END VDD - PIN VSS - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER met3 ; - RECT 419.68 6.76 419.98 7.24 ; - RECT 0 6.76 0.3 7.24 ; - LAYER met2 ; - RECT 409.76 8.02 410.24 8.16 ; - RECT 409.76 0 410.24 0.14 ; - RECT 399.76 8.02 400.24 8.16 ; - RECT 399.76 0 400.24 0.14 ; - RECT 389.76 8.02 390.24 8.16 ; - RECT 389.76 0 390.24 0.14 ; - RECT 379.76 8.02 380.24 8.16 ; - RECT 379.76 0 380.24 0.14 ; - RECT 369.76 8.02 370.24 8.16 ; - RECT 369.76 0 370.24 0.14 ; - RECT 359.76 8.02 360.24 8.16 ; - RECT 359.76 0 360.24 0.14 ; - RECT 349.76 8.02 350.24 8.16 ; - RECT 349.76 0 350.24 0.14 ; - RECT 339.76 8.02 340.24 8.16 ; - RECT 339.76 0 340.24 0.14 ; - RECT 329.76 8.02 330.24 8.16 ; - RECT 329.76 0 330.24 0.14 ; - RECT 319.76 8.02 320.24 8.16 ; - RECT 319.76 0 320.24 0.14 ; - RECT 309.76 8.02 310.24 8.16 ; - RECT 309.76 0 310.24 0.14 ; - RECT 299.76 8.02 300.24 8.16 ; - RECT 299.76 0 300.24 0.14 ; - RECT 289.76 8.02 290.24 8.16 ; - RECT 289.76 0 290.24 0.14 ; - RECT 279.76 8.02 280.24 8.16 ; - RECT 279.76 0 280.24 0.14 ; - RECT 269.76 8.02 270.24 8.16 ; - RECT 269.76 0 270.24 0.14 ; - RECT 259.76 8.02 260.24 8.16 ; - RECT 259.76 0 260.24 0.14 ; - RECT 249.76 8.02 250.24 8.16 ; - RECT 249.76 0 250.24 0.14 ; - RECT 239.76 8.02 240.24 8.16 ; - RECT 239.76 0 240.24 0.14 ; - RECT 229.76 8.02 230.24 8.16 ; - RECT 229.76 0 230.24 0.14 ; - RECT 219.76 8.02 220.24 8.16 ; - RECT 219.76 0 220.24 0.14 ; - RECT 209.76 8.02 210.24 8.16 ; - RECT 209.76 0 210.24 0.14 ; - RECT 199.76 8.02 200.24 8.16 ; - RECT 199.76 0 200.24 0.14 ; - RECT 189.76 8.02 190.24 8.16 ; - RECT 189.76 0 190.24 0.14 ; - RECT 179.76 8.02 180.24 8.16 ; - RECT 179.76 0 180.24 0.14 ; - RECT 169.76 8.02 170.24 8.16 ; - RECT 169.76 0 170.24 0.14 ; - RECT 159.76 8.02 160.24 8.16 ; - RECT 159.76 0 160.24 0.14 ; - RECT 149.76 8.02 150.24 8.16 ; - RECT 149.76 0 150.24 0.14 ; - RECT 139.76 8.02 140.24 8.16 ; - RECT 139.76 0 140.24 0.14 ; - RECT 129.76 8.02 130.24 8.16 ; - RECT 129.76 0 130.24 0.14 ; - RECT 119.76 8.02 120.24 8.16 ; - RECT 119.76 0 120.24 0.14 ; - RECT 109.76 8.02 110.24 8.16 ; - RECT 109.76 0 110.24 0.14 ; - RECT 99.76 8.02 100.24 8.16 ; - RECT 99.76 0 100.24 0.14 ; - RECT 89.76 8.02 90.24 8.16 ; - RECT 89.76 0 90.24 0.14 ; - RECT 79.76 8.02 80.24 8.16 ; - RECT 79.76 0 80.24 0.14 ; - RECT 69.76 8.02 70.24 8.16 ; - RECT 69.76 0 70.24 0.14 ; - RECT 59.76 8.02 60.24 8.16 ; - RECT 59.76 0 60.24 0.14 ; - RECT 49.76 8.02 50.24 8.16 ; - RECT 49.76 0 50.24 0.14 ; - RECT 39.76 8.02 40.24 8.16 ; - RECT 39.76 0 40.24 0.14 ; - RECT 29.76 8.02 30.24 8.16 ; - RECT 29.76 0 30.24 0.14 ; - RECT 19.76 8.02 20.24 8.16 ; - RECT 19.76 0 20.24 0.14 ; - RECT 9.76 8.02 10.24 8.16 ; - RECT 9.76 0 10.24 0.14 ; - LAYER met1 ; - RECT 419.84 5.2 419.98 5.68 ; - RECT 0 5.2 0.14 5.68 ; - RECT 419.84 -0.24 419.98 0.24 ; - RECT 0 -0.24 0.14 0.24 ; - END - END VSS OBS LAYER li1 ; RECT 0 -0.24 419.98 8.4 ; diff --git a/src/ram/test/make_8x8_mux4_sky130.ok b/src/ram/test/make_8x8_mux4_sky130.ok index 0307c64aefd..81984d8476d 100644 --- a/src/ram/test/make_8x8_mux4_sky130.ok +++ b/src/ram/test/make_8x8_mux4_sky130.ok @@ -9,16 +9,16 @@ [INFO RAM-0016] Selected aoi22 cell sky130_fd_sc_hd__a22oi_1 [INFO RAM-0024] Behavioral Verilog written for RAM8x8 [INFO PDN-0001] Inserting grid: ram_grid -[INFO PPL-0067] Restrict pins [ clk we[0] D[0] Q[0] D[1] ... ] to region 0.00u-419.98u at the TOP edge. -[INFO PPL-0067] Restrict pins [ addr_rw[0] addr_rw[1] addr_rw[2] ] to region 0.00u-8.16u at the RIGHT edge. -[INFO PPL-0001] Number of available slots 836 +[INFO PPL-0067] Restrict pins [ D[0] Q[0] D[1] Q[1] D[2] ... ] to region 0.00u-417.68u at the TOP edge. +[INFO PPL-0067] Restrict pins [ clk we[0] addr_rw[0] addr_rw[1] addr_rw[2] ... ] to region 0.00u-8.16u at the RIGHT edge. +[INFO PPL-0001] Number of available slots 830 [INFO PPL-0002] Number of I/O 21 [INFO PPL-0003] Number of I/O w/sink 21 [INFO PPL-0004] Number of I/O w/o sink 0 [INFO PPL-0005] Slots per section 200 [INFO PPL-0008] Successfully assigned pins to sections. -[INFO PPL-0012] I/O nets HPWL: 945.54 um. -[INFO DPL-0001] Placed 122 filler instances. +[INFO PPL-0012] I/O nets HPWL: 990.17 um. +[INFO DPL-0001] Placed 120 filler instances. [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via @@ -41,13 +41,13 @@ [INFO DRT-0168] Init region query. [INFO DRT-0033] FR_MASTERSLICE shape region query size = 0. [INFO DRT-0033] FR_VIA shape region query size = 0. -[INFO DRT-0033] li1 shape region query size = 8307. -[INFO DRT-0033] mcon shape region query size = 606. -[INFO DRT-0033] met1 shape region query size = 1590. +[INFO DRT-0033] li1 shape region query size = 8229. +[INFO DRT-0033] mcon shape region query size = 600. +[INFO DRT-0033] met1 shape region query size = 1572. [INFO DRT-0033] via shape region query size = 166. -[INFO DRT-0033] met2 shape region query size = 516. +[INFO DRT-0033] met2 shape region query size = 514. [INFO DRT-0033] via2 shape region query size = 83. -[INFO DRT-0033] met3 shape region query size = 92. +[INFO DRT-0033] met3 shape region query size = 94. [INFO DRT-0033] via3 shape region query size = 0. [INFO DRT-0033] met4 shape region query size = 0. [INFO DRT-0033] via4 shape region query size = 0. @@ -55,21 +55,18 @@ [INFO DRT-0178] Init guide query. [INFO DRT-0036] FR_MASTERSLICE guide region query size = 0. [INFO DRT-0036] FR_VIA guide region query size = 0. -[INFO DRT-0036] li1 guide region query size = 449. +[INFO DRT-0036] li1 guide region query size = 440. [INFO DRT-0036] mcon guide region query size = 0. -[INFO DRT-0036] met1 guide region query size = 299. +[INFO DRT-0036] met1 guide region query size = 293. [INFO DRT-0036] via guide region query size = 0. [INFO DRT-0036] met2 guide region query size = 73. [INFO DRT-0036] via2 guide region query size = 0. -[INFO DRT-0036] met3 guide region query size = 43. +[INFO DRT-0036] met3 guide region query size = 45. [INFO DRT-0036] via3 guide region query size = 0. [INFO DRT-0036] met4 guide region query size = 0. [INFO DRT-0036] via4 guide region query size = 0. [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. -[INFO RAM-0044] RAM maximum path delay: 1.946 ns -[INFO RAM-0045] RAM minimum path delay: 0.032 ns -[INFO RAM-0046] RAM estimated power: 313878.781 nW No differences found. No differences found. No differences found. diff --git a/src/ram/test/make_8x8_sky130.ok b/src/ram/test/make_8x8_sky130.ok index 66cefc2c8d6..a395beb2bbe 100644 --- a/src/ram/test/make_8x8_sky130.ok +++ b/src/ram/test/make_8x8_sky130.ok @@ -67,9 +67,6 @@ [INFO DRT-0036] via4 guide region query size = 0. [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. -[INFO RAM-0044] RAM maximum path delay: 1.114 ns -[INFO RAM-0045] RAM minimum path delay: 0.399 ns -[INFO RAM-0046] RAM estimated power: 265202.000 nW No differences found. No differences found. No differences found. From 2bfbf560e88b84928afa8dacfab4ce8d0b18c7ed Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Fri, 2 Oct 2026 16:32:21 -0400 Subject: [PATCH 18/19] ram: use critical path delay obtained from timing analysis as clock period for power report Signed-off-by: Thinh Nguyen --- src/ram/include/ram/ram.h | 3 ++- src/ram/src/ram.cpp | 18 +++++++++++++++++- src/ram/src/ram.i | 10 ++++++++-- src/ram/src/ram.tcl | 8 ++++++-- src/ram/test/make_7x7_2r1w_nangate45.ok | 4 ++++ src/ram/test/make_7x7_nangate45.ok | 4 ++++ src/ram/test/make_8x8_2r1w_sky130.ok | 4 ++++ src/ram/test/make_8x8_sky130.ok | 4 ++++ 8 files changed, 49 insertions(+), 6 deletions(-) diff --git a/src/ram/include/ram/ram.h b/src/ram/include/ram/ram.h index 6eae3c0046b..16b18902299 100644 --- a/src/ram/include/ram/ram.h +++ b/src/ram/include/ram/ram.h @@ -134,7 +134,8 @@ class RamGen int r_ports, int w_ports); - void reportTimingAndPower(); + double reportTiming(); + void reportPower(); private: void findMasters(); diff --git a/src/ram/src/ram.cpp b/src/ram/src/ram.cpp index 32b4b73be95..5159a7e8b25 100644 --- a/src/ram/src/ram.cpp +++ b/src/ram/src/ram.cpp @@ -2079,7 +2079,7 @@ static bool isClockPin(const sta::Pin* pin, sta::dbNetwork* network) return lp->isClock() || lp->isRegClk() || lp->isClockGateClock(); } -void RamGen::reportTimingAndPower() +double RamGen::reportTiming() { network_->setBlock(block_); sta_->updateTiming(false); @@ -2226,6 +2226,22 @@ void RamGen::reportTimingAndPower() time_unit->asString(hold_delay), time_unit->scaleAbbrevSuffix()); + if (setup_delay <= 0.0F) { + return 0.0; + } + logger_->info(RAM, + 47, + "Using maximum path delay of {} {} as the clock period for " + "power estimation", + time_unit->asString(setup_delay), + time_unit->scaleAbbrevSuffix()); + return time_unit->staToUser(setup_delay); +} + +void RamGen::reportPower() +{ + sta_->updateTiming(false); + sta::PowerResult total, sequential, combinational, clock, macro, pad; sta_->power( sta_->cmdScene(), total, sequential, combinational, clock, macro, pad); diff --git a/src/ram/src/ram.i b/src/ram/src/ram.i index f01ade007bc..9cefb9aab90 100644 --- a/src/ram/src/ram.i +++ b/src/ram/src/ram.i @@ -127,10 +127,16 @@ void ram_routing() ram_gen->ramRouting(thread_count); } -void ram_report_timing_power() +double ram_report_timing() { RamGen* ram_gen = ord::getRamGen(); - ram_gen->reportTimingAndPower(); + return ram_gen->reportTiming(); +} + +void ram_report_power() +{ + RamGen* ram_gen = ord::getRamGen(); + ram_gen->reportPower(); } void set_behavioral_verilog_filename(const char* filename) diff --git a/src/ram/src/ram.tcl b/src/ram/src/ram.tcl index 78b6d399fab..eb9b9c5cf81 100644 --- a/src/ram/src/ram.tcl +++ b/src/ram/src/ram.tcl @@ -298,5 +298,9 @@ proc generate_ram { args } { ram::ram_routing estimate_parasitics -global_routing - ram::ram_report_timing_power -} + set clock_period [ram::ram_report_timing] + if { $clock_period > 0 } { + create_clock -name ram_clk -period $clock_period [get_ports clk] + } + ram::ram_report_power +} \ No newline at end of file diff --git a/src/ram/test/make_7x7_2r1w_nangate45.ok b/src/ram/test/make_7x7_2r1w_nangate45.ok index e2b03632f05..a3058ad666c 100644 --- a/src/ram/test/make_7x7_2r1w_nangate45.ok +++ b/src/ram/test/make_7x7_2r1w_nangate45.ok @@ -113,6 +113,10 @@ [INFO DRT-0036] via9 guide region query size = 0. [INFO DRT-0036] metal10 guide region query size = 0. [INFO DRT-0179] Init gr pin query. +[INFO RAM-0044] RAM maximum path delay: 0.284 ns +[INFO RAM-0045] RAM minimum path delay: 0.116 ns +[INFO RAM-0047] Using maximum path delay of 0.284 ns as the clock period for power estimation +[INFO RAM-0046] RAM estimated power: 749876.125 nW No differences found. No differences found. No differences found. diff --git a/src/ram/test/make_7x7_nangate45.ok b/src/ram/test/make_7x7_nangate45.ok index 7c45868bbda..420c371f5f6 100644 --- a/src/ram/test/make_7x7_nangate45.ok +++ b/src/ram/test/make_7x7_nangate45.ok @@ -109,6 +109,10 @@ [INFO DRT-0036] via9 guide region query size = 0. [INFO DRT-0036] metal10 guide region query size = 0. [INFO DRT-0179] Init gr pin query. +[INFO RAM-0044] RAM maximum path delay: 0.282 ns +[INFO RAM-0045] RAM minimum path delay: 0.118 ns +[INFO RAM-0047] Using maximum path delay of 0.282 ns as the clock period for power estimation +[INFO RAM-0046] RAM estimated power: 550985.750 nW No differences found. No differences found. No differences found. diff --git a/src/ram/test/make_8x8_2r1w_sky130.ok b/src/ram/test/make_8x8_2r1w_sky130.ok index fc0abe7aa2f..068370c6955 100644 --- a/src/ram/test/make_8x8_2r1w_sky130.ok +++ b/src/ram/test/make_8x8_2r1w_sky130.ok @@ -67,6 +67,10 @@ [INFO DRT-0036] via4 guide region query size = 0. [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. +[INFO RAM-0044] RAM maximum path delay: 1.131 ns +[INFO RAM-0045] RAM minimum path delay: 0.395 ns +[INFO RAM-0047] Using maximum path delay of 1.131 ns as the clock period for power estimation +[INFO RAM-0046] RAM estimated power: 1161060.500 nW No differences found. No differences found. No differences found. diff --git a/src/ram/test/make_8x8_sky130.ok b/src/ram/test/make_8x8_sky130.ok index a395beb2bbe..d4ff2fb4ca6 100644 --- a/src/ram/test/make_8x8_sky130.ok +++ b/src/ram/test/make_8x8_sky130.ok @@ -67,6 +67,10 @@ [INFO DRT-0036] via4 guide region query size = 0. [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. +[INFO RAM-0044] RAM maximum path delay: 1.114 ns +[INFO RAM-0045] RAM minimum path delay: 0.399 ns +[INFO RAM-0047] Using maximum path delay of 1.114 ns as the clock period for power estimation +[INFO RAM-0046] RAM estimated power: 848681.312 nW No differences found. No differences found. No differences found. From 05f18386acee21540aa9267d8dc45b0351b298ed Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Fri, 2 Oct 2026 16:52:14 -0400 Subject: [PATCH 19/19] ram: add trailing newline to ram.tcl Signed-off-by: Thinh Nguyen --- src/ram/src/ram.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ram/src/ram.tcl b/src/ram/src/ram.tcl index eb9b9c5cf81..8c843d3f0d9 100644 --- a/src/ram/src/ram.tcl +++ b/src/ram/src/ram.tcl @@ -303,4 +303,4 @@ proc generate_ram { args } { create_clock -name ram_clk -period $clock_period [get_ports clk] } ram::ram_report_power -} \ No newline at end of file +}