From 0dde1cf2c558ebc575ec8e52b1272e1ca54b5e30 Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Mon, 6 Jul 2026 17:22:36 -0400 Subject: [PATCH 1/2] ram: remove explicit power_pin/ground_pin args from 2r1w test tcl files Signed-off-by: Thinh Nguyen --- src/ram/test/BUILD | 11 ++++- src/ram/test/make_7x7_2r1w_nangate45.lefok | 56 +++++++++++----------- src/ram/test/make_7x7_2r1w_nangate45.ok | 2 +- src/ram/test/make_7x7_2r1w_nangate45.tcl | 2 - src/ram/test/make_8x8_2r1w_sky130.lefok | 54 ++++++++++----------- src/ram/test/make_8x8_2r1w_sky130.ok | 2 +- src/ram/test/make_8x8_2r1w_sky130.tcl | 2 - 7 files changed, 67 insertions(+), 62 deletions(-) diff --git a/src/ram/test/BUILD b/src/ram/test/BUILD index 56e658c7f35..071fa2c0f0b 100644 --- a/src/ram/test/BUILD +++ b/src/ram/test/BUILD @@ -6,8 +6,10 @@ package(features = ["layering_check"]) # From CMakeLists.txt or_integration_tests(TESTS COMPULSORY_TESTS = [ - "make_8x8_sky130", + "make_7x7_2r1w_nangate45", "make_7x7_nangate45", + "make_8x8_2r1w_sky130", + "make_8x8_sky130", ] PASSFAIL_TESTS = [ @@ -49,12 +51,19 @@ filegroup( test_name + ".*", ], ) + { + "make_7x7_2r1w_nangate45": [ + "make_7x7_2r1w_nangate45_behavioral.vok", + "Nangate45/Nangate45.lef", + "Nangate45/Nangate45_tech.lef", + "Nangate45/Nangate45_typ.lib", + ], "make_7x7_nangate45": [ "make_7x7_nangate45_behavioral.vok", "Nangate45/Nangate45.lef", "Nangate45/Nangate45_tech.lef", "Nangate45/Nangate45_typ.lib", ], + "make_8x8_2r1w_sky130": ["make_8x8_2r1w_sky130_behavioral.vok"], "make_8x8_sky130": ["make_8x8_sky130_behavioral.vok"], }.get(test_name, []), ) diff --git a/src/ram/test/make_7x7_2r1w_nangate45.lefok b/src/ram/test/make_7x7_2r1w_nangate45.lefok index dd81f2346cd..720b8a596c0 100644 --- a/src/ram/test/make_7x7_2r1w_nangate45.lefok +++ b/src/ram/test/make_7x7_2r1w_nangate45.lefok @@ -265,6 +265,34 @@ MACRO RAM7x7 RECT 43.705 11.06 43.845 11.2 ; END END Q1[6] + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER metal4 ; + RECT 49.43 11.06 49.57 11.2 ; + RECT 49.43 0 49.57 0.14 ; + RECT 40.43 11.06 40.57 11.2 ; + RECT 40.43 0 40.57 0.14 ; + RECT 31.43 11.06 31.57 11.2 ; + RECT 31.43 0 31.57 0.14 ; + RECT 22.43 11.06 22.57 11.2 ; + RECT 22.43 0 22.57 0.14 ; + RECT 13.43 11.06 13.57 11.2 ; + RECT 13.43 0 13.57 0.14 ; + RECT 4.43 11.06 4.57 11.2 ; + RECT 4.43 0 4.57 0.14 ; + LAYER metal1 ; + RECT 56.55 9.76 56.62 9.84 ; + RECT 0 9.76 0.07 9.84 ; + RECT 56.55 6.96 56.62 7.04 ; + RECT 0 6.96 0.07 7.04 ; + RECT 56.55 4.16 56.62 4.24 ; + RECT 0 4.16 0.07 4.24 ; + RECT 56.55 1.36 56.62 1.44 ; + RECT 0 1.36 0.07 1.44 ; + END + END VDD PIN VSS DIRECTION INOUT ; USE GROUND ; @@ -295,34 +323,6 @@ MACRO RAM7x7 RECT 0 -0.04 0.07 0.04 ; END END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER metal4 ; - RECT 49.43 11.06 49.57 11.2 ; - RECT 49.43 0 49.57 0.14 ; - RECT 40.43 11.06 40.57 11.2 ; - RECT 40.43 0 40.57 0.14 ; - RECT 31.43 11.06 31.57 11.2 ; - RECT 31.43 0 31.57 0.14 ; - RECT 22.43 11.06 22.57 11.2 ; - RECT 22.43 0 22.57 0.14 ; - RECT 13.43 11.06 13.57 11.2 ; - RECT 13.43 0 13.57 0.14 ; - RECT 4.43 11.06 4.57 11.2 ; - RECT 4.43 0 4.57 0.14 ; - LAYER metal1 ; - RECT 56.55 9.76 56.62 9.84 ; - RECT 0 9.76 0.07 9.84 ; - RECT 56.55 6.96 56.62 7.04 ; - RECT 0 6.96 0.07 7.04 ; - RECT 56.55 4.16 56.62 4.24 ; - RECT 0 4.16 0.07 4.24 ; - RECT 56.55 1.36 56.62 1.44 ; - RECT 0 1.36 0.07 1.44 ; - END - END VDD OBS LAYER metal1 ; RECT 0 -0.07 56.62 11.27 ; diff --git a/src/ram/test/make_7x7_2r1w_nangate45.ok b/src/ram/test/make_7x7_2r1w_nangate45.ok index c2bd7f38f28..9bd44e8d530 100644 --- a/src/ram/test/make_7x7_2r1w_nangate45.ok +++ b/src/ram/test/make_7x7_2r1w_nangate45.ok @@ -115,4 +115,4 @@ [INFO DRT-0179] Init gr pin query. No differences found. No differences found. -No differences found. \ No newline at end of file +No differences found. diff --git a/src/ram/test/make_7x7_2r1w_nangate45.tcl b/src/ram/test/make_7x7_2r1w_nangate45.tcl index d6e6a5fe06b..b260fbfe52a 100644 --- a/src/ram/test/make_7x7_2r1w_nangate45.tcl +++ b/src/ram/test/make_7x7_2r1w_nangate45.tcl @@ -16,8 +16,6 @@ generate_ram \ -r_ports 2 \ -w_ports 1 \ -storage_cell DFF_X1 \ - -power_pin VDD \ - -ground_pin VSS \ -routing_layer {metal1 0.08} \ -ver_layer {metal4 0.14 9} \ -hor_layer {metal3 0.08 8} \ diff --git a/src/ram/test/make_8x8_2r1w_sky130.lefok b/src/ram/test/make_8x8_2r1w_sky130.lefok index 176762136a9..1dd6adc2541 100644 --- a/src/ram/test/make_8x8_2r1w_sky130.lefok +++ b/src/ram/test/make_8x8_2r1w_sky130.lefok @@ -289,33 +289,6 @@ MACRO RAM8x8 RECT 120.68 23.995 120.82 24.48 ; END END Q1[7] - PIN VSS - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER met3 ; - RECT 154.72 19.76 155.02 20.24 ; - RECT 0 19.76 0.3 20.24 ; - LAYER met2 ; - RECT 119.76 24.34 120.24 24.48 ; - RECT 119.76 0 120.24 0.14 ; - RECT 79.76 24.34 80.24 24.48 ; - RECT 79.76 0 80.24 0.14 ; - RECT 39.76 24.34 40.24 24.48 ; - RECT 39.76 0 40.24 0.14 ; - LAYER met1 ; - RECT 154.88 21.52 155.02 22 ; - RECT 0 21.52 0.14 22 ; - RECT 154.88 16.08 155.02 16.56 ; - RECT 0 16.08 0.14 16.56 ; - RECT 154.88 10.64 155.02 11.12 ; - RECT 0 10.64 0.14 11.12 ; - RECT 154.88 5.2 155.02 5.68 ; - RECT 0 5.2 0.14 5.68 ; - RECT 154.88 -0.24 155.02 0.24 ; - RECT 0 -0.24 0.14 0.24 ; - END - END VSS PIN VDD DIRECTION INOUT ; USE POWER ; @@ -345,6 +318,33 @@ MACRO RAM8x8 RECT 0 2.48 0.14 2.96 ; END END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER met3 ; + RECT 154.72 19.76 155.02 20.24 ; + RECT 0 19.76 0.3 20.24 ; + LAYER met2 ; + RECT 119.76 24.34 120.24 24.48 ; + RECT 119.76 0 120.24 0.14 ; + RECT 79.76 24.34 80.24 24.48 ; + RECT 79.76 0 80.24 0.14 ; + RECT 39.76 24.34 40.24 24.48 ; + RECT 39.76 0 40.24 0.14 ; + LAYER met1 ; + RECT 154.88 21.52 155.02 22 ; + RECT 0 21.52 0.14 22 ; + RECT 154.88 16.08 155.02 16.56 ; + RECT 0 16.08 0.14 16.56 ; + RECT 154.88 10.64 155.02 11.12 ; + RECT 0 10.64 0.14 11.12 ; + RECT 154.88 5.2 155.02 5.68 ; + RECT 0 5.2 0.14 5.68 ; + RECT 154.88 -0.24 155.02 0.24 ; + RECT 0 -0.24 0.14 0.24 ; + END + END VSS OBS LAYER li1 ; RECT 0 -0.24 155.02 24.72 ; diff --git a/src/ram/test/make_8x8_2r1w_sky130.ok b/src/ram/test/make_8x8_2r1w_sky130.ok index 957b0fe912a..23473ee77ed 100644 --- a/src/ram/test/make_8x8_2r1w_sky130.ok +++ b/src/ram/test/make_8x8_2r1w_sky130.ok @@ -10,7 +10,7 @@ [INFO RAM-0024] Behavioral Verilog written for RAM8x8 [INFO PDN-0001] Inserting grid: ram_grid [INFO PPL-0067] Restrict pins [ clk we[0] D[0] Q0[0] Q1[0] ... ] to region 0.00u-155.02u at the TOP edge. -[INFO PPL-0067] Restrict pins [ addr_w[0][0] addr_w[0][1] addr_w[0][2] addr_r[0][0] addr_r[0][1] ... ] to region 0.00u-24.48u at the RIGHT edge. +[INFO PPL-0067] Restrict pins [ addr_w[0] addr_w[1] addr_w[2] addr_r0[0] addr_r0[1] ... ] to region 0.00u-24.48u at the RIGHT edge. [INFO PPL-0001] Number of available slots 364 [INFO PPL-0002] Number of I/O 35 [INFO PPL-0003] Number of I/O w/sink 35 diff --git a/src/ram/test/make_8x8_2r1w_sky130.tcl b/src/ram/test/make_8x8_2r1w_sky130.tcl index b150dac1f8c..c3c764571b9 100644 --- a/src/ram/test/make_8x8_2r1w_sky130.tcl +++ b/src/ram/test/make_8x8_2r1w_sky130.tcl @@ -16,8 +16,6 @@ generate_ram \ -r_ports 2 \ -w_ports 1 \ -storage_cell sky130_fd_sc_hd__dfxtp_1 \ - -power_pin VPWR \ - -ground_pin VGND \ -routing_layer {met1 0.48} \ -ver_layer {met2 0.48 40} \ -hor_layer {met3 0.48 20} \ From 8ae331161d9ff1946d88ab695f5fccee3bec5d07 Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Tue, 7 Jul 2026 09:57:07 -0400 Subject: [PATCH 2/2] ram:fix typo in 8x8_2r1w_sky130 tcl file Signed-off-by: Thinh Nguyen --- src/ram/test/make_8x8_2r1w_sky130.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ram/test/make_8x8_2r1w_sky130.tcl b/src/ram/test/make_8x8_2r1w_sky130.tcl index c3c764571b9..2f00932978c 100644 --- a/src/ram/test/make_8x8_2r1w_sky130.tcl +++ b/src/ram/test/make_8x8_2r1w_sky130.tcl @@ -7,7 +7,7 @@ read_liberty sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib read_lef sky130hd/sky130hd.tlef read_lef sky130hd/sky130_fd_sc_hd_merged.lef -set behavioral_file [make_result_file make_8x8_1rw1r_behavioral.v] +set behavioral_file [make_result_file make_8x8_2rw1r_behavioral.v] generate_ram \ -mask_size 8 \