From 291e78b7f4e8246f3f2df45b938e6fb3ff72b42f Mon Sep 17 00:00:00 2001 From: dgaddy Date: Mon, 17 Aug 2026 13:11:59 -0700 Subject: [PATCH 1/7] gt2n: wire ORFS platform + FakeRAM tooling infrastructure Adds the ORFS-side patches needed for any gt2n build: flow/BUILD's platform allowlist (glob/file-type rules) didn't include gt2n, and gt2n has no OpenRCX rules so final_report.tcl needs an empty SPEF stub to satisfy declared build outputs. Registers gt2n in defs.bzl's PDK map. Bumps tools/bsg_fakeram to the gt2n analytical-path work (bitcell + timing constants + explicit pin layer overrides) and updates regenerate_sram.sh to skip the CACTI-binary check for analytical tech nodes, which gt2n (tech_nm=2) uses instead of CACTI. Documents the bsg_fakeram cfg snap-grid key mismatch (snake_case vs camelCase) fixed for gt2n NVDLA cfgs via this tooling. --- CLAUDE.md | 1 + MODULE.bazel | 2 ++ defs.bzl | 1 + patches/orfs-gt2n-flow-build.patch | 24 ++++++++++++++++++++++++ patches/orfs-no-rcx-spef-stub.patch | 10 ++++++++++ tools/bsg_fakeram | 2 +- tools/regenerate_sram.sh | 10 +++++++--- 7 files changed, 46 insertions(+), 4 deletions(-) create mode 100644 patches/orfs-gt2n-flow-build.patch create mode 100644 patches/orfs-no-rcx-spef-stub.patch diff --git a/CLAUDE.md b/CLAUDE.md index ba2f430c..5275f06c 100644 --- a/CLAUDE.md +++ b/CLAUDE.md @@ -144,6 +144,7 @@ Designs in this repo carry workarounds for upstream tool bugs. Update this table | **GRT-0183 heap underflow in `repair_antennas`** — `updateRouteGridsLayer` in `FastRoute.cpp` modified the routing grids vector in-place; when two jumpers were inserted on the same net at adjacent positions, their promoted endpoints merged into a single same-layer chain. `releaseNetResources` then decremented a `uint16_t` usage counter for an edge that was never incremented, wrapping to 65535. Triggered by sky130hd's high post-DRT antenna violation count (→ many diodes + jumpers, high probability of adjacent jumpers on the same net). | sky130hd NVDLA `partition_c` (baseline floorplan) | Local patch `patches/openroad-grt-0183-fix.patch` (upstream PR #10743, merged 2026-06-24). Remove once OR pin advances past 2026-06-24. | (this PR) | [OpenROAD#10156](https://github.com/The-OpenROAD-Project/OpenROAD/issues/10156), [#10273](https://github.com/The-OpenROAD-Project/OpenROAD/issues/10273) | | **OpenSTA `write_sdc` instance-name corruption** (new in OpenROAD 299f3015) — expanding a wildcard `set_false_path -to [get_pin */SETN]` / `*/RESETN` writes corrupted (invalid-UTF-8) instance names into `1_synth.sdc`; Tcl 9's strict UTF-8 then hard-fails floorplan reading it (`error reading "fileN": invalid or incomplete multibyte`) | NVDLA `partition_m` (asap7/sky130hd), `partition_c` (asap7/nangate45) | Remove the two redundant `-to [get_pin */SETN\|/RESETN]` async-reset false-paths from `constraint.sdc` (reset sources are already `-from` false-pathed and the reset nets are `set_ideal_network`, so no real timed path is lost) | (this PR) | None filed yet | | **bsg_fakeram `wd_in` LEF direction** — `generate_lef.py` set pin `DIRECTION` by physical die side, not function, so the upper half of every write-data bus was `OUTPUT` in LEF while Liberty said `input`; OpenROAD PnR shorted half of each `wd_in` bus → unroutable GRT-0116 (cnn-sky130hd net: 1964 iterms / 512 bogus drivers) | every fakeram design's pre-`c83ecb4` LEF (Section A + B); all prior `_final` passes invalid | Fork fix `c83ecb4` (submodule bumped `044c02b9`); regenerate all macros via `tools/regenerate_sram.sh` / `tools/reconstruct_cfg_from_lef.py`; vortex's 6 unsizable macros → FF-fallback | `c83ecb4` / `044c02b9` | Pre-existing in fork since `0e1b3c00` (Oct 2025); fixed in VLSIDA/bsg_fakeram | +| **bsg_fakeram snap-grid key mismatch** — cfg files set `snap_width_nm`/`snap_height_nm` (snake_case), but `class_process.py` only reads `snapWidth_nm`/`snapHeight_nm` (camelCase) and silently falls back to a 1 nm grid on a miss, so the intended platform site-grid snap never applies. Confirmed on committed asap7 LEF (`fakeram_64x256_1r1w`: `SIZE 107.137 BY 66.961` — divides evenly by 0.001 µm, not by the intended 0.190/1.400 µm grid) | **Every asap7 fakeram cfg in the repo** (NVDLA, cnn, coralnpu, NyuziProcessor, vortex, ternip, bp_processor, liteeth, litepci, eyeriss, snitch_cluster) — all use the wrong snake_case keys. nangate45/sky130hd cfgs are unaffected (correctly use camelCase). Suspected contributor to asap7 macro designs with unresolved timing/congestion (not yet confirmed) | Fixed so far only for gt2n `NVDLA` cfgs (this PR) — renamed keys, regenerated via `tools/regenerate_sram.sh`, confirmed macros now land on-grid. **asap7 cfgs across the suite not yet fixed or regenerated** — flagged for follow-up, no designs rebuilt against this yet | (this PR, gt2n only) | None filed yet | | **CTS-0105** false skip — yosys hierarchical synthesis output port buffers arrive in ODB with `dbSourceType::TIMING` instead of `NETLIST`; CTS skips them as pre-existing clock buffers and leaves the clock net unbuffered | asap7 NyuziProcessor; asap7/nangate45/sky130hd `bp_quad`, `bp_uno` | `PRE_CTS_TCL` script resets affected buffers' `dbSourceType` from `TIMING` → `NETLIST` before CTS runs | `81b0ed4b` | [OpenROAD#10177](https://github.com/The-OpenROAD-Project/OpenROAD/issues/10177) | | **MPL-0040** — `rtl_macro_placer` annealing failure on certain macro clusters | asap7 `bp_quad` (pipe_fma cluster), asap7 `cnn` | Hand-place fakeram macros in left-edge columns at FIRM status via `macros.tcl` so RTLMP only sees pre-placed macros; for cnn also drop `CORE_UTILIZATION` 65→60 | `09542e19` | [OpenROAD#9985](https://github.com/The-OpenROAD-Project/OpenROAD/issues/9985) | | **ODB-1200** in `repair_timing` — `InsertBufferBeforeLoads` iterates a stale load list and aborts the flow with `Load pin '...' is not connected to net '...'`. Triggered by the resizer's `SplitLoadMove` step in CTS-time repair_timing | asap7 `liteeth`; sky130hd `NyuziProcessor`; asap7 `NyuziProcessor` (surfaced post-wd_in-fix); asap7 `bp_quad`; asap7 `gemmini` | Most designs: `SKIP_CTS_REPAIR_TIMING = 1` (skips the whole repair pass; route still does its own hold-repair). Gemmini: drop `split_load` from `SETUP_MOVE_SEQUENCE` (`"unbuffer,sizeup,swap,buffer,clone"`) — keeps the rest of repair_timing working (try this first). asap7 `NyuziProcessor`: split_load-drop did **not** clear it (ODB-1200 recurred via another move) → escalated to the full `SKIP_CTS_REPAIR_TIMING = 1` | `87829fdb` | [HighTide#75](https://github.com/VLSIDA/HighTide/issues/75) | diff --git a/MODULE.bazel b/MODULE.bazel index b681540a..e98e306a 100644 --- a/MODULE.bazel +++ b/MODULE.bazel @@ -56,6 +56,8 @@ archive_override( patch_strip = 1, patches = [ "//patches:0036-fix-bazel-orfs-bazel_dep-non-dev-for-load-visibility.patch", + "//patches:orfs-gt2n-flow-build.patch", + "//patches:orfs-no-rcx-spef-stub.patch", ], strip_prefix = "OpenROAD-flow-scripts-fb65d5b487d2afd443fc1892330f622c776a57ac", urls = ["https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/archive/fb65d5b487d2afd443fc1892330f622c776a57ac.tar.gz"], diff --git a/defs.bzl b/defs.bzl index dec95584..4d91cb4b 100644 --- a/defs.bzl +++ b/defs.bzl @@ -5,6 +5,7 @@ load("@bazel-orfs//:openroad.bzl", "orfs_flow", "orfs_run") # PDK label mapping per platform PDKS = { "asap7": "@orfs//flow:asap7", + "gt2n": "@orfs//flow:gt2n", "nangate45": "@orfs//flow:nangate45", "sky130hd": "@orfs//flow:sky130hd", } diff --git a/patches/orfs-gt2n-flow-build.patch b/patches/orfs-gt2n-flow-build.patch new file mode 100644 index 00000000..72ad8760 --- /dev/null +++ b/patches/orfs-gt2n-flow-build.patch @@ -0,0 +1,24 @@ +--- a/flow/BUILD ++++ b/flow/BUILD +@@ -99,4 +99,14 @@ + "tcl", + "v", + ], ++ "gt2n": [ ++ "gds", ++ "lef", ++ "lib", ++ "lyt", ++ "lyp", ++ "mk", ++ "tcl", ++ "v", ++ ], + "ihp-sg13g2": [ +@@ -171,5 +181,6 @@ + "ihp-sg13g2", + "nangate45", + "sky130hd", + "sky130hs", ++ "gt2n", + ]] diff --git a/patches/orfs-no-rcx-spef-stub.patch b/patches/orfs-no-rcx-spef-stub.patch new file mode 100644 index 00000000..ebe7afb7 --- /dev/null +++ b/patches/orfs-no-rcx-spef-stub.patch @@ -0,0 +1,10 @@ +--- a/flow/scripts/final_report.tcl ++++ b/flow/scripts/final_report.tcl +@@ -56,4 +56,6 @@ + } else { + puts "OpenRCX is not enabled for this platform." + puts "Falling back to global route-based estimates." + log_cmd estimate_parasitics -global_routing ++ # No RCX rules: write an empty SPEF so declared build outputs are satisfied. ++ close [open $::env(RESULTS_DIR)/6_final.spef w] + } diff --git a/tools/bsg_fakeram b/tools/bsg_fakeram index c83ecb47..d7a0c2e0 160000 --- a/tools/bsg_fakeram +++ b/tools/bsg_fakeram @@ -1 +1 @@ -Subproject commit c83ecb47f5a90d2e92d589b4f63a2e38c25c1afd +Subproject commit d7a0c2e099648e6f2290675433240b64ec8832ca diff --git a/tools/regenerate_sram.sh b/tools/regenerate_sram.sh index 8b8690bb..7734fe51 100755 --- a/tools/regenerate_sram.sh +++ b/tools/regenerate_sram.sh @@ -28,9 +28,13 @@ if [[ ! -f "$CFG" ]]; then echo "error: no cfg at $CFG" >&2 exit 1 fi -if [[ ! -x "$ROOT/tools/bsg_fakeram/tools/cacti/cacti" ]]; then - echo "error: CACTI binary not built; run 'cd tools/bsg_fakeram && make tools'" >&2 - exit 1 +# Analytical tech nodes (7, 130, 2) skip CACTI entirely — only check if needed. +_TECH_NM=$(python3 -c "import json,sys; print(json.load(open(sys.argv[1]))['tech_nm'])" "$CFG" 2>/dev/null || echo "0") +if [[ "$_TECH_NM" != "7" && "$_TECH_NM" != "130" && "$_TECH_NM" != "2" ]]; then + if [[ ! -x "$ROOT/tools/bsg_fakeram/tools/cacti/cacti" ]]; then + echo "error: CACTI binary not built; run 'cd tools/bsg_fakeram && make tools'" >&2 + exit 1 + fi fi mkdir -p "$DST_LEF" "$DST_LIB" From 6fefbd34052d4072ca7949017854917eb485dc22 Mon Sep 17 00:00:00 2001 From: dgaddy Date: Mon, 17 Aug 2026 13:17:32 -0700 Subject: [PATCH 2/7] gt2n: port lfsr Reaches _final with 0 DRC/timing violations. CORE_UTILIZATION=80 (PLACE_DENSITY 0.85), MAX_ROUTING_LAYER=M11, MIN_CLK_ROUTING_LAYER=M4, clock period 160ps (period_min 139.38ps, ratio 1.15). --- designs/gt2n/lfsr/BUILD.bazel | 16 ++++++++++++++++ designs/gt2n/lfsr/constraint.sdc | 15 +++++++++++++++ designs/src/lfsr/DECISIONS.md | 23 +++++++++++++++++++++++ 3 files changed, 54 insertions(+) create mode 100644 designs/gt2n/lfsr/BUILD.bazel create mode 100644 designs/gt2n/lfsr/constraint.sdc diff --git a/designs/gt2n/lfsr/BUILD.bazel b/designs/gt2n/lfsr/BUILD.bazel new file mode 100644 index 00000000..07c2513d --- /dev/null +++ b/designs/gt2n/lfsr/BUILD.bazel @@ -0,0 +1,16 @@ +load("//:defs.bzl", "hightide_design") + +hightide_design( + name = "lfsr", + top = "lfsr_prbs_gen", + platform = "gt2n", + verilog_files = ["//designs/src/lfsr:rtl"], + sources = {"SDC_FILE": [":constraint.sdc"]}, + arguments = { + "CORE_UTILIZATION": "80", + "PLACE_DENSITY": "0.85", + "MAX_ROUTING_LAYER": "M11", + "MIN_CLK_ROUTING_LAYER": "M4", + "TNS_END_PERCENT": "100", + }, +) diff --git a/designs/gt2n/lfsr/constraint.sdc b/designs/gt2n/lfsr/constraint.sdc new file mode 100644 index 00000000..7ef8da10 --- /dev/null +++ b/designs/gt2n/lfsr/constraint.sdc @@ -0,0 +1,15 @@ +current_design lfsr_prbs_gen + +set clk_name core_clock +set clk_port_name clk +set clk_period 160 +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_port_name] + +create_clock -name $clk_name -period $clk_period $clk_port + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] + +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/designs/src/lfsr/DECISIONS.md b/designs/src/lfsr/DECISIONS.md index 74515d43..6e23b706 100644 --- a/designs/src/lfsr/DECISIONS.md +++ b/designs/src/lfsr/DECISIONS.md @@ -59,3 +59,26 @@ The three RTL files are no longer a git submodule + checked-in vendored copy. Th ### Known issues / open questions - None. + +## gt2n + +**Status**: finishing +**Last updated**: 2026-08-13 + +### Configuration +- `CORE_UTILIZATION = 80`, `PLACE_DENSITY = 0.85` +- `MAX_ROUTING_LAYER = M11`, `MIN_CLK_ROUTING_LAYER = M4` +- `TNS_END_PERCENT = 100` +- Clock: `160 ps` (period_min 139.38 ps; ratio 1.15) + +### Decisions +- **Platform bringup**: lfsr was the first gt2n design ported; two ORFS-side patches and a bsg_fakeram bump were required before any gt2n build could complete, and apply to every subsequent gt2n design (see the infra commit): + - **`orfs-gt2n-flow-build.patch`**: ORFS `flow/BUILD` hardcodes a per-platform allowlist for its Bazel glob/file-type rules; omitted gt2n. + - **`orfs-no-rcx-spef-stub.patch`**: gt2n has no OpenRCX rules file, so ORFS never writes a SPEF; Bazel's declared-output contract requires `6_final.spef` to exist. Patch writes an empty SPEF when RCX isn't enabled. + - **bsg_fakeram bump**: gt2n analytical bitcell/timing/pin-layer support. +- Reaches `_final` with WNS = 0, 0 DRC violations. Congestion never exceeded ~25% usage on any layer. +- **No antenna cells**: gt2n PDK ships no antenna filler cells. GRT-0246 ("no antenna cell found in the design library") fires on every gt2n build — benign; the router uses wire-jumping to resolve antenna violations, reaching 0 antenna DRC violations in the final report. +- **Backside PDN**: gt2n uses BSPDN (BPR followpins → BM1 → BM2 stripes, entirely on the backside stack). Signal layers M1–M13 carry no power. No `pdn.tcl` override is needed for std-cell-only designs — `platforms/gt2n/pdn.cfg` handles BSPDN correctly out of the box. + +### Known issues / open questions +- None. From 7a01fa6b1fe759ec61a6103e242c92d472343879 Mon Sep 17 00:00:00 2001 From: dgaddy Date: Mon, 17 Aug 2026 13:22:26 -0700 Subject: [PATCH 3/7] gt2n: port sha3 Reaches _final with 0 DRC/timing violations. CORE_UTILIZATION=75 (PLACE_DENSITY 0.85), MAX_ROUTING_LAYER=M11, MIN_CLK_ROUTING_LAYER=M4, HOLD_SLACK_MARGIN=3, clock period 425ps (period_min 423.17ps, ratio 1.004). --- designs/gt2n/sha3/BUILD.bazel | 16 ++++++++++++++++ designs/gt2n/sha3/constraint.sdc | 13 +++++++++++++ designs/src/sha3/DECISIONS.md | 18 ++++++++++++++++++ 3 files changed, 47 insertions(+) create mode 100644 designs/gt2n/sha3/BUILD.bazel create mode 100644 designs/gt2n/sha3/constraint.sdc diff --git a/designs/gt2n/sha3/BUILD.bazel b/designs/gt2n/sha3/BUILD.bazel new file mode 100644 index 00000000..0a66cff9 --- /dev/null +++ b/designs/gt2n/sha3/BUILD.bazel @@ -0,0 +1,16 @@ +load("//:defs.bzl", "hightide_design") + +hightide_design( + name = "sha3", + platform = "gt2n", + verilog_files = ["//designs/src/sha3:rtl"], + sources = {"SDC_FILE": [":constraint.sdc"]}, + arguments = { + "CORE_UTILIZATION": "75", + "PLACE_DENSITY": "0.85", + "MAX_ROUTING_LAYER": "M11", + "MIN_CLK_ROUTING_LAYER": "M4", + "HOLD_SLACK_MARGIN": "3", + "TNS_END_PERCENT": "100", + }, +) diff --git a/designs/gt2n/sha3/constraint.sdc b/designs/gt2n/sha3/constraint.sdc new file mode 100644 index 00000000..76777bc1 --- /dev/null +++ b/designs/gt2n/sha3/constraint.sdc @@ -0,0 +1,13 @@ +current_design sha3 + +set clk_name clk +set clk_port_name clock +set clk_period 425 + +set clk_port [get_ports $clk_port_name] + +create_clock -name $clk_name -period $clk_period $clk_port + +set non_clock_inputs [all_inputs -no_clocks] +set_input_delay 10 -clock $clk_name $non_clock_inputs +set_output_delay 10 -clock $clk_name [all_outputs] diff --git a/designs/src/sha3/DECISIONS.md b/designs/src/sha3/DECISIONS.md index f13b2d48..c4f40f67 100644 --- a/designs/src/sha3/DECISIONS.md +++ b/designs/src/sha3/DECISIONS.md @@ -93,3 +93,21 @@ Mid-size combinational-heavy core (~20k stdcells, no macros). ### Known issues / open questions - None. + +## gt2n + +**Status**: finishing +**Last updated**: 2026-08-14 + +### Configuration +- `CORE_UTILIZATION = 75`, `PLACE_DENSITY = 0.85` +- `MAX_ROUTING_LAYER = M11`, `MIN_CLK_ROUTING_LAYER = M4` +- `TNS_END_PERCENT = 100` +- Clock: `425 ps` (period_min 423.17 ps, ratio 1.004) + +### Decisions +- Reaches `_final` with 0 DRC/timing violations. +- **`HOLD_SLACK_MARGIN = 3`**: needed to clear small IO-input-path hold violations at this clock target without paying a clock-period cost. + +### Known issues / open questions +- None. From 934f62f7a919caa8020ca96584f6b8a2a40db433 Mon Sep 17 00:00:00 2001 From: dgaddy Date: Mon, 17 Aug 2026 13:25:17 -0700 Subject: [PATCH 4/7] gt2n: port minimax Reaches _final with CORE_UTILIZATION=60 (PLACE_DENSITY 0.7, CORE_ASPECT_RATIO 1.0, CORE_MARGIN 4), MAX_ROUTING_LAYER=M11, MIN_CLK_ROUTING_LAYER=M4, Fmax 1.28GHz (780ps). Small residual setup violation (WNS -0.5ps); 0 DRC violations. --- designs/gt2n/minimax/BUILD.bazel | 17 +++++++++++++++++ designs/gt2n/minimax/constraint.sdc | 14 ++++++++++++++ designs/src/minimax/DECISIONS.md | 18 ++++++++++++++++++ 3 files changed, 49 insertions(+) create mode 100644 designs/gt2n/minimax/BUILD.bazel create mode 100644 designs/gt2n/minimax/constraint.sdc diff --git a/designs/gt2n/minimax/BUILD.bazel b/designs/gt2n/minimax/BUILD.bazel new file mode 100644 index 00000000..31e8e946 --- /dev/null +++ b/designs/gt2n/minimax/BUILD.bazel @@ -0,0 +1,17 @@ +load("//:defs.bzl", "hightide_design") + +hightide_design( + name = "minimax", + platform = "gt2n", + verilog_files = ["//designs/src/minimax:rtl"], + sources = {"SDC_FILE": [":constraint.sdc"]}, + arguments = { + "PLACE_DENSITY": "0.7", + "CORE_UTILIZATION": "60", + "CORE_ASPECT_RATIO": "1.0", + "CORE_MARGIN": "4", + "MAX_ROUTING_LAYER": "M11", + "MIN_CLK_ROUTING_LAYER": "M4", + "TNS_END_PERCENT": "100", + }, +) diff --git a/designs/gt2n/minimax/constraint.sdc b/designs/gt2n/minimax/constraint.sdc new file mode 100644 index 00000000..77039cc1 --- /dev/null +++ b/designs/gt2n/minimax/constraint.sdc @@ -0,0 +1,14 @@ +current_design minimax + +set clk_name clk +set clk_period 780 +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_name] + +create_clock -name $clk_name -period $clk_period $clk_port + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] + +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/designs/src/minimax/DECISIONS.md b/designs/src/minimax/DECISIONS.md index ebe550d2..61371992 100644 --- a/designs/src/minimax/DECISIONS.md +++ b/designs/src/minimax/DECISIONS.md @@ -71,3 +71,21 @@ A small RISC-V core (~10–20k stdcells, no macros). Used as a real-RTL smoke t ### Known issues / open questions - None. + +## gt2n + +**Status**: finishing +**Last updated**: 2026-08-13 + +### Configuration +- `CORE_UTILIZATION = 60`, `PLACE_DENSITY = 0.7` +- `CORE_ASPECT_RATIO = 1.0`, `CORE_MARGIN = 4` +- `MAX_ROUTING_LAYER = M11`, `MIN_CLK_ROUTING_LAYER = M4` +- `TNS_END_PERCENT = 100` +- Fmax: `1.28 GHz` (780 ps clock period) + +### Decisions +- Reaches `_final` with 0 DRC violations. + +### Known issues / open questions +- None. From 4b31c9002857e264e383a04dbbe6a5aedd56c4bf Mon Sep 17 00:00:00 2001 From: dgaddy Date: Mon, 17 Aug 2026 13:31:41 -0700 Subject: [PATCH 5/7] gt2n: port floonoc Reaches _final with 0 DRC/timing violations. Custom io.tcl places 6,395 IO pins on M2/M3 (automated placement overflows routing at gt2n's pitches). DIE_AREA 80x80 (CORE_AREA 6 6 74 74), MAX_ROUTING_LAYER M11, MIN_CLK_ROUTING_LAYER M4, HOLD_SLACK_MARGIN 10, clock period 958ps (Fmax 1.04GHz). --- designs/gt2n/floonoc/BUILD.bazel | 30 +++++++ designs/gt2n/floonoc/constraint.sdc | 16 ++++ designs/gt2n/floonoc/io.tcl | 135 ++++++++++++++++++++++++++++ designs/src/floonoc/DECISIONS.md | 19 ++++ 4 files changed, 200 insertions(+) create mode 100644 designs/gt2n/floonoc/BUILD.bazel create mode 100644 designs/gt2n/floonoc/constraint.sdc create mode 100644 designs/gt2n/floonoc/io.tcl diff --git a/designs/gt2n/floonoc/BUILD.bazel b/designs/gt2n/floonoc/BUILD.bazel new file mode 100644 index 00000000..ad1e8130 --- /dev/null +++ b/designs/gt2n/floonoc/BUILD.bazel @@ -0,0 +1,30 @@ +load("//:defs.bzl", "hightide_design") + +hightide_design( + name = "floonoc", + top = "floonoc_mesh_top", + platform = "gt2n", + verilog_files = ["//designs/src/floonoc:rtl"], + sources = { + "SDC_FILE": [":constraint.sdc"], + "FOOTPRINT_TCL": [":io.tcl"], + }, + stage_data = {"synth": ["//designs/src/floonoc:rtl_data"]}, + arguments = { + "SYNTH_HDL_FRONTEND": "slang", + "VERILOG_INCLUDE_DIRS": "external/+_repo_rules+pulp_common_cells_src/include external/+_repo_rules+pulp_apb_src/include external/+_repo_rules+pulp_axi_src/include external/+_repo_rules+pulp_axi_stream_src/include external/+_repo_rules+pulp_obi_src/include external/+_repo_rules+pulp_register_interface_src/include external/+_repo_rules+floonoc_src/hw/include", + "VERILOG_DEFINES": "-D VERILATOR", + # Die sized for logic density; io.tcl's pin placement is die-size-parametric + # (queries ord::get_die_area at build time), so no manual re-tuning needed + # when resizing. Pin-fit floor: 1598 × M3_pitch 0.028 + 2×end_margin(5) = + # 54.7 µm minimum die edge — far below the size used here. See + # scratch_logs/floonoc_gt2n/floonoc_gt2n_qor_comparison.md for the + # utilization/clock tightening sweep that landed on this config. + "DIE_AREA": "0 0 80 80", + "CORE_AREA": "6 6 74 74", + "MAX_ROUTING_LAYER": "M11", + "MIN_CLK_ROUTING_LAYER": "M4", + "TNS_END_PERCENT": "100", + "HOLD_SLACK_MARGIN": "10", + }, +) diff --git a/designs/gt2n/floonoc/constraint.sdc b/designs/gt2n/floonoc/constraint.sdc new file mode 100644 index 00000000..385284d3 --- /dev/null +++ b/designs/gt2n/floonoc/constraint.sdc @@ -0,0 +1,16 @@ +current_design floonoc_mesh_top + +set clk_name clk +set clk_port_name clk_i +set clk_period 958 + +set clk_port [get_ports $clk_port_name] + +create_clock -name $clk_name -period $clk_period $clk_port + +set non_clock_inputs [all_inputs -no_clocks] +set_input_delay 10 -clock $clk_name $non_clock_inputs +set_output_delay 10 -clock $clk_name [all_outputs] + +# Async reset — exclude recovery/removal checks +set_false_path -from [get_ports rst_ni] diff --git a/designs/gt2n/floonoc/io.tcl b/designs/gt2n/floonoc/io.tcl new file mode 100644 index 00000000..590e44a3 --- /dev/null +++ b/designs/gt2n/floonoc/io.tcl @@ -0,0 +1,135 @@ +# Explicit IO pin placement for floonoc_mesh_top (gt2n) +# This file is invoked via FOOTPRINT_TCL, which makes ORFS skip the default +# place_pins annealer (see flow/scripts/io_placement.tcl). All 6395 pins +# are placed by this script — the annealer never runs. +# +# Banking strategy (~1599 pins/edge): bits walk clockwise around the perimeter +# so every corner connects numerically-adjacent bits of the same bus. Starting +# at top-left and walking clockwise the index strictly decreases: +# +# TOP (1599): hbm_wide_out_req_o [2987] @ top-left → [1389] @ top-right +# RIGHT (1599): hbm_wide_out_req_o [1388] @ top-right → [0] mid-right, +# hbm_narrow_out_req_o [979] → [770] @ bottom-right +# BOTTOM (1598): hbm_narrow_out_req_o [769] @ bottom-right → [0] mid-bottom, +# hbm_wide_out_rsp_i [2103] → [1276] @ bottom-left +# LEFT (1599): hbm_wide_out_rsp_i [1275] @ bottom-left → [0] mid-left, +# hbm_narrow_out_rsp_i [319] → [0], +# clk_i, rst_ni, test_enable_i (wraparound; not bus-continuous +# with top-left corner — unavoidable since bus indices terminate) +# +# Pins are placed 5 um INSIDE the die boundary (not exactly on it) so the +# pin shape is fully contained — earlier attempts with -force_to_die_boundary +# triggered GRT-0209 "pin completely outside die" on bigger-pin platforms. + +# ── gt2n layer config (from platforms/gt2n/config.mk + lef/gt2_tech.lef) ── +# +# IO_PLACER_H = M2 (HORIZONTAL layer → left/right edge pins) +# M2: WIDTH 0.012 um, PITCH 0.024 um +# hor_offset = WIDTH/2 = 0.006 um (center of first y-track) +# hor_pitch = 0.024 um +# +# IO_PLACER_V = M3 (VERTICAL layer → top/bottom edge pins) +# M3: WIDTH 0.014 um, PITCH 0.028 um +# ver_offset = WIDTH/2 = 0.007 um (center of first x-track) +# ver_pitch = 0.028 um +# +# Pin-fit check (129×129 die, end_margin 5.0 um each side → 119 um effective edge): +# top/bottom (M3 vertical, 1598 gaps): 1598 × 0.028 = 44.744 um < 119 um ✓ +# left/right (M2 horizontal, 1598 gaps): 1598 × 0.024 = 38.352 um < 119 um ✓ +# +# PSM-0069 note: edge_margin is kept at 5.0 um (no sky130hd-style reduction needed). +# The gt2n PDN is entirely backside: BPR followpins → BM1 → BM2, with only +# BPR↔BM1 and BM1↔BM2 vias — all on the backside stack. There are no frontside +# power stripes or vias on M1-M13. The PSM-0069 mechanism requires frontside PDN +# vias passing through intermediate frontside layers where IO pin DRC halos land; +# that path does not exist in gt2n, so the obstruction risk is absent. + +set hor_layer M2 ;# IO_PLACER_H — pins on left/right edges +set ver_layer M3 ;# IO_PLACER_V — pins on top/bottom edges +set hor_offset 0.006 ;# M2 y_offset = M2_width/2 = 0.012/2 +set hor_pitch 0.024 ;# M2 y_pitch +set ver_offset 0.007 ;# M3 x_offset = M3_width/2 = 0.014/2 +set ver_pitch 0.028 ;# M3 x_pitch + +set edge_margin 5.0 ;# distance from die edge — safe; see PSM-0069 note above +set end_margin 5.0 ;# distance from corner along the edge + +proc bus_pins {name high {low 0}} { + set pins {} + for {set i $low} {$i <= $high} {incr i} { + lappend pins "${name}\[${i}\]" + } + return $pins +} + +proc snap {val offset pitch} { + set k [expr {round(($val - $offset) / $pitch)}] + return [expr {$offset + $k * $pitch}] +} + +proc place_pins_on_edge {edge layer pins} { + upvar edge_margin em end_margin sm + upvar hor_offset ho hor_pitch hp ver_offset vo ver_pitch vp + + set n [llength $pins] + if {$n == 0} return + lassign [ord::get_die_area] lx ly ux uy + + switch $edge { + left - right { + set fixed_x [expr {$edge eq "left" ? $lx + $em : $ux - $em}] + set lo [expr {$ly + $sm}] + set hi [expr {$uy - $sm}] + for {set i 0} {$i < $n} {incr i} { + set frac [expr {($i + 0.5) / double($n)}] + set raw_y [expr {$lo + $frac * ($hi - $lo)}] + set y [snap $raw_y $ho $hp] + place_pin -pin_name [lindex $pins $i] -layer $layer \ + -location [list $fixed_x $y] + } + } + top - bottom { + set fixed_y [expr {$edge eq "top" ? $uy - $em : $ly + $em}] + set lo [expr {$lx + $sm}] + set hi [expr {$ux - $sm}] + for {set i 0} {$i < $n} {incr i} { + set frac [expr {($i + 0.5) / double($n)}] + set raw_x [expr {$lo + $frac * ($hi - $lo)}] + set x [snap $raw_x $vo $vp] + place_pin -pin_name [lindex $pins $i] -layer $layer \ + -location [list $x $fixed_y] + } + } + } +} + +# ── Per-edge pin lists ── +# place_pins_on_edge places list[0] at the LOW-coord end (left for top/bottom, +# bottom for left/right) and list[n-1] at the HIGH end. We construct each list +# so the perimeter walk reads in clockwise order with corners aligned. +# +# TOP (left → right): index 2987 down to 1389 +set top_pins [lreverse [bus_pins hbm_wide_out_req_o 2987 1389]] +# RIGHT (bottom → top): narrow_req[770..979] then wide_req[0..1388] +# (puts [770] at bottom-right corner adjacent to [769] on bottom edge, +# and [1388] at top-right corner adjacent to [1389] on top edge) +set right_pins [concat \ + [bus_pins hbm_narrow_out_req_o 979 770] \ + [bus_pins hbm_wide_out_req_o 1388 0]] +# BOTTOM (left → right): wide_rsp[1276..2103] then narrow_req[0..769] +# ([1276] at bottom-left adjacent to [1275] on left edge, +# [769] at bottom-right adjacent to [770] on right edge) +set bottom_pins [concat \ + [bus_pins hbm_wide_out_rsp_i 2103 1276] \ + [bus_pins hbm_narrow_out_req_o 769 0]] +# LEFT (bottom → top): wide_rsp[1275..0] then narrow_rsp[319..0] then ctrl +# ([1275] at bottom-left adjacent to [1276] on bottom edge) +set left_pins [concat \ + [lreverse [bus_pins hbm_wide_out_rsp_i 1275 0]] \ + [lreverse [bus_pins hbm_narrow_out_rsp_i 319 0]] \ + {clk_i rst_ni test_enable_i}] + +place_pins_on_edge top $ver_layer $top_pins +place_pins_on_edge right $hor_layer $right_pins +place_pins_on_edge bottom $ver_layer $bottom_pins +place_pins_on_edge left $hor_layer $left_pins diff --git a/designs/src/floonoc/DECISIONS.md b/designs/src/floonoc/DECISIONS.md index 27ac8108..a77bb733 100644 --- a/designs/src/floonoc/DECISIONS.md +++ b/designs/src/floonoc/DECISIONS.md @@ -70,3 +70,22 @@ The mesh is assembled hermetically by Bazel — no `dev/repo` submodule, no bend ### Known issues / open questions - None. + +## gt2n + +**Status**: finishing +**Last updated**: 2026-08-15 + +### Configuration +- Custom `FOOTPRINT_TCL = io.tcl` — explicit pin placement for 6,395 IO pins (see Decisions) +- `DIE_AREA = "0 0 80 80"`, `CORE_AREA = "6 6 74 74"` +- `MAX_ROUTING_LAYER = M11`, `MIN_CLK_ROUTING_LAYER = M4` +- `HOLD_SLACK_MARGIN = 10` +- `TNS_END_PERCENT = 100` +- Clock: `958 ps` (Fmax 1.04 GHz) + +### Decisions +- **Custom io.tcl**: mandatory for 6,395 IO pins — automated placement overflows routing at gt2n's tight pitches. Places pins on M2 (horizontal edges) / M3 (vertical edges), matching platform IO-placer defaults. + +### Known issues / open questions +- None. From b2098088a00f498411b3dd9eefb5cddbad7845b9 Mon Sep 17 00:00:00 2001 From: dgaddy Date: Mon, 17 Aug 2026 13:55:11 -0700 Subject: [PATCH 6/7] gt2n: port NVDLA (partitions a/c/m/o/p) All partitions reach _final. a/m/p close with 0 DRC/timing violations; o has minor hold violations (0 setup / 8 hold); c's incremental hold repair did not converge within ~18h (see DECISIONS.md). - partition_a: no macros (FF arrays), CORE_UTILIZATION=80, Fmax 1.12GHz (895ps), die area 4506 um^2 - partition_c: 65 SRAM macro instances (2 macro types, hand-placed 8x8 bank grid via macro_placement.tcl), MIN_CLK_ROUTING_LAYER=M6, clock period 1300ps, achieved Fmax 635.80MHz, die 855.8x716.9 um (~0.61mm^2 core) - partition_m: no macros, CORE_UTILIZATION=82, Fmax 1.52GHz (660ps), die area 1334 um^2 - partition_o: 17 SRAM macro instances (8 macro types), multi-clock (core + falcon, NVIDIA reference ratio 1.25), CORE_UTILIZATION=46, Fmax 440MHz (2270ps core clock), die area 54218 um^2 - partition_p: 6 SRAM macro instances (4 macro types), CORE_UTILIZATION=45, MIN_CLK_ROUTING_LAYER=M6, Fmax 698MHz (1433ps), die area 33257 um^2 Adds a fresh fakeram_gt2n.cfg for the 14 gt2n NVDLA SRAM macros across c/o/p. --- designs/gt2n/NVDLA/BUILD.bazel | 68 + designs/gt2n/NVDLA/partition_a/BUILD.bazel | 28 + designs/gt2n/NVDLA/partition_a/constraint.sdc | 31 + designs/gt2n/NVDLA/partition_a/pre_cts.tcl | 2 + designs/gt2n/NVDLA/partition_c/BUILD.bazel | 29 + designs/gt2n/NVDLA/partition_c/constraint.sdc | 48 + .../NVDLA/partition_c/macro_placement.tcl | 154 ++ designs/gt2n/NVDLA/partition_c/pre_cts.tcl | 1 + designs/gt2n/NVDLA/partition_c/pre_grt.tcl | 16 + designs/gt2n/NVDLA/partition_m/BUILD.bazel | 23 + designs/gt2n/NVDLA/partition_m/constraint.sdc | 36 + designs/gt2n/NVDLA/partition_m/pre_cts.tcl | 2 + designs/gt2n/NVDLA/partition_o/BUILD.bazel | 25 + designs/gt2n/NVDLA/partition_o/constraint.sdc | 54 + designs/gt2n/NVDLA/partition_o/pre_cts.tcl | 1 + designs/gt2n/NVDLA/partition_p/BUILD.bazel | 26 + designs/gt2n/NVDLA/partition_p/constraint.sdc | 37 + designs/gt2n/NVDLA/partition_p/pre_cts.tcl | 4 + .../NVDLA/sram/lef/fakeram_11x128_1r1w.lef | 551 ++++++ .../NVDLA/sram/lef/fakeram_14x80_1r1w.lef | 551 ++++++ .../NVDLA/sram/lef/fakeram_15x80_1r1w.lef | 569 ++++++ .../NVDLA/sram/lef/fakeram_16x160_1r1w.lef | 697 +++++++ .../NVDLA/sram/lef/fakeram_18x128_1r1w.lef | 677 +++++++ .../NVDLA/sram/lef/fakeram_22x60_1r1w.lef | 721 +++++++ .../NVDLA/sram/lef/fakeram_32x128_1r1w.lef | 929 +++++++++ .../NVDLA/sram/lef/fakeram_4x256_1r1w.lef | 369 ++++ .../NVDLA/sram/lef/fakeram_64x256_1r1w.lef | 1671 ++++++++++++++++ .../NVDLA/sram/lef/fakeram_65x160_1r1w.lef | 1763 +++++++++++++++++ .../NVDLA/sram/lef/fakeram_66x64_1r1w.lef | 1523 ++++++++++++++ .../NVDLA/sram/lef/fakeram_66x80_1r1w.lef | 1579 +++++++++++++++ .../NVDLA/sram/lef/fakeram_7x256_1r1w.lef | 497 +++++ .../NVDLA/sram/lef/fakeram_8x256_1r1w.lef | 515 +++++ .../NVDLA/sram/lib/fakeram_11x128_1r1w.lib | 515 +++++ .../NVDLA/sram/lib/fakeram_14x80_1r1w.lib | 515 +++++ .../NVDLA/sram/lib/fakeram_15x80_1r1w.lib | 515 +++++ .../NVDLA/sram/lib/fakeram_16x160_1r1w.lib | 515 +++++ .../NVDLA/sram/lib/fakeram_18x128_1r1w.lib | 515 +++++ .../NVDLA/sram/lib/fakeram_22x60_1r1w.lib | 515 +++++ .../NVDLA/sram/lib/fakeram_32x128_1r1w.lib | 515 +++++ .../NVDLA/sram/lib/fakeram_4x256_1r1w.lib | 515 +++++ .../NVDLA/sram/lib/fakeram_64x256_1r1w.lib | 515 +++++ .../NVDLA/sram/lib/fakeram_65x160_1r1w.lib | 515 +++++ .../NVDLA/sram/lib/fakeram_66x64_1r1w.lib | 515 +++++ .../NVDLA/sram/lib/fakeram_66x80_1r1w.lib | 515 +++++ .../NVDLA/sram/lib/fakeram_7x256_1r1w.lib | 515 +++++ .../NVDLA/sram/lib/fakeram_8x256_1r1w.lib | 515 +++++ designs/src/NVDLA/DECISIONS.md | 22 + .../src/NVDLA/dev/generated/fakeram_gt2n.cfg | 34 + .../dev/generated/partition_c_gt2n_macros.txt | 66 + 49 files changed, 20529 insertions(+) create mode 100644 designs/gt2n/NVDLA/BUILD.bazel create mode 100644 designs/gt2n/NVDLA/partition_a/BUILD.bazel create mode 100644 designs/gt2n/NVDLA/partition_a/constraint.sdc create mode 100644 designs/gt2n/NVDLA/partition_a/pre_cts.tcl create mode 100644 designs/gt2n/NVDLA/partition_c/BUILD.bazel create mode 100644 designs/gt2n/NVDLA/partition_c/constraint.sdc create mode 100644 designs/gt2n/NVDLA/partition_c/macro_placement.tcl create mode 100644 designs/gt2n/NVDLA/partition_c/pre_cts.tcl create mode 100644 designs/gt2n/NVDLA/partition_c/pre_grt.tcl create mode 100644 designs/gt2n/NVDLA/partition_m/BUILD.bazel create mode 100644 designs/gt2n/NVDLA/partition_m/constraint.sdc create mode 100644 designs/gt2n/NVDLA/partition_m/pre_cts.tcl create mode 100644 designs/gt2n/NVDLA/partition_o/BUILD.bazel create mode 100644 designs/gt2n/NVDLA/partition_o/constraint.sdc create mode 100644 designs/gt2n/NVDLA/partition_o/pre_cts.tcl create mode 100644 designs/gt2n/NVDLA/partition_p/BUILD.bazel create mode 100644 designs/gt2n/NVDLA/partition_p/constraint.sdc create mode 100644 designs/gt2n/NVDLA/partition_p/pre_cts.tcl create mode 100644 designs/gt2n/NVDLA/sram/lef/fakeram_11x128_1r1w.lef create mode 100644 designs/gt2n/NVDLA/sram/lef/fakeram_14x80_1r1w.lef create mode 100644 designs/gt2n/NVDLA/sram/lef/fakeram_15x80_1r1w.lef create mode 100644 designs/gt2n/NVDLA/sram/lef/fakeram_16x160_1r1w.lef create mode 100644 designs/gt2n/NVDLA/sram/lef/fakeram_18x128_1r1w.lef create mode 100644 designs/gt2n/NVDLA/sram/lef/fakeram_22x60_1r1w.lef create mode 100644 designs/gt2n/NVDLA/sram/lef/fakeram_32x128_1r1w.lef create mode 100644 designs/gt2n/NVDLA/sram/lef/fakeram_4x256_1r1w.lef create mode 100644 designs/gt2n/NVDLA/sram/lef/fakeram_64x256_1r1w.lef create mode 100644 designs/gt2n/NVDLA/sram/lef/fakeram_65x160_1r1w.lef create mode 100644 designs/gt2n/NVDLA/sram/lef/fakeram_66x64_1r1w.lef create mode 100644 designs/gt2n/NVDLA/sram/lef/fakeram_66x80_1r1w.lef create mode 100644 designs/gt2n/NVDLA/sram/lef/fakeram_7x256_1r1w.lef create mode 100644 designs/gt2n/NVDLA/sram/lef/fakeram_8x256_1r1w.lef create mode 100644 designs/gt2n/NVDLA/sram/lib/fakeram_11x128_1r1w.lib create mode 100644 designs/gt2n/NVDLA/sram/lib/fakeram_14x80_1r1w.lib create mode 100644 designs/gt2n/NVDLA/sram/lib/fakeram_15x80_1r1w.lib create mode 100644 designs/gt2n/NVDLA/sram/lib/fakeram_16x160_1r1w.lib create mode 100644 designs/gt2n/NVDLA/sram/lib/fakeram_18x128_1r1w.lib create mode 100644 designs/gt2n/NVDLA/sram/lib/fakeram_22x60_1r1w.lib create mode 100644 designs/gt2n/NVDLA/sram/lib/fakeram_32x128_1r1w.lib create mode 100644 designs/gt2n/NVDLA/sram/lib/fakeram_4x256_1r1w.lib create mode 100644 designs/gt2n/NVDLA/sram/lib/fakeram_64x256_1r1w.lib create mode 100644 designs/gt2n/NVDLA/sram/lib/fakeram_65x160_1r1w.lib create mode 100644 designs/gt2n/NVDLA/sram/lib/fakeram_66x64_1r1w.lib create mode 100644 designs/gt2n/NVDLA/sram/lib/fakeram_66x80_1r1w.lib create mode 100644 designs/gt2n/NVDLA/sram/lib/fakeram_7x256_1r1w.lib create mode 100644 designs/gt2n/NVDLA/sram/lib/fakeram_8x256_1r1w.lib create mode 100644 designs/src/NVDLA/dev/generated/fakeram_gt2n.cfg create mode 100644 designs/src/NVDLA/dev/generated/partition_c_gt2n_macros.txt diff --git a/designs/gt2n/NVDLA/BUILD.bazel b/designs/gt2n/NVDLA/BUILD.bazel new file mode 100644 index 00000000..e7ac5588 --- /dev/null +++ b/designs/gt2n/NVDLA/BUILD.bazel @@ -0,0 +1,68 @@ +package(default_visibility = ["//designs/gt2n/NVDLA:__subpackages__"]) + +# partition_p: 16x160, 65x160, 14x80, 66x80 (all stay as macros). +filegroup( + name = "sram_lefs_p", + srcs = [ + "sram/lef/fakeram_16x160_1r1w.lef", + "sram/lef/fakeram_65x160_1r1w.lef", + "sram/lef/fakeram_14x80_1r1w.lef", + "sram/lef/fakeram_66x80_1r1w.lef", + ], +) + +filegroup( + name = "sram_libs_p", + srcs = [ + "sram/lib/fakeram_16x160_1r1w.lib", + "sram/lib/fakeram_65x160_1r1w.lib", + "sram/lib/fakeram_14x80_1r1w.lib", + "sram/lib/fakeram_66x80_1r1w.lib", + ], +) + +# partition_o: 18x128, 8x256, 4x256, 7x256, 66x64, 15x80, 22x60, 32x128 (all stay as macros). +filegroup( + name = "sram_lefs_o", + srcs = [ + "sram/lef/fakeram_18x128_1r1w.lef", + "sram/lef/fakeram_8x256_1r1w.lef", + "sram/lef/fakeram_4x256_1r1w.lef", + "sram/lef/fakeram_7x256_1r1w.lef", + "sram/lef/fakeram_66x64_1r1w.lef", + "sram/lef/fakeram_15x80_1r1w.lef", + "sram/lef/fakeram_22x60_1r1w.lef", + "sram/lef/fakeram_32x128_1r1w.lef", + ], +) + +filegroup( + name = "sram_libs_o", + srcs = [ + "sram/lib/fakeram_18x128_1r1w.lib", + "sram/lib/fakeram_8x256_1r1w.lib", + "sram/lib/fakeram_4x256_1r1w.lib", + "sram/lib/fakeram_7x256_1r1w.lib", + "sram/lib/fakeram_66x64_1r1w.lib", + "sram/lib/fakeram_15x80_1r1w.lib", + "sram/lib/fakeram_22x60_1r1w.lib", + "sram/lib/fakeram_32x128_1r1w.lib", + ], +) + +# partition_c: 64x256, 11x128 (both stay as macros). +filegroup( + name = "sram_lefs_c", + srcs = [ + "sram/lef/fakeram_64x256_1r1w.lef", + "sram/lef/fakeram_11x128_1r1w.lef", + ], +) + +filegroup( + name = "sram_libs_c", + srcs = [ + "sram/lib/fakeram_64x256_1r1w.lib", + "sram/lib/fakeram_11x128_1r1w.lib", + ], +) diff --git a/designs/gt2n/NVDLA/partition_a/BUILD.bazel b/designs/gt2n/NVDLA/partition_a/BUILD.bazel new file mode 100644 index 00000000..4f1913d4 --- /dev/null +++ b/designs/gt2n/NVDLA/partition_a/BUILD.bazel @@ -0,0 +1,28 @@ +load("//:defs.bzl", "hightide_design") + +# partition_a has no FakeRAM macros (both SRAMs are FF arrays). +hightide_design( + name = "partition_a", + top = "NV_NVDLA_partition_a", + platform = "gt2n", + verilog_files = ["//designs/src/NVDLA:rtl"], + sources = { + "SDC_FILE": [":constraint.sdc"], + "PRE_CTS_TCL": [":pre_cts.tcl"], + }, + stage_data = {"synth": ["//designs/src/NVDLA:include"]}, + arguments = { + "SYNTH_HIERARCHICAL": "1", + "VERILOG_INCLUDE_DIRS": "bazel-out/k8-fastbuild/bin/designs/src/NVDLA/vmod/include bazel-out/k8-fastbuild/bin/designs/src/NVDLA/vmod/vlibs", + # 272x16 + 256x16 FF arrays (4352 + 4096 bits) — the 4352-bit + # instance trips the ORFS default 4096 cap (same as every + # other platform's partition_a). + "SYNTH_MEMORY_MAX_BITS": "8192", + "CORE_UTILIZATION": "80", + "PLACE_DENSITY": "0.88", + "MAX_ROUTING_LAYER": "M11", + "MIN_CLK_ROUTING_LAYER": "M4", + "TNS_END_PERCENT": "100", + "HOLD_SLACK_MARGIN": "20", + }, +) diff --git a/designs/gt2n/NVDLA/partition_a/constraint.sdc b/designs/gt2n/NVDLA/partition_a/constraint.sdc new file mode 100644 index 00000000..dc671fbc --- /dev/null +++ b/designs/gt2n/NVDLA/partition_a/constraint.sdc @@ -0,0 +1,31 @@ +current_design NV_NVDLA_partition_a + +set clk_name nvdla_core_clk +set clk_period 895 +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_name] + +create_clock -name $clk_name -period $clk_period -waveform [list 0 [expr $clk_period / 2]] $clk_port +set_clock_transition -rise -min 0.1 [get_clocks $clk_name] +set_clock_transition -rise -max 0.1 [get_clocks $clk_name] +set_clock_transition -fall -min 0.1 [get_clocks $clk_name] +set_clock_transition -fall -max 0.1 [get_clocks $clk_name] + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] + +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] + +set_ideal_network [get_ports direct_reset_] +set_ideal_network [get_ports dla_reset_rstn] +set_ideal_network -no_propagate [get_nets nvdla_core_rstn] +set_ideal_network [get_ports test_mode] + +set_false_path -from [get_ports direct_reset_] +set_false_path -from [get_ports dla_reset_rstn] +set_false_path -from [get_ports test_mode] +set_false_path -from [get_ports pwrbus_ram_pd*] +set_false_path -from [get_ports tmc2slcg_disable_clock_gating] +set_false_path -from [get_ports global_clk_ovr_on] +set_false_path -from [get_ports nvdla_clk_ovr_on] diff --git a/designs/gt2n/NVDLA/partition_a/pre_cts.tcl b/designs/gt2n/NVDLA/partition_a/pre_cts.tcl new file mode 100644 index 00000000..276ec787 --- /dev/null +++ b/designs/gt2n/NVDLA/partition_a/pre_cts.tcl @@ -0,0 +1,2 @@ +# to match MIN_CLK_ROUTING_LAYER=M4. +set_wire_rc -clock -layer M4 diff --git a/designs/gt2n/NVDLA/partition_c/BUILD.bazel b/designs/gt2n/NVDLA/partition_c/BUILD.bazel new file mode 100644 index 00000000..9d1ae340 --- /dev/null +++ b/designs/gt2n/NVDLA/partition_c/BUILD.bazel @@ -0,0 +1,29 @@ +load("//:defs.bzl", "hightide_design") + +hightide_design( + name = "partition_c", + top = "NV_NVDLA_partition_c", + platform = "gt2n", + verilog_files = ["//designs/src/NVDLA:rtl"], + sources = { + "SDC_FILE": [":constraint.sdc"], + "ADDITIONAL_LEFS": ["//designs/gt2n/NVDLA:sram_lefs_c"], + "ADDITIONAL_LIBS": ["//designs/gt2n/NVDLA:sram_libs_c"], + "PRE_CTS_TCL": [":pre_cts.tcl"], + "PRE_GLOBAL_ROUTE_TCL": [":pre_grt.tcl"], + "MACRO_PLACEMENT_TCL": [":macro_placement.tcl"], + }, + stage_data = {"synth": ["//designs/src/NVDLA:include"]}, + arguments = { + "SYNTH_HIERARCHICAL": "1", + "VERILOG_INCLUDE_DIRS": "bazel-out/k8-fastbuild/bin/designs/src/NVDLA/vmod/include bazel-out/k8-fastbuild/bin/designs/src/NVDLA/vmod/vlibs", + "DIE_AREA": "0 0 855.792 716.928", + "CORE_AREA": "1.008 1.008 854.784 715.808", + "MAX_ROUTING_LAYER": "M11", + # Macro heavy designs appear to benefit from raising the minimum clock routing layer to M6 on gt2n + "MIN_CLK_ROUTING_LAYER": "M6", + "MACRO_BLOCKAGE_HALO": "0.5", + "TNS_END_PERCENT": "100", + "NUM_CORES": "16", + }, +) diff --git a/designs/gt2n/NVDLA/partition_c/constraint.sdc b/designs/gt2n/NVDLA/partition_c/constraint.sdc new file mode 100644 index 00000000..76c41336 --- /dev/null +++ b/designs/gt2n/NVDLA/partition_c/constraint.sdc @@ -0,0 +1,48 @@ +current_design NV_NVDLA_partition_c + +set clk_name nvdla_core_clk +set clk_period 1300 + +set clk_port [get_ports $clk_name] + +create_clock -name $clk_name -period $clk_period -waveform [list 0 [expr $clk_period / 2]] $clk_port + +set_clock_transition -rise -min 0.1 [get_clocks $clk_name] +set_clock_transition -rise -max 0.1 [get_clocks $clk_name] +set_clock_transition -fall -min 0.1 [get_clocks $clk_name] +set_clock_transition -fall -max 0.1 [get_clocks $clk_name] + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] + +# Delay credit more realistically models the capture-side clock insertion latency of whatever +# receives this partition's boundary outputs, since all partitions are intended as a single die. +# The delay was chosen to be approximately half of the worst clock network latency seen +# within this partition, while stile being expressed relative to the clock period. +set_output_delay [expr -$clk_period * 1.5] -clock $clk_name [all_outputs] + +set_ideal_network [get_ports global_clk_ovr_on] +set_ideal_network [get_ports test_mode] +set_ideal_network [get_ports direct_reset_] +set_ideal_network [get_ports dla_reset_rstn] +set_ideal_network [get_ports nvdla_core_clk] +set_ideal_network [get_ports nvdla_clk_ovr_on] +set_ideal_network [get_ports tmc2slcg_disable_clock_gating] +set_ideal_network [get_ports pwrbus_ram_pd*] +set_ideal_network [get_nets nvdla_core_rstn] + +set_false_path -from [get_ports direct_reset_] +set_false_path -from [get_ports dla_reset_rstn] +set_false_path -from [get_ports test_mode] +set_false_path -from [get_ports pwrbus_ram_pd*] +set_false_path -from [get_ports tmc2slcg_disable_clock_gating] +set_false_path -from [get_ports global_clk_ovr_on] +set_false_path -from [get_ports nvdla_clk_ovr_on] + +# -through (not -to */SETN|RESETN) works around an OpenSTA write_sdc +# instance-name corruption bug on the wildcard form; see CLAUDE.md. +set_false_path -through [get_pins {u_partition_c_reset.sync_reset_synced_rstn.NV_GENERIC_CELL.q$_DFF_PN0_/Q}] +set_false_path -through [get_pins {u_partition_c_reset.sync_reset_synced_rstn.NV_GENERIC_CELL.d0$_DFF_PN0_/Q}] + +set_max_fanout 128 [current_design] + +set_wire_load_mode enclosed diff --git a/designs/gt2n/NVDLA/partition_c/macro_placement.tcl b/designs/gt2n/NVDLA/partition_c/macro_placement.tcl new file mode 100644 index 00000000..a06582b1 --- /dev/null +++ b/designs/gt2n/NVDLA/partition_c/macro_placement.tcl @@ -0,0 +1,154 @@ +# Manual macro grid: 8 columns x 8 rows populated (64 SRAM bank macros + +# 1 aside FIFO). Nominal columns (3-6) occupy rows 1-4,7-10; shifted +# columns (1,2,7,8) occupy rows 2-9 -- this leaves an open rectangular +# gap spanning the middle 4 columns x rows 5-6. +# +# Column gaps: 1,3,4,5,7 = 10um; 2,6 = 28um. Row gaps: 1,3,4,5,6,7,9 = +# 10um; 2,8 = 28um. Die/core area sized to match (CORE_AREA/DIE_AREA in +# BUILD.bazel). +# +# CDMA_IMG FIFO aside macro sits inside column gap 2, centered +# vertically in the empty rows5-6 gap of the nominal columns. +# +# Orientation alternates MX/R0 by row (top-down). +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank0_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {11.008 582.048} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank0_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {111.98 582.048} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank1_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {230.952 648.928} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank1_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {331.924 648.928} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank2_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {432.896 648.928} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank2_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {533.868 648.928} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank3_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {652.84 582.048} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank3_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {753.812 582.048} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank4_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {11.008 497.168} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank4_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {111.98 497.168} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank5_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {230.952 582.048} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank5_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {331.924 582.048} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank6_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {432.896 582.048} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank6_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {533.868 582.048} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank7_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {652.84 497.168} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank7_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {753.812 497.168} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank8_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {11.008 430.288} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank8_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {111.98 430.288} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank9_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {230.952 497.168} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank9_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {331.924 497.168} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank10_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {432.896 497.168} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank10_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {533.868 497.168} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank11_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {652.84 430.288} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank11_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {753.812 430.288} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank12_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {11.008 363.408} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank12_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {111.98 363.408} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank13_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {230.952 430.288} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank13_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {331.924 430.288} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank14_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {432.896 430.288} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank14_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {533.868 430.288} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank15_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {652.84 363.408} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank15_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {753.812 363.408} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank16_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {11.008 296.528} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank16_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {111.98 296.528} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank17_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {230.952 229.648} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank17_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {331.924 229.648} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank18_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {432.896 229.648} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank18_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {533.868 229.648} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank19_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {652.84 296.528} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank19_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {753.812 296.528} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank20_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {11.008 229.648} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank20_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {111.98 229.648} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank21_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {230.952 162.768} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank21_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {331.924 162.768} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank22_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {432.896 162.768} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank22_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {533.868 162.768} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank23_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {652.84 229.648} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank23_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {753.812 229.648} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank24_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {11.008 162.768} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank24_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {111.98 162.768} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank25_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {230.952 77.888} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank25_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {331.924 77.888} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank26_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {432.896 77.888} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank26_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {533.868 77.888} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank27_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {652.84 162.768} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank27_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {753.812 162.768} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank28_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {11.008 77.888} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank28_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {111.98 77.888} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank29_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {230.952 11.008} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank29_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {331.924 11.008} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank30_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {432.896 11.008} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank30_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {533.868 11.008} -orientation R0 +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank31_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {652.84 77.888} -orientation MX +place_macro -macro_name {u_NV_NVDLA_cbuf/u_cbuf_ram_bank31_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} -location {753.812 77.888} -orientation MX + +# CDMA_IMG FIFO macro (15.666 x 28.512): see header comment -- centered +# in column gap 2 (6.167um clearance each side), centered vertically in +# the nominal-column middle gap. +place_macro -macro_name {u_NV_NVDLA_cdma/u_img.u_sg/u_NV_NVDLA_CDMA_IMG_fifo.ram.r_nv_ram_rwsp_128x11.ram_Inst_128X11.sram} -location {209.119 344.152} -orientation R0 + +set _blk [ord::get_db_block] +foreach _m { + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank0_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank0_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank10_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank10_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank11_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank11_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank12_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank12_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank13_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank13_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank14_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank14_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank15_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank15_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank16_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank16_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank17_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank17_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank18_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank18_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank19_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank19_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank1_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank1_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank20_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank20_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank21_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank21_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank22_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank22_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank23_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank23_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank24_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank24_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank25_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank25_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank26_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank26_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank27_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank27_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank28_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank28_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank29_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank29_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank2_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank2_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank30_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank30_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank31_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank31_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank3_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank3_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank4_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank4_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank5_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank5_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank6_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank6_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank7_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank7_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank8_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank8_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank9_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cbuf/u_cbuf_ram_bank9_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram} + {u_NV_NVDLA_cdma/u_img.u_sg/u_NV_NVDLA_CDMA_IMG_fifo.ram.r_nv_ram_rwsp_128x11.ram_Inst_128X11.sram} +} { + set _i [$_blk findInst $_m] + if {$_i ne "NULL" && $_i ne ""} { $_i setPlacementStatus FIRM } +} diff --git a/designs/gt2n/NVDLA/partition_c/pre_cts.tcl b/designs/gt2n/NVDLA/partition_c/pre_cts.tcl new file mode 100644 index 00000000..95bb8fee --- /dev/null +++ b/designs/gt2n/NVDLA/partition_c/pre_cts.tcl @@ -0,0 +1 @@ +set_wire_rc -clock -layer M6 diff --git a/designs/gt2n/NVDLA/partition_c/pre_grt.tcl b/designs/gt2n/NVDLA/partition_c/pre_grt.tcl new file mode 100644 index 00000000..3821196c --- /dev/null +++ b/designs/gt2n/NVDLA/partition_c/pre_grt.tcl @@ -0,0 +1,16 @@ +# input_delay applied here (post-CTS) instead of in constraint.sdc because +# the need to more realistically model the interpartitional signals (that would share a clock as one die) +# calls for an input delay greater than the period. +# While more realistic in this particular scenario, this produces poor placement and cts results unless applied post-CTS. + +set clk_name nvdla_core_clk +set clk_port [get_ports $clk_name] +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set_input_delay 1950 -clock [get_clocks $clk_name] $non_clock_inputs + +# Incremental hold repair disabled, needs 18 or more hours to complete. +# May be able to resolve remaining hold violations if allowed to run to completion. +rename repair_timing_helper repair_timing_helper_orig +proc repair_timing_helper { args } { + repair_timing_helper_orig {*}$args -setup +} diff --git a/designs/gt2n/NVDLA/partition_m/BUILD.bazel b/designs/gt2n/NVDLA/partition_m/BUILD.bazel new file mode 100644 index 00000000..5c04c3ca --- /dev/null +++ b/designs/gt2n/NVDLA/partition_m/BUILD.bazel @@ -0,0 +1,23 @@ +load("//:defs.bzl", "hightide_design") + +# partition_m has no FakeRAM macros (config.mk omits ADDITIONAL_LEFS/LIBS). +hightide_design( + name = "partition_m", + top = "NV_NVDLA_partition_m", + platform = "gt2n", + verilog_files = ["//designs/src/NVDLA:rtl"], + sources = { + "SDC_FILE": [":constraint.sdc"], + "PRE_CTS_TCL": [":pre_cts.tcl"], + }, + stage_data = {"synth": ["//designs/src/NVDLA:include"]}, + arguments = { + "SYNTH_HIERARCHICAL": "1", + "VERILOG_INCLUDE_DIRS": "bazel-out/k8-fastbuild/bin/designs/src/NVDLA/vmod/include bazel-out/k8-fastbuild/bin/designs/src/NVDLA/vmod/vlibs", + "CORE_UTILIZATION": "82", + "PLACE_DENSITY": "0.87", + "MAX_ROUTING_LAYER": "M11", + "MIN_CLK_ROUTING_LAYER": "M4", + "TNS_END_PERCENT": "100", + }, +) diff --git a/designs/gt2n/NVDLA/partition_m/constraint.sdc b/designs/gt2n/NVDLA/partition_m/constraint.sdc new file mode 100644 index 00000000..a92cbdc4 --- /dev/null +++ b/designs/gt2n/NVDLA/partition_m/constraint.sdc @@ -0,0 +1,36 @@ +current_design NV_NVDLA_partition_m + +set clk_name nvdla_core_clk +set clk_period 660 +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_name] + +create_clock -name $clk_name -period $clk_period -waveform [list 0 [expr $clk_period / 2]] $clk_port +set_clock_transition -rise -min 0.1 [get_clocks $clk_name] +set_clock_transition -rise -max 0.1 [get_clocks $clk_name] +set_clock_transition -fall -min 0.1 [get_clocks $clk_name] +set_clock_transition -fall -max 0.1 [get_clocks $clk_name] + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] + +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] + +set_ideal_network [get_ports direct_reset_] +set_ideal_network [get_ports dla_reset_rstn] +set_ideal_network -no_propagate [get_nets nvdla_core_rstn] +set_ideal_network [get_ports test_mode] + +set_false_path -from [get_ports direct_reset_] +set_false_path -from [get_ports dla_reset_rstn] +set_false_path -from [get_ports test_mode] +set_false_path -from [get_ports tmc2slcg_disable_clock_gating] +set_false_path -from [get_ports global_clk_ovr_on] +set_false_path -from [get_ports nvdla_clk_ovr_on] +# async set/reset `-to [get_pin */SETN|/RESETN]` false-paths omitted — +# the OpenSTA write_sdc bug (bazel-orfs 553c1c3 / OpenROAD 299f3015) +# corrupts wildcard-expanded instance names (invalid UTF-8) and Tcl 9 +# then hard-fails floorplan. Redundant: reset sources already -from +# false-pathed and reset nets are set_ideal_network. Matches the fix +# already applied on asap7/nangate45/sky130hd partition_m. diff --git a/designs/gt2n/NVDLA/partition_m/pre_cts.tcl b/designs/gt2n/NVDLA/partition_m/pre_cts.tcl new file mode 100644 index 00000000..b9c974ac --- /dev/null +++ b/designs/gt2n/NVDLA/partition_m/pre_cts.tcl @@ -0,0 +1,2 @@ +# To match MIN_CLK_ROUTING_LAYER=M6. +set_wire_rc -clock -layer M6 diff --git a/designs/gt2n/NVDLA/partition_o/BUILD.bazel b/designs/gt2n/NVDLA/partition_o/BUILD.bazel new file mode 100644 index 00000000..7136313c --- /dev/null +++ b/designs/gt2n/NVDLA/partition_o/BUILD.bazel @@ -0,0 +1,25 @@ +load("//:defs.bzl", "hightide_design") + +hightide_design( + name = "partition_o", + top = "NV_NVDLA_partition_o", + platform = "gt2n", + verilog_files = ["//designs/src/NVDLA:rtl"], + sources = { + "SDC_FILE": [":constraint.sdc"], + "ADDITIONAL_LEFS": ["//designs/gt2n/NVDLA:sram_lefs_o"], + "ADDITIONAL_LIBS": ["//designs/gt2n/NVDLA:sram_libs_o"], + "PRE_CTS_TCL": [":pre_cts.tcl"], + }, + stage_data = {"synth": ["//designs/src/NVDLA:include"]}, + arguments = { + "SYNTH_HIERARCHICAL": "1", + "VERILOG_INCLUDE_DIRS": "bazel-out/k8-fastbuild/bin/designs/src/NVDLA/vmod/include bazel-out/k8-fastbuild/bin/designs/src/NVDLA/vmod/vlibs", + "CORE_UTILIZATION": "46", + "MAX_ROUTING_LAYER": "M11", + "MIN_CLK_ROUTING_LAYER": "M4", + "MACRO_PLACE_HALO": "8 8", + "TNS_END_PERCENT": "100", + "HOLD_SLACK_MARGIN": "40", + }, +) diff --git a/designs/gt2n/NVDLA/partition_o/constraint.sdc b/designs/gt2n/NVDLA/partition_o/constraint.sdc new file mode 100644 index 00000000..162c572f --- /dev/null +++ b/designs/gt2n/NVDLA/partition_o/constraint.sdc @@ -0,0 +1,54 @@ +# =================================================================== +# NVDLA partition_o — gt2n timing constraints +# clk_period tuned to close setup (period_min * 1.10, per the HighTide +# clock-loosening convention — see CLAUDE.md "Pushing clock frequency"). +# clk_falcon_period tracks clk_period at the NVIDIA reference falcon:core +# ratio (2500/2000 = 1.25, from asap7's unmodified reference constraint.sdc). +# =================================================================== +current_design NV_NVDLA_partition_o + +set clk_name nvdla_core_clk +set clk_falcon_name nvdla_falcon_clk +set clk_period 2270 +set clk_falcon_period 2838 +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_name] +set clk_falcon_port [get_ports $clk_falcon_name] + +create_clock -name $clk_name -period $clk_period -waveform [list 0 [expr $clk_period / 2]] $clk_port +set_clock_transition -rise -min 0.1 [get_clocks $clk_name] +set_clock_transition -rise -max 0.1 [get_clocks $clk_name] +set_clock_transition -fall -min 0.1 [get_clocks $clk_name] +set_clock_transition -fall -max 0.1 [get_clocks $clk_name] + +create_clock -name $clk_falcon_name -period $clk_falcon_period -waveform [list 0 [expr $clk_falcon_period / 2]] $clk_falcon_port +set_clock_transition -rise -min 0.1 [get_clocks $clk_falcon_name] +set_clock_transition -rise -max 0.1 [get_clocks $clk_falcon_name] +set_clock_transition -fall -min 0.1 [get_clocks $clk_falcon_name] +set_clock_transition -fall -max 0.1 [get_clocks $clk_falcon_name] + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] "^($clk_port|$clk_falcon_port)$"] + +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] + +# Scoped hold fixes: sdp2csb_resp_valid and cmac_b2csb_resp_valid are zero-logic passthrough +# primary inputs from sibling gt2n partitions, with no on-chip source register to model skew +# against, so the blanket -min under-budgets their minimum arrival. +set_input_delay -min 494 -clock $clk_name [get_ports {sdp2csb_resp_*}] +set_input_delay -min 469 -clock $clk_name [get_ports {cmac_b2csb_resp_*}] + +set_ideal_network [get_ports test_mode] +set_ideal_network [get_ports direct_reset_] +set_ideal_network [get_ports dla_reset_rstn] +set_ideal_network [get_nets nvdla_core_rstn] + +set_false_path -from [get_ports direct_reset_] +set_false_path -from [get_ports dla_reset_rstn] +set_false_path -from [get_ports test_mode] +set_false_path -from [get_ports pwrbus_ram_pd*] +set_false_path -from [get_ports tmc2slcg_disable_clock_gating] +set_false_path -from [get_ports global_clk_ovr_on] +set_false_path -from [get_clocks nvdla_core_clk] -to [get_clocks nvdla_falcon_clk] +set_false_path -from [get_clocks nvdla_falcon_clk] -to [get_clocks nvdla_core_clk] diff --git a/designs/gt2n/NVDLA/partition_o/pre_cts.tcl b/designs/gt2n/NVDLA/partition_o/pre_cts.tcl new file mode 100644 index 00000000..5a9cfb41 --- /dev/null +++ b/designs/gt2n/NVDLA/partition_o/pre_cts.tcl @@ -0,0 +1 @@ +set_wire_rc -clock -layer M4 diff --git a/designs/gt2n/NVDLA/partition_p/BUILD.bazel b/designs/gt2n/NVDLA/partition_p/BUILD.bazel new file mode 100644 index 00000000..88375618 --- /dev/null +++ b/designs/gt2n/NVDLA/partition_p/BUILD.bazel @@ -0,0 +1,26 @@ +load("//:defs.bzl", "hightide_design") + +hightide_design( + name = "partition_p", + top = "NV_NVDLA_partition_p", + platform = "gt2n", + verilog_files = ["//designs/src/NVDLA:rtl"], + sources = { + "SDC_FILE": [":constraint.sdc"], + "ADDITIONAL_LEFS": ["//designs/gt2n/NVDLA:sram_lefs_p"], + "ADDITIONAL_LIBS": ["//designs/gt2n/NVDLA:sram_libs_p"], + "PRE_CTS_TCL": [":pre_cts.tcl"], + }, + stage_data = {"synth": ["//designs/src/NVDLA:include"]}, + arguments = { + "SYNTH_HIERARCHICAL": "1", + "VERILOG_INCLUDE_DIRS": "bazel-out/k8-fastbuild/bin/designs/src/NVDLA/vmod/include bazel-out/k8-fastbuild/bin/designs/src/NVDLA/vmod/vlibs", + "CORE_UTILIZATION": "45", + "MAX_ROUTING_LAYER": "M11", + "MIN_CLK_ROUTING_LAYER": "M6", + "MACRO_PLACE_HALO": "5 5", + "MACRO_BLOCKAGE_HALO": "0.5", + "TNS_END_PERCENT": "100", + "HOLD_SLACK_MARGIN": "50", + }, +) diff --git a/designs/gt2n/NVDLA/partition_p/constraint.sdc b/designs/gt2n/NVDLA/partition_p/constraint.sdc new file mode 100644 index 00000000..58f7ed91 --- /dev/null +++ b/designs/gt2n/NVDLA/partition_p/constraint.sdc @@ -0,0 +1,37 @@ +current_design NV_NVDLA_partition_p + +set clk_name nvdla_core_clk +set clk_period 1433 +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_name] + +create_clock -name $clk_name -period $clk_period -waveform [list 0 [expr $clk_period / 2]] $clk_port +set_clock_transition -rise -min 0.1 [get_clocks $clk_name] +set_clock_transition -rise -max 0.1 [get_clocks $clk_name] +set_clock_transition -fall -min 0.1 [get_clocks $clk_name] +set_clock_transition -fall -max 0.1 [get_clocks $clk_name] + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] + +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] + +# Scoped hold fix (2026-07-22) +set_input_delay -min 341 -clock $clk_name [get_ports {csb2sdp_req_pd*}] + +# Second scoped hold fix (2026-07-22) +set_input_delay -min 311 -clock $clk_name [get_ports {mcif2sdp_wr_rsp_complete*}] + +set_ideal_network [get_ports direct_reset_] +set_ideal_network [get_ports dla_reset_rstn] +set_ideal_network -no_propagate [get_nets nvdla_core_rstn] +set_ideal_network [get_ports test_mode] + +set_false_path -from [get_ports direct_reset_] +set_false_path -from [get_ports dla_reset_rstn] +set_false_path -from [get_ports test_mode] +set_false_path -from [get_ports pwrbus_ram_pd*] +set_false_path -from [get_ports tmc2slcg_disable_clock_gating] +set_false_path -from [get_ports global_clk_ovr_on] +set_false_path -from [get_ports nvdla_clk_ovr_on] diff --git a/designs/gt2n/NVDLA/partition_p/pre_cts.tcl b/designs/gt2n/NVDLA/partition_p/pre_cts.tcl new file mode 100644 index 00000000..b4f80906 --- /dev/null +++ b/designs/gt2n/NVDLA/partition_p/pre_cts.tcl @@ -0,0 +1,4 @@ +# Platform default (platforms/gt2n/setRC.tcl) models clock wire RC at M5 +# (166.95 ohm/um, top of the local tier). Re-model at M6, the first +# intermediate-tier layer (26.55 ohm/um), to match MIN_CLK_ROUTING_LAYER=M6. +set_wire_rc -clock -layer M6 diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_11x128_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_11x128_1r1w.lef new file mode 100644 index 00000000..0b39b3a1 --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_11x128_1r1w.lef @@ -0,0 +1,551 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_11x128_1r1w + FOREIGN fakeram_11x128_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 15.666 BY 28.512 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 0.138 0.036 0.150 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 2.946 0.036 2.958 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 5.754 0.036 5.766 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.630 0.138 15.666 0.150 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.630 2.946 15.666 2.958 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.630 5.754 15.666 5.766 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 0.000 0.175 0.042 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.421 0.000 1.435 0.042 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.681 0.000 2.695 0.042 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.941 0.000 3.955 0.042 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.201 0.000 5.215 0.042 ; + END + END w0_wd_in[10] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.461 0.000 6.475 0.042 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.721 0.000 7.735 0.042 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.981 0.000 8.995 0.042 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.241 0.000 10.255 0.042 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.501 0.000 11.515 0.042 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.761 0.000 12.775 0.042 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 28.470 0.175 28.512 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.533 28.470 1.547 28.512 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.905 28.470 2.919 28.512 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.277 28.470 4.291 28.512 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.649 28.470 5.663 28.512 ; + END + END r0_rd_out[10] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 8.562 0.036 8.574 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 11.370 0.036 11.382 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 14.178 0.036 14.190 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 16.986 0.036 16.998 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.630 8.562 15.666 8.574 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.630 11.370 15.666 11.382 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.630 14.178 15.666 14.190 ; + END + END w0_addr_in[6] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 19.794 0.036 19.806 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 22.602 0.036 22.614 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 25.410 0.036 25.422 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 28.218 0.036 28.230 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.630 16.986 15.666 16.998 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.630 19.794 15.666 19.806 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.630 22.602 15.666 22.614 ; + END + END r0_addr_in[6] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.021 28.470 7.035 28.512 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.393 28.470 8.407 28.512 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.765 28.470 9.779 28.512 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.137 28.470 11.151 28.512 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.509 28.470 12.523 28.512 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.168 0.120 15.498 0.168 ; + RECT 0.168 0.504 15.498 0.552 ; + RECT 0.168 0.888 15.498 0.936 ; + RECT 0.168 1.272 15.498 1.320 ; + RECT 0.168 1.656 15.498 1.704 ; + RECT 0.168 2.040 15.498 2.088 ; + RECT 0.168 2.424 15.498 2.472 ; + RECT 0.168 2.808 15.498 2.856 ; + RECT 0.168 3.192 15.498 3.240 ; + RECT 0.168 3.576 15.498 3.624 ; + RECT 0.168 3.960 15.498 4.008 ; + RECT 0.168 4.344 15.498 4.392 ; + RECT 0.168 4.728 15.498 4.776 ; + RECT 0.168 5.112 15.498 5.160 ; + RECT 0.168 5.496 15.498 5.544 ; + RECT 0.168 5.880 15.498 5.928 ; + RECT 0.168 6.264 15.498 6.312 ; + RECT 0.168 6.648 15.498 6.696 ; + RECT 0.168 7.032 15.498 7.080 ; + RECT 0.168 7.416 15.498 7.464 ; + RECT 0.168 7.800 15.498 7.848 ; + RECT 0.168 8.184 15.498 8.232 ; + RECT 0.168 8.568 15.498 8.616 ; + RECT 0.168 8.952 15.498 9.000 ; + RECT 0.168 9.336 15.498 9.384 ; + RECT 0.168 9.720 15.498 9.768 ; + RECT 0.168 10.104 15.498 10.152 ; + RECT 0.168 10.488 15.498 10.536 ; + RECT 0.168 10.872 15.498 10.920 ; + RECT 0.168 11.256 15.498 11.304 ; + RECT 0.168 11.640 15.498 11.688 ; + RECT 0.168 12.024 15.498 12.072 ; + RECT 0.168 12.408 15.498 12.456 ; + RECT 0.168 12.792 15.498 12.840 ; + RECT 0.168 13.176 15.498 13.224 ; + RECT 0.168 13.560 15.498 13.608 ; + RECT 0.168 13.944 15.498 13.992 ; + RECT 0.168 14.328 15.498 14.376 ; + RECT 0.168 14.712 15.498 14.760 ; + RECT 0.168 15.096 15.498 15.144 ; + RECT 0.168 15.480 15.498 15.528 ; + RECT 0.168 15.864 15.498 15.912 ; + RECT 0.168 16.248 15.498 16.296 ; + RECT 0.168 16.632 15.498 16.680 ; + RECT 0.168 17.016 15.498 17.064 ; + RECT 0.168 17.400 15.498 17.448 ; + RECT 0.168 17.784 15.498 17.832 ; + RECT 0.168 18.168 15.498 18.216 ; + RECT 0.168 18.552 15.498 18.600 ; + RECT 0.168 18.936 15.498 18.984 ; + RECT 0.168 19.320 15.498 19.368 ; + RECT 0.168 19.704 15.498 19.752 ; + RECT 0.168 20.088 15.498 20.136 ; + RECT 0.168 20.472 15.498 20.520 ; + RECT 0.168 20.856 15.498 20.904 ; + RECT 0.168 21.240 15.498 21.288 ; + RECT 0.168 21.624 15.498 21.672 ; + RECT 0.168 22.008 15.498 22.056 ; + RECT 0.168 22.392 15.498 22.440 ; + RECT 0.168 22.776 15.498 22.824 ; + RECT 0.168 23.160 15.498 23.208 ; + RECT 0.168 23.544 15.498 23.592 ; + RECT 0.168 23.928 15.498 23.976 ; + RECT 0.168 24.312 15.498 24.360 ; + RECT 0.168 24.696 15.498 24.744 ; + RECT 0.168 25.080 15.498 25.128 ; + RECT 0.168 25.464 15.498 25.512 ; + RECT 0.168 25.848 15.498 25.896 ; + RECT 0.168 26.232 15.498 26.280 ; + RECT 0.168 26.616 15.498 26.664 ; + RECT 0.168 27.000 15.498 27.048 ; + RECT 0.168 27.384 15.498 27.432 ; + RECT 0.168 27.768 15.498 27.816 ; + RECT 0.168 28.152 15.498 28.200 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.168 0.120 15.498 0.168 ; + RECT 0.168 0.504 15.498 0.552 ; + RECT 0.168 0.888 15.498 0.936 ; + RECT 0.168 1.272 15.498 1.320 ; + RECT 0.168 1.656 15.498 1.704 ; + RECT 0.168 2.040 15.498 2.088 ; + RECT 0.168 2.424 15.498 2.472 ; + RECT 0.168 2.808 15.498 2.856 ; + RECT 0.168 3.192 15.498 3.240 ; + RECT 0.168 3.576 15.498 3.624 ; + RECT 0.168 3.960 15.498 4.008 ; + RECT 0.168 4.344 15.498 4.392 ; + RECT 0.168 4.728 15.498 4.776 ; + RECT 0.168 5.112 15.498 5.160 ; + RECT 0.168 5.496 15.498 5.544 ; + RECT 0.168 5.880 15.498 5.928 ; + RECT 0.168 6.264 15.498 6.312 ; + RECT 0.168 6.648 15.498 6.696 ; + RECT 0.168 7.032 15.498 7.080 ; + RECT 0.168 7.416 15.498 7.464 ; + RECT 0.168 7.800 15.498 7.848 ; + RECT 0.168 8.184 15.498 8.232 ; + RECT 0.168 8.568 15.498 8.616 ; + RECT 0.168 8.952 15.498 9.000 ; + RECT 0.168 9.336 15.498 9.384 ; + RECT 0.168 9.720 15.498 9.768 ; + RECT 0.168 10.104 15.498 10.152 ; + RECT 0.168 10.488 15.498 10.536 ; + RECT 0.168 10.872 15.498 10.920 ; + RECT 0.168 11.256 15.498 11.304 ; + RECT 0.168 11.640 15.498 11.688 ; + RECT 0.168 12.024 15.498 12.072 ; + RECT 0.168 12.408 15.498 12.456 ; + RECT 0.168 12.792 15.498 12.840 ; + RECT 0.168 13.176 15.498 13.224 ; + RECT 0.168 13.560 15.498 13.608 ; + RECT 0.168 13.944 15.498 13.992 ; + RECT 0.168 14.328 15.498 14.376 ; + RECT 0.168 14.712 15.498 14.760 ; + RECT 0.168 15.096 15.498 15.144 ; + RECT 0.168 15.480 15.498 15.528 ; + RECT 0.168 15.864 15.498 15.912 ; + RECT 0.168 16.248 15.498 16.296 ; + RECT 0.168 16.632 15.498 16.680 ; + RECT 0.168 17.016 15.498 17.064 ; + RECT 0.168 17.400 15.498 17.448 ; + RECT 0.168 17.784 15.498 17.832 ; + RECT 0.168 18.168 15.498 18.216 ; + RECT 0.168 18.552 15.498 18.600 ; + RECT 0.168 18.936 15.498 18.984 ; + RECT 0.168 19.320 15.498 19.368 ; + RECT 0.168 19.704 15.498 19.752 ; + RECT 0.168 20.088 15.498 20.136 ; + RECT 0.168 20.472 15.498 20.520 ; + RECT 0.168 20.856 15.498 20.904 ; + RECT 0.168 21.240 15.498 21.288 ; + RECT 0.168 21.624 15.498 21.672 ; + RECT 0.168 22.008 15.498 22.056 ; + RECT 0.168 22.392 15.498 22.440 ; + RECT 0.168 22.776 15.498 22.824 ; + RECT 0.168 23.160 15.498 23.208 ; + RECT 0.168 23.544 15.498 23.592 ; + RECT 0.168 23.928 15.498 23.976 ; + RECT 0.168 24.312 15.498 24.360 ; + RECT 0.168 24.696 15.498 24.744 ; + RECT 0.168 25.080 15.498 25.128 ; + RECT 0.168 25.464 15.498 25.512 ; + RECT 0.168 25.848 15.498 25.896 ; + RECT 0.168 26.232 15.498 26.280 ; + RECT 0.168 26.616 15.498 26.664 ; + RECT 0.168 27.000 15.498 27.048 ; + RECT 0.168 27.384 15.498 27.432 ; + RECT 0.168 27.768 15.498 27.816 ; + RECT 0.168 28.152 15.498 28.200 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 15.666 28.512 ; + LAYER M2 ; + RECT 0 0 15.666 28.512 ; + LAYER M3 ; + RECT 0 0 15.666 28.512 ; + LAYER M4 ; + RECT 0 0 15.666 28.512 ; + END +END fakeram_11x128_1r1w + +END LIBRARY diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_14x80_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_14x80_1r1w.lef new file mode 100644 index 00000000..892a7d82 --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_14x80_1r1w.lef @@ -0,0 +1,551 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_14x80_1r1w + FOREIGN fakeram_14x80_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 19.908 BY 17.856 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 0.138 0.036 0.150 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 1.722 0.036 1.734 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 3.306 0.036 3.318 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 4.890 0.036 4.902 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 19.872 0.138 19.908 0.150 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 19.872 1.722 19.908 1.734 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 19.872 3.306 19.908 3.318 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 0.000 0.175 0.042 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.533 0.000 1.547 0.042 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.905 0.000 2.919 0.042 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.277 0.000 4.291 0.042 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.649 0.000 5.663 0.042 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.021 0.000 7.035 0.042 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.393 0.000 8.407 0.042 ; + END + END w0_wd_in[13] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.765 0.000 9.779 0.042 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.137 0.000 11.151 0.042 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.509 0.000 12.523 0.042 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.881 0.000 13.895 0.042 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.253 0.000 15.267 0.042 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.625 0.000 16.639 0.042 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.997 0.000 18.011 0.042 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 17.814 0.175 17.856 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.785 17.814 1.799 17.856 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.409 17.814 3.423 17.856 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.033 17.814 5.047 17.856 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.657 17.814 6.671 17.856 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.281 17.814 8.295 17.856 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.905 17.814 9.919 17.856 ; + END + END r0_rd_out[13] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 6.474 0.036 6.486 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 8.058 0.036 8.070 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 9.642 0.036 9.654 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 11.226 0.036 11.238 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 19.872 4.890 19.908 4.902 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 19.872 6.474 19.908 6.486 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 19.872 8.058 19.908 8.070 ; + END + END w0_addr_in[6] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 12.810 0.036 12.822 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 14.394 0.036 14.406 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 15.978 0.036 15.990 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 17.562 0.036 17.574 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 19.872 9.642 19.908 9.654 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 19.872 11.226 19.908 11.238 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 19.872 12.810 19.908 12.822 ; + END + END r0_addr_in[6] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.529 17.814 11.543 17.856 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.153 17.814 13.167 17.856 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.777 17.814 14.791 17.856 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.401 17.814 16.415 17.856 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.025 17.814 18.039 17.856 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.168 0.120 19.740 0.168 ; + RECT 0.168 0.504 19.740 0.552 ; + RECT 0.168 0.888 19.740 0.936 ; + RECT 0.168 1.272 19.740 1.320 ; + RECT 0.168 1.656 19.740 1.704 ; + RECT 0.168 2.040 19.740 2.088 ; + RECT 0.168 2.424 19.740 2.472 ; + RECT 0.168 2.808 19.740 2.856 ; + RECT 0.168 3.192 19.740 3.240 ; + RECT 0.168 3.576 19.740 3.624 ; + RECT 0.168 3.960 19.740 4.008 ; + RECT 0.168 4.344 19.740 4.392 ; + RECT 0.168 4.728 19.740 4.776 ; + RECT 0.168 5.112 19.740 5.160 ; + RECT 0.168 5.496 19.740 5.544 ; + RECT 0.168 5.880 19.740 5.928 ; + RECT 0.168 6.264 19.740 6.312 ; + RECT 0.168 6.648 19.740 6.696 ; + RECT 0.168 7.032 19.740 7.080 ; + RECT 0.168 7.416 19.740 7.464 ; + RECT 0.168 7.800 19.740 7.848 ; + RECT 0.168 8.184 19.740 8.232 ; + RECT 0.168 8.568 19.740 8.616 ; + RECT 0.168 8.952 19.740 9.000 ; + RECT 0.168 9.336 19.740 9.384 ; + RECT 0.168 9.720 19.740 9.768 ; + RECT 0.168 10.104 19.740 10.152 ; + RECT 0.168 10.488 19.740 10.536 ; + RECT 0.168 10.872 19.740 10.920 ; + RECT 0.168 11.256 19.740 11.304 ; + RECT 0.168 11.640 19.740 11.688 ; + RECT 0.168 12.024 19.740 12.072 ; + RECT 0.168 12.408 19.740 12.456 ; + RECT 0.168 12.792 19.740 12.840 ; + RECT 0.168 13.176 19.740 13.224 ; + RECT 0.168 13.560 19.740 13.608 ; + RECT 0.168 13.944 19.740 13.992 ; + RECT 0.168 14.328 19.740 14.376 ; + RECT 0.168 14.712 19.740 14.760 ; + RECT 0.168 15.096 19.740 15.144 ; + RECT 0.168 15.480 19.740 15.528 ; + RECT 0.168 15.864 19.740 15.912 ; + RECT 0.168 16.248 19.740 16.296 ; + RECT 0.168 16.632 19.740 16.680 ; + RECT 0.168 17.016 19.740 17.064 ; + RECT 0.168 17.400 19.740 17.448 ; + RECT 0.168 17.784 19.740 17.832 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.168 0.120 19.740 0.168 ; + RECT 0.168 0.504 19.740 0.552 ; + RECT 0.168 0.888 19.740 0.936 ; + RECT 0.168 1.272 19.740 1.320 ; + RECT 0.168 1.656 19.740 1.704 ; + RECT 0.168 2.040 19.740 2.088 ; + RECT 0.168 2.424 19.740 2.472 ; + RECT 0.168 2.808 19.740 2.856 ; + RECT 0.168 3.192 19.740 3.240 ; + RECT 0.168 3.576 19.740 3.624 ; + RECT 0.168 3.960 19.740 4.008 ; + RECT 0.168 4.344 19.740 4.392 ; + RECT 0.168 4.728 19.740 4.776 ; + RECT 0.168 5.112 19.740 5.160 ; + RECT 0.168 5.496 19.740 5.544 ; + RECT 0.168 5.880 19.740 5.928 ; + RECT 0.168 6.264 19.740 6.312 ; + RECT 0.168 6.648 19.740 6.696 ; + RECT 0.168 7.032 19.740 7.080 ; + RECT 0.168 7.416 19.740 7.464 ; + RECT 0.168 7.800 19.740 7.848 ; + RECT 0.168 8.184 19.740 8.232 ; + RECT 0.168 8.568 19.740 8.616 ; + RECT 0.168 8.952 19.740 9.000 ; + RECT 0.168 9.336 19.740 9.384 ; + RECT 0.168 9.720 19.740 9.768 ; + RECT 0.168 10.104 19.740 10.152 ; + RECT 0.168 10.488 19.740 10.536 ; + RECT 0.168 10.872 19.740 10.920 ; + RECT 0.168 11.256 19.740 11.304 ; + RECT 0.168 11.640 19.740 11.688 ; + RECT 0.168 12.024 19.740 12.072 ; + RECT 0.168 12.408 19.740 12.456 ; + RECT 0.168 12.792 19.740 12.840 ; + RECT 0.168 13.176 19.740 13.224 ; + RECT 0.168 13.560 19.740 13.608 ; + RECT 0.168 13.944 19.740 13.992 ; + RECT 0.168 14.328 19.740 14.376 ; + RECT 0.168 14.712 19.740 14.760 ; + RECT 0.168 15.096 19.740 15.144 ; + RECT 0.168 15.480 19.740 15.528 ; + RECT 0.168 15.864 19.740 15.912 ; + RECT 0.168 16.248 19.740 16.296 ; + RECT 0.168 16.632 19.740 16.680 ; + RECT 0.168 17.016 19.740 17.064 ; + RECT 0.168 17.400 19.740 17.448 ; + RECT 0.168 17.784 19.740 17.832 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 19.908 17.856 ; + LAYER M2 ; + RECT 0 0 19.908 17.856 ; + LAYER M3 ; + RECT 0 0 19.908 17.856 ; + LAYER M4 ; + RECT 0 0 19.908 17.856 ; + END +END fakeram_14x80_1r1w + +END LIBRARY diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_15x80_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_15x80_1r1w.lef new file mode 100644 index 00000000..78bc384e --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_15x80_1r1w.lef @@ -0,0 +1,569 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_15x80_1r1w + FOREIGN fakeram_15x80_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 21.336 BY 17.856 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 0.138 0.036 0.150 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 1.722 0.036 1.734 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 3.306 0.036 3.318 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 4.890 0.036 4.902 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 21.300 0.138 21.336 0.150 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 21.300 1.722 21.336 1.734 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 21.300 3.306 21.336 3.318 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 21.300 4.890 21.336 4.902 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 0.000 0.175 0.042 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.449 0.000 1.463 0.042 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.737 0.000 2.751 0.042 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.025 0.000 4.039 0.042 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.313 0.000 5.327 0.042 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.601 0.000 6.615 0.042 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.889 0.000 7.903 0.042 ; + END + END w0_wd_in[14] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.177 0.000 9.191 0.042 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.465 0.000 10.479 0.042 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.753 0.000 11.767 0.042 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.041 0.000 13.055 0.042 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.329 0.000 14.343 0.042 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.617 0.000 15.631 0.042 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.905 0.000 16.919 0.042 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.193 0.000 18.207 0.042 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 17.814 0.175 17.856 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.757 17.814 1.771 17.856 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.353 17.814 3.367 17.856 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.949 17.814 4.963 17.856 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.545 17.814 6.559 17.856 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.141 17.814 8.155 17.856 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.737 17.814 9.751 17.856 ; + END + END r0_rd_out[14] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 6.474 0.036 6.486 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 8.058 0.036 8.070 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 9.642 0.036 9.654 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 11.226 0.036 11.238 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 21.300 6.474 21.336 6.486 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 21.300 8.058 21.336 8.070 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 21.300 9.642 21.336 9.654 ; + END + END w0_addr_in[6] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 12.810 0.036 12.822 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 14.394 0.036 14.406 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 15.978 0.036 15.990 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 17.562 0.036 17.574 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 21.300 11.226 21.336 11.238 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 21.300 12.810 21.336 12.822 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 21.300 14.394 21.336 14.406 ; + END + END r0_addr_in[6] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.333 17.814 11.347 17.856 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.929 17.814 12.943 17.856 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.525 17.814 14.539 17.856 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.121 17.814 16.135 17.856 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.717 17.814 17.731 17.856 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.168 0.120 21.168 0.168 ; + RECT 0.168 0.504 21.168 0.552 ; + RECT 0.168 0.888 21.168 0.936 ; + RECT 0.168 1.272 21.168 1.320 ; + RECT 0.168 1.656 21.168 1.704 ; + RECT 0.168 2.040 21.168 2.088 ; + RECT 0.168 2.424 21.168 2.472 ; + RECT 0.168 2.808 21.168 2.856 ; + RECT 0.168 3.192 21.168 3.240 ; + RECT 0.168 3.576 21.168 3.624 ; + RECT 0.168 3.960 21.168 4.008 ; + RECT 0.168 4.344 21.168 4.392 ; + RECT 0.168 4.728 21.168 4.776 ; + RECT 0.168 5.112 21.168 5.160 ; + RECT 0.168 5.496 21.168 5.544 ; + RECT 0.168 5.880 21.168 5.928 ; + RECT 0.168 6.264 21.168 6.312 ; + RECT 0.168 6.648 21.168 6.696 ; + RECT 0.168 7.032 21.168 7.080 ; + RECT 0.168 7.416 21.168 7.464 ; + RECT 0.168 7.800 21.168 7.848 ; + RECT 0.168 8.184 21.168 8.232 ; + RECT 0.168 8.568 21.168 8.616 ; + RECT 0.168 8.952 21.168 9.000 ; + RECT 0.168 9.336 21.168 9.384 ; + RECT 0.168 9.720 21.168 9.768 ; + RECT 0.168 10.104 21.168 10.152 ; + RECT 0.168 10.488 21.168 10.536 ; + RECT 0.168 10.872 21.168 10.920 ; + RECT 0.168 11.256 21.168 11.304 ; + RECT 0.168 11.640 21.168 11.688 ; + RECT 0.168 12.024 21.168 12.072 ; + RECT 0.168 12.408 21.168 12.456 ; + RECT 0.168 12.792 21.168 12.840 ; + RECT 0.168 13.176 21.168 13.224 ; + RECT 0.168 13.560 21.168 13.608 ; + RECT 0.168 13.944 21.168 13.992 ; + RECT 0.168 14.328 21.168 14.376 ; + RECT 0.168 14.712 21.168 14.760 ; + RECT 0.168 15.096 21.168 15.144 ; + RECT 0.168 15.480 21.168 15.528 ; + RECT 0.168 15.864 21.168 15.912 ; + RECT 0.168 16.248 21.168 16.296 ; + RECT 0.168 16.632 21.168 16.680 ; + RECT 0.168 17.016 21.168 17.064 ; + RECT 0.168 17.400 21.168 17.448 ; + RECT 0.168 17.784 21.168 17.832 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.168 0.120 21.168 0.168 ; + RECT 0.168 0.504 21.168 0.552 ; + RECT 0.168 0.888 21.168 0.936 ; + RECT 0.168 1.272 21.168 1.320 ; + RECT 0.168 1.656 21.168 1.704 ; + RECT 0.168 2.040 21.168 2.088 ; + RECT 0.168 2.424 21.168 2.472 ; + RECT 0.168 2.808 21.168 2.856 ; + RECT 0.168 3.192 21.168 3.240 ; + RECT 0.168 3.576 21.168 3.624 ; + RECT 0.168 3.960 21.168 4.008 ; + RECT 0.168 4.344 21.168 4.392 ; + RECT 0.168 4.728 21.168 4.776 ; + RECT 0.168 5.112 21.168 5.160 ; + RECT 0.168 5.496 21.168 5.544 ; + RECT 0.168 5.880 21.168 5.928 ; + RECT 0.168 6.264 21.168 6.312 ; + RECT 0.168 6.648 21.168 6.696 ; + RECT 0.168 7.032 21.168 7.080 ; + RECT 0.168 7.416 21.168 7.464 ; + RECT 0.168 7.800 21.168 7.848 ; + RECT 0.168 8.184 21.168 8.232 ; + RECT 0.168 8.568 21.168 8.616 ; + RECT 0.168 8.952 21.168 9.000 ; + RECT 0.168 9.336 21.168 9.384 ; + RECT 0.168 9.720 21.168 9.768 ; + RECT 0.168 10.104 21.168 10.152 ; + RECT 0.168 10.488 21.168 10.536 ; + RECT 0.168 10.872 21.168 10.920 ; + RECT 0.168 11.256 21.168 11.304 ; + RECT 0.168 11.640 21.168 11.688 ; + RECT 0.168 12.024 21.168 12.072 ; + RECT 0.168 12.408 21.168 12.456 ; + RECT 0.168 12.792 21.168 12.840 ; + RECT 0.168 13.176 21.168 13.224 ; + RECT 0.168 13.560 21.168 13.608 ; + RECT 0.168 13.944 21.168 13.992 ; + RECT 0.168 14.328 21.168 14.376 ; + RECT 0.168 14.712 21.168 14.760 ; + RECT 0.168 15.096 21.168 15.144 ; + RECT 0.168 15.480 21.168 15.528 ; + RECT 0.168 15.864 21.168 15.912 ; + RECT 0.168 16.248 21.168 16.296 ; + RECT 0.168 16.632 21.168 16.680 ; + RECT 0.168 17.016 21.168 17.064 ; + RECT 0.168 17.400 21.168 17.448 ; + RECT 0.168 17.784 21.168 17.832 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 21.336 17.856 ; + LAYER M2 ; + RECT 0 0 21.336 17.856 ; + LAYER M3 ; + RECT 0 0 21.336 17.856 ; + LAYER M4 ; + RECT 0 0 21.336 17.856 ; + END +END fakeram_15x80_1r1w + +END LIBRARY diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_16x160_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_16x160_1r1w.lef new file mode 100644 index 00000000..729287f2 --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_16x160_1r1w.lef @@ -0,0 +1,697 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_16x160_1r1w + FOREIGN fakeram_16x160_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 22.764 BY 35.568 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 0.138 0.036 0.150 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 3.066 0.036 3.078 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 5.994 0.036 6.006 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 8.922 0.036 8.934 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 0.138 22.764 0.150 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 3.066 22.764 3.078 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 5.994 22.764 6.006 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 8.922 22.764 8.934 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 0.000 0.175 0.042 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.561 0.000 1.575 0.042 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.961 0.000 2.975 0.042 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.361 0.000 4.375 0.042 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.761 0.000 5.775 0.042 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.161 0.000 7.175 0.042 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.561 0.000 8.575 0.042 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.961 0.000 9.975 0.042 ; + END + END w0_wd_in[15] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.361 0.000 11.375 0.042 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.761 0.000 12.775 0.042 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.161 0.000 14.175 0.042 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.561 0.000 15.575 0.042 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.961 0.000 16.975 0.042 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.361 0.000 18.375 0.042 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.761 0.000 19.775 0.042 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.161 0.000 21.175 0.042 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 35.526 0.175 35.568 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.869 35.526 1.883 35.568 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.577 35.526 3.591 35.568 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.285 35.526 5.299 35.568 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.993 35.526 7.007 35.568 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.701 35.526 8.715 35.568 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.409 35.526 10.423 35.568 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.117 35.526 12.131 35.568 ; + END + END r0_rd_out[15] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 11.850 0.036 11.862 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 14.778 0.036 14.790 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 17.706 0.036 17.718 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 20.634 0.036 20.646 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 11.850 22.764 11.862 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 14.778 22.764 14.790 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 17.706 22.764 17.718 ; + END + END w0_addr_in[6] + PIN w0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 20.634 22.764 20.646 ; + END + END w0_addr_in[7] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 23.562 0.036 23.574 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 26.490 0.036 26.502 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 29.418 0.036 29.430 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 32.346 0.036 32.358 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 23.562 22.764 23.574 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 26.490 22.764 26.502 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 29.418 22.764 29.430 ; + END + END r0_addr_in[6] + PIN r0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 32.346 22.764 32.358 ; + END + END r0_addr_in[7] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.825 35.526 13.839 35.568 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.533 35.526 15.547 35.568 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.241 35.526 17.255 35.568 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.949 35.526 18.963 35.568 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.657 35.526 20.671 35.568 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.168 0.120 22.596 0.168 ; + RECT 0.168 0.504 22.596 0.552 ; + RECT 0.168 0.888 22.596 0.936 ; + RECT 0.168 1.272 22.596 1.320 ; + RECT 0.168 1.656 22.596 1.704 ; + RECT 0.168 2.040 22.596 2.088 ; + RECT 0.168 2.424 22.596 2.472 ; + RECT 0.168 2.808 22.596 2.856 ; + RECT 0.168 3.192 22.596 3.240 ; + RECT 0.168 3.576 22.596 3.624 ; + RECT 0.168 3.960 22.596 4.008 ; + RECT 0.168 4.344 22.596 4.392 ; + RECT 0.168 4.728 22.596 4.776 ; + RECT 0.168 5.112 22.596 5.160 ; + RECT 0.168 5.496 22.596 5.544 ; + RECT 0.168 5.880 22.596 5.928 ; + RECT 0.168 6.264 22.596 6.312 ; + RECT 0.168 6.648 22.596 6.696 ; + RECT 0.168 7.032 22.596 7.080 ; + RECT 0.168 7.416 22.596 7.464 ; + RECT 0.168 7.800 22.596 7.848 ; + RECT 0.168 8.184 22.596 8.232 ; + RECT 0.168 8.568 22.596 8.616 ; + RECT 0.168 8.952 22.596 9.000 ; + RECT 0.168 9.336 22.596 9.384 ; + RECT 0.168 9.720 22.596 9.768 ; + RECT 0.168 10.104 22.596 10.152 ; + RECT 0.168 10.488 22.596 10.536 ; + RECT 0.168 10.872 22.596 10.920 ; + RECT 0.168 11.256 22.596 11.304 ; + RECT 0.168 11.640 22.596 11.688 ; + RECT 0.168 12.024 22.596 12.072 ; + RECT 0.168 12.408 22.596 12.456 ; + RECT 0.168 12.792 22.596 12.840 ; + RECT 0.168 13.176 22.596 13.224 ; + RECT 0.168 13.560 22.596 13.608 ; + RECT 0.168 13.944 22.596 13.992 ; + RECT 0.168 14.328 22.596 14.376 ; + RECT 0.168 14.712 22.596 14.760 ; + RECT 0.168 15.096 22.596 15.144 ; + RECT 0.168 15.480 22.596 15.528 ; + RECT 0.168 15.864 22.596 15.912 ; + RECT 0.168 16.248 22.596 16.296 ; + RECT 0.168 16.632 22.596 16.680 ; + RECT 0.168 17.016 22.596 17.064 ; + RECT 0.168 17.400 22.596 17.448 ; + RECT 0.168 17.784 22.596 17.832 ; + RECT 0.168 18.168 22.596 18.216 ; + RECT 0.168 18.552 22.596 18.600 ; + RECT 0.168 18.936 22.596 18.984 ; + RECT 0.168 19.320 22.596 19.368 ; + RECT 0.168 19.704 22.596 19.752 ; + RECT 0.168 20.088 22.596 20.136 ; + RECT 0.168 20.472 22.596 20.520 ; + RECT 0.168 20.856 22.596 20.904 ; + RECT 0.168 21.240 22.596 21.288 ; + RECT 0.168 21.624 22.596 21.672 ; + RECT 0.168 22.008 22.596 22.056 ; + RECT 0.168 22.392 22.596 22.440 ; + RECT 0.168 22.776 22.596 22.824 ; + RECT 0.168 23.160 22.596 23.208 ; + RECT 0.168 23.544 22.596 23.592 ; + RECT 0.168 23.928 22.596 23.976 ; + RECT 0.168 24.312 22.596 24.360 ; + RECT 0.168 24.696 22.596 24.744 ; + RECT 0.168 25.080 22.596 25.128 ; + RECT 0.168 25.464 22.596 25.512 ; + RECT 0.168 25.848 22.596 25.896 ; + RECT 0.168 26.232 22.596 26.280 ; + RECT 0.168 26.616 22.596 26.664 ; + RECT 0.168 27.000 22.596 27.048 ; + RECT 0.168 27.384 22.596 27.432 ; + RECT 0.168 27.768 22.596 27.816 ; + RECT 0.168 28.152 22.596 28.200 ; + RECT 0.168 28.536 22.596 28.584 ; + RECT 0.168 28.920 22.596 28.968 ; + RECT 0.168 29.304 22.596 29.352 ; + RECT 0.168 29.688 22.596 29.736 ; + RECT 0.168 30.072 22.596 30.120 ; + RECT 0.168 30.456 22.596 30.504 ; + RECT 0.168 30.840 22.596 30.888 ; + RECT 0.168 31.224 22.596 31.272 ; + RECT 0.168 31.608 22.596 31.656 ; + RECT 0.168 31.992 22.596 32.040 ; + RECT 0.168 32.376 22.596 32.424 ; + RECT 0.168 32.760 22.596 32.808 ; + RECT 0.168 33.144 22.596 33.192 ; + RECT 0.168 33.528 22.596 33.576 ; + RECT 0.168 33.912 22.596 33.960 ; + RECT 0.168 34.296 22.596 34.344 ; + RECT 0.168 34.680 22.596 34.728 ; + RECT 0.168 35.064 22.596 35.112 ; + RECT 0.168 35.448 22.596 35.496 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.168 0.120 22.596 0.168 ; + RECT 0.168 0.504 22.596 0.552 ; + RECT 0.168 0.888 22.596 0.936 ; + RECT 0.168 1.272 22.596 1.320 ; + RECT 0.168 1.656 22.596 1.704 ; + RECT 0.168 2.040 22.596 2.088 ; + RECT 0.168 2.424 22.596 2.472 ; + RECT 0.168 2.808 22.596 2.856 ; + RECT 0.168 3.192 22.596 3.240 ; + RECT 0.168 3.576 22.596 3.624 ; + RECT 0.168 3.960 22.596 4.008 ; + RECT 0.168 4.344 22.596 4.392 ; + RECT 0.168 4.728 22.596 4.776 ; + RECT 0.168 5.112 22.596 5.160 ; + RECT 0.168 5.496 22.596 5.544 ; + RECT 0.168 5.880 22.596 5.928 ; + RECT 0.168 6.264 22.596 6.312 ; + RECT 0.168 6.648 22.596 6.696 ; + RECT 0.168 7.032 22.596 7.080 ; + RECT 0.168 7.416 22.596 7.464 ; + RECT 0.168 7.800 22.596 7.848 ; + RECT 0.168 8.184 22.596 8.232 ; + RECT 0.168 8.568 22.596 8.616 ; + RECT 0.168 8.952 22.596 9.000 ; + RECT 0.168 9.336 22.596 9.384 ; + RECT 0.168 9.720 22.596 9.768 ; + RECT 0.168 10.104 22.596 10.152 ; + RECT 0.168 10.488 22.596 10.536 ; + RECT 0.168 10.872 22.596 10.920 ; + RECT 0.168 11.256 22.596 11.304 ; + RECT 0.168 11.640 22.596 11.688 ; + RECT 0.168 12.024 22.596 12.072 ; + RECT 0.168 12.408 22.596 12.456 ; + RECT 0.168 12.792 22.596 12.840 ; + RECT 0.168 13.176 22.596 13.224 ; + RECT 0.168 13.560 22.596 13.608 ; + RECT 0.168 13.944 22.596 13.992 ; + RECT 0.168 14.328 22.596 14.376 ; + RECT 0.168 14.712 22.596 14.760 ; + RECT 0.168 15.096 22.596 15.144 ; + RECT 0.168 15.480 22.596 15.528 ; + RECT 0.168 15.864 22.596 15.912 ; + RECT 0.168 16.248 22.596 16.296 ; + RECT 0.168 16.632 22.596 16.680 ; + RECT 0.168 17.016 22.596 17.064 ; + RECT 0.168 17.400 22.596 17.448 ; + RECT 0.168 17.784 22.596 17.832 ; + RECT 0.168 18.168 22.596 18.216 ; + RECT 0.168 18.552 22.596 18.600 ; + RECT 0.168 18.936 22.596 18.984 ; + RECT 0.168 19.320 22.596 19.368 ; + RECT 0.168 19.704 22.596 19.752 ; + RECT 0.168 20.088 22.596 20.136 ; + RECT 0.168 20.472 22.596 20.520 ; + RECT 0.168 20.856 22.596 20.904 ; + RECT 0.168 21.240 22.596 21.288 ; + RECT 0.168 21.624 22.596 21.672 ; + RECT 0.168 22.008 22.596 22.056 ; + RECT 0.168 22.392 22.596 22.440 ; + RECT 0.168 22.776 22.596 22.824 ; + RECT 0.168 23.160 22.596 23.208 ; + RECT 0.168 23.544 22.596 23.592 ; + RECT 0.168 23.928 22.596 23.976 ; + RECT 0.168 24.312 22.596 24.360 ; + RECT 0.168 24.696 22.596 24.744 ; + RECT 0.168 25.080 22.596 25.128 ; + RECT 0.168 25.464 22.596 25.512 ; + RECT 0.168 25.848 22.596 25.896 ; + RECT 0.168 26.232 22.596 26.280 ; + RECT 0.168 26.616 22.596 26.664 ; + RECT 0.168 27.000 22.596 27.048 ; + RECT 0.168 27.384 22.596 27.432 ; + RECT 0.168 27.768 22.596 27.816 ; + RECT 0.168 28.152 22.596 28.200 ; + RECT 0.168 28.536 22.596 28.584 ; + RECT 0.168 28.920 22.596 28.968 ; + RECT 0.168 29.304 22.596 29.352 ; + RECT 0.168 29.688 22.596 29.736 ; + RECT 0.168 30.072 22.596 30.120 ; + RECT 0.168 30.456 22.596 30.504 ; + RECT 0.168 30.840 22.596 30.888 ; + RECT 0.168 31.224 22.596 31.272 ; + RECT 0.168 31.608 22.596 31.656 ; + RECT 0.168 31.992 22.596 32.040 ; + RECT 0.168 32.376 22.596 32.424 ; + RECT 0.168 32.760 22.596 32.808 ; + RECT 0.168 33.144 22.596 33.192 ; + RECT 0.168 33.528 22.596 33.576 ; + RECT 0.168 33.912 22.596 33.960 ; + RECT 0.168 34.296 22.596 34.344 ; + RECT 0.168 34.680 22.596 34.728 ; + RECT 0.168 35.064 22.596 35.112 ; + RECT 0.168 35.448 22.596 35.496 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 22.764 35.568 ; + LAYER M2 ; + RECT 0 0 22.764 35.568 ; + LAYER M3 ; + RECT 0 0 22.764 35.568 ; + LAYER M4 ; + RECT 0 0 22.764 35.568 ; + END +END fakeram_16x160_1r1w + +END LIBRARY diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_18x128_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_18x128_1r1w.lef new file mode 100644 index 00000000..acea2bd4 --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_18x128_1r1w.lef @@ -0,0 +1,677 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_18x128_1r1w + FOREIGN fakeram_18x128_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 25.620 BY 28.512 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 0.138 0.036 0.150 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 2.466 0.036 2.478 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 4.794 0.036 4.806 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 7.122 0.036 7.134 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 9.450 0.036 9.462 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 25.584 0.138 25.620 0.150 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 25.584 2.466 25.620 2.478 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 25.584 4.794 25.620 4.806 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 25.584 7.122 25.620 7.134 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 0.000 0.175 0.042 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.561 0.000 1.575 0.042 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.961 0.000 2.975 0.042 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.361 0.000 4.375 0.042 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.761 0.000 5.775 0.042 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.161 0.000 7.175 0.042 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.561 0.000 8.575 0.042 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.961 0.000 9.975 0.042 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.361 0.000 11.375 0.042 ; + END + END w0_wd_in[17] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.761 0.000 12.775 0.042 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.161 0.000 14.175 0.042 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.561 0.000 15.575 0.042 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.961 0.000 16.975 0.042 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.361 0.000 18.375 0.042 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.761 0.000 19.775 0.042 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.161 0.000 21.175 0.042 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.561 0.000 22.575 0.042 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.961 0.000 23.975 0.042 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 28.470 0.175 28.512 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.953 28.470 1.967 28.512 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.745 28.470 3.759 28.512 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.537 28.470 5.551 28.512 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.329 28.470 7.343 28.512 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.121 28.470 9.135 28.512 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.913 28.470 10.927 28.512 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.705 28.470 12.719 28.512 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.497 28.470 14.511 28.512 ; + END + END r0_rd_out[17] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 11.778 0.036 11.790 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 14.106 0.036 14.118 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 16.434 0.036 16.446 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 18.762 0.036 18.774 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 25.584 9.450 25.620 9.462 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 25.584 11.778 25.620 11.790 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 25.584 14.106 25.620 14.118 ; + END + END w0_addr_in[6] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 21.090 0.036 21.102 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 23.418 0.036 23.430 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 25.746 0.036 25.758 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 28.074 0.036 28.086 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 25.584 16.434 25.620 16.446 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 25.584 18.762 25.620 18.774 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 25.584 21.090 25.620 21.102 ; + END + END r0_addr_in[6] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.289 28.470 16.303 28.512 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.081 28.470 18.095 28.512 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.873 28.470 19.887 28.512 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.665 28.470 21.679 28.512 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.457 28.470 23.471 28.512 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.168 0.120 25.452 0.168 ; + RECT 0.168 0.504 25.452 0.552 ; + RECT 0.168 0.888 25.452 0.936 ; + RECT 0.168 1.272 25.452 1.320 ; + RECT 0.168 1.656 25.452 1.704 ; + RECT 0.168 2.040 25.452 2.088 ; + RECT 0.168 2.424 25.452 2.472 ; + RECT 0.168 2.808 25.452 2.856 ; + RECT 0.168 3.192 25.452 3.240 ; + RECT 0.168 3.576 25.452 3.624 ; + RECT 0.168 3.960 25.452 4.008 ; + RECT 0.168 4.344 25.452 4.392 ; + RECT 0.168 4.728 25.452 4.776 ; + RECT 0.168 5.112 25.452 5.160 ; + RECT 0.168 5.496 25.452 5.544 ; + RECT 0.168 5.880 25.452 5.928 ; + RECT 0.168 6.264 25.452 6.312 ; + RECT 0.168 6.648 25.452 6.696 ; + RECT 0.168 7.032 25.452 7.080 ; + RECT 0.168 7.416 25.452 7.464 ; + RECT 0.168 7.800 25.452 7.848 ; + RECT 0.168 8.184 25.452 8.232 ; + RECT 0.168 8.568 25.452 8.616 ; + RECT 0.168 8.952 25.452 9.000 ; + RECT 0.168 9.336 25.452 9.384 ; + RECT 0.168 9.720 25.452 9.768 ; + RECT 0.168 10.104 25.452 10.152 ; + RECT 0.168 10.488 25.452 10.536 ; + RECT 0.168 10.872 25.452 10.920 ; + RECT 0.168 11.256 25.452 11.304 ; + RECT 0.168 11.640 25.452 11.688 ; + RECT 0.168 12.024 25.452 12.072 ; + RECT 0.168 12.408 25.452 12.456 ; + RECT 0.168 12.792 25.452 12.840 ; + RECT 0.168 13.176 25.452 13.224 ; + RECT 0.168 13.560 25.452 13.608 ; + RECT 0.168 13.944 25.452 13.992 ; + RECT 0.168 14.328 25.452 14.376 ; + RECT 0.168 14.712 25.452 14.760 ; + RECT 0.168 15.096 25.452 15.144 ; + RECT 0.168 15.480 25.452 15.528 ; + RECT 0.168 15.864 25.452 15.912 ; + RECT 0.168 16.248 25.452 16.296 ; + RECT 0.168 16.632 25.452 16.680 ; + RECT 0.168 17.016 25.452 17.064 ; + RECT 0.168 17.400 25.452 17.448 ; + RECT 0.168 17.784 25.452 17.832 ; + RECT 0.168 18.168 25.452 18.216 ; + RECT 0.168 18.552 25.452 18.600 ; + RECT 0.168 18.936 25.452 18.984 ; + RECT 0.168 19.320 25.452 19.368 ; + RECT 0.168 19.704 25.452 19.752 ; + RECT 0.168 20.088 25.452 20.136 ; + RECT 0.168 20.472 25.452 20.520 ; + RECT 0.168 20.856 25.452 20.904 ; + RECT 0.168 21.240 25.452 21.288 ; + RECT 0.168 21.624 25.452 21.672 ; + RECT 0.168 22.008 25.452 22.056 ; + RECT 0.168 22.392 25.452 22.440 ; + RECT 0.168 22.776 25.452 22.824 ; + RECT 0.168 23.160 25.452 23.208 ; + RECT 0.168 23.544 25.452 23.592 ; + RECT 0.168 23.928 25.452 23.976 ; + RECT 0.168 24.312 25.452 24.360 ; + RECT 0.168 24.696 25.452 24.744 ; + RECT 0.168 25.080 25.452 25.128 ; + RECT 0.168 25.464 25.452 25.512 ; + RECT 0.168 25.848 25.452 25.896 ; + RECT 0.168 26.232 25.452 26.280 ; + RECT 0.168 26.616 25.452 26.664 ; + RECT 0.168 27.000 25.452 27.048 ; + RECT 0.168 27.384 25.452 27.432 ; + RECT 0.168 27.768 25.452 27.816 ; + RECT 0.168 28.152 25.452 28.200 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.168 0.120 25.452 0.168 ; + RECT 0.168 0.504 25.452 0.552 ; + RECT 0.168 0.888 25.452 0.936 ; + RECT 0.168 1.272 25.452 1.320 ; + RECT 0.168 1.656 25.452 1.704 ; + RECT 0.168 2.040 25.452 2.088 ; + RECT 0.168 2.424 25.452 2.472 ; + RECT 0.168 2.808 25.452 2.856 ; + RECT 0.168 3.192 25.452 3.240 ; + RECT 0.168 3.576 25.452 3.624 ; + RECT 0.168 3.960 25.452 4.008 ; + RECT 0.168 4.344 25.452 4.392 ; + RECT 0.168 4.728 25.452 4.776 ; + RECT 0.168 5.112 25.452 5.160 ; + RECT 0.168 5.496 25.452 5.544 ; + RECT 0.168 5.880 25.452 5.928 ; + RECT 0.168 6.264 25.452 6.312 ; + RECT 0.168 6.648 25.452 6.696 ; + RECT 0.168 7.032 25.452 7.080 ; + RECT 0.168 7.416 25.452 7.464 ; + RECT 0.168 7.800 25.452 7.848 ; + RECT 0.168 8.184 25.452 8.232 ; + RECT 0.168 8.568 25.452 8.616 ; + RECT 0.168 8.952 25.452 9.000 ; + RECT 0.168 9.336 25.452 9.384 ; + RECT 0.168 9.720 25.452 9.768 ; + RECT 0.168 10.104 25.452 10.152 ; + RECT 0.168 10.488 25.452 10.536 ; + RECT 0.168 10.872 25.452 10.920 ; + RECT 0.168 11.256 25.452 11.304 ; + RECT 0.168 11.640 25.452 11.688 ; + RECT 0.168 12.024 25.452 12.072 ; + RECT 0.168 12.408 25.452 12.456 ; + RECT 0.168 12.792 25.452 12.840 ; + RECT 0.168 13.176 25.452 13.224 ; + RECT 0.168 13.560 25.452 13.608 ; + RECT 0.168 13.944 25.452 13.992 ; + RECT 0.168 14.328 25.452 14.376 ; + RECT 0.168 14.712 25.452 14.760 ; + RECT 0.168 15.096 25.452 15.144 ; + RECT 0.168 15.480 25.452 15.528 ; + RECT 0.168 15.864 25.452 15.912 ; + RECT 0.168 16.248 25.452 16.296 ; + RECT 0.168 16.632 25.452 16.680 ; + RECT 0.168 17.016 25.452 17.064 ; + RECT 0.168 17.400 25.452 17.448 ; + RECT 0.168 17.784 25.452 17.832 ; + RECT 0.168 18.168 25.452 18.216 ; + RECT 0.168 18.552 25.452 18.600 ; + RECT 0.168 18.936 25.452 18.984 ; + RECT 0.168 19.320 25.452 19.368 ; + RECT 0.168 19.704 25.452 19.752 ; + RECT 0.168 20.088 25.452 20.136 ; + RECT 0.168 20.472 25.452 20.520 ; + RECT 0.168 20.856 25.452 20.904 ; + RECT 0.168 21.240 25.452 21.288 ; + RECT 0.168 21.624 25.452 21.672 ; + RECT 0.168 22.008 25.452 22.056 ; + RECT 0.168 22.392 25.452 22.440 ; + RECT 0.168 22.776 25.452 22.824 ; + RECT 0.168 23.160 25.452 23.208 ; + RECT 0.168 23.544 25.452 23.592 ; + RECT 0.168 23.928 25.452 23.976 ; + RECT 0.168 24.312 25.452 24.360 ; + RECT 0.168 24.696 25.452 24.744 ; + RECT 0.168 25.080 25.452 25.128 ; + RECT 0.168 25.464 25.452 25.512 ; + RECT 0.168 25.848 25.452 25.896 ; + RECT 0.168 26.232 25.452 26.280 ; + RECT 0.168 26.616 25.452 26.664 ; + RECT 0.168 27.000 25.452 27.048 ; + RECT 0.168 27.384 25.452 27.432 ; + RECT 0.168 27.768 25.452 27.816 ; + RECT 0.168 28.152 25.452 28.200 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 25.620 28.512 ; + LAYER M2 ; + RECT 0 0 25.620 28.512 ; + LAYER M3 ; + RECT 0 0 25.620 28.512 ; + LAYER M4 ; + RECT 0 0 25.620 28.512 ; + END +END fakeram_18x128_1r1w + +END LIBRARY diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_22x60_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_22x60_1r1w.lef new file mode 100644 index 00000000..4dea7985 --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_22x60_1r1w.lef @@ -0,0 +1,721 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_22x60_1r1w + FOREIGN fakeram_22x60_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 15.666 BY 26.640 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 0.138 0.036 0.150 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 2.322 0.036 2.334 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 4.506 0.036 4.518 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 6.690 0.036 6.702 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 8.874 0.036 8.886 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 11.058 0.036 11.070 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.630 0.138 15.666 0.150 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.630 2.322 15.666 2.334 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.630 4.506 15.666 4.518 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.630 6.690 15.666 6.702 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.630 8.874 15.666 8.886 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 0.000 0.175 0.042 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.833 0.000 0.847 0.042 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.505 0.000 1.519 0.042 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.177 0.000 2.191 0.042 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.849 0.000 2.863 0.042 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.521 0.000 3.535 0.042 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.193 0.000 4.207 0.042 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.865 0.000 4.879 0.042 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.537 0.000 5.551 0.042 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.209 0.000 6.223 0.042 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.881 0.000 6.895 0.042 ; + END + END w0_wd_in[21] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.553 0.000 7.567 0.042 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.225 0.000 8.239 0.042 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.897 0.000 8.911 0.042 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.569 0.000 9.583 0.042 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.241 0.000 10.255 0.042 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.913 0.000 10.927 0.042 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.585 0.000 11.599 0.042 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.257 0.000 12.271 0.042 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.929 0.000 12.943 0.042 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.601 0.000 13.615 0.042 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.273 0.000 14.287 0.042 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 26.598 0.175 26.640 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.113 26.598 1.127 26.640 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.065 26.598 2.079 26.640 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.017 26.598 3.031 26.640 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.969 26.598 3.983 26.640 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.921 26.598 4.935 26.640 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.873 26.598 5.887 26.640 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.825 26.598 6.839 26.640 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.777 26.598 7.791 26.640 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.729 26.598 8.743 26.640 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.681 26.598 9.695 26.640 ; + END + END r0_rd_out[21] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 13.242 0.036 13.254 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 15.426 0.036 15.438 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 17.610 0.036 17.622 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.630 11.058 15.666 11.070 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.630 13.242 15.666 13.254 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.630 15.426 15.666 15.438 ; + END + END w0_addr_in[5] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 19.794 0.036 19.806 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 21.978 0.036 21.990 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 24.162 0.036 24.174 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.630 17.610 15.666 17.622 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.630 19.794 15.666 19.806 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.630 21.978 15.666 21.990 ; + END + END r0_addr_in[5] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.633 26.598 10.647 26.640 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.585 26.598 11.599 26.640 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.537 26.598 12.551 26.640 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.489 26.598 13.503 26.640 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.441 26.598 14.455 26.640 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.168 0.120 15.498 0.168 ; + RECT 0.168 0.504 15.498 0.552 ; + RECT 0.168 0.888 15.498 0.936 ; + RECT 0.168 1.272 15.498 1.320 ; + RECT 0.168 1.656 15.498 1.704 ; + RECT 0.168 2.040 15.498 2.088 ; + RECT 0.168 2.424 15.498 2.472 ; + RECT 0.168 2.808 15.498 2.856 ; + RECT 0.168 3.192 15.498 3.240 ; + RECT 0.168 3.576 15.498 3.624 ; + RECT 0.168 3.960 15.498 4.008 ; + RECT 0.168 4.344 15.498 4.392 ; + RECT 0.168 4.728 15.498 4.776 ; + RECT 0.168 5.112 15.498 5.160 ; + RECT 0.168 5.496 15.498 5.544 ; + RECT 0.168 5.880 15.498 5.928 ; + RECT 0.168 6.264 15.498 6.312 ; + RECT 0.168 6.648 15.498 6.696 ; + RECT 0.168 7.032 15.498 7.080 ; + RECT 0.168 7.416 15.498 7.464 ; + RECT 0.168 7.800 15.498 7.848 ; + RECT 0.168 8.184 15.498 8.232 ; + RECT 0.168 8.568 15.498 8.616 ; + RECT 0.168 8.952 15.498 9.000 ; + RECT 0.168 9.336 15.498 9.384 ; + RECT 0.168 9.720 15.498 9.768 ; + RECT 0.168 10.104 15.498 10.152 ; + RECT 0.168 10.488 15.498 10.536 ; + RECT 0.168 10.872 15.498 10.920 ; + RECT 0.168 11.256 15.498 11.304 ; + RECT 0.168 11.640 15.498 11.688 ; + RECT 0.168 12.024 15.498 12.072 ; + RECT 0.168 12.408 15.498 12.456 ; + RECT 0.168 12.792 15.498 12.840 ; + RECT 0.168 13.176 15.498 13.224 ; + RECT 0.168 13.560 15.498 13.608 ; + RECT 0.168 13.944 15.498 13.992 ; + RECT 0.168 14.328 15.498 14.376 ; + RECT 0.168 14.712 15.498 14.760 ; + RECT 0.168 15.096 15.498 15.144 ; + RECT 0.168 15.480 15.498 15.528 ; + RECT 0.168 15.864 15.498 15.912 ; + RECT 0.168 16.248 15.498 16.296 ; + RECT 0.168 16.632 15.498 16.680 ; + RECT 0.168 17.016 15.498 17.064 ; + RECT 0.168 17.400 15.498 17.448 ; + RECT 0.168 17.784 15.498 17.832 ; + RECT 0.168 18.168 15.498 18.216 ; + RECT 0.168 18.552 15.498 18.600 ; + RECT 0.168 18.936 15.498 18.984 ; + RECT 0.168 19.320 15.498 19.368 ; + RECT 0.168 19.704 15.498 19.752 ; + RECT 0.168 20.088 15.498 20.136 ; + RECT 0.168 20.472 15.498 20.520 ; + RECT 0.168 20.856 15.498 20.904 ; + RECT 0.168 21.240 15.498 21.288 ; + RECT 0.168 21.624 15.498 21.672 ; + RECT 0.168 22.008 15.498 22.056 ; + RECT 0.168 22.392 15.498 22.440 ; + RECT 0.168 22.776 15.498 22.824 ; + RECT 0.168 23.160 15.498 23.208 ; + RECT 0.168 23.544 15.498 23.592 ; + RECT 0.168 23.928 15.498 23.976 ; + RECT 0.168 24.312 15.498 24.360 ; + RECT 0.168 24.696 15.498 24.744 ; + RECT 0.168 25.080 15.498 25.128 ; + RECT 0.168 25.464 15.498 25.512 ; + RECT 0.168 25.848 15.498 25.896 ; + RECT 0.168 26.232 15.498 26.280 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.168 0.120 15.498 0.168 ; + RECT 0.168 0.504 15.498 0.552 ; + RECT 0.168 0.888 15.498 0.936 ; + RECT 0.168 1.272 15.498 1.320 ; + RECT 0.168 1.656 15.498 1.704 ; + RECT 0.168 2.040 15.498 2.088 ; + RECT 0.168 2.424 15.498 2.472 ; + RECT 0.168 2.808 15.498 2.856 ; + RECT 0.168 3.192 15.498 3.240 ; + RECT 0.168 3.576 15.498 3.624 ; + RECT 0.168 3.960 15.498 4.008 ; + RECT 0.168 4.344 15.498 4.392 ; + RECT 0.168 4.728 15.498 4.776 ; + RECT 0.168 5.112 15.498 5.160 ; + RECT 0.168 5.496 15.498 5.544 ; + RECT 0.168 5.880 15.498 5.928 ; + RECT 0.168 6.264 15.498 6.312 ; + RECT 0.168 6.648 15.498 6.696 ; + RECT 0.168 7.032 15.498 7.080 ; + RECT 0.168 7.416 15.498 7.464 ; + RECT 0.168 7.800 15.498 7.848 ; + RECT 0.168 8.184 15.498 8.232 ; + RECT 0.168 8.568 15.498 8.616 ; + RECT 0.168 8.952 15.498 9.000 ; + RECT 0.168 9.336 15.498 9.384 ; + RECT 0.168 9.720 15.498 9.768 ; + RECT 0.168 10.104 15.498 10.152 ; + RECT 0.168 10.488 15.498 10.536 ; + RECT 0.168 10.872 15.498 10.920 ; + RECT 0.168 11.256 15.498 11.304 ; + RECT 0.168 11.640 15.498 11.688 ; + RECT 0.168 12.024 15.498 12.072 ; + RECT 0.168 12.408 15.498 12.456 ; + RECT 0.168 12.792 15.498 12.840 ; + RECT 0.168 13.176 15.498 13.224 ; + RECT 0.168 13.560 15.498 13.608 ; + RECT 0.168 13.944 15.498 13.992 ; + RECT 0.168 14.328 15.498 14.376 ; + RECT 0.168 14.712 15.498 14.760 ; + RECT 0.168 15.096 15.498 15.144 ; + RECT 0.168 15.480 15.498 15.528 ; + RECT 0.168 15.864 15.498 15.912 ; + RECT 0.168 16.248 15.498 16.296 ; + RECT 0.168 16.632 15.498 16.680 ; + RECT 0.168 17.016 15.498 17.064 ; + RECT 0.168 17.400 15.498 17.448 ; + RECT 0.168 17.784 15.498 17.832 ; + RECT 0.168 18.168 15.498 18.216 ; + RECT 0.168 18.552 15.498 18.600 ; + RECT 0.168 18.936 15.498 18.984 ; + RECT 0.168 19.320 15.498 19.368 ; + RECT 0.168 19.704 15.498 19.752 ; + RECT 0.168 20.088 15.498 20.136 ; + RECT 0.168 20.472 15.498 20.520 ; + RECT 0.168 20.856 15.498 20.904 ; + RECT 0.168 21.240 15.498 21.288 ; + RECT 0.168 21.624 15.498 21.672 ; + RECT 0.168 22.008 15.498 22.056 ; + RECT 0.168 22.392 15.498 22.440 ; + RECT 0.168 22.776 15.498 22.824 ; + RECT 0.168 23.160 15.498 23.208 ; + RECT 0.168 23.544 15.498 23.592 ; + RECT 0.168 23.928 15.498 23.976 ; + RECT 0.168 24.312 15.498 24.360 ; + RECT 0.168 24.696 15.498 24.744 ; + RECT 0.168 25.080 15.498 25.128 ; + RECT 0.168 25.464 15.498 25.512 ; + RECT 0.168 25.848 15.498 25.896 ; + RECT 0.168 26.232 15.498 26.280 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 15.666 26.640 ; + LAYER M2 ; + RECT 0 0 15.666 26.640 ; + LAYER M3 ; + RECT 0 0 15.666 26.640 ; + LAYER M4 ; + RECT 0 0 15.666 26.640 ; + END +END fakeram_22x60_1r1w + +END LIBRARY diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_32x128_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_32x128_1r1w.lef new file mode 100644 index 00000000..13f4c0ce --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_32x128_1r1w.lef @@ -0,0 +1,929 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_32x128_1r1w + FOREIGN fakeram_32x128_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 45.486 BY 28.512 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 0.138 0.036 0.150 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 2.010 0.036 2.022 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 3.882 0.036 3.894 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 5.754 0.036 5.766 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 7.626 0.036 7.638 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 9.498 0.036 9.510 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 11.370 0.036 11.382 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 13.242 0.036 13.254 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 45.450 0.138 45.486 0.150 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 45.450 2.010 45.486 2.022 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 45.450 3.882 45.486 3.894 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 45.450 5.754 45.486 5.766 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 45.450 7.626 45.486 7.638 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 45.450 9.498 45.486 9.510 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 45.450 11.370 45.486 11.382 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 45.450 13.242 45.486 13.254 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 0.000 0.175 0.042 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.561 0.000 1.575 0.042 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.961 0.000 2.975 0.042 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.361 0.000 4.375 0.042 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.761 0.000 5.775 0.042 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.161 0.000 7.175 0.042 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.561 0.000 8.575 0.042 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.961 0.000 9.975 0.042 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.361 0.000 11.375 0.042 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.761 0.000 12.775 0.042 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.161 0.000 14.175 0.042 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.561 0.000 15.575 0.042 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.961 0.000 16.975 0.042 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.361 0.000 18.375 0.042 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.761 0.000 19.775 0.042 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.161 0.000 21.175 0.042 ; + END + END w0_wd_in[31] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.561 0.000 22.575 0.042 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.961 0.000 23.975 0.042 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.361 0.000 25.375 0.042 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.761 0.000 26.775 0.042 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.161 0.000 28.175 0.042 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.561 0.000 29.575 0.042 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.961 0.000 30.975 0.042 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.361 0.000 32.375 0.042 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.761 0.000 33.775 0.042 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.161 0.000 35.175 0.042 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.561 0.000 36.575 0.042 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.961 0.000 37.975 0.042 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.361 0.000 39.375 0.042 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.761 0.000 40.775 0.042 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.161 0.000 42.175 0.042 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.561 0.000 43.575 0.042 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 28.470 0.175 28.512 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.289 28.470 2.303 28.512 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.417 28.470 4.431 28.512 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.545 28.470 6.559 28.512 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.673 28.470 8.687 28.512 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.801 28.470 10.815 28.512 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.929 28.470 12.943 28.512 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.057 28.470 15.071 28.512 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.185 28.470 17.199 28.512 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.313 28.470 19.327 28.512 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.441 28.470 21.455 28.512 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.569 28.470 23.583 28.512 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.697 28.470 25.711 28.512 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.825 28.470 27.839 28.512 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.953 28.470 29.967 28.512 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.081 28.470 32.095 28.512 ; + END + END r0_rd_out[31] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 15.114 0.036 15.126 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 16.986 0.036 16.998 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 18.858 0.036 18.870 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 20.730 0.036 20.742 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 45.450 15.114 45.486 15.126 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 45.450 16.986 45.486 16.998 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 45.450 18.858 45.486 18.870 ; + END + END w0_addr_in[6] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 22.602 0.036 22.614 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 24.474 0.036 24.486 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 26.346 0.036 26.358 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 28.218 0.036 28.230 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 45.450 20.730 45.486 20.742 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 45.450 22.602 45.486 22.614 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 45.450 24.474 45.486 24.486 ; + END + END r0_addr_in[6] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.209 28.470 34.223 28.512 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.337 28.470 36.351 28.512 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.465 28.470 38.479 28.512 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.593 28.470 40.607 28.512 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.721 28.470 42.735 28.512 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.168 0.120 45.318 0.168 ; + RECT 0.168 0.504 45.318 0.552 ; + RECT 0.168 0.888 45.318 0.936 ; + RECT 0.168 1.272 45.318 1.320 ; + RECT 0.168 1.656 45.318 1.704 ; + RECT 0.168 2.040 45.318 2.088 ; + RECT 0.168 2.424 45.318 2.472 ; + RECT 0.168 2.808 45.318 2.856 ; + RECT 0.168 3.192 45.318 3.240 ; + RECT 0.168 3.576 45.318 3.624 ; + RECT 0.168 3.960 45.318 4.008 ; + RECT 0.168 4.344 45.318 4.392 ; + RECT 0.168 4.728 45.318 4.776 ; + RECT 0.168 5.112 45.318 5.160 ; + RECT 0.168 5.496 45.318 5.544 ; + RECT 0.168 5.880 45.318 5.928 ; + RECT 0.168 6.264 45.318 6.312 ; + RECT 0.168 6.648 45.318 6.696 ; + RECT 0.168 7.032 45.318 7.080 ; + RECT 0.168 7.416 45.318 7.464 ; + RECT 0.168 7.800 45.318 7.848 ; + RECT 0.168 8.184 45.318 8.232 ; + RECT 0.168 8.568 45.318 8.616 ; + RECT 0.168 8.952 45.318 9.000 ; + RECT 0.168 9.336 45.318 9.384 ; + RECT 0.168 9.720 45.318 9.768 ; + RECT 0.168 10.104 45.318 10.152 ; + RECT 0.168 10.488 45.318 10.536 ; + RECT 0.168 10.872 45.318 10.920 ; + RECT 0.168 11.256 45.318 11.304 ; + RECT 0.168 11.640 45.318 11.688 ; + RECT 0.168 12.024 45.318 12.072 ; + RECT 0.168 12.408 45.318 12.456 ; + RECT 0.168 12.792 45.318 12.840 ; + RECT 0.168 13.176 45.318 13.224 ; + RECT 0.168 13.560 45.318 13.608 ; + RECT 0.168 13.944 45.318 13.992 ; + RECT 0.168 14.328 45.318 14.376 ; + RECT 0.168 14.712 45.318 14.760 ; + RECT 0.168 15.096 45.318 15.144 ; + RECT 0.168 15.480 45.318 15.528 ; + RECT 0.168 15.864 45.318 15.912 ; + RECT 0.168 16.248 45.318 16.296 ; + RECT 0.168 16.632 45.318 16.680 ; + RECT 0.168 17.016 45.318 17.064 ; + RECT 0.168 17.400 45.318 17.448 ; + RECT 0.168 17.784 45.318 17.832 ; + RECT 0.168 18.168 45.318 18.216 ; + RECT 0.168 18.552 45.318 18.600 ; + RECT 0.168 18.936 45.318 18.984 ; + RECT 0.168 19.320 45.318 19.368 ; + RECT 0.168 19.704 45.318 19.752 ; + RECT 0.168 20.088 45.318 20.136 ; + RECT 0.168 20.472 45.318 20.520 ; + RECT 0.168 20.856 45.318 20.904 ; + RECT 0.168 21.240 45.318 21.288 ; + RECT 0.168 21.624 45.318 21.672 ; + RECT 0.168 22.008 45.318 22.056 ; + RECT 0.168 22.392 45.318 22.440 ; + RECT 0.168 22.776 45.318 22.824 ; + RECT 0.168 23.160 45.318 23.208 ; + RECT 0.168 23.544 45.318 23.592 ; + RECT 0.168 23.928 45.318 23.976 ; + RECT 0.168 24.312 45.318 24.360 ; + RECT 0.168 24.696 45.318 24.744 ; + RECT 0.168 25.080 45.318 25.128 ; + RECT 0.168 25.464 45.318 25.512 ; + RECT 0.168 25.848 45.318 25.896 ; + RECT 0.168 26.232 45.318 26.280 ; + RECT 0.168 26.616 45.318 26.664 ; + RECT 0.168 27.000 45.318 27.048 ; + RECT 0.168 27.384 45.318 27.432 ; + RECT 0.168 27.768 45.318 27.816 ; + RECT 0.168 28.152 45.318 28.200 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.168 0.120 45.318 0.168 ; + RECT 0.168 0.504 45.318 0.552 ; + RECT 0.168 0.888 45.318 0.936 ; + RECT 0.168 1.272 45.318 1.320 ; + RECT 0.168 1.656 45.318 1.704 ; + RECT 0.168 2.040 45.318 2.088 ; + RECT 0.168 2.424 45.318 2.472 ; + RECT 0.168 2.808 45.318 2.856 ; + RECT 0.168 3.192 45.318 3.240 ; + RECT 0.168 3.576 45.318 3.624 ; + RECT 0.168 3.960 45.318 4.008 ; + RECT 0.168 4.344 45.318 4.392 ; + RECT 0.168 4.728 45.318 4.776 ; + RECT 0.168 5.112 45.318 5.160 ; + RECT 0.168 5.496 45.318 5.544 ; + RECT 0.168 5.880 45.318 5.928 ; + RECT 0.168 6.264 45.318 6.312 ; + RECT 0.168 6.648 45.318 6.696 ; + RECT 0.168 7.032 45.318 7.080 ; + RECT 0.168 7.416 45.318 7.464 ; + RECT 0.168 7.800 45.318 7.848 ; + RECT 0.168 8.184 45.318 8.232 ; + RECT 0.168 8.568 45.318 8.616 ; + RECT 0.168 8.952 45.318 9.000 ; + RECT 0.168 9.336 45.318 9.384 ; + RECT 0.168 9.720 45.318 9.768 ; + RECT 0.168 10.104 45.318 10.152 ; + RECT 0.168 10.488 45.318 10.536 ; + RECT 0.168 10.872 45.318 10.920 ; + RECT 0.168 11.256 45.318 11.304 ; + RECT 0.168 11.640 45.318 11.688 ; + RECT 0.168 12.024 45.318 12.072 ; + RECT 0.168 12.408 45.318 12.456 ; + RECT 0.168 12.792 45.318 12.840 ; + RECT 0.168 13.176 45.318 13.224 ; + RECT 0.168 13.560 45.318 13.608 ; + RECT 0.168 13.944 45.318 13.992 ; + RECT 0.168 14.328 45.318 14.376 ; + RECT 0.168 14.712 45.318 14.760 ; + RECT 0.168 15.096 45.318 15.144 ; + RECT 0.168 15.480 45.318 15.528 ; + RECT 0.168 15.864 45.318 15.912 ; + RECT 0.168 16.248 45.318 16.296 ; + RECT 0.168 16.632 45.318 16.680 ; + RECT 0.168 17.016 45.318 17.064 ; + RECT 0.168 17.400 45.318 17.448 ; + RECT 0.168 17.784 45.318 17.832 ; + RECT 0.168 18.168 45.318 18.216 ; + RECT 0.168 18.552 45.318 18.600 ; + RECT 0.168 18.936 45.318 18.984 ; + RECT 0.168 19.320 45.318 19.368 ; + RECT 0.168 19.704 45.318 19.752 ; + RECT 0.168 20.088 45.318 20.136 ; + RECT 0.168 20.472 45.318 20.520 ; + RECT 0.168 20.856 45.318 20.904 ; + RECT 0.168 21.240 45.318 21.288 ; + RECT 0.168 21.624 45.318 21.672 ; + RECT 0.168 22.008 45.318 22.056 ; + RECT 0.168 22.392 45.318 22.440 ; + RECT 0.168 22.776 45.318 22.824 ; + RECT 0.168 23.160 45.318 23.208 ; + RECT 0.168 23.544 45.318 23.592 ; + RECT 0.168 23.928 45.318 23.976 ; + RECT 0.168 24.312 45.318 24.360 ; + RECT 0.168 24.696 45.318 24.744 ; + RECT 0.168 25.080 45.318 25.128 ; + RECT 0.168 25.464 45.318 25.512 ; + RECT 0.168 25.848 45.318 25.896 ; + RECT 0.168 26.232 45.318 26.280 ; + RECT 0.168 26.616 45.318 26.664 ; + RECT 0.168 27.000 45.318 27.048 ; + RECT 0.168 27.384 45.318 27.432 ; + RECT 0.168 27.768 45.318 27.816 ; + RECT 0.168 28.152 45.318 28.200 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 45.486 28.512 ; + LAYER M2 ; + RECT 0 0 45.486 28.512 ; + LAYER M3 ; + RECT 0 0 45.486 28.512 ; + LAYER M4 ; + RECT 0 0 45.486 28.512 ; + END +END fakeram_32x128_1r1w + +END LIBRARY diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_4x256_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_4x256_1r1w.lef new file mode 100644 index 00000000..49850602 --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_4x256_1r1w.lef @@ -0,0 +1,369 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_4x256_1r1w + FOREIGN fakeram_4x256_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 22.764 BY 14.256 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 0.138 0.036 0.150 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 0.138 22.764 0.150 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 0.000 0.175 0.042 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.761 0.000 5.775 0.042 ; + END + END w0_wd_in[3] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.361 0.000 11.375 0.042 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.961 0.000 16.975 0.042 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 14.214 0.175 14.256 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.353 14.214 3.367 14.256 ; + END + END r0_rd_out[3] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 1.674 0.036 1.686 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 3.210 0.036 3.222 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 4.746 0.036 4.758 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 6.282 0.036 6.294 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 1.674 22.764 1.686 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 3.210 22.764 3.222 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 4.746 22.764 4.758 ; + END + END w0_addr_in[6] + PIN w0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 6.282 22.764 6.294 ; + END + END w0_addr_in[7] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 7.818 0.036 7.830 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 9.354 0.036 9.366 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 10.890 0.036 10.902 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 12.426 0.036 12.438 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 7.818 22.764 7.830 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 9.354 22.764 9.366 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 10.890 22.764 10.902 ; + END + END r0_addr_in[6] + PIN r0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 12.426 22.764 12.438 ; + END + END r0_addr_in[7] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.545 14.214 6.559 14.256 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.737 14.214 9.751 14.256 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.929 14.214 12.943 14.256 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.121 14.214 16.135 14.256 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.313 14.214 19.327 14.256 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.168 0.120 22.596 0.168 ; + RECT 0.168 0.504 22.596 0.552 ; + RECT 0.168 0.888 22.596 0.936 ; + RECT 0.168 1.272 22.596 1.320 ; + RECT 0.168 1.656 22.596 1.704 ; + RECT 0.168 2.040 22.596 2.088 ; + RECT 0.168 2.424 22.596 2.472 ; + RECT 0.168 2.808 22.596 2.856 ; + RECT 0.168 3.192 22.596 3.240 ; + RECT 0.168 3.576 22.596 3.624 ; + RECT 0.168 3.960 22.596 4.008 ; + RECT 0.168 4.344 22.596 4.392 ; + RECT 0.168 4.728 22.596 4.776 ; + RECT 0.168 5.112 22.596 5.160 ; + RECT 0.168 5.496 22.596 5.544 ; + RECT 0.168 5.880 22.596 5.928 ; + RECT 0.168 6.264 22.596 6.312 ; + RECT 0.168 6.648 22.596 6.696 ; + RECT 0.168 7.032 22.596 7.080 ; + RECT 0.168 7.416 22.596 7.464 ; + RECT 0.168 7.800 22.596 7.848 ; + RECT 0.168 8.184 22.596 8.232 ; + RECT 0.168 8.568 22.596 8.616 ; + RECT 0.168 8.952 22.596 9.000 ; + RECT 0.168 9.336 22.596 9.384 ; + RECT 0.168 9.720 22.596 9.768 ; + RECT 0.168 10.104 22.596 10.152 ; + RECT 0.168 10.488 22.596 10.536 ; + RECT 0.168 10.872 22.596 10.920 ; + RECT 0.168 11.256 22.596 11.304 ; + RECT 0.168 11.640 22.596 11.688 ; + RECT 0.168 12.024 22.596 12.072 ; + RECT 0.168 12.408 22.596 12.456 ; + RECT 0.168 12.792 22.596 12.840 ; + RECT 0.168 13.176 22.596 13.224 ; + RECT 0.168 13.560 22.596 13.608 ; + RECT 0.168 13.944 22.596 13.992 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.168 0.120 22.596 0.168 ; + RECT 0.168 0.504 22.596 0.552 ; + RECT 0.168 0.888 22.596 0.936 ; + RECT 0.168 1.272 22.596 1.320 ; + RECT 0.168 1.656 22.596 1.704 ; + RECT 0.168 2.040 22.596 2.088 ; + RECT 0.168 2.424 22.596 2.472 ; + RECT 0.168 2.808 22.596 2.856 ; + RECT 0.168 3.192 22.596 3.240 ; + RECT 0.168 3.576 22.596 3.624 ; + RECT 0.168 3.960 22.596 4.008 ; + RECT 0.168 4.344 22.596 4.392 ; + RECT 0.168 4.728 22.596 4.776 ; + RECT 0.168 5.112 22.596 5.160 ; + RECT 0.168 5.496 22.596 5.544 ; + RECT 0.168 5.880 22.596 5.928 ; + RECT 0.168 6.264 22.596 6.312 ; + RECT 0.168 6.648 22.596 6.696 ; + RECT 0.168 7.032 22.596 7.080 ; + RECT 0.168 7.416 22.596 7.464 ; + RECT 0.168 7.800 22.596 7.848 ; + RECT 0.168 8.184 22.596 8.232 ; + RECT 0.168 8.568 22.596 8.616 ; + RECT 0.168 8.952 22.596 9.000 ; + RECT 0.168 9.336 22.596 9.384 ; + RECT 0.168 9.720 22.596 9.768 ; + RECT 0.168 10.104 22.596 10.152 ; + RECT 0.168 10.488 22.596 10.536 ; + RECT 0.168 10.872 22.596 10.920 ; + RECT 0.168 11.256 22.596 11.304 ; + RECT 0.168 11.640 22.596 11.688 ; + RECT 0.168 12.024 22.596 12.072 ; + RECT 0.168 12.408 22.596 12.456 ; + RECT 0.168 12.792 22.596 12.840 ; + RECT 0.168 13.176 22.596 13.224 ; + RECT 0.168 13.560 22.596 13.608 ; + RECT 0.168 13.944 22.596 13.992 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 22.764 14.256 ; + LAYER M2 ; + RECT 0 0 22.764 14.256 ; + LAYER M3 ; + RECT 0 0 22.764 14.256 ; + LAYER M4 ; + RECT 0 0 22.764 14.256 ; + END +END fakeram_4x256_1r1w + +END LIBRARY diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_64x256_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_64x256_1r1w.lef new file mode 100644 index 00000000..4e3e6be1 --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_64x256_1r1w.lef @@ -0,0 +1,1671 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_64x256_1r1w + FOREIGN fakeram_64x256_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 90.972 BY 56.880 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 0.138 0.036 0.150 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 2.490 0.036 2.502 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 4.842 0.036 4.854 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 7.194 0.036 7.206 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 9.546 0.036 9.558 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 11.898 0.036 11.910 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 14.250 0.036 14.262 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 16.602 0.036 16.614 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 18.954 0.036 18.966 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 21.306 0.036 21.318 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 23.658 0.036 23.670 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 26.010 0.036 26.022 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 28.362 0.036 28.374 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 30.714 0.036 30.726 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 33.066 0.036 33.078 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 35.418 0.036 35.430 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 90.936 0.138 90.972 0.150 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 90.936 2.490 90.972 2.502 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 90.936 4.842 90.972 4.854 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 90.936 7.194 90.972 7.206 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 90.936 9.546 90.972 9.558 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 90.936 11.898 90.972 11.910 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 90.936 14.250 90.972 14.262 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 90.936 16.602 90.972 16.614 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 90.936 18.954 90.972 18.966 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 90.936 21.306 90.972 21.318 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 90.936 23.658 90.972 23.670 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 90.936 26.010 90.972 26.022 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 90.936 28.362 90.972 28.374 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 90.936 30.714 90.972 30.726 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 90.936 33.066 90.972 33.078 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 90.936 35.418 90.972 35.430 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 0.000 0.175 0.042 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.561 0.000 1.575 0.042 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.961 0.000 2.975 0.042 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.361 0.000 4.375 0.042 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.761 0.000 5.775 0.042 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.161 0.000 7.175 0.042 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.561 0.000 8.575 0.042 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.961 0.000 9.975 0.042 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.361 0.000 11.375 0.042 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.761 0.000 12.775 0.042 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.161 0.000 14.175 0.042 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.561 0.000 15.575 0.042 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.961 0.000 16.975 0.042 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.361 0.000 18.375 0.042 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.761 0.000 19.775 0.042 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.161 0.000 21.175 0.042 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.561 0.000 22.575 0.042 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.961 0.000 23.975 0.042 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.361 0.000 25.375 0.042 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.761 0.000 26.775 0.042 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.161 0.000 28.175 0.042 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.561 0.000 29.575 0.042 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.961 0.000 30.975 0.042 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.361 0.000 32.375 0.042 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.761 0.000 33.775 0.042 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.161 0.000 35.175 0.042 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.561 0.000 36.575 0.042 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.961 0.000 37.975 0.042 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.361 0.000 39.375 0.042 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.761 0.000 40.775 0.042 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.161 0.000 42.175 0.042 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.561 0.000 43.575 0.042 ; + END + END w0_wd_in[63] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.961 0.000 44.975 0.042 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.361 0.000 46.375 0.042 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.761 0.000 47.775 0.042 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.161 0.000 49.175 0.042 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.561 0.000 50.575 0.042 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.961 0.000 51.975 0.042 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.361 0.000 53.375 0.042 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.761 0.000 54.775 0.042 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.161 0.000 56.175 0.042 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.561 0.000 57.575 0.042 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.961 0.000 58.975 0.042 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.361 0.000 60.375 0.042 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.761 0.000 61.775 0.042 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.161 0.000 63.175 0.042 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.561 0.000 64.575 0.042 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.961 0.000 65.975 0.042 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.361 0.000 67.375 0.042 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.761 0.000 68.775 0.042 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.161 0.000 70.175 0.042 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.561 0.000 71.575 0.042 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.961 0.000 72.975 0.042 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.361 0.000 74.375 0.042 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.761 0.000 75.775 0.042 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.161 0.000 77.175 0.042 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.561 0.000 78.575 0.042 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.961 0.000 79.975 0.042 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.361 0.000 81.375 0.042 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.761 0.000 82.775 0.042 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.161 0.000 84.175 0.042 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.561 0.000 85.575 0.042 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.961 0.000 86.975 0.042 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.361 0.000 88.375 0.042 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 56.838 0.175 56.880 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.597 56.838 2.611 56.880 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.033 56.838 5.047 56.880 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.469 56.838 7.483 56.880 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.905 56.838 9.919 56.880 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.341 56.838 12.355 56.880 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.777 56.838 14.791 56.880 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.213 56.838 17.227 56.880 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.649 56.838 19.663 56.880 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.085 56.838 22.099 56.880 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.521 56.838 24.535 56.880 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.957 56.838 26.971 56.880 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.393 56.838 29.407 56.880 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.829 56.838 31.843 56.880 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.265 56.838 34.279 56.880 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.701 56.838 36.715 56.880 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.137 56.838 39.151 56.880 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.573 56.838 41.587 56.880 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.009 56.838 44.023 56.880 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.445 56.838 46.459 56.880 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.881 56.838 48.895 56.880 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.317 56.838 51.331 56.880 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.753 56.838 53.767 56.880 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.189 56.838 56.203 56.880 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.625 56.838 58.639 56.880 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.061 56.838 61.075 56.880 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.497 56.838 63.511 56.880 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.933 56.838 65.947 56.880 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.369 56.838 68.383 56.880 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.805 56.838 70.819 56.880 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.241 56.838 73.255 56.880 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.677 56.838 75.691 56.880 ; + END + END r0_rd_out[63] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 37.770 0.036 37.782 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 40.122 0.036 40.134 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 42.474 0.036 42.486 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 44.826 0.036 44.838 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 90.936 37.770 90.972 37.782 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 90.936 40.122 90.972 40.134 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 90.936 42.474 90.972 42.486 ; + END + END w0_addr_in[6] + PIN w0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 90.936 44.826 90.972 44.838 ; + END + END w0_addr_in[7] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 47.178 0.036 47.190 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 49.530 0.036 49.542 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 51.882 0.036 51.894 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 54.234 0.036 54.246 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 90.936 47.178 90.972 47.190 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 90.936 49.530 90.972 49.542 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 90.936 51.882 90.972 51.894 ; + END + END r0_addr_in[6] + PIN r0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 90.936 54.234 90.972 54.246 ; + END + END r0_addr_in[7] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.113 56.838 78.127 56.880 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.549 56.838 80.563 56.880 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.985 56.838 82.999 56.880 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.421 56.838 85.435 56.880 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.857 56.838 87.871 56.880 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.168 0.120 90.804 0.168 ; + RECT 0.168 0.504 90.804 0.552 ; + RECT 0.168 0.888 90.804 0.936 ; + RECT 0.168 1.272 90.804 1.320 ; + RECT 0.168 1.656 90.804 1.704 ; + RECT 0.168 2.040 90.804 2.088 ; + RECT 0.168 2.424 90.804 2.472 ; + RECT 0.168 2.808 90.804 2.856 ; + RECT 0.168 3.192 90.804 3.240 ; + RECT 0.168 3.576 90.804 3.624 ; + RECT 0.168 3.960 90.804 4.008 ; + RECT 0.168 4.344 90.804 4.392 ; + RECT 0.168 4.728 90.804 4.776 ; + RECT 0.168 5.112 90.804 5.160 ; + RECT 0.168 5.496 90.804 5.544 ; + RECT 0.168 5.880 90.804 5.928 ; + RECT 0.168 6.264 90.804 6.312 ; + RECT 0.168 6.648 90.804 6.696 ; + RECT 0.168 7.032 90.804 7.080 ; + RECT 0.168 7.416 90.804 7.464 ; + RECT 0.168 7.800 90.804 7.848 ; + RECT 0.168 8.184 90.804 8.232 ; + RECT 0.168 8.568 90.804 8.616 ; + RECT 0.168 8.952 90.804 9.000 ; + RECT 0.168 9.336 90.804 9.384 ; + RECT 0.168 9.720 90.804 9.768 ; + RECT 0.168 10.104 90.804 10.152 ; + RECT 0.168 10.488 90.804 10.536 ; + RECT 0.168 10.872 90.804 10.920 ; + RECT 0.168 11.256 90.804 11.304 ; + RECT 0.168 11.640 90.804 11.688 ; + RECT 0.168 12.024 90.804 12.072 ; + RECT 0.168 12.408 90.804 12.456 ; + RECT 0.168 12.792 90.804 12.840 ; + RECT 0.168 13.176 90.804 13.224 ; + RECT 0.168 13.560 90.804 13.608 ; + RECT 0.168 13.944 90.804 13.992 ; + RECT 0.168 14.328 90.804 14.376 ; + RECT 0.168 14.712 90.804 14.760 ; + RECT 0.168 15.096 90.804 15.144 ; + RECT 0.168 15.480 90.804 15.528 ; + RECT 0.168 15.864 90.804 15.912 ; + RECT 0.168 16.248 90.804 16.296 ; + RECT 0.168 16.632 90.804 16.680 ; + RECT 0.168 17.016 90.804 17.064 ; + RECT 0.168 17.400 90.804 17.448 ; + RECT 0.168 17.784 90.804 17.832 ; + RECT 0.168 18.168 90.804 18.216 ; + RECT 0.168 18.552 90.804 18.600 ; + RECT 0.168 18.936 90.804 18.984 ; + RECT 0.168 19.320 90.804 19.368 ; + RECT 0.168 19.704 90.804 19.752 ; + RECT 0.168 20.088 90.804 20.136 ; + RECT 0.168 20.472 90.804 20.520 ; + RECT 0.168 20.856 90.804 20.904 ; + RECT 0.168 21.240 90.804 21.288 ; + RECT 0.168 21.624 90.804 21.672 ; + RECT 0.168 22.008 90.804 22.056 ; + RECT 0.168 22.392 90.804 22.440 ; + RECT 0.168 22.776 90.804 22.824 ; + RECT 0.168 23.160 90.804 23.208 ; + RECT 0.168 23.544 90.804 23.592 ; + RECT 0.168 23.928 90.804 23.976 ; + RECT 0.168 24.312 90.804 24.360 ; + RECT 0.168 24.696 90.804 24.744 ; + RECT 0.168 25.080 90.804 25.128 ; + RECT 0.168 25.464 90.804 25.512 ; + RECT 0.168 25.848 90.804 25.896 ; + RECT 0.168 26.232 90.804 26.280 ; + RECT 0.168 26.616 90.804 26.664 ; + RECT 0.168 27.000 90.804 27.048 ; + RECT 0.168 27.384 90.804 27.432 ; + RECT 0.168 27.768 90.804 27.816 ; + RECT 0.168 28.152 90.804 28.200 ; + RECT 0.168 28.536 90.804 28.584 ; + RECT 0.168 28.920 90.804 28.968 ; + RECT 0.168 29.304 90.804 29.352 ; + RECT 0.168 29.688 90.804 29.736 ; + RECT 0.168 30.072 90.804 30.120 ; + RECT 0.168 30.456 90.804 30.504 ; + RECT 0.168 30.840 90.804 30.888 ; + RECT 0.168 31.224 90.804 31.272 ; + RECT 0.168 31.608 90.804 31.656 ; + RECT 0.168 31.992 90.804 32.040 ; + RECT 0.168 32.376 90.804 32.424 ; + RECT 0.168 32.760 90.804 32.808 ; + RECT 0.168 33.144 90.804 33.192 ; + RECT 0.168 33.528 90.804 33.576 ; + RECT 0.168 33.912 90.804 33.960 ; + RECT 0.168 34.296 90.804 34.344 ; + RECT 0.168 34.680 90.804 34.728 ; + RECT 0.168 35.064 90.804 35.112 ; + RECT 0.168 35.448 90.804 35.496 ; + RECT 0.168 35.832 90.804 35.880 ; + RECT 0.168 36.216 90.804 36.264 ; + RECT 0.168 36.600 90.804 36.648 ; + RECT 0.168 36.984 90.804 37.032 ; + RECT 0.168 37.368 90.804 37.416 ; + RECT 0.168 37.752 90.804 37.800 ; + RECT 0.168 38.136 90.804 38.184 ; + RECT 0.168 38.520 90.804 38.568 ; + RECT 0.168 38.904 90.804 38.952 ; + RECT 0.168 39.288 90.804 39.336 ; + RECT 0.168 39.672 90.804 39.720 ; + RECT 0.168 40.056 90.804 40.104 ; + RECT 0.168 40.440 90.804 40.488 ; + RECT 0.168 40.824 90.804 40.872 ; + RECT 0.168 41.208 90.804 41.256 ; + RECT 0.168 41.592 90.804 41.640 ; + RECT 0.168 41.976 90.804 42.024 ; + RECT 0.168 42.360 90.804 42.408 ; + RECT 0.168 42.744 90.804 42.792 ; + RECT 0.168 43.128 90.804 43.176 ; + RECT 0.168 43.512 90.804 43.560 ; + RECT 0.168 43.896 90.804 43.944 ; + RECT 0.168 44.280 90.804 44.328 ; + RECT 0.168 44.664 90.804 44.712 ; + RECT 0.168 45.048 90.804 45.096 ; + RECT 0.168 45.432 90.804 45.480 ; + RECT 0.168 45.816 90.804 45.864 ; + RECT 0.168 46.200 90.804 46.248 ; + RECT 0.168 46.584 90.804 46.632 ; + RECT 0.168 46.968 90.804 47.016 ; + RECT 0.168 47.352 90.804 47.400 ; + RECT 0.168 47.736 90.804 47.784 ; + RECT 0.168 48.120 90.804 48.168 ; + RECT 0.168 48.504 90.804 48.552 ; + RECT 0.168 48.888 90.804 48.936 ; + RECT 0.168 49.272 90.804 49.320 ; + RECT 0.168 49.656 90.804 49.704 ; + RECT 0.168 50.040 90.804 50.088 ; + RECT 0.168 50.424 90.804 50.472 ; + RECT 0.168 50.808 90.804 50.856 ; + RECT 0.168 51.192 90.804 51.240 ; + RECT 0.168 51.576 90.804 51.624 ; + RECT 0.168 51.960 90.804 52.008 ; + RECT 0.168 52.344 90.804 52.392 ; + RECT 0.168 52.728 90.804 52.776 ; + RECT 0.168 53.112 90.804 53.160 ; + RECT 0.168 53.496 90.804 53.544 ; + RECT 0.168 53.880 90.804 53.928 ; + RECT 0.168 54.264 90.804 54.312 ; + RECT 0.168 54.648 90.804 54.696 ; + RECT 0.168 55.032 90.804 55.080 ; + RECT 0.168 55.416 90.804 55.464 ; + RECT 0.168 55.800 90.804 55.848 ; + RECT 0.168 56.184 90.804 56.232 ; + RECT 0.168 56.568 90.804 56.616 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.168 0.120 90.804 0.168 ; + RECT 0.168 0.504 90.804 0.552 ; + RECT 0.168 0.888 90.804 0.936 ; + RECT 0.168 1.272 90.804 1.320 ; + RECT 0.168 1.656 90.804 1.704 ; + RECT 0.168 2.040 90.804 2.088 ; + RECT 0.168 2.424 90.804 2.472 ; + RECT 0.168 2.808 90.804 2.856 ; + RECT 0.168 3.192 90.804 3.240 ; + RECT 0.168 3.576 90.804 3.624 ; + RECT 0.168 3.960 90.804 4.008 ; + RECT 0.168 4.344 90.804 4.392 ; + RECT 0.168 4.728 90.804 4.776 ; + RECT 0.168 5.112 90.804 5.160 ; + RECT 0.168 5.496 90.804 5.544 ; + RECT 0.168 5.880 90.804 5.928 ; + RECT 0.168 6.264 90.804 6.312 ; + RECT 0.168 6.648 90.804 6.696 ; + RECT 0.168 7.032 90.804 7.080 ; + RECT 0.168 7.416 90.804 7.464 ; + RECT 0.168 7.800 90.804 7.848 ; + RECT 0.168 8.184 90.804 8.232 ; + RECT 0.168 8.568 90.804 8.616 ; + RECT 0.168 8.952 90.804 9.000 ; + RECT 0.168 9.336 90.804 9.384 ; + RECT 0.168 9.720 90.804 9.768 ; + RECT 0.168 10.104 90.804 10.152 ; + RECT 0.168 10.488 90.804 10.536 ; + RECT 0.168 10.872 90.804 10.920 ; + RECT 0.168 11.256 90.804 11.304 ; + RECT 0.168 11.640 90.804 11.688 ; + RECT 0.168 12.024 90.804 12.072 ; + RECT 0.168 12.408 90.804 12.456 ; + RECT 0.168 12.792 90.804 12.840 ; + RECT 0.168 13.176 90.804 13.224 ; + RECT 0.168 13.560 90.804 13.608 ; + RECT 0.168 13.944 90.804 13.992 ; + RECT 0.168 14.328 90.804 14.376 ; + RECT 0.168 14.712 90.804 14.760 ; + RECT 0.168 15.096 90.804 15.144 ; + RECT 0.168 15.480 90.804 15.528 ; + RECT 0.168 15.864 90.804 15.912 ; + RECT 0.168 16.248 90.804 16.296 ; + RECT 0.168 16.632 90.804 16.680 ; + RECT 0.168 17.016 90.804 17.064 ; + RECT 0.168 17.400 90.804 17.448 ; + RECT 0.168 17.784 90.804 17.832 ; + RECT 0.168 18.168 90.804 18.216 ; + RECT 0.168 18.552 90.804 18.600 ; + RECT 0.168 18.936 90.804 18.984 ; + RECT 0.168 19.320 90.804 19.368 ; + RECT 0.168 19.704 90.804 19.752 ; + RECT 0.168 20.088 90.804 20.136 ; + RECT 0.168 20.472 90.804 20.520 ; + RECT 0.168 20.856 90.804 20.904 ; + RECT 0.168 21.240 90.804 21.288 ; + RECT 0.168 21.624 90.804 21.672 ; + RECT 0.168 22.008 90.804 22.056 ; + RECT 0.168 22.392 90.804 22.440 ; + RECT 0.168 22.776 90.804 22.824 ; + RECT 0.168 23.160 90.804 23.208 ; + RECT 0.168 23.544 90.804 23.592 ; + RECT 0.168 23.928 90.804 23.976 ; + RECT 0.168 24.312 90.804 24.360 ; + RECT 0.168 24.696 90.804 24.744 ; + RECT 0.168 25.080 90.804 25.128 ; + RECT 0.168 25.464 90.804 25.512 ; + RECT 0.168 25.848 90.804 25.896 ; + RECT 0.168 26.232 90.804 26.280 ; + RECT 0.168 26.616 90.804 26.664 ; + RECT 0.168 27.000 90.804 27.048 ; + RECT 0.168 27.384 90.804 27.432 ; + RECT 0.168 27.768 90.804 27.816 ; + RECT 0.168 28.152 90.804 28.200 ; + RECT 0.168 28.536 90.804 28.584 ; + RECT 0.168 28.920 90.804 28.968 ; + RECT 0.168 29.304 90.804 29.352 ; + RECT 0.168 29.688 90.804 29.736 ; + RECT 0.168 30.072 90.804 30.120 ; + RECT 0.168 30.456 90.804 30.504 ; + RECT 0.168 30.840 90.804 30.888 ; + RECT 0.168 31.224 90.804 31.272 ; + RECT 0.168 31.608 90.804 31.656 ; + RECT 0.168 31.992 90.804 32.040 ; + RECT 0.168 32.376 90.804 32.424 ; + RECT 0.168 32.760 90.804 32.808 ; + RECT 0.168 33.144 90.804 33.192 ; + RECT 0.168 33.528 90.804 33.576 ; + RECT 0.168 33.912 90.804 33.960 ; + RECT 0.168 34.296 90.804 34.344 ; + RECT 0.168 34.680 90.804 34.728 ; + RECT 0.168 35.064 90.804 35.112 ; + RECT 0.168 35.448 90.804 35.496 ; + RECT 0.168 35.832 90.804 35.880 ; + RECT 0.168 36.216 90.804 36.264 ; + RECT 0.168 36.600 90.804 36.648 ; + RECT 0.168 36.984 90.804 37.032 ; + RECT 0.168 37.368 90.804 37.416 ; + RECT 0.168 37.752 90.804 37.800 ; + RECT 0.168 38.136 90.804 38.184 ; + RECT 0.168 38.520 90.804 38.568 ; + RECT 0.168 38.904 90.804 38.952 ; + RECT 0.168 39.288 90.804 39.336 ; + RECT 0.168 39.672 90.804 39.720 ; + RECT 0.168 40.056 90.804 40.104 ; + RECT 0.168 40.440 90.804 40.488 ; + RECT 0.168 40.824 90.804 40.872 ; + RECT 0.168 41.208 90.804 41.256 ; + RECT 0.168 41.592 90.804 41.640 ; + RECT 0.168 41.976 90.804 42.024 ; + RECT 0.168 42.360 90.804 42.408 ; + RECT 0.168 42.744 90.804 42.792 ; + RECT 0.168 43.128 90.804 43.176 ; + RECT 0.168 43.512 90.804 43.560 ; + RECT 0.168 43.896 90.804 43.944 ; + RECT 0.168 44.280 90.804 44.328 ; + RECT 0.168 44.664 90.804 44.712 ; + RECT 0.168 45.048 90.804 45.096 ; + RECT 0.168 45.432 90.804 45.480 ; + RECT 0.168 45.816 90.804 45.864 ; + RECT 0.168 46.200 90.804 46.248 ; + RECT 0.168 46.584 90.804 46.632 ; + RECT 0.168 46.968 90.804 47.016 ; + RECT 0.168 47.352 90.804 47.400 ; + RECT 0.168 47.736 90.804 47.784 ; + RECT 0.168 48.120 90.804 48.168 ; + RECT 0.168 48.504 90.804 48.552 ; + RECT 0.168 48.888 90.804 48.936 ; + RECT 0.168 49.272 90.804 49.320 ; + RECT 0.168 49.656 90.804 49.704 ; + RECT 0.168 50.040 90.804 50.088 ; + RECT 0.168 50.424 90.804 50.472 ; + RECT 0.168 50.808 90.804 50.856 ; + RECT 0.168 51.192 90.804 51.240 ; + RECT 0.168 51.576 90.804 51.624 ; + RECT 0.168 51.960 90.804 52.008 ; + RECT 0.168 52.344 90.804 52.392 ; + RECT 0.168 52.728 90.804 52.776 ; + RECT 0.168 53.112 90.804 53.160 ; + RECT 0.168 53.496 90.804 53.544 ; + RECT 0.168 53.880 90.804 53.928 ; + RECT 0.168 54.264 90.804 54.312 ; + RECT 0.168 54.648 90.804 54.696 ; + RECT 0.168 55.032 90.804 55.080 ; + RECT 0.168 55.416 90.804 55.464 ; + RECT 0.168 55.800 90.804 55.848 ; + RECT 0.168 56.184 90.804 56.232 ; + RECT 0.168 56.568 90.804 56.616 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 90.972 56.880 ; + LAYER M2 ; + RECT 0 0 90.972 56.880 ; + LAYER M3 ; + RECT 0 0 90.972 56.880 ; + LAYER M4 ; + RECT 0 0 90.972 56.880 ; + END +END fakeram_64x256_1r1w + +END LIBRARY diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_65x160_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_65x160_1r1w.lef new file mode 100644 index 00000000..c68328e3 --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_65x160_1r1w.lef @@ -0,0 +1,1763 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_65x160_1r1w + FOREIGN fakeram_65x160_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 46.200 BY 71.136 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 0.138 0.036 0.150 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 2.970 0.036 2.982 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 5.802 0.036 5.814 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 8.634 0.036 8.646 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 11.466 0.036 11.478 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 14.298 0.036 14.310 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 17.130 0.036 17.142 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 19.962 0.036 19.974 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 22.794 0.036 22.806 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 25.626 0.036 25.638 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 28.458 0.036 28.470 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 31.290 0.036 31.302 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 34.122 0.036 34.134 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 36.954 0.036 36.966 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 39.786 0.036 39.798 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 42.618 0.036 42.630 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 45.450 0.036 45.462 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.164 0.138 46.200 0.150 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.164 2.970 46.200 2.982 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.164 5.802 46.200 5.814 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.164 8.634 46.200 8.646 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.164 11.466 46.200 11.478 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.164 14.298 46.200 14.310 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.164 17.130 46.200 17.142 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.164 19.962 46.200 19.974 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.164 22.794 46.200 22.806 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.164 25.626 46.200 25.638 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.164 28.458 46.200 28.470 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.164 31.290 46.200 31.302 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.164 34.122 46.200 34.134 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.164 36.954 46.200 36.966 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.164 39.786 46.200 39.798 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.164 42.618 46.200 42.630 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 0.000 0.175 0.042 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.833 0.000 0.847 0.042 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.505 0.000 1.519 0.042 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.177 0.000 2.191 0.042 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.849 0.000 2.863 0.042 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.521 0.000 3.535 0.042 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.193 0.000 4.207 0.042 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.865 0.000 4.879 0.042 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.537 0.000 5.551 0.042 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.209 0.000 6.223 0.042 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.881 0.000 6.895 0.042 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.553 0.000 7.567 0.042 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.225 0.000 8.239 0.042 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.897 0.000 8.911 0.042 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.569 0.000 9.583 0.042 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.241 0.000 10.255 0.042 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.913 0.000 10.927 0.042 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.585 0.000 11.599 0.042 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.257 0.000 12.271 0.042 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.929 0.000 12.943 0.042 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.601 0.000 13.615 0.042 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.273 0.000 14.287 0.042 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.945 0.000 14.959 0.042 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.617 0.000 15.631 0.042 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.289 0.000 16.303 0.042 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.961 0.000 16.975 0.042 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.633 0.000 17.647 0.042 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.305 0.000 18.319 0.042 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.977 0.000 18.991 0.042 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.649 0.000 19.663 0.042 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.321 0.000 20.335 0.042 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.993 0.000 21.007 0.042 ; + END + END w0_wd_in[64] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.665 0.000 21.679 0.042 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.337 0.000 22.351 0.042 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.009 0.000 23.023 0.042 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.681 0.000 23.695 0.042 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.353 0.000 24.367 0.042 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.025 0.000 25.039 0.042 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.697 0.000 25.711 0.042 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.369 0.000 26.383 0.042 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.041 0.000 27.055 0.042 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.713 0.000 27.727 0.042 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.385 0.000 28.399 0.042 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.057 0.000 29.071 0.042 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.729 0.000 29.743 0.042 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.401 0.000 30.415 0.042 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.073 0.000 31.087 0.042 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.745 0.000 31.759 0.042 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.417 0.000 32.431 0.042 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.089 0.000 33.103 0.042 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.761 0.000 33.775 0.042 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.433 0.000 34.447 0.042 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.105 0.000 35.119 0.042 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.777 0.000 35.791 0.042 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.449 0.000 36.463 0.042 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.121 0.000 37.135 0.042 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.793 0.000 37.807 0.042 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.465 0.000 38.479 0.042 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.137 0.000 39.151 0.042 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.809 0.000 39.823 0.042 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.481 0.000 40.495 0.042 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.153 0.000 41.167 0.042 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.825 0.000 41.839 0.042 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.497 0.000 42.511 0.042 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.169 0.000 43.183 0.042 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 71.094 0.175 71.136 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.365 71.094 1.379 71.136 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.569 71.094 2.583 71.136 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.773 71.094 3.787 71.136 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.977 71.094 4.991 71.136 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.181 71.094 6.195 71.136 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.385 71.094 7.399 71.136 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.589 71.094 8.603 71.136 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.793 71.094 9.807 71.136 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.997 71.094 11.011 71.136 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.201 71.094 12.215 71.136 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.405 71.094 13.419 71.136 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.609 71.094 14.623 71.136 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.813 71.094 15.827 71.136 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.017 71.094 17.031 71.136 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.221 71.094 18.235 71.136 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.425 71.094 19.439 71.136 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.629 71.094 20.643 71.136 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.833 71.094 21.847 71.136 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.037 71.094 23.051 71.136 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.241 71.094 24.255 71.136 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.445 71.094 25.459 71.136 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.649 71.094 26.663 71.136 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.853 71.094 27.867 71.136 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.057 71.094 29.071 71.136 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.261 71.094 30.275 71.136 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.465 71.094 31.479 71.136 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.669 71.094 32.683 71.136 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.873 71.094 33.887 71.136 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.077 71.094 35.091 71.136 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.281 71.094 36.295 71.136 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.485 71.094 37.499 71.136 ; + END + END r0_rd_out[64] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 48.282 0.036 48.294 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 51.114 0.036 51.126 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 53.946 0.036 53.958 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 56.778 0.036 56.790 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.164 45.450 46.200 45.462 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.164 48.282 46.200 48.294 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.164 51.114 46.200 51.126 ; + END + END w0_addr_in[6] + PIN w0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.164 53.946 46.200 53.958 ; + END + END w0_addr_in[7] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 59.610 0.036 59.622 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 62.442 0.036 62.454 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 65.274 0.036 65.286 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 68.106 0.036 68.118 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.164 56.778 46.200 56.790 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.164 59.610 46.200 59.622 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.164 62.442 46.200 62.454 ; + END + END r0_addr_in[6] + PIN r0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.164 65.274 46.200 65.286 ; + END + END r0_addr_in[7] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.689 71.094 38.703 71.136 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.893 71.094 39.907 71.136 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.097 71.094 41.111 71.136 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.301 71.094 42.315 71.136 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.505 71.094 43.519 71.136 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.168 0.120 46.032 0.168 ; + RECT 0.168 0.504 46.032 0.552 ; + RECT 0.168 0.888 46.032 0.936 ; + RECT 0.168 1.272 46.032 1.320 ; + RECT 0.168 1.656 46.032 1.704 ; + RECT 0.168 2.040 46.032 2.088 ; + RECT 0.168 2.424 46.032 2.472 ; + RECT 0.168 2.808 46.032 2.856 ; + RECT 0.168 3.192 46.032 3.240 ; + RECT 0.168 3.576 46.032 3.624 ; + RECT 0.168 3.960 46.032 4.008 ; + RECT 0.168 4.344 46.032 4.392 ; + RECT 0.168 4.728 46.032 4.776 ; + RECT 0.168 5.112 46.032 5.160 ; + RECT 0.168 5.496 46.032 5.544 ; + RECT 0.168 5.880 46.032 5.928 ; + RECT 0.168 6.264 46.032 6.312 ; + RECT 0.168 6.648 46.032 6.696 ; + RECT 0.168 7.032 46.032 7.080 ; + RECT 0.168 7.416 46.032 7.464 ; + RECT 0.168 7.800 46.032 7.848 ; + RECT 0.168 8.184 46.032 8.232 ; + RECT 0.168 8.568 46.032 8.616 ; + RECT 0.168 8.952 46.032 9.000 ; + RECT 0.168 9.336 46.032 9.384 ; + RECT 0.168 9.720 46.032 9.768 ; + RECT 0.168 10.104 46.032 10.152 ; + RECT 0.168 10.488 46.032 10.536 ; + RECT 0.168 10.872 46.032 10.920 ; + RECT 0.168 11.256 46.032 11.304 ; + RECT 0.168 11.640 46.032 11.688 ; + RECT 0.168 12.024 46.032 12.072 ; + RECT 0.168 12.408 46.032 12.456 ; + RECT 0.168 12.792 46.032 12.840 ; + RECT 0.168 13.176 46.032 13.224 ; + RECT 0.168 13.560 46.032 13.608 ; + RECT 0.168 13.944 46.032 13.992 ; + RECT 0.168 14.328 46.032 14.376 ; + RECT 0.168 14.712 46.032 14.760 ; + RECT 0.168 15.096 46.032 15.144 ; + RECT 0.168 15.480 46.032 15.528 ; + RECT 0.168 15.864 46.032 15.912 ; + RECT 0.168 16.248 46.032 16.296 ; + RECT 0.168 16.632 46.032 16.680 ; + RECT 0.168 17.016 46.032 17.064 ; + RECT 0.168 17.400 46.032 17.448 ; + RECT 0.168 17.784 46.032 17.832 ; + RECT 0.168 18.168 46.032 18.216 ; + RECT 0.168 18.552 46.032 18.600 ; + RECT 0.168 18.936 46.032 18.984 ; + RECT 0.168 19.320 46.032 19.368 ; + RECT 0.168 19.704 46.032 19.752 ; + RECT 0.168 20.088 46.032 20.136 ; + RECT 0.168 20.472 46.032 20.520 ; + RECT 0.168 20.856 46.032 20.904 ; + RECT 0.168 21.240 46.032 21.288 ; + RECT 0.168 21.624 46.032 21.672 ; + RECT 0.168 22.008 46.032 22.056 ; + RECT 0.168 22.392 46.032 22.440 ; + RECT 0.168 22.776 46.032 22.824 ; + RECT 0.168 23.160 46.032 23.208 ; + RECT 0.168 23.544 46.032 23.592 ; + RECT 0.168 23.928 46.032 23.976 ; + RECT 0.168 24.312 46.032 24.360 ; + RECT 0.168 24.696 46.032 24.744 ; + RECT 0.168 25.080 46.032 25.128 ; + RECT 0.168 25.464 46.032 25.512 ; + RECT 0.168 25.848 46.032 25.896 ; + RECT 0.168 26.232 46.032 26.280 ; + RECT 0.168 26.616 46.032 26.664 ; + RECT 0.168 27.000 46.032 27.048 ; + RECT 0.168 27.384 46.032 27.432 ; + RECT 0.168 27.768 46.032 27.816 ; + RECT 0.168 28.152 46.032 28.200 ; + RECT 0.168 28.536 46.032 28.584 ; + RECT 0.168 28.920 46.032 28.968 ; + RECT 0.168 29.304 46.032 29.352 ; + RECT 0.168 29.688 46.032 29.736 ; + RECT 0.168 30.072 46.032 30.120 ; + RECT 0.168 30.456 46.032 30.504 ; + RECT 0.168 30.840 46.032 30.888 ; + RECT 0.168 31.224 46.032 31.272 ; + RECT 0.168 31.608 46.032 31.656 ; + RECT 0.168 31.992 46.032 32.040 ; + RECT 0.168 32.376 46.032 32.424 ; + RECT 0.168 32.760 46.032 32.808 ; + RECT 0.168 33.144 46.032 33.192 ; + RECT 0.168 33.528 46.032 33.576 ; + RECT 0.168 33.912 46.032 33.960 ; + RECT 0.168 34.296 46.032 34.344 ; + RECT 0.168 34.680 46.032 34.728 ; + RECT 0.168 35.064 46.032 35.112 ; + RECT 0.168 35.448 46.032 35.496 ; + RECT 0.168 35.832 46.032 35.880 ; + RECT 0.168 36.216 46.032 36.264 ; + RECT 0.168 36.600 46.032 36.648 ; + RECT 0.168 36.984 46.032 37.032 ; + RECT 0.168 37.368 46.032 37.416 ; + RECT 0.168 37.752 46.032 37.800 ; + RECT 0.168 38.136 46.032 38.184 ; + RECT 0.168 38.520 46.032 38.568 ; + RECT 0.168 38.904 46.032 38.952 ; + RECT 0.168 39.288 46.032 39.336 ; + RECT 0.168 39.672 46.032 39.720 ; + RECT 0.168 40.056 46.032 40.104 ; + RECT 0.168 40.440 46.032 40.488 ; + RECT 0.168 40.824 46.032 40.872 ; + RECT 0.168 41.208 46.032 41.256 ; + RECT 0.168 41.592 46.032 41.640 ; + RECT 0.168 41.976 46.032 42.024 ; + RECT 0.168 42.360 46.032 42.408 ; + RECT 0.168 42.744 46.032 42.792 ; + RECT 0.168 43.128 46.032 43.176 ; + RECT 0.168 43.512 46.032 43.560 ; + RECT 0.168 43.896 46.032 43.944 ; + RECT 0.168 44.280 46.032 44.328 ; + RECT 0.168 44.664 46.032 44.712 ; + RECT 0.168 45.048 46.032 45.096 ; + RECT 0.168 45.432 46.032 45.480 ; + RECT 0.168 45.816 46.032 45.864 ; + RECT 0.168 46.200 46.032 46.248 ; + RECT 0.168 46.584 46.032 46.632 ; + RECT 0.168 46.968 46.032 47.016 ; + RECT 0.168 47.352 46.032 47.400 ; + RECT 0.168 47.736 46.032 47.784 ; + RECT 0.168 48.120 46.032 48.168 ; + RECT 0.168 48.504 46.032 48.552 ; + RECT 0.168 48.888 46.032 48.936 ; + RECT 0.168 49.272 46.032 49.320 ; + RECT 0.168 49.656 46.032 49.704 ; + RECT 0.168 50.040 46.032 50.088 ; + RECT 0.168 50.424 46.032 50.472 ; + RECT 0.168 50.808 46.032 50.856 ; + RECT 0.168 51.192 46.032 51.240 ; + RECT 0.168 51.576 46.032 51.624 ; + RECT 0.168 51.960 46.032 52.008 ; + RECT 0.168 52.344 46.032 52.392 ; + RECT 0.168 52.728 46.032 52.776 ; + RECT 0.168 53.112 46.032 53.160 ; + RECT 0.168 53.496 46.032 53.544 ; + RECT 0.168 53.880 46.032 53.928 ; + RECT 0.168 54.264 46.032 54.312 ; + RECT 0.168 54.648 46.032 54.696 ; + RECT 0.168 55.032 46.032 55.080 ; + RECT 0.168 55.416 46.032 55.464 ; + RECT 0.168 55.800 46.032 55.848 ; + RECT 0.168 56.184 46.032 56.232 ; + RECT 0.168 56.568 46.032 56.616 ; + RECT 0.168 56.952 46.032 57.000 ; + RECT 0.168 57.336 46.032 57.384 ; + RECT 0.168 57.720 46.032 57.768 ; + RECT 0.168 58.104 46.032 58.152 ; + RECT 0.168 58.488 46.032 58.536 ; + RECT 0.168 58.872 46.032 58.920 ; + RECT 0.168 59.256 46.032 59.304 ; + RECT 0.168 59.640 46.032 59.688 ; + RECT 0.168 60.024 46.032 60.072 ; + RECT 0.168 60.408 46.032 60.456 ; + RECT 0.168 60.792 46.032 60.840 ; + RECT 0.168 61.176 46.032 61.224 ; + RECT 0.168 61.560 46.032 61.608 ; + RECT 0.168 61.944 46.032 61.992 ; + RECT 0.168 62.328 46.032 62.376 ; + RECT 0.168 62.712 46.032 62.760 ; + RECT 0.168 63.096 46.032 63.144 ; + RECT 0.168 63.480 46.032 63.528 ; + RECT 0.168 63.864 46.032 63.912 ; + RECT 0.168 64.248 46.032 64.296 ; + RECT 0.168 64.632 46.032 64.680 ; + RECT 0.168 65.016 46.032 65.064 ; + RECT 0.168 65.400 46.032 65.448 ; + RECT 0.168 65.784 46.032 65.832 ; + RECT 0.168 66.168 46.032 66.216 ; + RECT 0.168 66.552 46.032 66.600 ; + RECT 0.168 66.936 46.032 66.984 ; + RECT 0.168 67.320 46.032 67.368 ; + RECT 0.168 67.704 46.032 67.752 ; + RECT 0.168 68.088 46.032 68.136 ; + RECT 0.168 68.472 46.032 68.520 ; + RECT 0.168 68.856 46.032 68.904 ; + RECT 0.168 69.240 46.032 69.288 ; + RECT 0.168 69.624 46.032 69.672 ; + RECT 0.168 70.008 46.032 70.056 ; + RECT 0.168 70.392 46.032 70.440 ; + RECT 0.168 70.776 46.032 70.824 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.168 0.120 46.032 0.168 ; + RECT 0.168 0.504 46.032 0.552 ; + RECT 0.168 0.888 46.032 0.936 ; + RECT 0.168 1.272 46.032 1.320 ; + RECT 0.168 1.656 46.032 1.704 ; + RECT 0.168 2.040 46.032 2.088 ; + RECT 0.168 2.424 46.032 2.472 ; + RECT 0.168 2.808 46.032 2.856 ; + RECT 0.168 3.192 46.032 3.240 ; + RECT 0.168 3.576 46.032 3.624 ; + RECT 0.168 3.960 46.032 4.008 ; + RECT 0.168 4.344 46.032 4.392 ; + RECT 0.168 4.728 46.032 4.776 ; + RECT 0.168 5.112 46.032 5.160 ; + RECT 0.168 5.496 46.032 5.544 ; + RECT 0.168 5.880 46.032 5.928 ; + RECT 0.168 6.264 46.032 6.312 ; + RECT 0.168 6.648 46.032 6.696 ; + RECT 0.168 7.032 46.032 7.080 ; + RECT 0.168 7.416 46.032 7.464 ; + RECT 0.168 7.800 46.032 7.848 ; + RECT 0.168 8.184 46.032 8.232 ; + RECT 0.168 8.568 46.032 8.616 ; + RECT 0.168 8.952 46.032 9.000 ; + RECT 0.168 9.336 46.032 9.384 ; + RECT 0.168 9.720 46.032 9.768 ; + RECT 0.168 10.104 46.032 10.152 ; + RECT 0.168 10.488 46.032 10.536 ; + RECT 0.168 10.872 46.032 10.920 ; + RECT 0.168 11.256 46.032 11.304 ; + RECT 0.168 11.640 46.032 11.688 ; + RECT 0.168 12.024 46.032 12.072 ; + RECT 0.168 12.408 46.032 12.456 ; + RECT 0.168 12.792 46.032 12.840 ; + RECT 0.168 13.176 46.032 13.224 ; + RECT 0.168 13.560 46.032 13.608 ; + RECT 0.168 13.944 46.032 13.992 ; + RECT 0.168 14.328 46.032 14.376 ; + RECT 0.168 14.712 46.032 14.760 ; + RECT 0.168 15.096 46.032 15.144 ; + RECT 0.168 15.480 46.032 15.528 ; + RECT 0.168 15.864 46.032 15.912 ; + RECT 0.168 16.248 46.032 16.296 ; + RECT 0.168 16.632 46.032 16.680 ; + RECT 0.168 17.016 46.032 17.064 ; + RECT 0.168 17.400 46.032 17.448 ; + RECT 0.168 17.784 46.032 17.832 ; + RECT 0.168 18.168 46.032 18.216 ; + RECT 0.168 18.552 46.032 18.600 ; + RECT 0.168 18.936 46.032 18.984 ; + RECT 0.168 19.320 46.032 19.368 ; + RECT 0.168 19.704 46.032 19.752 ; + RECT 0.168 20.088 46.032 20.136 ; + RECT 0.168 20.472 46.032 20.520 ; + RECT 0.168 20.856 46.032 20.904 ; + RECT 0.168 21.240 46.032 21.288 ; + RECT 0.168 21.624 46.032 21.672 ; + RECT 0.168 22.008 46.032 22.056 ; + RECT 0.168 22.392 46.032 22.440 ; + RECT 0.168 22.776 46.032 22.824 ; + RECT 0.168 23.160 46.032 23.208 ; + RECT 0.168 23.544 46.032 23.592 ; + RECT 0.168 23.928 46.032 23.976 ; + RECT 0.168 24.312 46.032 24.360 ; + RECT 0.168 24.696 46.032 24.744 ; + RECT 0.168 25.080 46.032 25.128 ; + RECT 0.168 25.464 46.032 25.512 ; + RECT 0.168 25.848 46.032 25.896 ; + RECT 0.168 26.232 46.032 26.280 ; + RECT 0.168 26.616 46.032 26.664 ; + RECT 0.168 27.000 46.032 27.048 ; + RECT 0.168 27.384 46.032 27.432 ; + RECT 0.168 27.768 46.032 27.816 ; + RECT 0.168 28.152 46.032 28.200 ; + RECT 0.168 28.536 46.032 28.584 ; + RECT 0.168 28.920 46.032 28.968 ; + RECT 0.168 29.304 46.032 29.352 ; + RECT 0.168 29.688 46.032 29.736 ; + RECT 0.168 30.072 46.032 30.120 ; + RECT 0.168 30.456 46.032 30.504 ; + RECT 0.168 30.840 46.032 30.888 ; + RECT 0.168 31.224 46.032 31.272 ; + RECT 0.168 31.608 46.032 31.656 ; + RECT 0.168 31.992 46.032 32.040 ; + RECT 0.168 32.376 46.032 32.424 ; + RECT 0.168 32.760 46.032 32.808 ; + RECT 0.168 33.144 46.032 33.192 ; + RECT 0.168 33.528 46.032 33.576 ; + RECT 0.168 33.912 46.032 33.960 ; + RECT 0.168 34.296 46.032 34.344 ; + RECT 0.168 34.680 46.032 34.728 ; + RECT 0.168 35.064 46.032 35.112 ; + RECT 0.168 35.448 46.032 35.496 ; + RECT 0.168 35.832 46.032 35.880 ; + RECT 0.168 36.216 46.032 36.264 ; + RECT 0.168 36.600 46.032 36.648 ; + RECT 0.168 36.984 46.032 37.032 ; + RECT 0.168 37.368 46.032 37.416 ; + RECT 0.168 37.752 46.032 37.800 ; + RECT 0.168 38.136 46.032 38.184 ; + RECT 0.168 38.520 46.032 38.568 ; + RECT 0.168 38.904 46.032 38.952 ; + RECT 0.168 39.288 46.032 39.336 ; + RECT 0.168 39.672 46.032 39.720 ; + RECT 0.168 40.056 46.032 40.104 ; + RECT 0.168 40.440 46.032 40.488 ; + RECT 0.168 40.824 46.032 40.872 ; + RECT 0.168 41.208 46.032 41.256 ; + RECT 0.168 41.592 46.032 41.640 ; + RECT 0.168 41.976 46.032 42.024 ; + RECT 0.168 42.360 46.032 42.408 ; + RECT 0.168 42.744 46.032 42.792 ; + RECT 0.168 43.128 46.032 43.176 ; + RECT 0.168 43.512 46.032 43.560 ; + RECT 0.168 43.896 46.032 43.944 ; + RECT 0.168 44.280 46.032 44.328 ; + RECT 0.168 44.664 46.032 44.712 ; + RECT 0.168 45.048 46.032 45.096 ; + RECT 0.168 45.432 46.032 45.480 ; + RECT 0.168 45.816 46.032 45.864 ; + RECT 0.168 46.200 46.032 46.248 ; + RECT 0.168 46.584 46.032 46.632 ; + RECT 0.168 46.968 46.032 47.016 ; + RECT 0.168 47.352 46.032 47.400 ; + RECT 0.168 47.736 46.032 47.784 ; + RECT 0.168 48.120 46.032 48.168 ; + RECT 0.168 48.504 46.032 48.552 ; + RECT 0.168 48.888 46.032 48.936 ; + RECT 0.168 49.272 46.032 49.320 ; + RECT 0.168 49.656 46.032 49.704 ; + RECT 0.168 50.040 46.032 50.088 ; + RECT 0.168 50.424 46.032 50.472 ; + RECT 0.168 50.808 46.032 50.856 ; + RECT 0.168 51.192 46.032 51.240 ; + RECT 0.168 51.576 46.032 51.624 ; + RECT 0.168 51.960 46.032 52.008 ; + RECT 0.168 52.344 46.032 52.392 ; + RECT 0.168 52.728 46.032 52.776 ; + RECT 0.168 53.112 46.032 53.160 ; + RECT 0.168 53.496 46.032 53.544 ; + RECT 0.168 53.880 46.032 53.928 ; + RECT 0.168 54.264 46.032 54.312 ; + RECT 0.168 54.648 46.032 54.696 ; + RECT 0.168 55.032 46.032 55.080 ; + RECT 0.168 55.416 46.032 55.464 ; + RECT 0.168 55.800 46.032 55.848 ; + RECT 0.168 56.184 46.032 56.232 ; + RECT 0.168 56.568 46.032 56.616 ; + RECT 0.168 56.952 46.032 57.000 ; + RECT 0.168 57.336 46.032 57.384 ; + RECT 0.168 57.720 46.032 57.768 ; + RECT 0.168 58.104 46.032 58.152 ; + RECT 0.168 58.488 46.032 58.536 ; + RECT 0.168 58.872 46.032 58.920 ; + RECT 0.168 59.256 46.032 59.304 ; + RECT 0.168 59.640 46.032 59.688 ; + RECT 0.168 60.024 46.032 60.072 ; + RECT 0.168 60.408 46.032 60.456 ; + RECT 0.168 60.792 46.032 60.840 ; + RECT 0.168 61.176 46.032 61.224 ; + RECT 0.168 61.560 46.032 61.608 ; + RECT 0.168 61.944 46.032 61.992 ; + RECT 0.168 62.328 46.032 62.376 ; + RECT 0.168 62.712 46.032 62.760 ; + RECT 0.168 63.096 46.032 63.144 ; + RECT 0.168 63.480 46.032 63.528 ; + RECT 0.168 63.864 46.032 63.912 ; + RECT 0.168 64.248 46.032 64.296 ; + RECT 0.168 64.632 46.032 64.680 ; + RECT 0.168 65.016 46.032 65.064 ; + RECT 0.168 65.400 46.032 65.448 ; + RECT 0.168 65.784 46.032 65.832 ; + RECT 0.168 66.168 46.032 66.216 ; + RECT 0.168 66.552 46.032 66.600 ; + RECT 0.168 66.936 46.032 66.984 ; + RECT 0.168 67.320 46.032 67.368 ; + RECT 0.168 67.704 46.032 67.752 ; + RECT 0.168 68.088 46.032 68.136 ; + RECT 0.168 68.472 46.032 68.520 ; + RECT 0.168 68.856 46.032 68.904 ; + RECT 0.168 69.240 46.032 69.288 ; + RECT 0.168 69.624 46.032 69.672 ; + RECT 0.168 70.008 46.032 70.056 ; + RECT 0.168 70.392 46.032 70.440 ; + RECT 0.168 70.776 46.032 70.824 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 46.200 71.136 ; + LAYER M2 ; + RECT 0 0 46.200 71.136 ; + LAYER M3 ; + RECT 0 0 46.200 71.136 ; + LAYER M4 ; + RECT 0 0 46.200 71.136 ; + END +END fakeram_65x160_1r1w + +END LIBRARY diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_66x64_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_66x64_1r1w.lef new file mode 100644 index 00000000..422e5adf --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_66x64_1r1w.lef @@ -0,0 +1,1523 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_66x64_1r1w + FOREIGN fakeram_66x64_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 46.914 BY 28.512 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 0.138 0.036 0.150 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 1.362 0.036 1.374 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 2.586 0.036 2.598 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 3.810 0.036 3.822 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 5.034 0.036 5.046 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 6.258 0.036 6.270 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 7.482 0.036 7.494 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 8.706 0.036 8.718 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 9.930 0.036 9.942 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 11.154 0.036 11.166 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 12.378 0.036 12.390 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 13.602 0.036 13.614 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 14.826 0.036 14.838 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 16.050 0.036 16.062 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 17.274 0.036 17.286 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 18.498 0.036 18.510 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 19.722 0.036 19.734 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 0.138 46.914 0.150 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 1.362 46.914 1.374 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 2.586 46.914 2.598 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 3.810 46.914 3.822 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 5.034 46.914 5.046 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 6.258 46.914 6.270 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 7.482 46.914 7.494 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 8.706 46.914 8.718 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 9.930 46.914 9.942 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 11.154 46.914 11.166 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 12.378 46.914 12.390 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 13.602 46.914 13.614 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 14.826 46.914 14.838 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 16.050 46.914 16.062 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 17.274 46.914 17.286 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 18.498 46.914 18.510 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 0.000 0.175 0.042 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.861 0.000 0.875 0.042 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.561 0.000 1.575 0.042 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.261 0.000 2.275 0.042 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.961 0.000 2.975 0.042 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.661 0.000 3.675 0.042 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.361 0.000 4.375 0.042 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.061 0.000 5.075 0.042 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.761 0.000 5.775 0.042 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.461 0.000 6.475 0.042 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.161 0.000 7.175 0.042 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.861 0.000 7.875 0.042 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.561 0.000 8.575 0.042 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.261 0.000 9.275 0.042 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.961 0.000 9.975 0.042 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.661 0.000 10.675 0.042 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.361 0.000 11.375 0.042 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.061 0.000 12.075 0.042 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.761 0.000 12.775 0.042 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.461 0.000 13.475 0.042 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.161 0.000 14.175 0.042 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.861 0.000 14.875 0.042 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.561 0.000 15.575 0.042 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.261 0.000 16.275 0.042 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.961 0.000 16.975 0.042 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.661 0.000 17.675 0.042 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.361 0.000 18.375 0.042 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.061 0.000 19.075 0.042 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.761 0.000 19.775 0.042 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.461 0.000 20.475 0.042 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.161 0.000 21.175 0.042 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.861 0.000 21.875 0.042 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.561 0.000 22.575 0.042 ; + END + END w0_wd_in[65] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.261 0.000 23.275 0.042 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.961 0.000 23.975 0.042 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.661 0.000 24.675 0.042 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.361 0.000 25.375 0.042 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.061 0.000 26.075 0.042 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.761 0.000 26.775 0.042 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.461 0.000 27.475 0.042 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.161 0.000 28.175 0.042 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.861 0.000 28.875 0.042 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.561 0.000 29.575 0.042 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.261 0.000 30.275 0.042 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.961 0.000 30.975 0.042 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.661 0.000 31.675 0.042 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.361 0.000 32.375 0.042 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.061 0.000 33.075 0.042 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.761 0.000 33.775 0.042 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.461 0.000 34.475 0.042 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.161 0.000 35.175 0.042 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.861 0.000 35.875 0.042 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.561 0.000 36.575 0.042 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.261 0.000 37.275 0.042 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.961 0.000 37.975 0.042 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.661 0.000 38.675 0.042 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.361 0.000 39.375 0.042 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.061 0.000 40.075 0.042 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.761 0.000 40.775 0.042 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.461 0.000 41.475 0.042 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.161 0.000 42.175 0.042 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.861 0.000 42.875 0.042 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.561 0.000 43.575 0.042 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.261 0.000 44.275 0.042 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.961 0.000 44.975 0.042 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.661 0.000 45.675 0.042 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 28.470 0.175 28.512 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.365 28.470 1.379 28.512 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.569 28.470 2.583 28.512 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.773 28.470 3.787 28.512 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.977 28.470 4.991 28.512 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.181 28.470 6.195 28.512 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.385 28.470 7.399 28.512 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.589 28.470 8.603 28.512 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.793 28.470 9.807 28.512 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.997 28.470 11.011 28.512 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.201 28.470 12.215 28.512 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.405 28.470 13.419 28.512 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.609 28.470 14.623 28.512 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.813 28.470 15.827 28.512 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.017 28.470 17.031 28.512 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.221 28.470 18.235 28.512 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.425 28.470 19.439 28.512 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.629 28.470 20.643 28.512 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.833 28.470 21.847 28.512 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.037 28.470 23.051 28.512 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.241 28.470 24.255 28.512 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.445 28.470 25.459 28.512 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.649 28.470 26.663 28.512 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.853 28.470 27.867 28.512 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.057 28.470 29.071 28.512 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.261 28.470 30.275 28.512 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.465 28.470 31.479 28.512 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.669 28.470 32.683 28.512 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.873 28.470 33.887 28.512 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.077 28.470 35.091 28.512 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.281 28.470 36.295 28.512 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.485 28.470 37.499 28.512 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.689 28.470 38.703 28.512 ; + END + END r0_rd_out[65] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 20.946 0.036 20.958 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 22.170 0.036 22.182 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 23.394 0.036 23.406 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 19.722 46.914 19.734 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 20.946 46.914 20.958 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 22.170 46.914 22.182 ; + END + END w0_addr_in[5] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 24.618 0.036 24.630 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 25.842 0.036 25.854 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 27.066 0.036 27.078 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 23.394 46.914 23.406 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 24.618 46.914 24.630 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 25.842 46.914 25.854 ; + END + END r0_addr_in[5] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.893 28.470 39.907 28.512 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.097 28.470 41.111 28.512 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.301 28.470 42.315 28.512 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.505 28.470 43.519 28.512 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.709 28.470 44.723 28.512 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.168 0.120 46.746 0.168 ; + RECT 0.168 0.504 46.746 0.552 ; + RECT 0.168 0.888 46.746 0.936 ; + RECT 0.168 1.272 46.746 1.320 ; + RECT 0.168 1.656 46.746 1.704 ; + RECT 0.168 2.040 46.746 2.088 ; + RECT 0.168 2.424 46.746 2.472 ; + RECT 0.168 2.808 46.746 2.856 ; + RECT 0.168 3.192 46.746 3.240 ; + RECT 0.168 3.576 46.746 3.624 ; + RECT 0.168 3.960 46.746 4.008 ; + RECT 0.168 4.344 46.746 4.392 ; + RECT 0.168 4.728 46.746 4.776 ; + RECT 0.168 5.112 46.746 5.160 ; + RECT 0.168 5.496 46.746 5.544 ; + RECT 0.168 5.880 46.746 5.928 ; + RECT 0.168 6.264 46.746 6.312 ; + RECT 0.168 6.648 46.746 6.696 ; + RECT 0.168 7.032 46.746 7.080 ; + RECT 0.168 7.416 46.746 7.464 ; + RECT 0.168 7.800 46.746 7.848 ; + RECT 0.168 8.184 46.746 8.232 ; + RECT 0.168 8.568 46.746 8.616 ; + RECT 0.168 8.952 46.746 9.000 ; + RECT 0.168 9.336 46.746 9.384 ; + RECT 0.168 9.720 46.746 9.768 ; + RECT 0.168 10.104 46.746 10.152 ; + RECT 0.168 10.488 46.746 10.536 ; + RECT 0.168 10.872 46.746 10.920 ; + RECT 0.168 11.256 46.746 11.304 ; + RECT 0.168 11.640 46.746 11.688 ; + RECT 0.168 12.024 46.746 12.072 ; + RECT 0.168 12.408 46.746 12.456 ; + RECT 0.168 12.792 46.746 12.840 ; + RECT 0.168 13.176 46.746 13.224 ; + RECT 0.168 13.560 46.746 13.608 ; + RECT 0.168 13.944 46.746 13.992 ; + RECT 0.168 14.328 46.746 14.376 ; + RECT 0.168 14.712 46.746 14.760 ; + RECT 0.168 15.096 46.746 15.144 ; + RECT 0.168 15.480 46.746 15.528 ; + RECT 0.168 15.864 46.746 15.912 ; + RECT 0.168 16.248 46.746 16.296 ; + RECT 0.168 16.632 46.746 16.680 ; + RECT 0.168 17.016 46.746 17.064 ; + RECT 0.168 17.400 46.746 17.448 ; + RECT 0.168 17.784 46.746 17.832 ; + RECT 0.168 18.168 46.746 18.216 ; + RECT 0.168 18.552 46.746 18.600 ; + RECT 0.168 18.936 46.746 18.984 ; + RECT 0.168 19.320 46.746 19.368 ; + RECT 0.168 19.704 46.746 19.752 ; + RECT 0.168 20.088 46.746 20.136 ; + RECT 0.168 20.472 46.746 20.520 ; + RECT 0.168 20.856 46.746 20.904 ; + RECT 0.168 21.240 46.746 21.288 ; + RECT 0.168 21.624 46.746 21.672 ; + RECT 0.168 22.008 46.746 22.056 ; + RECT 0.168 22.392 46.746 22.440 ; + RECT 0.168 22.776 46.746 22.824 ; + RECT 0.168 23.160 46.746 23.208 ; + RECT 0.168 23.544 46.746 23.592 ; + RECT 0.168 23.928 46.746 23.976 ; + RECT 0.168 24.312 46.746 24.360 ; + RECT 0.168 24.696 46.746 24.744 ; + RECT 0.168 25.080 46.746 25.128 ; + RECT 0.168 25.464 46.746 25.512 ; + RECT 0.168 25.848 46.746 25.896 ; + RECT 0.168 26.232 46.746 26.280 ; + RECT 0.168 26.616 46.746 26.664 ; + RECT 0.168 27.000 46.746 27.048 ; + RECT 0.168 27.384 46.746 27.432 ; + RECT 0.168 27.768 46.746 27.816 ; + RECT 0.168 28.152 46.746 28.200 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.168 0.120 46.746 0.168 ; + RECT 0.168 0.504 46.746 0.552 ; + RECT 0.168 0.888 46.746 0.936 ; + RECT 0.168 1.272 46.746 1.320 ; + RECT 0.168 1.656 46.746 1.704 ; + RECT 0.168 2.040 46.746 2.088 ; + RECT 0.168 2.424 46.746 2.472 ; + RECT 0.168 2.808 46.746 2.856 ; + RECT 0.168 3.192 46.746 3.240 ; + RECT 0.168 3.576 46.746 3.624 ; + RECT 0.168 3.960 46.746 4.008 ; + RECT 0.168 4.344 46.746 4.392 ; + RECT 0.168 4.728 46.746 4.776 ; + RECT 0.168 5.112 46.746 5.160 ; + RECT 0.168 5.496 46.746 5.544 ; + RECT 0.168 5.880 46.746 5.928 ; + RECT 0.168 6.264 46.746 6.312 ; + RECT 0.168 6.648 46.746 6.696 ; + RECT 0.168 7.032 46.746 7.080 ; + RECT 0.168 7.416 46.746 7.464 ; + RECT 0.168 7.800 46.746 7.848 ; + RECT 0.168 8.184 46.746 8.232 ; + RECT 0.168 8.568 46.746 8.616 ; + RECT 0.168 8.952 46.746 9.000 ; + RECT 0.168 9.336 46.746 9.384 ; + RECT 0.168 9.720 46.746 9.768 ; + RECT 0.168 10.104 46.746 10.152 ; + RECT 0.168 10.488 46.746 10.536 ; + RECT 0.168 10.872 46.746 10.920 ; + RECT 0.168 11.256 46.746 11.304 ; + RECT 0.168 11.640 46.746 11.688 ; + RECT 0.168 12.024 46.746 12.072 ; + RECT 0.168 12.408 46.746 12.456 ; + RECT 0.168 12.792 46.746 12.840 ; + RECT 0.168 13.176 46.746 13.224 ; + RECT 0.168 13.560 46.746 13.608 ; + RECT 0.168 13.944 46.746 13.992 ; + RECT 0.168 14.328 46.746 14.376 ; + RECT 0.168 14.712 46.746 14.760 ; + RECT 0.168 15.096 46.746 15.144 ; + RECT 0.168 15.480 46.746 15.528 ; + RECT 0.168 15.864 46.746 15.912 ; + RECT 0.168 16.248 46.746 16.296 ; + RECT 0.168 16.632 46.746 16.680 ; + RECT 0.168 17.016 46.746 17.064 ; + RECT 0.168 17.400 46.746 17.448 ; + RECT 0.168 17.784 46.746 17.832 ; + RECT 0.168 18.168 46.746 18.216 ; + RECT 0.168 18.552 46.746 18.600 ; + RECT 0.168 18.936 46.746 18.984 ; + RECT 0.168 19.320 46.746 19.368 ; + RECT 0.168 19.704 46.746 19.752 ; + RECT 0.168 20.088 46.746 20.136 ; + RECT 0.168 20.472 46.746 20.520 ; + RECT 0.168 20.856 46.746 20.904 ; + RECT 0.168 21.240 46.746 21.288 ; + RECT 0.168 21.624 46.746 21.672 ; + RECT 0.168 22.008 46.746 22.056 ; + RECT 0.168 22.392 46.746 22.440 ; + RECT 0.168 22.776 46.746 22.824 ; + RECT 0.168 23.160 46.746 23.208 ; + RECT 0.168 23.544 46.746 23.592 ; + RECT 0.168 23.928 46.746 23.976 ; + RECT 0.168 24.312 46.746 24.360 ; + RECT 0.168 24.696 46.746 24.744 ; + RECT 0.168 25.080 46.746 25.128 ; + RECT 0.168 25.464 46.746 25.512 ; + RECT 0.168 25.848 46.746 25.896 ; + RECT 0.168 26.232 46.746 26.280 ; + RECT 0.168 26.616 46.746 26.664 ; + RECT 0.168 27.000 46.746 27.048 ; + RECT 0.168 27.384 46.746 27.432 ; + RECT 0.168 27.768 46.746 27.816 ; + RECT 0.168 28.152 46.746 28.200 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 46.914 28.512 ; + LAYER M2 ; + RECT 0 0 46.914 28.512 ; + LAYER M3 ; + RECT 0 0 46.914 28.512 ; + LAYER M4 ; + RECT 0 0 46.914 28.512 ; + END +END fakeram_66x64_1r1w + +END LIBRARY diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_66x80_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_66x80_1r1w.lef new file mode 100644 index 00000000..46d263ca --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_66x80_1r1w.lef @@ -0,0 +1,1579 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_66x80_1r1w + FOREIGN fakeram_66x80_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 46.914 BY 35.568 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 0.138 0.036 0.150 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 1.602 0.036 1.614 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 3.066 0.036 3.078 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 4.530 0.036 4.542 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 5.994 0.036 6.006 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 7.458 0.036 7.470 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 8.922 0.036 8.934 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 10.386 0.036 10.398 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 11.850 0.036 11.862 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 13.314 0.036 13.326 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 14.778 0.036 14.790 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 16.242 0.036 16.254 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 17.706 0.036 17.718 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 19.170 0.036 19.182 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 20.634 0.036 20.646 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 22.098 0.036 22.110 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 23.562 0.036 23.574 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 0.138 46.914 0.150 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 1.602 46.914 1.614 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 3.066 46.914 3.078 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 4.530 46.914 4.542 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 5.994 46.914 6.006 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 7.458 46.914 7.470 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 8.922 46.914 8.934 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 10.386 46.914 10.398 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 11.850 46.914 11.862 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 13.314 46.914 13.326 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 14.778 46.914 14.790 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 16.242 46.914 16.254 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 17.706 46.914 17.718 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 19.170 46.914 19.182 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 20.634 46.914 20.646 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 22.098 46.914 22.110 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 0.000 0.175 0.042 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.861 0.000 0.875 0.042 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.561 0.000 1.575 0.042 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.261 0.000 2.275 0.042 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.961 0.000 2.975 0.042 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.661 0.000 3.675 0.042 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.361 0.000 4.375 0.042 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.061 0.000 5.075 0.042 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.761 0.000 5.775 0.042 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.461 0.000 6.475 0.042 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.161 0.000 7.175 0.042 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.861 0.000 7.875 0.042 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.561 0.000 8.575 0.042 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.261 0.000 9.275 0.042 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.961 0.000 9.975 0.042 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.661 0.000 10.675 0.042 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.361 0.000 11.375 0.042 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.061 0.000 12.075 0.042 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.761 0.000 12.775 0.042 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.461 0.000 13.475 0.042 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.161 0.000 14.175 0.042 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.861 0.000 14.875 0.042 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.561 0.000 15.575 0.042 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.261 0.000 16.275 0.042 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.961 0.000 16.975 0.042 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.661 0.000 17.675 0.042 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.361 0.000 18.375 0.042 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.061 0.000 19.075 0.042 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.761 0.000 19.775 0.042 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.461 0.000 20.475 0.042 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.161 0.000 21.175 0.042 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.861 0.000 21.875 0.042 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.561 0.000 22.575 0.042 ; + END + END w0_wd_in[65] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.261 0.000 23.275 0.042 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.961 0.000 23.975 0.042 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.661 0.000 24.675 0.042 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.361 0.000 25.375 0.042 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.061 0.000 26.075 0.042 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.761 0.000 26.775 0.042 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.461 0.000 27.475 0.042 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.161 0.000 28.175 0.042 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.861 0.000 28.875 0.042 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.561 0.000 29.575 0.042 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.261 0.000 30.275 0.042 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.961 0.000 30.975 0.042 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.661 0.000 31.675 0.042 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.361 0.000 32.375 0.042 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.061 0.000 33.075 0.042 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.761 0.000 33.775 0.042 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.461 0.000 34.475 0.042 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.161 0.000 35.175 0.042 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.861 0.000 35.875 0.042 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.561 0.000 36.575 0.042 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.261 0.000 37.275 0.042 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.961 0.000 37.975 0.042 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.661 0.000 38.675 0.042 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.361 0.000 39.375 0.042 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.061 0.000 40.075 0.042 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.761 0.000 40.775 0.042 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.461 0.000 41.475 0.042 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.161 0.000 42.175 0.042 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.861 0.000 42.875 0.042 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.561 0.000 43.575 0.042 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.261 0.000 44.275 0.042 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.961 0.000 44.975 0.042 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.661 0.000 45.675 0.042 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 35.526 0.175 35.568 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.365 35.526 1.379 35.568 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.569 35.526 2.583 35.568 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.773 35.526 3.787 35.568 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.977 35.526 4.991 35.568 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.181 35.526 6.195 35.568 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.385 35.526 7.399 35.568 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.589 35.526 8.603 35.568 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.793 35.526 9.807 35.568 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.997 35.526 11.011 35.568 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.201 35.526 12.215 35.568 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.405 35.526 13.419 35.568 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.609 35.526 14.623 35.568 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.813 35.526 15.827 35.568 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.017 35.526 17.031 35.568 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.221 35.526 18.235 35.568 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.425 35.526 19.439 35.568 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.629 35.526 20.643 35.568 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.833 35.526 21.847 35.568 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.037 35.526 23.051 35.568 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.241 35.526 24.255 35.568 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.445 35.526 25.459 35.568 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.649 35.526 26.663 35.568 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.853 35.526 27.867 35.568 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.057 35.526 29.071 35.568 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.261 35.526 30.275 35.568 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.465 35.526 31.479 35.568 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.669 35.526 32.683 35.568 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.873 35.526 33.887 35.568 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.077 35.526 35.091 35.568 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.281 35.526 36.295 35.568 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.485 35.526 37.499 35.568 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.689 35.526 38.703 35.568 ; + END + END r0_rd_out[65] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 25.026 0.036 25.038 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 26.490 0.036 26.502 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 27.954 0.036 27.966 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 29.418 0.036 29.430 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 23.562 46.914 23.574 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 25.026 46.914 25.038 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 26.490 46.914 26.502 ; + END + END w0_addr_in[6] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 30.882 0.036 30.894 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 32.346 0.036 32.358 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 33.810 0.036 33.822 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 35.274 0.036 35.286 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 27.954 46.914 27.966 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 29.418 46.914 29.430 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 46.878 30.882 46.914 30.894 ; + END + END r0_addr_in[6] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.893 35.526 39.907 35.568 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.097 35.526 41.111 35.568 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.301 35.526 42.315 35.568 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.505 35.526 43.519 35.568 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.709 35.526 44.723 35.568 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.168 0.120 46.746 0.168 ; + RECT 0.168 0.504 46.746 0.552 ; + RECT 0.168 0.888 46.746 0.936 ; + RECT 0.168 1.272 46.746 1.320 ; + RECT 0.168 1.656 46.746 1.704 ; + RECT 0.168 2.040 46.746 2.088 ; + RECT 0.168 2.424 46.746 2.472 ; + RECT 0.168 2.808 46.746 2.856 ; + RECT 0.168 3.192 46.746 3.240 ; + RECT 0.168 3.576 46.746 3.624 ; + RECT 0.168 3.960 46.746 4.008 ; + RECT 0.168 4.344 46.746 4.392 ; + RECT 0.168 4.728 46.746 4.776 ; + RECT 0.168 5.112 46.746 5.160 ; + RECT 0.168 5.496 46.746 5.544 ; + RECT 0.168 5.880 46.746 5.928 ; + RECT 0.168 6.264 46.746 6.312 ; + RECT 0.168 6.648 46.746 6.696 ; + RECT 0.168 7.032 46.746 7.080 ; + RECT 0.168 7.416 46.746 7.464 ; + RECT 0.168 7.800 46.746 7.848 ; + RECT 0.168 8.184 46.746 8.232 ; + RECT 0.168 8.568 46.746 8.616 ; + RECT 0.168 8.952 46.746 9.000 ; + RECT 0.168 9.336 46.746 9.384 ; + RECT 0.168 9.720 46.746 9.768 ; + RECT 0.168 10.104 46.746 10.152 ; + RECT 0.168 10.488 46.746 10.536 ; + RECT 0.168 10.872 46.746 10.920 ; + RECT 0.168 11.256 46.746 11.304 ; + RECT 0.168 11.640 46.746 11.688 ; + RECT 0.168 12.024 46.746 12.072 ; + RECT 0.168 12.408 46.746 12.456 ; + RECT 0.168 12.792 46.746 12.840 ; + RECT 0.168 13.176 46.746 13.224 ; + RECT 0.168 13.560 46.746 13.608 ; + RECT 0.168 13.944 46.746 13.992 ; + RECT 0.168 14.328 46.746 14.376 ; + RECT 0.168 14.712 46.746 14.760 ; + RECT 0.168 15.096 46.746 15.144 ; + RECT 0.168 15.480 46.746 15.528 ; + RECT 0.168 15.864 46.746 15.912 ; + RECT 0.168 16.248 46.746 16.296 ; + RECT 0.168 16.632 46.746 16.680 ; + RECT 0.168 17.016 46.746 17.064 ; + RECT 0.168 17.400 46.746 17.448 ; + RECT 0.168 17.784 46.746 17.832 ; + RECT 0.168 18.168 46.746 18.216 ; + RECT 0.168 18.552 46.746 18.600 ; + RECT 0.168 18.936 46.746 18.984 ; + RECT 0.168 19.320 46.746 19.368 ; + RECT 0.168 19.704 46.746 19.752 ; + RECT 0.168 20.088 46.746 20.136 ; + RECT 0.168 20.472 46.746 20.520 ; + RECT 0.168 20.856 46.746 20.904 ; + RECT 0.168 21.240 46.746 21.288 ; + RECT 0.168 21.624 46.746 21.672 ; + RECT 0.168 22.008 46.746 22.056 ; + RECT 0.168 22.392 46.746 22.440 ; + RECT 0.168 22.776 46.746 22.824 ; + RECT 0.168 23.160 46.746 23.208 ; + RECT 0.168 23.544 46.746 23.592 ; + RECT 0.168 23.928 46.746 23.976 ; + RECT 0.168 24.312 46.746 24.360 ; + RECT 0.168 24.696 46.746 24.744 ; + RECT 0.168 25.080 46.746 25.128 ; + RECT 0.168 25.464 46.746 25.512 ; + RECT 0.168 25.848 46.746 25.896 ; + RECT 0.168 26.232 46.746 26.280 ; + RECT 0.168 26.616 46.746 26.664 ; + RECT 0.168 27.000 46.746 27.048 ; + RECT 0.168 27.384 46.746 27.432 ; + RECT 0.168 27.768 46.746 27.816 ; + RECT 0.168 28.152 46.746 28.200 ; + RECT 0.168 28.536 46.746 28.584 ; + RECT 0.168 28.920 46.746 28.968 ; + RECT 0.168 29.304 46.746 29.352 ; + RECT 0.168 29.688 46.746 29.736 ; + RECT 0.168 30.072 46.746 30.120 ; + RECT 0.168 30.456 46.746 30.504 ; + RECT 0.168 30.840 46.746 30.888 ; + RECT 0.168 31.224 46.746 31.272 ; + RECT 0.168 31.608 46.746 31.656 ; + RECT 0.168 31.992 46.746 32.040 ; + RECT 0.168 32.376 46.746 32.424 ; + RECT 0.168 32.760 46.746 32.808 ; + RECT 0.168 33.144 46.746 33.192 ; + RECT 0.168 33.528 46.746 33.576 ; + RECT 0.168 33.912 46.746 33.960 ; + RECT 0.168 34.296 46.746 34.344 ; + RECT 0.168 34.680 46.746 34.728 ; + RECT 0.168 35.064 46.746 35.112 ; + RECT 0.168 35.448 46.746 35.496 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.168 0.120 46.746 0.168 ; + RECT 0.168 0.504 46.746 0.552 ; + RECT 0.168 0.888 46.746 0.936 ; + RECT 0.168 1.272 46.746 1.320 ; + RECT 0.168 1.656 46.746 1.704 ; + RECT 0.168 2.040 46.746 2.088 ; + RECT 0.168 2.424 46.746 2.472 ; + RECT 0.168 2.808 46.746 2.856 ; + RECT 0.168 3.192 46.746 3.240 ; + RECT 0.168 3.576 46.746 3.624 ; + RECT 0.168 3.960 46.746 4.008 ; + RECT 0.168 4.344 46.746 4.392 ; + RECT 0.168 4.728 46.746 4.776 ; + RECT 0.168 5.112 46.746 5.160 ; + RECT 0.168 5.496 46.746 5.544 ; + RECT 0.168 5.880 46.746 5.928 ; + RECT 0.168 6.264 46.746 6.312 ; + RECT 0.168 6.648 46.746 6.696 ; + RECT 0.168 7.032 46.746 7.080 ; + RECT 0.168 7.416 46.746 7.464 ; + RECT 0.168 7.800 46.746 7.848 ; + RECT 0.168 8.184 46.746 8.232 ; + RECT 0.168 8.568 46.746 8.616 ; + RECT 0.168 8.952 46.746 9.000 ; + RECT 0.168 9.336 46.746 9.384 ; + RECT 0.168 9.720 46.746 9.768 ; + RECT 0.168 10.104 46.746 10.152 ; + RECT 0.168 10.488 46.746 10.536 ; + RECT 0.168 10.872 46.746 10.920 ; + RECT 0.168 11.256 46.746 11.304 ; + RECT 0.168 11.640 46.746 11.688 ; + RECT 0.168 12.024 46.746 12.072 ; + RECT 0.168 12.408 46.746 12.456 ; + RECT 0.168 12.792 46.746 12.840 ; + RECT 0.168 13.176 46.746 13.224 ; + RECT 0.168 13.560 46.746 13.608 ; + RECT 0.168 13.944 46.746 13.992 ; + RECT 0.168 14.328 46.746 14.376 ; + RECT 0.168 14.712 46.746 14.760 ; + RECT 0.168 15.096 46.746 15.144 ; + RECT 0.168 15.480 46.746 15.528 ; + RECT 0.168 15.864 46.746 15.912 ; + RECT 0.168 16.248 46.746 16.296 ; + RECT 0.168 16.632 46.746 16.680 ; + RECT 0.168 17.016 46.746 17.064 ; + RECT 0.168 17.400 46.746 17.448 ; + RECT 0.168 17.784 46.746 17.832 ; + RECT 0.168 18.168 46.746 18.216 ; + RECT 0.168 18.552 46.746 18.600 ; + RECT 0.168 18.936 46.746 18.984 ; + RECT 0.168 19.320 46.746 19.368 ; + RECT 0.168 19.704 46.746 19.752 ; + RECT 0.168 20.088 46.746 20.136 ; + RECT 0.168 20.472 46.746 20.520 ; + RECT 0.168 20.856 46.746 20.904 ; + RECT 0.168 21.240 46.746 21.288 ; + RECT 0.168 21.624 46.746 21.672 ; + RECT 0.168 22.008 46.746 22.056 ; + RECT 0.168 22.392 46.746 22.440 ; + RECT 0.168 22.776 46.746 22.824 ; + RECT 0.168 23.160 46.746 23.208 ; + RECT 0.168 23.544 46.746 23.592 ; + RECT 0.168 23.928 46.746 23.976 ; + RECT 0.168 24.312 46.746 24.360 ; + RECT 0.168 24.696 46.746 24.744 ; + RECT 0.168 25.080 46.746 25.128 ; + RECT 0.168 25.464 46.746 25.512 ; + RECT 0.168 25.848 46.746 25.896 ; + RECT 0.168 26.232 46.746 26.280 ; + RECT 0.168 26.616 46.746 26.664 ; + RECT 0.168 27.000 46.746 27.048 ; + RECT 0.168 27.384 46.746 27.432 ; + RECT 0.168 27.768 46.746 27.816 ; + RECT 0.168 28.152 46.746 28.200 ; + RECT 0.168 28.536 46.746 28.584 ; + RECT 0.168 28.920 46.746 28.968 ; + RECT 0.168 29.304 46.746 29.352 ; + RECT 0.168 29.688 46.746 29.736 ; + RECT 0.168 30.072 46.746 30.120 ; + RECT 0.168 30.456 46.746 30.504 ; + RECT 0.168 30.840 46.746 30.888 ; + RECT 0.168 31.224 46.746 31.272 ; + RECT 0.168 31.608 46.746 31.656 ; + RECT 0.168 31.992 46.746 32.040 ; + RECT 0.168 32.376 46.746 32.424 ; + RECT 0.168 32.760 46.746 32.808 ; + RECT 0.168 33.144 46.746 33.192 ; + RECT 0.168 33.528 46.746 33.576 ; + RECT 0.168 33.912 46.746 33.960 ; + RECT 0.168 34.296 46.746 34.344 ; + RECT 0.168 34.680 46.746 34.728 ; + RECT 0.168 35.064 46.746 35.112 ; + RECT 0.168 35.448 46.746 35.496 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 46.914 35.568 ; + LAYER M2 ; + RECT 0 0 46.914 35.568 ; + LAYER M3 ; + RECT 0 0 46.914 35.568 ; + LAYER M4 ; + RECT 0 0 46.914 35.568 ; + END +END fakeram_66x80_1r1w + +END LIBRARY diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_7x256_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_7x256_1r1w.lef new file mode 100644 index 00000000..ba83905d --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_7x256_1r1w.lef @@ -0,0 +1,497 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_7x256_1r1w + FOREIGN fakeram_7x256_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 19.908 BY 28.512 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 0.138 0.036 0.150 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 2.946 0.036 2.958 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 19.872 0.138 19.908 0.150 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 19.872 2.946 19.908 2.958 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 0.000 0.175 0.042 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.597 0.000 2.611 0.042 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.033 0.000 5.047 0.042 ; + END + END w0_wd_in[6] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.469 0.000 7.483 0.042 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.905 0.000 9.919 0.042 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.341 0.000 12.355 0.042 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.777 0.000 14.791 0.042 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 28.470 0.175 28.512 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.317 28.470 2.331 28.512 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.473 28.470 4.487 28.512 ; + END + END r0_rd_out[6] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 5.754 0.036 5.766 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 8.562 0.036 8.574 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 11.370 0.036 11.382 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 14.178 0.036 14.190 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 19.872 5.754 19.908 5.766 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 19.872 8.562 19.908 8.574 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 19.872 11.370 19.908 11.382 ; + END + END w0_addr_in[6] + PIN w0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 19.872 14.178 19.908 14.190 ; + END + END w0_addr_in[7] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 16.986 0.036 16.998 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 19.794 0.036 19.806 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 22.602 0.036 22.614 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 25.410 0.036 25.422 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 19.872 16.986 19.908 16.998 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 19.872 19.794 19.908 19.806 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 19.872 22.602 19.908 22.614 ; + END + END r0_addr_in[6] + PIN r0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 19.872 25.410 19.908 25.422 ; + END + END r0_addr_in[7] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.629 28.470 6.643 28.512 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.785 28.470 8.799 28.512 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.941 28.470 10.955 28.512 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.097 28.470 13.111 28.512 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.253 28.470 15.267 28.512 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.168 0.120 19.740 0.168 ; + RECT 0.168 0.504 19.740 0.552 ; + RECT 0.168 0.888 19.740 0.936 ; + RECT 0.168 1.272 19.740 1.320 ; + RECT 0.168 1.656 19.740 1.704 ; + RECT 0.168 2.040 19.740 2.088 ; + RECT 0.168 2.424 19.740 2.472 ; + RECT 0.168 2.808 19.740 2.856 ; + RECT 0.168 3.192 19.740 3.240 ; + RECT 0.168 3.576 19.740 3.624 ; + RECT 0.168 3.960 19.740 4.008 ; + RECT 0.168 4.344 19.740 4.392 ; + RECT 0.168 4.728 19.740 4.776 ; + RECT 0.168 5.112 19.740 5.160 ; + RECT 0.168 5.496 19.740 5.544 ; + RECT 0.168 5.880 19.740 5.928 ; + RECT 0.168 6.264 19.740 6.312 ; + RECT 0.168 6.648 19.740 6.696 ; + RECT 0.168 7.032 19.740 7.080 ; + RECT 0.168 7.416 19.740 7.464 ; + RECT 0.168 7.800 19.740 7.848 ; + RECT 0.168 8.184 19.740 8.232 ; + RECT 0.168 8.568 19.740 8.616 ; + RECT 0.168 8.952 19.740 9.000 ; + RECT 0.168 9.336 19.740 9.384 ; + RECT 0.168 9.720 19.740 9.768 ; + RECT 0.168 10.104 19.740 10.152 ; + RECT 0.168 10.488 19.740 10.536 ; + RECT 0.168 10.872 19.740 10.920 ; + RECT 0.168 11.256 19.740 11.304 ; + RECT 0.168 11.640 19.740 11.688 ; + RECT 0.168 12.024 19.740 12.072 ; + RECT 0.168 12.408 19.740 12.456 ; + RECT 0.168 12.792 19.740 12.840 ; + RECT 0.168 13.176 19.740 13.224 ; + RECT 0.168 13.560 19.740 13.608 ; + RECT 0.168 13.944 19.740 13.992 ; + RECT 0.168 14.328 19.740 14.376 ; + RECT 0.168 14.712 19.740 14.760 ; + RECT 0.168 15.096 19.740 15.144 ; + RECT 0.168 15.480 19.740 15.528 ; + RECT 0.168 15.864 19.740 15.912 ; + RECT 0.168 16.248 19.740 16.296 ; + RECT 0.168 16.632 19.740 16.680 ; + RECT 0.168 17.016 19.740 17.064 ; + RECT 0.168 17.400 19.740 17.448 ; + RECT 0.168 17.784 19.740 17.832 ; + RECT 0.168 18.168 19.740 18.216 ; + RECT 0.168 18.552 19.740 18.600 ; + RECT 0.168 18.936 19.740 18.984 ; + RECT 0.168 19.320 19.740 19.368 ; + RECT 0.168 19.704 19.740 19.752 ; + RECT 0.168 20.088 19.740 20.136 ; + RECT 0.168 20.472 19.740 20.520 ; + RECT 0.168 20.856 19.740 20.904 ; + RECT 0.168 21.240 19.740 21.288 ; + RECT 0.168 21.624 19.740 21.672 ; + RECT 0.168 22.008 19.740 22.056 ; + RECT 0.168 22.392 19.740 22.440 ; + RECT 0.168 22.776 19.740 22.824 ; + RECT 0.168 23.160 19.740 23.208 ; + RECT 0.168 23.544 19.740 23.592 ; + RECT 0.168 23.928 19.740 23.976 ; + RECT 0.168 24.312 19.740 24.360 ; + RECT 0.168 24.696 19.740 24.744 ; + RECT 0.168 25.080 19.740 25.128 ; + RECT 0.168 25.464 19.740 25.512 ; + RECT 0.168 25.848 19.740 25.896 ; + RECT 0.168 26.232 19.740 26.280 ; + RECT 0.168 26.616 19.740 26.664 ; + RECT 0.168 27.000 19.740 27.048 ; + RECT 0.168 27.384 19.740 27.432 ; + RECT 0.168 27.768 19.740 27.816 ; + RECT 0.168 28.152 19.740 28.200 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.168 0.120 19.740 0.168 ; + RECT 0.168 0.504 19.740 0.552 ; + RECT 0.168 0.888 19.740 0.936 ; + RECT 0.168 1.272 19.740 1.320 ; + RECT 0.168 1.656 19.740 1.704 ; + RECT 0.168 2.040 19.740 2.088 ; + RECT 0.168 2.424 19.740 2.472 ; + RECT 0.168 2.808 19.740 2.856 ; + RECT 0.168 3.192 19.740 3.240 ; + RECT 0.168 3.576 19.740 3.624 ; + RECT 0.168 3.960 19.740 4.008 ; + RECT 0.168 4.344 19.740 4.392 ; + RECT 0.168 4.728 19.740 4.776 ; + RECT 0.168 5.112 19.740 5.160 ; + RECT 0.168 5.496 19.740 5.544 ; + RECT 0.168 5.880 19.740 5.928 ; + RECT 0.168 6.264 19.740 6.312 ; + RECT 0.168 6.648 19.740 6.696 ; + RECT 0.168 7.032 19.740 7.080 ; + RECT 0.168 7.416 19.740 7.464 ; + RECT 0.168 7.800 19.740 7.848 ; + RECT 0.168 8.184 19.740 8.232 ; + RECT 0.168 8.568 19.740 8.616 ; + RECT 0.168 8.952 19.740 9.000 ; + RECT 0.168 9.336 19.740 9.384 ; + RECT 0.168 9.720 19.740 9.768 ; + RECT 0.168 10.104 19.740 10.152 ; + RECT 0.168 10.488 19.740 10.536 ; + RECT 0.168 10.872 19.740 10.920 ; + RECT 0.168 11.256 19.740 11.304 ; + RECT 0.168 11.640 19.740 11.688 ; + RECT 0.168 12.024 19.740 12.072 ; + RECT 0.168 12.408 19.740 12.456 ; + RECT 0.168 12.792 19.740 12.840 ; + RECT 0.168 13.176 19.740 13.224 ; + RECT 0.168 13.560 19.740 13.608 ; + RECT 0.168 13.944 19.740 13.992 ; + RECT 0.168 14.328 19.740 14.376 ; + RECT 0.168 14.712 19.740 14.760 ; + RECT 0.168 15.096 19.740 15.144 ; + RECT 0.168 15.480 19.740 15.528 ; + RECT 0.168 15.864 19.740 15.912 ; + RECT 0.168 16.248 19.740 16.296 ; + RECT 0.168 16.632 19.740 16.680 ; + RECT 0.168 17.016 19.740 17.064 ; + RECT 0.168 17.400 19.740 17.448 ; + RECT 0.168 17.784 19.740 17.832 ; + RECT 0.168 18.168 19.740 18.216 ; + RECT 0.168 18.552 19.740 18.600 ; + RECT 0.168 18.936 19.740 18.984 ; + RECT 0.168 19.320 19.740 19.368 ; + RECT 0.168 19.704 19.740 19.752 ; + RECT 0.168 20.088 19.740 20.136 ; + RECT 0.168 20.472 19.740 20.520 ; + RECT 0.168 20.856 19.740 20.904 ; + RECT 0.168 21.240 19.740 21.288 ; + RECT 0.168 21.624 19.740 21.672 ; + RECT 0.168 22.008 19.740 22.056 ; + RECT 0.168 22.392 19.740 22.440 ; + RECT 0.168 22.776 19.740 22.824 ; + RECT 0.168 23.160 19.740 23.208 ; + RECT 0.168 23.544 19.740 23.592 ; + RECT 0.168 23.928 19.740 23.976 ; + RECT 0.168 24.312 19.740 24.360 ; + RECT 0.168 24.696 19.740 24.744 ; + RECT 0.168 25.080 19.740 25.128 ; + RECT 0.168 25.464 19.740 25.512 ; + RECT 0.168 25.848 19.740 25.896 ; + RECT 0.168 26.232 19.740 26.280 ; + RECT 0.168 26.616 19.740 26.664 ; + RECT 0.168 27.000 19.740 27.048 ; + RECT 0.168 27.384 19.740 27.432 ; + RECT 0.168 27.768 19.740 27.816 ; + RECT 0.168 28.152 19.740 28.200 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 19.908 28.512 ; + LAYER M2 ; + RECT 0 0 19.908 28.512 ; + LAYER M3 ; + RECT 0 0 19.908 28.512 ; + LAYER M4 ; + RECT 0 0 19.908 28.512 ; + END +END fakeram_7x256_1r1w + +END LIBRARY diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_8x256_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_8x256_1r1w.lef new file mode 100644 index 00000000..d8a8c9ee --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_8x256_1r1w.lef @@ -0,0 +1,515 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_8x256_1r1w + FOREIGN fakeram_8x256_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 22.764 BY 28.512 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 0.138 0.036 0.150 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 2.946 0.036 2.958 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 0.138 22.764 0.150 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 2.946 22.764 2.958 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 0.000 0.175 0.042 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.961 0.000 2.975 0.042 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.761 0.000 5.775 0.042 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.561 0.000 8.575 0.042 ; + END + END w0_wd_in[7] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.361 0.000 11.375 0.042 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.161 0.000 14.175 0.042 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.961 0.000 16.975 0.042 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.761 0.000 19.775 0.042 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 28.470 0.175 28.512 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.625 28.470 2.639 28.512 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.089 28.470 5.103 28.512 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.553 28.470 7.567 28.512 ; + END + END r0_rd_out[7] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 5.754 0.036 5.766 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 8.562 0.036 8.574 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 11.370 0.036 11.382 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 14.178 0.036 14.190 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 5.754 22.764 5.766 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 8.562 22.764 8.574 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 11.370 22.764 11.382 ; + END + END w0_addr_in[6] + PIN w0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 14.178 22.764 14.190 ; + END + END w0_addr_in[7] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 16.986 0.036 16.998 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 19.794 0.036 19.806 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 22.602 0.036 22.614 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 25.410 0.036 25.422 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 16.986 22.764 16.998 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 19.794 22.764 19.806 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 22.602 22.764 22.614 ; + END + END r0_addr_in[6] + PIN r0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 22.728 25.410 22.764 25.422 ; + END + END r0_addr_in[7] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.017 28.470 10.031 28.512 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.481 28.470 12.495 28.512 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.945 28.470 14.959 28.512 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.409 28.470 17.423 28.512 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.873 28.470 19.887 28.512 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.168 0.120 22.596 0.168 ; + RECT 0.168 0.504 22.596 0.552 ; + RECT 0.168 0.888 22.596 0.936 ; + RECT 0.168 1.272 22.596 1.320 ; + RECT 0.168 1.656 22.596 1.704 ; + RECT 0.168 2.040 22.596 2.088 ; + RECT 0.168 2.424 22.596 2.472 ; + RECT 0.168 2.808 22.596 2.856 ; + RECT 0.168 3.192 22.596 3.240 ; + RECT 0.168 3.576 22.596 3.624 ; + RECT 0.168 3.960 22.596 4.008 ; + RECT 0.168 4.344 22.596 4.392 ; + RECT 0.168 4.728 22.596 4.776 ; + RECT 0.168 5.112 22.596 5.160 ; + RECT 0.168 5.496 22.596 5.544 ; + RECT 0.168 5.880 22.596 5.928 ; + RECT 0.168 6.264 22.596 6.312 ; + RECT 0.168 6.648 22.596 6.696 ; + RECT 0.168 7.032 22.596 7.080 ; + RECT 0.168 7.416 22.596 7.464 ; + RECT 0.168 7.800 22.596 7.848 ; + RECT 0.168 8.184 22.596 8.232 ; + RECT 0.168 8.568 22.596 8.616 ; + RECT 0.168 8.952 22.596 9.000 ; + RECT 0.168 9.336 22.596 9.384 ; + RECT 0.168 9.720 22.596 9.768 ; + RECT 0.168 10.104 22.596 10.152 ; + RECT 0.168 10.488 22.596 10.536 ; + RECT 0.168 10.872 22.596 10.920 ; + RECT 0.168 11.256 22.596 11.304 ; + RECT 0.168 11.640 22.596 11.688 ; + RECT 0.168 12.024 22.596 12.072 ; + RECT 0.168 12.408 22.596 12.456 ; + RECT 0.168 12.792 22.596 12.840 ; + RECT 0.168 13.176 22.596 13.224 ; + RECT 0.168 13.560 22.596 13.608 ; + RECT 0.168 13.944 22.596 13.992 ; + RECT 0.168 14.328 22.596 14.376 ; + RECT 0.168 14.712 22.596 14.760 ; + RECT 0.168 15.096 22.596 15.144 ; + RECT 0.168 15.480 22.596 15.528 ; + RECT 0.168 15.864 22.596 15.912 ; + RECT 0.168 16.248 22.596 16.296 ; + RECT 0.168 16.632 22.596 16.680 ; + RECT 0.168 17.016 22.596 17.064 ; + RECT 0.168 17.400 22.596 17.448 ; + RECT 0.168 17.784 22.596 17.832 ; + RECT 0.168 18.168 22.596 18.216 ; + RECT 0.168 18.552 22.596 18.600 ; + RECT 0.168 18.936 22.596 18.984 ; + RECT 0.168 19.320 22.596 19.368 ; + RECT 0.168 19.704 22.596 19.752 ; + RECT 0.168 20.088 22.596 20.136 ; + RECT 0.168 20.472 22.596 20.520 ; + RECT 0.168 20.856 22.596 20.904 ; + RECT 0.168 21.240 22.596 21.288 ; + RECT 0.168 21.624 22.596 21.672 ; + RECT 0.168 22.008 22.596 22.056 ; + RECT 0.168 22.392 22.596 22.440 ; + RECT 0.168 22.776 22.596 22.824 ; + RECT 0.168 23.160 22.596 23.208 ; + RECT 0.168 23.544 22.596 23.592 ; + RECT 0.168 23.928 22.596 23.976 ; + RECT 0.168 24.312 22.596 24.360 ; + RECT 0.168 24.696 22.596 24.744 ; + RECT 0.168 25.080 22.596 25.128 ; + RECT 0.168 25.464 22.596 25.512 ; + RECT 0.168 25.848 22.596 25.896 ; + RECT 0.168 26.232 22.596 26.280 ; + RECT 0.168 26.616 22.596 26.664 ; + RECT 0.168 27.000 22.596 27.048 ; + RECT 0.168 27.384 22.596 27.432 ; + RECT 0.168 27.768 22.596 27.816 ; + RECT 0.168 28.152 22.596 28.200 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.168 0.120 22.596 0.168 ; + RECT 0.168 0.504 22.596 0.552 ; + RECT 0.168 0.888 22.596 0.936 ; + RECT 0.168 1.272 22.596 1.320 ; + RECT 0.168 1.656 22.596 1.704 ; + RECT 0.168 2.040 22.596 2.088 ; + RECT 0.168 2.424 22.596 2.472 ; + RECT 0.168 2.808 22.596 2.856 ; + RECT 0.168 3.192 22.596 3.240 ; + RECT 0.168 3.576 22.596 3.624 ; + RECT 0.168 3.960 22.596 4.008 ; + RECT 0.168 4.344 22.596 4.392 ; + RECT 0.168 4.728 22.596 4.776 ; + RECT 0.168 5.112 22.596 5.160 ; + RECT 0.168 5.496 22.596 5.544 ; + RECT 0.168 5.880 22.596 5.928 ; + RECT 0.168 6.264 22.596 6.312 ; + RECT 0.168 6.648 22.596 6.696 ; + RECT 0.168 7.032 22.596 7.080 ; + RECT 0.168 7.416 22.596 7.464 ; + RECT 0.168 7.800 22.596 7.848 ; + RECT 0.168 8.184 22.596 8.232 ; + RECT 0.168 8.568 22.596 8.616 ; + RECT 0.168 8.952 22.596 9.000 ; + RECT 0.168 9.336 22.596 9.384 ; + RECT 0.168 9.720 22.596 9.768 ; + RECT 0.168 10.104 22.596 10.152 ; + RECT 0.168 10.488 22.596 10.536 ; + RECT 0.168 10.872 22.596 10.920 ; + RECT 0.168 11.256 22.596 11.304 ; + RECT 0.168 11.640 22.596 11.688 ; + RECT 0.168 12.024 22.596 12.072 ; + RECT 0.168 12.408 22.596 12.456 ; + RECT 0.168 12.792 22.596 12.840 ; + RECT 0.168 13.176 22.596 13.224 ; + RECT 0.168 13.560 22.596 13.608 ; + RECT 0.168 13.944 22.596 13.992 ; + RECT 0.168 14.328 22.596 14.376 ; + RECT 0.168 14.712 22.596 14.760 ; + RECT 0.168 15.096 22.596 15.144 ; + RECT 0.168 15.480 22.596 15.528 ; + RECT 0.168 15.864 22.596 15.912 ; + RECT 0.168 16.248 22.596 16.296 ; + RECT 0.168 16.632 22.596 16.680 ; + RECT 0.168 17.016 22.596 17.064 ; + RECT 0.168 17.400 22.596 17.448 ; + RECT 0.168 17.784 22.596 17.832 ; + RECT 0.168 18.168 22.596 18.216 ; + RECT 0.168 18.552 22.596 18.600 ; + RECT 0.168 18.936 22.596 18.984 ; + RECT 0.168 19.320 22.596 19.368 ; + RECT 0.168 19.704 22.596 19.752 ; + RECT 0.168 20.088 22.596 20.136 ; + RECT 0.168 20.472 22.596 20.520 ; + RECT 0.168 20.856 22.596 20.904 ; + RECT 0.168 21.240 22.596 21.288 ; + RECT 0.168 21.624 22.596 21.672 ; + RECT 0.168 22.008 22.596 22.056 ; + RECT 0.168 22.392 22.596 22.440 ; + RECT 0.168 22.776 22.596 22.824 ; + RECT 0.168 23.160 22.596 23.208 ; + RECT 0.168 23.544 22.596 23.592 ; + RECT 0.168 23.928 22.596 23.976 ; + RECT 0.168 24.312 22.596 24.360 ; + RECT 0.168 24.696 22.596 24.744 ; + RECT 0.168 25.080 22.596 25.128 ; + RECT 0.168 25.464 22.596 25.512 ; + RECT 0.168 25.848 22.596 25.896 ; + RECT 0.168 26.232 22.596 26.280 ; + RECT 0.168 26.616 22.596 26.664 ; + RECT 0.168 27.000 22.596 27.048 ; + RECT 0.168 27.384 22.596 27.432 ; + RECT 0.168 27.768 22.596 27.816 ; + RECT 0.168 28.152 22.596 28.200 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 22.764 28.512 ; + LAYER M2 ; + RECT 0 0 22.764 28.512 ; + LAYER M3 ; + RECT 0 0 22.764 28.512 ; + LAYER M4 ; + RECT 0 0 22.764 28.512 ; + END +END fakeram_8x256_1r1w + +END LIBRARY diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_11x128_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_11x128_1r1w.lib new file mode 100644 index 00000000..61496ab5 --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_11x128_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_11x128_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-08-01 08:31:13Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.125; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_11x128_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_11x128_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_11x128_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_11x128_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_11x128_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_11x128_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 11; + bit_from : 10; + bit_to : 0 ; + downto : true ; + } + type (fakeram_11x128_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_11x128_1r1w) { + area : 446.669; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 11; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_11x128_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_11x128_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_11x128_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_11x128_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_11x128_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_11x128_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + cell_fall(fakeram_11x128_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + rise_transition(fakeram_11x128_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + fall_transition(fakeram_11x128_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_11x128_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_11x128_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_11x128_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + cell_leakage_power : 100.000; +} + +} diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_14x80_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_14x80_1r1w.lib new file mode 100644 index 00000000..0d4f32dd --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_14x80_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_14x80_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-08-01 08:31:13Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.125; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_14x80_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_14x80_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_14x80_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_14x80_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_14x80_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_14x80_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 14; + bit_from : 13; + bit_to : 0 ; + downto : true ; + } + type (fakeram_14x80_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_14x80_1r1w) { + area : 355.477; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 14; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_14x80_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_14x80_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_14x80_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_14x80_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_14x80_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_14x80_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + cell_fall(fakeram_14x80_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + rise_transition(fakeram_14x80_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + fall_transition(fakeram_14x80_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_14x80_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_14x80_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_14x80_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + cell_leakage_power : 100.000; +} + +} diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_15x80_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_15x80_1r1w.lib new file mode 100644 index 00000000..3a8be37c --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_15x80_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_15x80_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-08-01 08:31:13Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.125; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_15x80_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_15x80_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_15x80_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_15x80_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_15x80_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_15x80_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 15; + bit_from : 14; + bit_to : 0 ; + downto : true ; + } + type (fakeram_15x80_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_15x80_1r1w) { + area : 380.976; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 15; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_15x80_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_15x80_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_15x80_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_15x80_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_15x80_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_15x80_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + cell_fall(fakeram_15x80_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + rise_transition(fakeram_15x80_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + fall_transition(fakeram_15x80_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_15x80_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_15x80_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_15x80_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + cell_leakage_power : 100.000; +} + +} diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_16x160_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_16x160_1r1w.lib new file mode 100644 index 00000000..07570b10 --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_16x160_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_16x160_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-08-01 08:31:13Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.125; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_16x160_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_16x160_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_16x160_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_16x160_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_16x160_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_16x160_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 16; + bit_from : 15; + bit_to : 0 ; + downto : true ; + } + type (fakeram_16x160_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_16x160_1r1w) { + area : 809.670; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 16; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_16x160_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_16x160_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_16x160_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_16x160_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_16x160_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_16x160_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + cell_fall(fakeram_16x160_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + rise_transition(fakeram_16x160_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + fall_transition(fakeram_16x160_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_16x160_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_16x160_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_16x160_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + cell_leakage_power : 100.000; +} + +} diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_18x128_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_18x128_1r1w.lib new file mode 100644 index 00000000..d7c352e5 --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_18x128_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_18x128_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-08-01 08:31:13Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.125; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_18x128_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_18x128_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_18x128_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_18x128_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_18x128_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_18x128_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 18; + bit_from : 17; + bit_to : 0 ; + downto : true ; + } + type (fakeram_18x128_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_18x128_1r1w) { + area : 730.477; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 18; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_18x128_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_18x128_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_18x128_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_18x128_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_18x128_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_18x128_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + cell_fall(fakeram_18x128_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + rise_transition(fakeram_18x128_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + fall_transition(fakeram_18x128_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_18x128_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_18x128_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_18x128_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + cell_leakage_power : 100.000; +} + +} diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_22x60_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_22x60_1r1w.lib new file mode 100644 index 00000000..e14adfbc --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_22x60_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_22x60_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-08-01 08:31:13Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.125; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_22x60_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_22x60_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_22x60_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_22x60_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_22x60_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_22x60_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 22; + bit_from : 21; + bit_to : 0 ; + downto : true ; + } + type (fakeram_22x60_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_22x60_1r1w) { + area : 417.342; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 22; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_22x60_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_22x60_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_22x60_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_22x60_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_22x60_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_22x60_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + cell_fall(fakeram_22x60_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + rise_transition(fakeram_22x60_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + fall_transition(fakeram_22x60_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_22x60_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_22x60_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_22x60_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + cell_leakage_power : 100.000; +} + +} diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_32x128_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_32x128_1r1w.lib new file mode 100644 index 00000000..3bf4b402 --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_32x128_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_32x128_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-08-01 08:31:13Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.125; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_32x128_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_32x128_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_32x128_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_32x128_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_32x128_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_32x128_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 32; + bit_from : 31; + bit_to : 0 ; + downto : true ; + } + type (fakeram_32x128_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_32x128_1r1w) { + area : 1296.897; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 32; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_32x128_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_32x128_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_32x128_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_32x128_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_32x128_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_32x128_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + cell_fall(fakeram_32x128_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + rise_transition(fakeram_32x128_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + fall_transition(fakeram_32x128_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_32x128_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_32x128_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_32x128_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + cell_leakage_power : 100.000; +} + +} diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_4x256_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_4x256_1r1w.lib new file mode 100644 index 00000000..01274137 --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_4x256_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_4x256_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-08-01 08:31:13Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.125; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_4x256_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_4x256_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_4x256_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_4x256_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_4x256_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_4x256_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 4; + bit_from : 3; + bit_to : 0 ; + downto : true ; + } + type (fakeram_4x256_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_4x256_1r1w) { + area : 324.524; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 4; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_4x256_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_4x256_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_4x256_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_4x256_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_4x256_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_4x256_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + cell_fall(fakeram_4x256_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + rise_transition(fakeram_4x256_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + fall_transition(fakeram_4x256_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_4x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_4x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_4x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_4x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_4x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_4x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_4x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_4x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_4x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_4x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_4x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_4x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_4x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_4x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_4x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_4x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_4x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_4x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_4x256_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_4x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_4x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_4x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_4x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_4x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_4x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_4x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_4x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_4x256_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_4x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_4x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_4x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_4x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_4x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_4x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_4x256_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_4x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_4x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_4x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_4x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_4x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_4x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + cell_leakage_power : 100.000; +} + +} diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_64x256_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_64x256_1r1w.lib new file mode 100644 index 00000000..127bf539 --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_64x256_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_64x256_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-08-01 08:31:13Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.125; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_64x256_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_64x256_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_64x256_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_64x256_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_64x256_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_64x256_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 64; + bit_from : 63; + bit_to : 0 ; + downto : true ; + } + type (fakeram_64x256_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_64x256_1r1w) { + area : 5174.487; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 64; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_64x256_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_64x256_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_64x256_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_64x256_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_64x256_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_64x256_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + cell_fall(fakeram_64x256_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + rise_transition(fakeram_64x256_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + fall_transition(fakeram_64x256_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_64x256_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_64x256_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_64x256_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + cell_leakage_power : 100.000; +} + +} diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_65x160_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_65x160_1r1w.lib new file mode 100644 index 00000000..8293c213 --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_65x160_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_65x160_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-08-01 08:31:13Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.125; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_65x160_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_65x160_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_65x160_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_65x160_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_65x160_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_65x160_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 65; + bit_from : 64; + bit_to : 0 ; + downto : true ; + } + type (fakeram_65x160_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_65x160_1r1w) { + area : 3286.483; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 65; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_65x160_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_65x160_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_65x160_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_65x160_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_65x160_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_65x160_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + cell_fall(fakeram_65x160_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + rise_transition(fakeram_65x160_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + fall_transition(fakeram_65x160_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_65x160_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_65x160_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_65x160_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + cell_leakage_power : 100.000; +} + +} diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_66x64_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_66x64_1r1w.lib new file mode 100644 index 00000000..bf2d5af9 --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_66x64_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_66x64_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-08-01 08:31:13Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.125; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_66x64_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_66x64_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_66x64_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_66x64_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_66x64_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_66x64_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 66; + bit_from : 65; + bit_to : 0 ; + downto : true ; + } + type (fakeram_66x64_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_66x64_1r1w) { + area : 1337.612; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 66; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_66x64_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_66x64_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_66x64_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_66x64_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_66x64_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_66x64_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + cell_fall(fakeram_66x64_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + rise_transition(fakeram_66x64_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + fall_transition(fakeram_66x64_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_66x64_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_66x64_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_66x64_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + cell_leakage_power : 100.000; +} + +} diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_66x80_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_66x80_1r1w.lib new file mode 100644 index 00000000..41a9d343 --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_66x80_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_66x80_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-08-01 08:31:13Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.125; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_66x80_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_66x80_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_66x80_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_66x80_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_66x80_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_66x80_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 66; + bit_from : 65; + bit_to : 0 ; + downto : true ; + } + type (fakeram_66x80_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_66x80_1r1w) { + area : 1668.637; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 66; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_66x80_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_66x80_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_66x80_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_66x80_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_66x80_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_66x80_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + cell_fall(fakeram_66x80_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + rise_transition(fakeram_66x80_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + fall_transition(fakeram_66x80_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_66x80_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_66x80_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_66x80_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + cell_leakage_power : 100.000; +} + +} diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_7x256_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_7x256_1r1w.lib new file mode 100644 index 00000000..f155b648 --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_7x256_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_7x256_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-08-01 08:31:13Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.125; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_7x256_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_7x256_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_7x256_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_7x256_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_7x256_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_7x256_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } + type (fakeram_7x256_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_7x256_1r1w) { + area : 567.617; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 7; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_7x256_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_7x256_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_7x256_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_7x256_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_7x256_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_7x256_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + cell_fall(fakeram_7x256_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + rise_transition(fakeram_7x256_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + fall_transition(fakeram_7x256_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_7x256_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_7x256_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_7x256_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + cell_leakage_power : 100.000; +} + +} diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_8x256_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_8x256_1r1w.lib new file mode 100644 index 00000000..115b0a53 --- /dev/null +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_8x256_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_8x256_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-08-01 08:31:13Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.125; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_8x256_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_8x256_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_8x256_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_8x256_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_8x256_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_8x256_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } + type (fakeram_8x256_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_8x256_1r1w) { + area : 649.047; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 8; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_8x256_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_8x256_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.075 ; + internal_power(){ + rise_power(fakeram_8x256_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_8x256_1r1w_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_8x256_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_8x256_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + cell_fall(fakeram_8x256_1r1w_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.500"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + rise_transition(fakeram_8x256_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + fall_transition(fakeram_8x256_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.005, 0.125") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_8x256_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_8x256_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_8x256_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + cell_leakage_power : 100.000; +} + +} diff --git a/designs/src/NVDLA/DECISIONS.md b/designs/src/NVDLA/DECISIONS.md index c184a7fc..f515650c 100644 --- a/designs/src/NVDLA/DECISIONS.md +++ b/designs/src/NVDLA/DECISIONS.md @@ -95,3 +95,25 @@ The FF stubs are emitted by `designs/src/NVDLA/dev/gen_ff_rams.py` into `designs - **GRT-0183** (`repair_antennas` heap underflow, triggered by sky130hd's high antenna count): fixed by `patches/openroad-grt-0183-fix.patch` (upstream PR #10743, merged 2026-06-24 — remove once OR pin advances past that date). - **SDC fix**: replaced `set_false_path -to [get_pin */RESETN|/SETN]` (asap7 pin names, silent no-ops on sky130hd) with port-level `-from` false-paths; added `set_ideal_network [get_nets {nvdla_core_rstn}]`. - WNS +0.03 ns, Fmax **66.80 MHz** (`period_min` 14.97 ns vs 15 ns), 0 DRC violations, `CORE_UTILIZATION` 25, `PLACE_DENSITY` 0.20, ~265 k logic cells, core 128.9 mm². + +## gt2n + +**Status**: finishing. Per-partition details and known issues below. + +### Configuration +- **partition_a** (no macros, FF-array SRAMs): `CORE_UTILIZATION=80`, `PLACE_DENSITY=0.88`, `MAX_ROUTING_LAYER=M11`, `MIN_CLK_ROUTING_LAYER=M4`, `HOLD_SLACK_MARGIN=20`, `SYNTH_MEMORY_MAX_BITS=8192` (4352-bit FF instance trips the ORFS default 4096 cap). Clock: 895 ps (Fmax 1.12 GHz). Die area 4506 µm². +- **partition_c** (65 SRAM macro instances, 2 macro types: `64x256`/`11x128`): `DIE_AREA="0 0 855.792 716.928"`, `CORE_AREA="1.008 1.008 854.784 715.808"`, `MAX_ROUTING_LAYER=M11`, `MIN_CLK_ROUTING_LAYER=M6`, `MACRO_BLOCKAGE_HALO=0.5`. Clock: 1300 ps, achieved Fmax 635.80 MHz. +- **partition_m** (no SRAM macros): `CORE_UTILIZATION=82`, `PLACE_DENSITY=0.87`, `MAX_ROUTING_LAYER=M11`, `MIN_CLK_ROUTING_LAYER=M4`. Clock: 660 ps (Fmax 1.52 GHz). Die area 1334 µm². +- **partition_o** (17 SRAM macro instances, 8 macro types): `CORE_UTILIZATION=46`, `MAX_ROUTING_LAYER=M11`, `MIN_CLK_ROUTING_LAYER=M4`, `MACRO_PLACE_HALO="8 8"`, `HOLD_SLACK_MARGIN=40`. Multi-clock: `nvdla_core_clk` (2270 ps, Fmax 440 MHz) + `nvdla_falcon_clk` tracked at the NVIDIA reference core:falcon ratio (1.25). Die area 54218 µm². +- **partition_p** (6 SRAM macro instances, 4 macro types): `CORE_UTILIZATION=45`, `MAX_ROUTING_LAYER=M11`, `MIN_CLK_ROUTING_LAYER=M6`, `MACRO_PLACE_HALO="5 5"`, `MACRO_BLOCKAGE_HALO=0.5`, `HOLD_SLACK_MARGIN=50`. Clock: 1433 ps (Fmax 698 MHz). Die area 33257 µm². +- `TNS_END_PERCENT=100` on all five. + +### Decisions +- **asap7 is not a reliable reference for gt2n targets**: gt2n's per-square sheet resistance is dramatically higher than asap7's even at layers with near-identical pitch — e.g. M4 (0.042µm gt2n vs 0.048µm asap7, only ~12.5% apart) is 3.506 Ω/□ on gt2n vs 0.433 Ω/□ on asap7, an 8.1x gap that pitch differences can't explain. This isn't a material story either — gt2n uses ruthenium at the lower layers specifically because it scales better than copper at nanoscale linewidths, so a real process should look relatively *better* here, not 8x worse. The more plausible explanation is that asap7, an older predictive/academic PDK, is simply optimistic on interconnect resistance relative to what a real advanced-node process delivers. Fmax/area achieved on asap7 for the same RTL should not be treated as a dependable target for gt2n. +- **FakeRAM cfg**: partitions c/o/p share `fakeram_gt2n.cfg` (14 SRAM macro configs). +- **partition_c**: uses a hand-placed 8×8 SRAM bank grid (`macro_placement.tcl`) and applies an inter-partition I/O delay credit post-CTS (`pre_grt.tcl`) to more realistically model the clock-network latency that boundary signals would see if the partitions were connected as one die. +- **partition_o / partition_p**: several inter-partition boundary signals are zero-logic passthroughs of primary inputs with no on-chip source register in the standalone per-partition build, so the blanket `set_input_delay` under-budgets their true minimum arrival. Both partitions add scoped `-min` overrides on those specific signals in `constraint.sdc`. + +### Known issues / open questions +- **partition_o**: minor hold violations (8, worst −58.34 ps). +- **partition_c**: incremental hold repair at global routing did not converge within ~18h (run setup-only instead) — may close with more time. diff --git a/designs/src/NVDLA/dev/generated/fakeram_gt2n.cfg b/designs/src/NVDLA/dev/generated/fakeram_gt2n.cfg new file mode 100644 index 00000000..ab71ff8e --- /dev/null +++ b/designs/src/NVDLA/dev/generated/fakeram_gt2n.cfg @@ -0,0 +1,34 @@ +{ + "tech_nm": 2, + "voltage": 0.7, + "metalPrefix": "M", + + "LRpinWidth_nm": 12, + "LRpinPitch_nm": 24, + "LRpinLayer": "M2", + + "TBpinWidth_nm": 14, + "TBpinPitch_nm": 28, + "TBpinLayer": "M3", + + "flipPins": false, + "snapWidth_nm": 42, + "snapHeight_nm": 144, + + "srams": [ + { "name": "fakeram_16x160_1r1w", "width": 16, "depth": 160, "banks": 1, "no_wmask": "true", "ports": {"r": 1, "w": 1, "rw": 0} }, + { "name": "fakeram_65x160_1r1w", "width": 65, "depth": 160, "banks": 1, "no_wmask": "true", "ports": {"r": 1, "w": 1, "rw": 0} }, + { "name": "fakeram_14x80_1r1w", "width": 14, "depth": 80, "banks": 1, "no_wmask": "true", "ports": {"r": 1, "w": 1, "rw": 0} }, + { "name": "fakeram_66x80_1r1w", "width": 66, "depth": 80, "banks": 1, "no_wmask": "true", "ports": {"r": 1, "w": 1, "rw": 0} }, + { "name": "fakeram_18x128_1r1w", "width": 18, "depth": 128, "banks": 1, "no_wmask": "true", "ports": {"r": 1, "w": 1, "rw": 0} }, + { "name": "fakeram_8x256_1r1w", "width": 8, "depth": 256, "banks": 1, "no_wmask": "true", "ports": {"r": 1, "w": 1, "rw": 0} }, + { "name": "fakeram_4x256_1r1w", "width": 4, "depth": 256, "banks": 1, "no_wmask": "true", "ports": {"r": 1, "w": 1, "rw": 0} }, + { "name": "fakeram_7x256_1r1w", "width": 7, "depth": 256, "banks": 1, "no_wmask": "true", "ports": {"r": 1, "w": 1, "rw": 0} }, + { "name": "fakeram_66x64_1r1w", "width": 66, "depth": 64, "banks": 1, "no_wmask": "true", "ports": {"r": 1, "w": 1, "rw": 0} }, + { "name": "fakeram_15x80_1r1w", "width": 15, "depth": 80, "banks": 1, "no_wmask": "true", "ports": {"r": 1, "w": 1, "rw": 0} }, + { "name": "fakeram_22x60_1r1w", "width": 22, "depth": 60, "banks": 1, "no_wmask": "true", "ports": {"r": 1, "w": 1, "rw": 0} }, + { "name": "fakeram_32x128_1r1w", "width": 32, "depth": 128, "banks": 1, "no_wmask": "true", "ports": {"r": 1, "w": 1, "rw": 0} }, + { "name": "fakeram_64x256_1r1w", "width": 64, "depth": 256, "banks": 1, "no_wmask": "true", "ports": {"r": 1, "w": 1, "rw": 0} }, + { "name": "fakeram_11x128_1r1w", "width": 11, "depth": 128, "banks": 1, "no_wmask": "true", "ports": {"r": 1, "w": 1, "rw": 0} } + ] +} diff --git a/designs/src/NVDLA/dev/generated/partition_c_gt2n_macros.txt b/designs/src/NVDLA/dev/generated/partition_c_gt2n_macros.txt new file mode 100644 index 00000000..79f81b8e --- /dev/null +++ b/designs/src/NVDLA/dev/generated/partition_c_gt2n_macros.txt @@ -0,0 +1,66 @@ +CORE_UM 1.008 1.008 1015.728 1049.008 +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank0_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R0 | 258.0 969.8 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank0_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R180 | 16.0 796.1 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank10_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R0 | 137.0 622.3 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank10_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R180 | 16.0 361.7 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank11_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R180 | 16.0 187.9 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank11_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R0 | 137.0 361.7 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank12_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R0 | 137.0 448.5 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank12_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MY | 16.0 448.5 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank13_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MY | 16.0 709.2 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank13_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MX | 137.0 101.0 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank14_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R0 | 137.0 187.9 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank14_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R180 | 16.0 101.0 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank15_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R0 | 137.0 274.8 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank15_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MY | 16.0 274.8 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank16_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R0 | 603.6 102.9 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank16_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R180 | 482.6 16.0 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank17_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MY | 1087.5 16.0 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank17_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R0 | 1208.5 16.0 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank18_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MY | 361.7 16.0 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank18_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R0 | 845.5 16.0 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank19_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MX | 966.5 16.0 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank19_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MY | 724.6 102.9 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank1_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R180 | 137.0 796.1 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank1_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R0 | 258.0 1056.7 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank20_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R0 | 966.5 102.9 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank20_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MY | 845.5 102.9 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank21_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MY | 482.6 102.9 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank21_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R0 | 1087.5 102.9 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank22_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MY | 603.6 16.0 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank22_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R0 | 724.6 16.0 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank23_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R0 | 1208.5 102.9 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank23_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MY | 361.7 102.9 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank24_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R0 | 966.5 276.6 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank24_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MY | 482.6 276.6 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank25_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R0 | 845.5 276.6 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank25_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MX | 845.5 189.8 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank26_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R180 | 361.7 189.8 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank26_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R0 | 1208.5 276.6 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank27_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MX | 1087.5 189.8 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank27_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MY | 724.6 276.6 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank28_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MY | 603.6 276.6 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank28_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R0 | 1087.5 276.6 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank29_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MY | 361.7 276.6 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank29_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MX | 1208.5 189.8 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank2_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R0 | 378.9 1056.7 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank2_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R180 | 137.0 882.9 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank30_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MY | 603.6 189.8 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank30_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R0 | 966.5 189.8 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank31_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R0 | 724.6 189.8 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank31_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MY | 482.6 189.8 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank3_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MX | 378.9 969.8 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank3_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MY | 16.0 1056.7 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank4_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MY | 137.0 969.8 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank4_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MX | 378.9 796.1 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank5_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MY | 137.0 1056.7 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank5_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MX | 378.9 882.9 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank6_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MY | 16.0 882.9 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank6_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MX | 258.0 796.1 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank7_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MY | 16.0 969.8 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank7_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MX | 258.0 882.9 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank8_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R0 | 137.0 709.2 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank8_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R180 | 16.0 622.3 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank9_ram0.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | R0 | 137.0 535.4 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cbuf/u_cbuf_ram_bank9_ram1.r_nv_ram_rws_256x64.ram_Inst_256X64.sram | fakeram_64x256_1r1w | MY | 16.0 535.4 | 90.972x56.88 | LOCKED +MACRO u_NV_NVDLA_cdma/u_img.u_sg/u_NV_NVDLA_CDMA_IMG_fifo.ram.r_nv_ram_rwsp_128x11.ram_Inst_128X11.sram | fakeram_11x128_1r1w | MX | 164.1 16.0 | 15.666x28.512 | LOCKED From 412b383857c76a3094cb19801a00464875f6b14f Mon Sep 17 00:00:00 2001 From: dgaddy Date: Sat, 22 Aug 2026 11:39:12 -0700 Subject: [PATCH 7/7] gt2n: fix NVDLA/floonoc/lfsr issues found in platform-port review Updated QoR for changed designs: | Design | Fmax | Die area (um^2) | |--------------------|-------------|------------------| | NVDLA partition_c | 673.54 MHz | 613541 | | NVDLA partition_m | 1.68 GHz | 1334 | | NVDLA partition_o | 467.90 MHz | 54218 | | NVDLA partition_p | 630.47 MHz | 33257 | Bumps tools/bsg_fakeram to the merged master tip (was pinned to an unreachable pull-request ref) and regenerates all 14 gt2n NVDLA SRAM macros against it. NVDLA partition fixes: - partition_m: CTS clock wire model now matches MIN_CLK_ROUTING_LAYER (M4, was M6); added HOLD_SLACK_MARGIN=5. Fmax 1.68 GHz (was 1.52 GHz), 0 setup/hold violations. - partition_o: fixed a clock-port exclusion filter that never matched, so set_input_delay was landing on the clock ports; scoped hold-fix -min overrides now have matching -max values. Fmax 467.90 MHz core / 1736.15 MHz falcon (was 440 MHz), 0 setup/hold violations (was 8 hold violations). - partition_p: same -min/-max fix as partition_o; retimed 1433ps->1635ps (period_min * 1.10) to restore clean closure after the -max fix tightened setup. Fmax 630.47 MHz (was 698 MHz), 0 setup/hold violations. - partition_c: constraint.sdc now applies an early blanket input delay so synth/floorplan/place/CTS see a real constraint instead of none (pre_grt.tcl still overrides it post-CTS with the full inter- partition value); output delay credit is now a literal -1950ps instead of a clk_period-relative formula, matching how the value was actually derived; reset-synchronizer false-paths now match on p_SSYNC2DO_C_PP's RTL-declared q/d0 net names instead of synthesis- internal cell names, with a guard that errors loudly if either net goes missing; dropped a hardcoded NUM_CORES=16. Fmax improved to 673.54 MHz; still has 75 setup and 2497 hold violations at the 1300ps target -- incremental hold repair remains the known ~18h-non-convergence issue. floonoc: corrected a stale pin-fit comment (was citing a 129x129 die, actual DIE_AREA is 80x80) and dropped a BUILD.bazel comment reference to a scratch file that isn't in the repo. lfsr: fixed a doc typo (platforms/gt2n/pdn.cfg -> pdn.tcl; the pinned ORFS ships pdn.tcl, not pdn.cfg). Updates designs/src/NVDLA/DECISIONS.md's gt2n section. --- designs/gt2n/NVDLA/partition_c/BUILD.bazel | 1 - designs/gt2n/NVDLA/partition_c/constraint.sdc | 29 +- designs/gt2n/NVDLA/partition_c/pre_grt.tcl | 20 +- designs/gt2n/NVDLA/partition_m/BUILD.bazel | 1 + designs/gt2n/NVDLA/partition_m/pre_cts.tcl | 4 +- designs/gt2n/NVDLA/partition_o/constraint.sdc | 8 +- designs/gt2n/NVDLA/partition_p/constraint.sdc | 9 +- .../NVDLA/sram/lef/fakeram_11x128_1r1w.lef | 148 +++---- .../NVDLA/sram/lef/fakeram_14x80_1r1w.lef | 93 +++-- .../NVDLA/sram/lef/fakeram_15x80_1r1w.lef | 93 +++-- .../NVDLA/sram/lef/fakeram_16x160_1r1w.lef | 185 +++++---- .../NVDLA/sram/lef/fakeram_18x128_1r1w.lef | 148 +++---- .../NVDLA/sram/lef/fakeram_22x60_1r1w.lef | 138 +++---- .../NVDLA/sram/lef/fakeram_32x128_1r1w.lef | 148 +++---- .../NVDLA/sram/lef/fakeram_4x256_1r1w.lef | 74 ++-- .../NVDLA/sram/lef/fakeram_64x256_1r1w.lef | 296 +++++++------- .../NVDLA/sram/lef/fakeram_65x160_1r1w.lef | 370 +++++++++--------- .../NVDLA/sram/lef/fakeram_66x64_1r1w.lef | 148 +++---- .../NVDLA/sram/lef/fakeram_66x80_1r1w.lef | 185 +++++---- .../NVDLA/sram/lef/fakeram_7x256_1r1w.lef | 148 +++---- .../NVDLA/sram/lef/fakeram_8x256_1r1w.lef | 148 +++---- .../NVDLA/sram/lib/fakeram_11x128_1r1w.lib | 128 +++--- .../NVDLA/sram/lib/fakeram_14x80_1r1w.lib | 128 +++--- .../NVDLA/sram/lib/fakeram_15x80_1r1w.lib | 128 +++--- .../NVDLA/sram/lib/fakeram_16x160_1r1w.lib | 128 +++--- .../NVDLA/sram/lib/fakeram_18x128_1r1w.lib | 128 +++--- .../NVDLA/sram/lib/fakeram_22x60_1r1w.lib | 128 +++--- .../NVDLA/sram/lib/fakeram_32x128_1r1w.lib | 128 +++--- .../NVDLA/sram/lib/fakeram_4x256_1r1w.lib | 128 +++--- .../NVDLA/sram/lib/fakeram_64x256_1r1w.lib | 128 +++--- .../NVDLA/sram/lib/fakeram_65x160_1r1w.lib | 128 +++--- .../NVDLA/sram/lib/fakeram_66x64_1r1w.lib | 128 +++--- .../NVDLA/sram/lib/fakeram_66x80_1r1w.lib | 128 +++--- .../NVDLA/sram/lib/fakeram_7x256_1r1w.lib | 128 +++--- .../NVDLA/sram/lib/fakeram_8x256_1r1w.lib | 128 +++--- designs/gt2n/floonoc/BUILD.bazel | 4 +- designs/gt2n/floonoc/io.tcl | 6 +- designs/src/NVDLA/DECISIONS.md | 15 +- designs/src/lfsr/DECISIONS.md | 2 +- tools/bsg_fakeram | 2 +- 40 files changed, 2117 insertions(+), 2098 deletions(-) diff --git a/designs/gt2n/NVDLA/partition_c/BUILD.bazel b/designs/gt2n/NVDLA/partition_c/BUILD.bazel index 9d1ae340..0423ab2f 100644 --- a/designs/gt2n/NVDLA/partition_c/BUILD.bazel +++ b/designs/gt2n/NVDLA/partition_c/BUILD.bazel @@ -24,6 +24,5 @@ hightide_design( "MIN_CLK_ROUTING_LAYER": "M6", "MACRO_BLOCKAGE_HALO": "0.5", "TNS_END_PERCENT": "100", - "NUM_CORES": "16", }, ) diff --git a/designs/gt2n/NVDLA/partition_c/constraint.sdc b/designs/gt2n/NVDLA/partition_c/constraint.sdc index 76c41336..b9d1493b 100644 --- a/designs/gt2n/NVDLA/partition_c/constraint.sdc +++ b/designs/gt2n/NVDLA/partition_c/constraint.sdc @@ -2,6 +2,7 @@ current_design NV_NVDLA_partition_c set clk_name nvdla_core_clk set clk_period 1300 +set clk_io_pct 0.2 set clk_port [get_ports $clk_name] @@ -14,11 +15,15 @@ set_clock_transition -fall -max 0.1 [get_clocks $clk_name] set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +# Blanket delay so synth/floorplan/place/CTS see a real input constraint; pre_grt.tcl +# overrides this post-CTS with the true (period-exceeding) cross-partition delay. +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs + # Delay credit more realistically models the capture-side clock insertion latency of whatever # receives this partition's boundary outputs, since all partitions are intended as a single die. -# The delay was chosen to be approximately half of the worst clock network latency seen -# within this partition, while stile being expressed relative to the clock period. -set_output_delay [expr -$clk_period * 1.5] -clock $clk_name [all_outputs] +# Fixed at -1950 ps -- approximately half of the worst clock network latency observed in this +# partition. +set_output_delay -1950 -clock $clk_name [all_outputs] set_ideal_network [get_ports global_clk_ovr_on] set_ideal_network [get_ports test_mode] @@ -38,10 +43,20 @@ set_false_path -from [get_ports tmc2slcg_disable_clock_gating] set_false_path -from [get_ports global_clk_ovr_on] set_false_path -from [get_ports nvdla_clk_ovr_on] -# -through (not -to */SETN|RESETN) works around an OpenSTA write_sdc -# instance-name corruption bug on the wildcard form; see CLAUDE.md. -set_false_path -through [get_pins {u_partition_c_reset.sync_reset_synced_rstn.NV_GENERIC_CELL.q$_DFF_PN0_/Q}] -set_false_path -through [get_pins {u_partition_c_reset.sync_reset_synced_rstn.NV_GENERIC_CELL.d0$_DFF_PN0_/Q}] +# -through [get_nets ...] on q/d0 -- regs declared directly in NVDLA's p_SSYNC2DO_C_PP.v +# primitive, not synthesis-tool-internal names, so this stays valid across yosys versions. +# Errors loudly if a toolchain change ever makes either net disappear, instead of silently +# dropping the false-path and reintroducing recovery/removal violations on this reset's fanout. +foreach reset_sync_net { + u_partition_c_reset.sync_reset_synced_rstn.NV_GENERIC_CELL.q + u_partition_c_reset.sync_reset_synced_rstn.NV_GENERIC_CELL.d0 +} { + set net [get_nets $reset_sync_net] + if {[llength $net] == 0} { + error "constraint.sdc: reset synchronizer net $reset_sync_net not found -- update this false-path" + } + set_false_path -through $net +} set_max_fanout 128 [current_design] diff --git a/designs/gt2n/NVDLA/partition_c/pre_grt.tcl b/designs/gt2n/NVDLA/partition_c/pre_grt.tcl index 3821196c..8c7ede81 100644 --- a/designs/gt2n/NVDLA/partition_c/pre_grt.tcl +++ b/designs/gt2n/NVDLA/partition_c/pre_grt.tcl @@ -1,16 +1,20 @@ -# input_delay applied here (post-CTS) instead of in constraint.sdc because -# the need to more realistically model the interpartitional signals (that would share a clock as one die) -# calls for an input delay greater than the period. -# While more realistic in this particular scenario, this produces poor placement and cts results unless applied post-CTS. +# Overrides constraint.sdc's blanket clk_io_pct input delay: the interpartitional signals +# (that would share a clock as one die) need a more realistic delay that exceeds the clock +# period, which produces poor placement and CTS results unless applied post-CTS instead. set clk_name nvdla_core_clk set clk_port [get_ports $clk_name] set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] set_input_delay 1950 -clock [get_clocks $clk_name] $non_clock_inputs -# Incremental hold repair disabled, needs 18 or more hours to complete. +# Incremental hold repair disabled, needs 18 or more hours to complete. # May be able to resolve remaining hold violations if allowed to run to completion. -rename repair_timing_helper repair_timing_helper_orig -proc repair_timing_helper { args } { - repair_timing_helper_orig {*}$args -setup +# Proc override (not SKIP_INCREMENTAL_REPAIR) because we want setup repair to still +# run here, just not hold -- SKIP_INCREMENTAL_REPAIR would drop both. +# Guarded: PRE GLOBAL_ROUTE can be sourced more than once per process. +if {[info procs repair_timing_helper_orig] eq {}} { + rename repair_timing_helper repair_timing_helper_orig + proc repair_timing_helper { args } { + repair_timing_helper_orig {*}$args -setup + } } diff --git a/designs/gt2n/NVDLA/partition_m/BUILD.bazel b/designs/gt2n/NVDLA/partition_m/BUILD.bazel index 5c04c3ca..a6f5e6e6 100644 --- a/designs/gt2n/NVDLA/partition_m/BUILD.bazel +++ b/designs/gt2n/NVDLA/partition_m/BUILD.bazel @@ -19,5 +19,6 @@ hightide_design( "MAX_ROUTING_LAYER": "M11", "MIN_CLK_ROUTING_LAYER": "M4", "TNS_END_PERCENT": "100", + "HOLD_SLACK_MARGIN": "5", }, ) diff --git a/designs/gt2n/NVDLA/partition_m/pre_cts.tcl b/designs/gt2n/NVDLA/partition_m/pre_cts.tcl index b9c974ac..7b95b7d7 100644 --- a/designs/gt2n/NVDLA/partition_m/pre_cts.tcl +++ b/designs/gt2n/NVDLA/partition_m/pre_cts.tcl @@ -1,2 +1,2 @@ -# To match MIN_CLK_ROUTING_LAYER=M6. -set_wire_rc -clock -layer M6 +# To match MIN_CLK_ROUTING_LAYER=M4. +set_wire_rc -clock -layer M4 diff --git a/designs/gt2n/NVDLA/partition_o/constraint.sdc b/designs/gt2n/NVDLA/partition_o/constraint.sdc index 162c572f..9697cd7c 100644 --- a/designs/gt2n/NVDLA/partition_o/constraint.sdc +++ b/designs/gt2n/NVDLA/partition_o/constraint.sdc @@ -28,16 +28,20 @@ set_clock_transition -rise -max 0.1 [get_clocks $clk_falcon_name] set_clock_transition -fall -min 0.1 [get_clocks $clk_falcon_name] set_clock_transition -fall -max 0.1 [get_clocks $clk_falcon_name] -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] "^($clk_port|$clk_falcon_port)$"] +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [lsearch -inline -all -not -exact $non_clock_inputs $clk_falcon_port] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] # Scoped hold fixes: sdp2csb_resp_valid and cmac_b2csb_resp_valid are zero-logic passthrough # primary inputs from sibling gt2n partitions, with no on-chip source register to model skew -# against, so the blanket -min under-budgets their minimum arrival. +# against, so the blanket -min under-budgets their minimum arrival. -max set equal to -min +# (same zero-window assumption the blanket delay above uses) so setup stays min<=max. set_input_delay -min 494 -clock $clk_name [get_ports {sdp2csb_resp_*}] +set_input_delay -max 494 -clock $clk_name [get_ports {sdp2csb_resp_*}] set_input_delay -min 469 -clock $clk_name [get_ports {cmac_b2csb_resp_*}] +set_input_delay -max 469 -clock $clk_name [get_ports {cmac_b2csb_resp_*}] set_ideal_network [get_ports test_mode] set_ideal_network [get_ports direct_reset_] diff --git a/designs/gt2n/NVDLA/partition_p/constraint.sdc b/designs/gt2n/NVDLA/partition_p/constraint.sdc index 58f7ed91..9b3173f4 100644 --- a/designs/gt2n/NVDLA/partition_p/constraint.sdc +++ b/designs/gt2n/NVDLA/partition_p/constraint.sdc @@ -1,7 +1,7 @@ current_design NV_NVDLA_partition_p set clk_name nvdla_core_clk -set clk_period 1433 +set clk_period 1635 set clk_io_pct 0.2 set clk_port [get_ports $clk_name] @@ -17,11 +17,14 @@ set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] -# Scoped hold fix (2026-07-22) +# Scoped hold fix (2026-07-22). -max set equal to -min (same zero-window assumption the +# blanket delay above uses) so setup stays min<=max. set_input_delay -min 341 -clock $clk_name [get_ports {csb2sdp_req_pd*}] +set_input_delay -max 341 -clock $clk_name [get_ports {csb2sdp_req_pd*}] -# Second scoped hold fix (2026-07-22) +# Second scoped hold fix (2026-07-22), same min<=max rationale as above. set_input_delay -min 311 -clock $clk_name [get_ports {mcif2sdp_wr_rsp_complete*}] +set_input_delay -max 311 -clock $clk_name [get_ports {mcif2sdp_wr_rsp_complete*}] set_ideal_network [get_ports direct_reset_] set_ideal_network [get_ports dla_reset_rstn] diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_11x128_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_11x128_1r1w.lef index 0b39b3a1..215837c5 100644 --- a/designs/gt2n/NVDLA/sram/lef/fakeram_11x128_1r1w.lef +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_11x128_1r1w.lef @@ -460,80 +460,80 @@ MACRO fakeram_11x128_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.168 0.120 15.498 0.168 ; - RECT 0.168 0.504 15.498 0.552 ; - RECT 0.168 0.888 15.498 0.936 ; - RECT 0.168 1.272 15.498 1.320 ; - RECT 0.168 1.656 15.498 1.704 ; - RECT 0.168 2.040 15.498 2.088 ; - RECT 0.168 2.424 15.498 2.472 ; - RECT 0.168 2.808 15.498 2.856 ; - RECT 0.168 3.192 15.498 3.240 ; - RECT 0.168 3.576 15.498 3.624 ; - RECT 0.168 3.960 15.498 4.008 ; - RECT 0.168 4.344 15.498 4.392 ; - RECT 0.168 4.728 15.498 4.776 ; - RECT 0.168 5.112 15.498 5.160 ; - RECT 0.168 5.496 15.498 5.544 ; - RECT 0.168 5.880 15.498 5.928 ; - RECT 0.168 6.264 15.498 6.312 ; - RECT 0.168 6.648 15.498 6.696 ; - RECT 0.168 7.032 15.498 7.080 ; - RECT 0.168 7.416 15.498 7.464 ; - RECT 0.168 7.800 15.498 7.848 ; - RECT 0.168 8.184 15.498 8.232 ; - RECT 0.168 8.568 15.498 8.616 ; - RECT 0.168 8.952 15.498 9.000 ; - RECT 0.168 9.336 15.498 9.384 ; - RECT 0.168 9.720 15.498 9.768 ; - RECT 0.168 10.104 15.498 10.152 ; - RECT 0.168 10.488 15.498 10.536 ; - RECT 0.168 10.872 15.498 10.920 ; - RECT 0.168 11.256 15.498 11.304 ; - RECT 0.168 11.640 15.498 11.688 ; - RECT 0.168 12.024 15.498 12.072 ; - RECT 0.168 12.408 15.498 12.456 ; - RECT 0.168 12.792 15.498 12.840 ; - RECT 0.168 13.176 15.498 13.224 ; - RECT 0.168 13.560 15.498 13.608 ; - RECT 0.168 13.944 15.498 13.992 ; - RECT 0.168 14.328 15.498 14.376 ; - RECT 0.168 14.712 15.498 14.760 ; - RECT 0.168 15.096 15.498 15.144 ; - RECT 0.168 15.480 15.498 15.528 ; - RECT 0.168 15.864 15.498 15.912 ; - RECT 0.168 16.248 15.498 16.296 ; - RECT 0.168 16.632 15.498 16.680 ; - RECT 0.168 17.016 15.498 17.064 ; - RECT 0.168 17.400 15.498 17.448 ; - RECT 0.168 17.784 15.498 17.832 ; - RECT 0.168 18.168 15.498 18.216 ; - RECT 0.168 18.552 15.498 18.600 ; - RECT 0.168 18.936 15.498 18.984 ; - RECT 0.168 19.320 15.498 19.368 ; - RECT 0.168 19.704 15.498 19.752 ; - RECT 0.168 20.088 15.498 20.136 ; - RECT 0.168 20.472 15.498 20.520 ; - RECT 0.168 20.856 15.498 20.904 ; - RECT 0.168 21.240 15.498 21.288 ; - RECT 0.168 21.624 15.498 21.672 ; - RECT 0.168 22.008 15.498 22.056 ; - RECT 0.168 22.392 15.498 22.440 ; - RECT 0.168 22.776 15.498 22.824 ; - RECT 0.168 23.160 15.498 23.208 ; - RECT 0.168 23.544 15.498 23.592 ; - RECT 0.168 23.928 15.498 23.976 ; - RECT 0.168 24.312 15.498 24.360 ; - RECT 0.168 24.696 15.498 24.744 ; - RECT 0.168 25.080 15.498 25.128 ; - RECT 0.168 25.464 15.498 25.512 ; - RECT 0.168 25.848 15.498 25.896 ; - RECT 0.168 26.232 15.498 26.280 ; - RECT 0.168 26.616 15.498 26.664 ; - RECT 0.168 27.000 15.498 27.048 ; - RECT 0.168 27.384 15.498 27.432 ; - RECT 0.168 27.768 15.498 27.816 ; - RECT 0.168 28.152 15.498 28.200 ; + RECT 0.168 0.312 15.498 0.360 ; + RECT 0.168 0.696 15.498 0.744 ; + RECT 0.168 1.080 15.498 1.128 ; + RECT 0.168 1.464 15.498 1.512 ; + RECT 0.168 1.848 15.498 1.896 ; + RECT 0.168 2.232 15.498 2.280 ; + RECT 0.168 2.616 15.498 2.664 ; + RECT 0.168 3.000 15.498 3.048 ; + RECT 0.168 3.384 15.498 3.432 ; + RECT 0.168 3.768 15.498 3.816 ; + RECT 0.168 4.152 15.498 4.200 ; + RECT 0.168 4.536 15.498 4.584 ; + RECT 0.168 4.920 15.498 4.968 ; + RECT 0.168 5.304 15.498 5.352 ; + RECT 0.168 5.688 15.498 5.736 ; + RECT 0.168 6.072 15.498 6.120 ; + RECT 0.168 6.456 15.498 6.504 ; + RECT 0.168 6.840 15.498 6.888 ; + RECT 0.168 7.224 15.498 7.272 ; + RECT 0.168 7.608 15.498 7.656 ; + RECT 0.168 7.992 15.498 8.040 ; + RECT 0.168 8.376 15.498 8.424 ; + RECT 0.168 8.760 15.498 8.808 ; + RECT 0.168 9.144 15.498 9.192 ; + RECT 0.168 9.528 15.498 9.576 ; + RECT 0.168 9.912 15.498 9.960 ; + RECT 0.168 10.296 15.498 10.344 ; + RECT 0.168 10.680 15.498 10.728 ; + RECT 0.168 11.064 15.498 11.112 ; + RECT 0.168 11.448 15.498 11.496 ; + RECT 0.168 11.832 15.498 11.880 ; + RECT 0.168 12.216 15.498 12.264 ; + RECT 0.168 12.600 15.498 12.648 ; + RECT 0.168 12.984 15.498 13.032 ; + RECT 0.168 13.368 15.498 13.416 ; + RECT 0.168 13.752 15.498 13.800 ; + RECT 0.168 14.136 15.498 14.184 ; + RECT 0.168 14.520 15.498 14.568 ; + RECT 0.168 14.904 15.498 14.952 ; + RECT 0.168 15.288 15.498 15.336 ; + RECT 0.168 15.672 15.498 15.720 ; + RECT 0.168 16.056 15.498 16.104 ; + RECT 0.168 16.440 15.498 16.488 ; + RECT 0.168 16.824 15.498 16.872 ; + RECT 0.168 17.208 15.498 17.256 ; + RECT 0.168 17.592 15.498 17.640 ; + RECT 0.168 17.976 15.498 18.024 ; + RECT 0.168 18.360 15.498 18.408 ; + RECT 0.168 18.744 15.498 18.792 ; + RECT 0.168 19.128 15.498 19.176 ; + RECT 0.168 19.512 15.498 19.560 ; + RECT 0.168 19.896 15.498 19.944 ; + RECT 0.168 20.280 15.498 20.328 ; + RECT 0.168 20.664 15.498 20.712 ; + RECT 0.168 21.048 15.498 21.096 ; + RECT 0.168 21.432 15.498 21.480 ; + RECT 0.168 21.816 15.498 21.864 ; + RECT 0.168 22.200 15.498 22.248 ; + RECT 0.168 22.584 15.498 22.632 ; + RECT 0.168 22.968 15.498 23.016 ; + RECT 0.168 23.352 15.498 23.400 ; + RECT 0.168 23.736 15.498 23.784 ; + RECT 0.168 24.120 15.498 24.168 ; + RECT 0.168 24.504 15.498 24.552 ; + RECT 0.168 24.888 15.498 24.936 ; + RECT 0.168 25.272 15.498 25.320 ; + RECT 0.168 25.656 15.498 25.704 ; + RECT 0.168 26.040 15.498 26.088 ; + RECT 0.168 26.424 15.498 26.472 ; + RECT 0.168 26.808 15.498 26.856 ; + RECT 0.168 27.192 15.498 27.240 ; + RECT 0.168 27.576 15.498 27.624 ; + RECT 0.168 27.960 15.498 28.008 ; + RECT 0.168 28.344 15.498 28.392 ; END END VDD OBS diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_14x80_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_14x80_1r1w.lef index 892a7d82..0d8826a8 100644 --- a/designs/gt2n/NVDLA/sram/lef/fakeram_14x80_1r1w.lef +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_14x80_1r1w.lef @@ -487,53 +487,52 @@ MACRO fakeram_14x80_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.168 0.120 19.740 0.168 ; - RECT 0.168 0.504 19.740 0.552 ; - RECT 0.168 0.888 19.740 0.936 ; - RECT 0.168 1.272 19.740 1.320 ; - RECT 0.168 1.656 19.740 1.704 ; - RECT 0.168 2.040 19.740 2.088 ; - RECT 0.168 2.424 19.740 2.472 ; - RECT 0.168 2.808 19.740 2.856 ; - RECT 0.168 3.192 19.740 3.240 ; - RECT 0.168 3.576 19.740 3.624 ; - RECT 0.168 3.960 19.740 4.008 ; - RECT 0.168 4.344 19.740 4.392 ; - RECT 0.168 4.728 19.740 4.776 ; - RECT 0.168 5.112 19.740 5.160 ; - RECT 0.168 5.496 19.740 5.544 ; - RECT 0.168 5.880 19.740 5.928 ; - RECT 0.168 6.264 19.740 6.312 ; - RECT 0.168 6.648 19.740 6.696 ; - RECT 0.168 7.032 19.740 7.080 ; - RECT 0.168 7.416 19.740 7.464 ; - RECT 0.168 7.800 19.740 7.848 ; - RECT 0.168 8.184 19.740 8.232 ; - RECT 0.168 8.568 19.740 8.616 ; - RECT 0.168 8.952 19.740 9.000 ; - RECT 0.168 9.336 19.740 9.384 ; - RECT 0.168 9.720 19.740 9.768 ; - RECT 0.168 10.104 19.740 10.152 ; - RECT 0.168 10.488 19.740 10.536 ; - RECT 0.168 10.872 19.740 10.920 ; - RECT 0.168 11.256 19.740 11.304 ; - RECT 0.168 11.640 19.740 11.688 ; - RECT 0.168 12.024 19.740 12.072 ; - RECT 0.168 12.408 19.740 12.456 ; - RECT 0.168 12.792 19.740 12.840 ; - RECT 0.168 13.176 19.740 13.224 ; - RECT 0.168 13.560 19.740 13.608 ; - RECT 0.168 13.944 19.740 13.992 ; - RECT 0.168 14.328 19.740 14.376 ; - RECT 0.168 14.712 19.740 14.760 ; - RECT 0.168 15.096 19.740 15.144 ; - RECT 0.168 15.480 19.740 15.528 ; - RECT 0.168 15.864 19.740 15.912 ; - RECT 0.168 16.248 19.740 16.296 ; - RECT 0.168 16.632 19.740 16.680 ; - RECT 0.168 17.016 19.740 17.064 ; - RECT 0.168 17.400 19.740 17.448 ; - RECT 0.168 17.784 19.740 17.832 ; + RECT 0.168 0.312 19.740 0.360 ; + RECT 0.168 0.696 19.740 0.744 ; + RECT 0.168 1.080 19.740 1.128 ; + RECT 0.168 1.464 19.740 1.512 ; + RECT 0.168 1.848 19.740 1.896 ; + RECT 0.168 2.232 19.740 2.280 ; + RECT 0.168 2.616 19.740 2.664 ; + RECT 0.168 3.000 19.740 3.048 ; + RECT 0.168 3.384 19.740 3.432 ; + RECT 0.168 3.768 19.740 3.816 ; + RECT 0.168 4.152 19.740 4.200 ; + RECT 0.168 4.536 19.740 4.584 ; + RECT 0.168 4.920 19.740 4.968 ; + RECT 0.168 5.304 19.740 5.352 ; + RECT 0.168 5.688 19.740 5.736 ; + RECT 0.168 6.072 19.740 6.120 ; + RECT 0.168 6.456 19.740 6.504 ; + RECT 0.168 6.840 19.740 6.888 ; + RECT 0.168 7.224 19.740 7.272 ; + RECT 0.168 7.608 19.740 7.656 ; + RECT 0.168 7.992 19.740 8.040 ; + RECT 0.168 8.376 19.740 8.424 ; + RECT 0.168 8.760 19.740 8.808 ; + RECT 0.168 9.144 19.740 9.192 ; + RECT 0.168 9.528 19.740 9.576 ; + RECT 0.168 9.912 19.740 9.960 ; + RECT 0.168 10.296 19.740 10.344 ; + RECT 0.168 10.680 19.740 10.728 ; + RECT 0.168 11.064 19.740 11.112 ; + RECT 0.168 11.448 19.740 11.496 ; + RECT 0.168 11.832 19.740 11.880 ; + RECT 0.168 12.216 19.740 12.264 ; + RECT 0.168 12.600 19.740 12.648 ; + RECT 0.168 12.984 19.740 13.032 ; + RECT 0.168 13.368 19.740 13.416 ; + RECT 0.168 13.752 19.740 13.800 ; + RECT 0.168 14.136 19.740 14.184 ; + RECT 0.168 14.520 19.740 14.568 ; + RECT 0.168 14.904 19.740 14.952 ; + RECT 0.168 15.288 19.740 15.336 ; + RECT 0.168 15.672 19.740 15.720 ; + RECT 0.168 16.056 19.740 16.104 ; + RECT 0.168 16.440 19.740 16.488 ; + RECT 0.168 16.824 19.740 16.872 ; + RECT 0.168 17.208 19.740 17.256 ; + RECT 0.168 17.592 19.740 17.640 ; END END VDD OBS diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_15x80_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_15x80_1r1w.lef index 78bc384e..115bdd32 100644 --- a/designs/gt2n/NVDLA/sram/lef/fakeram_15x80_1r1w.lef +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_15x80_1r1w.lef @@ -505,53 +505,52 @@ MACRO fakeram_15x80_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.168 0.120 21.168 0.168 ; - RECT 0.168 0.504 21.168 0.552 ; - RECT 0.168 0.888 21.168 0.936 ; - RECT 0.168 1.272 21.168 1.320 ; - RECT 0.168 1.656 21.168 1.704 ; - RECT 0.168 2.040 21.168 2.088 ; - RECT 0.168 2.424 21.168 2.472 ; - RECT 0.168 2.808 21.168 2.856 ; - RECT 0.168 3.192 21.168 3.240 ; - RECT 0.168 3.576 21.168 3.624 ; - RECT 0.168 3.960 21.168 4.008 ; - RECT 0.168 4.344 21.168 4.392 ; - RECT 0.168 4.728 21.168 4.776 ; - RECT 0.168 5.112 21.168 5.160 ; - RECT 0.168 5.496 21.168 5.544 ; - RECT 0.168 5.880 21.168 5.928 ; - RECT 0.168 6.264 21.168 6.312 ; - RECT 0.168 6.648 21.168 6.696 ; - RECT 0.168 7.032 21.168 7.080 ; - RECT 0.168 7.416 21.168 7.464 ; - RECT 0.168 7.800 21.168 7.848 ; - RECT 0.168 8.184 21.168 8.232 ; - RECT 0.168 8.568 21.168 8.616 ; - RECT 0.168 8.952 21.168 9.000 ; - RECT 0.168 9.336 21.168 9.384 ; - RECT 0.168 9.720 21.168 9.768 ; - RECT 0.168 10.104 21.168 10.152 ; - RECT 0.168 10.488 21.168 10.536 ; - RECT 0.168 10.872 21.168 10.920 ; - RECT 0.168 11.256 21.168 11.304 ; - RECT 0.168 11.640 21.168 11.688 ; - RECT 0.168 12.024 21.168 12.072 ; - RECT 0.168 12.408 21.168 12.456 ; - RECT 0.168 12.792 21.168 12.840 ; - RECT 0.168 13.176 21.168 13.224 ; - RECT 0.168 13.560 21.168 13.608 ; - RECT 0.168 13.944 21.168 13.992 ; - RECT 0.168 14.328 21.168 14.376 ; - RECT 0.168 14.712 21.168 14.760 ; - RECT 0.168 15.096 21.168 15.144 ; - RECT 0.168 15.480 21.168 15.528 ; - RECT 0.168 15.864 21.168 15.912 ; - RECT 0.168 16.248 21.168 16.296 ; - RECT 0.168 16.632 21.168 16.680 ; - RECT 0.168 17.016 21.168 17.064 ; - RECT 0.168 17.400 21.168 17.448 ; - RECT 0.168 17.784 21.168 17.832 ; + RECT 0.168 0.312 21.168 0.360 ; + RECT 0.168 0.696 21.168 0.744 ; + RECT 0.168 1.080 21.168 1.128 ; + RECT 0.168 1.464 21.168 1.512 ; + RECT 0.168 1.848 21.168 1.896 ; + RECT 0.168 2.232 21.168 2.280 ; + RECT 0.168 2.616 21.168 2.664 ; + RECT 0.168 3.000 21.168 3.048 ; + RECT 0.168 3.384 21.168 3.432 ; + RECT 0.168 3.768 21.168 3.816 ; + RECT 0.168 4.152 21.168 4.200 ; + RECT 0.168 4.536 21.168 4.584 ; + RECT 0.168 4.920 21.168 4.968 ; + RECT 0.168 5.304 21.168 5.352 ; + RECT 0.168 5.688 21.168 5.736 ; + RECT 0.168 6.072 21.168 6.120 ; + RECT 0.168 6.456 21.168 6.504 ; + RECT 0.168 6.840 21.168 6.888 ; + RECT 0.168 7.224 21.168 7.272 ; + RECT 0.168 7.608 21.168 7.656 ; + RECT 0.168 7.992 21.168 8.040 ; + RECT 0.168 8.376 21.168 8.424 ; + RECT 0.168 8.760 21.168 8.808 ; + RECT 0.168 9.144 21.168 9.192 ; + RECT 0.168 9.528 21.168 9.576 ; + RECT 0.168 9.912 21.168 9.960 ; + RECT 0.168 10.296 21.168 10.344 ; + RECT 0.168 10.680 21.168 10.728 ; + RECT 0.168 11.064 21.168 11.112 ; + RECT 0.168 11.448 21.168 11.496 ; + RECT 0.168 11.832 21.168 11.880 ; + RECT 0.168 12.216 21.168 12.264 ; + RECT 0.168 12.600 21.168 12.648 ; + RECT 0.168 12.984 21.168 13.032 ; + RECT 0.168 13.368 21.168 13.416 ; + RECT 0.168 13.752 21.168 13.800 ; + RECT 0.168 14.136 21.168 14.184 ; + RECT 0.168 14.520 21.168 14.568 ; + RECT 0.168 14.904 21.168 14.952 ; + RECT 0.168 15.288 21.168 15.336 ; + RECT 0.168 15.672 21.168 15.720 ; + RECT 0.168 16.056 21.168 16.104 ; + RECT 0.168 16.440 21.168 16.488 ; + RECT 0.168 16.824 21.168 16.872 ; + RECT 0.168 17.208 21.168 17.256 ; + RECT 0.168 17.592 21.168 17.640 ; END END VDD OBS diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_16x160_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_16x160_1r1w.lef index 729287f2..30ecf9af 100644 --- a/designs/gt2n/NVDLA/sram/lef/fakeram_16x160_1r1w.lef +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_16x160_1r1w.lef @@ -587,99 +587,98 @@ MACRO fakeram_16x160_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.168 0.120 22.596 0.168 ; - RECT 0.168 0.504 22.596 0.552 ; - RECT 0.168 0.888 22.596 0.936 ; - RECT 0.168 1.272 22.596 1.320 ; - RECT 0.168 1.656 22.596 1.704 ; - RECT 0.168 2.040 22.596 2.088 ; - RECT 0.168 2.424 22.596 2.472 ; - RECT 0.168 2.808 22.596 2.856 ; - RECT 0.168 3.192 22.596 3.240 ; - RECT 0.168 3.576 22.596 3.624 ; - RECT 0.168 3.960 22.596 4.008 ; - RECT 0.168 4.344 22.596 4.392 ; - RECT 0.168 4.728 22.596 4.776 ; - RECT 0.168 5.112 22.596 5.160 ; - RECT 0.168 5.496 22.596 5.544 ; - RECT 0.168 5.880 22.596 5.928 ; - RECT 0.168 6.264 22.596 6.312 ; - RECT 0.168 6.648 22.596 6.696 ; - RECT 0.168 7.032 22.596 7.080 ; - RECT 0.168 7.416 22.596 7.464 ; - RECT 0.168 7.800 22.596 7.848 ; - RECT 0.168 8.184 22.596 8.232 ; - RECT 0.168 8.568 22.596 8.616 ; - RECT 0.168 8.952 22.596 9.000 ; - RECT 0.168 9.336 22.596 9.384 ; - RECT 0.168 9.720 22.596 9.768 ; - RECT 0.168 10.104 22.596 10.152 ; - RECT 0.168 10.488 22.596 10.536 ; - RECT 0.168 10.872 22.596 10.920 ; - RECT 0.168 11.256 22.596 11.304 ; - RECT 0.168 11.640 22.596 11.688 ; - RECT 0.168 12.024 22.596 12.072 ; - RECT 0.168 12.408 22.596 12.456 ; - RECT 0.168 12.792 22.596 12.840 ; - RECT 0.168 13.176 22.596 13.224 ; - RECT 0.168 13.560 22.596 13.608 ; - RECT 0.168 13.944 22.596 13.992 ; - RECT 0.168 14.328 22.596 14.376 ; - RECT 0.168 14.712 22.596 14.760 ; - RECT 0.168 15.096 22.596 15.144 ; - RECT 0.168 15.480 22.596 15.528 ; - RECT 0.168 15.864 22.596 15.912 ; - RECT 0.168 16.248 22.596 16.296 ; - RECT 0.168 16.632 22.596 16.680 ; - RECT 0.168 17.016 22.596 17.064 ; - RECT 0.168 17.400 22.596 17.448 ; - RECT 0.168 17.784 22.596 17.832 ; - RECT 0.168 18.168 22.596 18.216 ; - RECT 0.168 18.552 22.596 18.600 ; - RECT 0.168 18.936 22.596 18.984 ; - RECT 0.168 19.320 22.596 19.368 ; - RECT 0.168 19.704 22.596 19.752 ; - RECT 0.168 20.088 22.596 20.136 ; - RECT 0.168 20.472 22.596 20.520 ; - RECT 0.168 20.856 22.596 20.904 ; - RECT 0.168 21.240 22.596 21.288 ; - RECT 0.168 21.624 22.596 21.672 ; - RECT 0.168 22.008 22.596 22.056 ; - RECT 0.168 22.392 22.596 22.440 ; - RECT 0.168 22.776 22.596 22.824 ; - RECT 0.168 23.160 22.596 23.208 ; - RECT 0.168 23.544 22.596 23.592 ; - RECT 0.168 23.928 22.596 23.976 ; - RECT 0.168 24.312 22.596 24.360 ; - RECT 0.168 24.696 22.596 24.744 ; - RECT 0.168 25.080 22.596 25.128 ; - RECT 0.168 25.464 22.596 25.512 ; - RECT 0.168 25.848 22.596 25.896 ; - RECT 0.168 26.232 22.596 26.280 ; - RECT 0.168 26.616 22.596 26.664 ; - RECT 0.168 27.000 22.596 27.048 ; - RECT 0.168 27.384 22.596 27.432 ; - RECT 0.168 27.768 22.596 27.816 ; - RECT 0.168 28.152 22.596 28.200 ; - RECT 0.168 28.536 22.596 28.584 ; - RECT 0.168 28.920 22.596 28.968 ; - RECT 0.168 29.304 22.596 29.352 ; - RECT 0.168 29.688 22.596 29.736 ; - RECT 0.168 30.072 22.596 30.120 ; - RECT 0.168 30.456 22.596 30.504 ; - RECT 0.168 30.840 22.596 30.888 ; - RECT 0.168 31.224 22.596 31.272 ; - RECT 0.168 31.608 22.596 31.656 ; - RECT 0.168 31.992 22.596 32.040 ; - RECT 0.168 32.376 22.596 32.424 ; - RECT 0.168 32.760 22.596 32.808 ; - RECT 0.168 33.144 22.596 33.192 ; - RECT 0.168 33.528 22.596 33.576 ; - RECT 0.168 33.912 22.596 33.960 ; - RECT 0.168 34.296 22.596 34.344 ; - RECT 0.168 34.680 22.596 34.728 ; - RECT 0.168 35.064 22.596 35.112 ; - RECT 0.168 35.448 22.596 35.496 ; + RECT 0.168 0.312 22.596 0.360 ; + RECT 0.168 0.696 22.596 0.744 ; + RECT 0.168 1.080 22.596 1.128 ; + RECT 0.168 1.464 22.596 1.512 ; + RECT 0.168 1.848 22.596 1.896 ; + RECT 0.168 2.232 22.596 2.280 ; + RECT 0.168 2.616 22.596 2.664 ; + RECT 0.168 3.000 22.596 3.048 ; + RECT 0.168 3.384 22.596 3.432 ; + RECT 0.168 3.768 22.596 3.816 ; + RECT 0.168 4.152 22.596 4.200 ; + RECT 0.168 4.536 22.596 4.584 ; + RECT 0.168 4.920 22.596 4.968 ; + RECT 0.168 5.304 22.596 5.352 ; + RECT 0.168 5.688 22.596 5.736 ; + RECT 0.168 6.072 22.596 6.120 ; + RECT 0.168 6.456 22.596 6.504 ; + RECT 0.168 6.840 22.596 6.888 ; + RECT 0.168 7.224 22.596 7.272 ; + RECT 0.168 7.608 22.596 7.656 ; + RECT 0.168 7.992 22.596 8.040 ; + RECT 0.168 8.376 22.596 8.424 ; + RECT 0.168 8.760 22.596 8.808 ; + RECT 0.168 9.144 22.596 9.192 ; + RECT 0.168 9.528 22.596 9.576 ; + RECT 0.168 9.912 22.596 9.960 ; + RECT 0.168 10.296 22.596 10.344 ; + RECT 0.168 10.680 22.596 10.728 ; + RECT 0.168 11.064 22.596 11.112 ; + RECT 0.168 11.448 22.596 11.496 ; + RECT 0.168 11.832 22.596 11.880 ; + RECT 0.168 12.216 22.596 12.264 ; + RECT 0.168 12.600 22.596 12.648 ; + RECT 0.168 12.984 22.596 13.032 ; + RECT 0.168 13.368 22.596 13.416 ; + RECT 0.168 13.752 22.596 13.800 ; + RECT 0.168 14.136 22.596 14.184 ; + RECT 0.168 14.520 22.596 14.568 ; + RECT 0.168 14.904 22.596 14.952 ; + RECT 0.168 15.288 22.596 15.336 ; + RECT 0.168 15.672 22.596 15.720 ; + RECT 0.168 16.056 22.596 16.104 ; + RECT 0.168 16.440 22.596 16.488 ; + RECT 0.168 16.824 22.596 16.872 ; + RECT 0.168 17.208 22.596 17.256 ; + RECT 0.168 17.592 22.596 17.640 ; + RECT 0.168 17.976 22.596 18.024 ; + RECT 0.168 18.360 22.596 18.408 ; + RECT 0.168 18.744 22.596 18.792 ; + RECT 0.168 19.128 22.596 19.176 ; + RECT 0.168 19.512 22.596 19.560 ; + RECT 0.168 19.896 22.596 19.944 ; + RECT 0.168 20.280 22.596 20.328 ; + RECT 0.168 20.664 22.596 20.712 ; + RECT 0.168 21.048 22.596 21.096 ; + RECT 0.168 21.432 22.596 21.480 ; + RECT 0.168 21.816 22.596 21.864 ; + RECT 0.168 22.200 22.596 22.248 ; + RECT 0.168 22.584 22.596 22.632 ; + RECT 0.168 22.968 22.596 23.016 ; + RECT 0.168 23.352 22.596 23.400 ; + RECT 0.168 23.736 22.596 23.784 ; + RECT 0.168 24.120 22.596 24.168 ; + RECT 0.168 24.504 22.596 24.552 ; + RECT 0.168 24.888 22.596 24.936 ; + RECT 0.168 25.272 22.596 25.320 ; + RECT 0.168 25.656 22.596 25.704 ; + RECT 0.168 26.040 22.596 26.088 ; + RECT 0.168 26.424 22.596 26.472 ; + RECT 0.168 26.808 22.596 26.856 ; + RECT 0.168 27.192 22.596 27.240 ; + RECT 0.168 27.576 22.596 27.624 ; + RECT 0.168 27.960 22.596 28.008 ; + RECT 0.168 28.344 22.596 28.392 ; + RECT 0.168 28.728 22.596 28.776 ; + RECT 0.168 29.112 22.596 29.160 ; + RECT 0.168 29.496 22.596 29.544 ; + RECT 0.168 29.880 22.596 29.928 ; + RECT 0.168 30.264 22.596 30.312 ; + RECT 0.168 30.648 22.596 30.696 ; + RECT 0.168 31.032 22.596 31.080 ; + RECT 0.168 31.416 22.596 31.464 ; + RECT 0.168 31.800 22.596 31.848 ; + RECT 0.168 32.184 22.596 32.232 ; + RECT 0.168 32.568 22.596 32.616 ; + RECT 0.168 32.952 22.596 33.000 ; + RECT 0.168 33.336 22.596 33.384 ; + RECT 0.168 33.720 22.596 33.768 ; + RECT 0.168 34.104 22.596 34.152 ; + RECT 0.168 34.488 22.596 34.536 ; + RECT 0.168 34.872 22.596 34.920 ; + RECT 0.168 35.256 22.596 35.304 ; END END VDD OBS diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_18x128_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_18x128_1r1w.lef index acea2bd4..770093a8 100644 --- a/designs/gt2n/NVDLA/sram/lef/fakeram_18x128_1r1w.lef +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_18x128_1r1w.lef @@ -586,80 +586,80 @@ MACRO fakeram_18x128_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.168 0.120 25.452 0.168 ; - RECT 0.168 0.504 25.452 0.552 ; - RECT 0.168 0.888 25.452 0.936 ; - RECT 0.168 1.272 25.452 1.320 ; - RECT 0.168 1.656 25.452 1.704 ; - RECT 0.168 2.040 25.452 2.088 ; - RECT 0.168 2.424 25.452 2.472 ; - RECT 0.168 2.808 25.452 2.856 ; - RECT 0.168 3.192 25.452 3.240 ; - RECT 0.168 3.576 25.452 3.624 ; - RECT 0.168 3.960 25.452 4.008 ; - RECT 0.168 4.344 25.452 4.392 ; - RECT 0.168 4.728 25.452 4.776 ; - RECT 0.168 5.112 25.452 5.160 ; - RECT 0.168 5.496 25.452 5.544 ; - RECT 0.168 5.880 25.452 5.928 ; - RECT 0.168 6.264 25.452 6.312 ; - RECT 0.168 6.648 25.452 6.696 ; - RECT 0.168 7.032 25.452 7.080 ; - RECT 0.168 7.416 25.452 7.464 ; - RECT 0.168 7.800 25.452 7.848 ; - RECT 0.168 8.184 25.452 8.232 ; - RECT 0.168 8.568 25.452 8.616 ; - RECT 0.168 8.952 25.452 9.000 ; - RECT 0.168 9.336 25.452 9.384 ; - RECT 0.168 9.720 25.452 9.768 ; - RECT 0.168 10.104 25.452 10.152 ; - RECT 0.168 10.488 25.452 10.536 ; - RECT 0.168 10.872 25.452 10.920 ; - RECT 0.168 11.256 25.452 11.304 ; - RECT 0.168 11.640 25.452 11.688 ; - RECT 0.168 12.024 25.452 12.072 ; - RECT 0.168 12.408 25.452 12.456 ; - RECT 0.168 12.792 25.452 12.840 ; - RECT 0.168 13.176 25.452 13.224 ; - RECT 0.168 13.560 25.452 13.608 ; - RECT 0.168 13.944 25.452 13.992 ; - RECT 0.168 14.328 25.452 14.376 ; - RECT 0.168 14.712 25.452 14.760 ; - RECT 0.168 15.096 25.452 15.144 ; - RECT 0.168 15.480 25.452 15.528 ; - RECT 0.168 15.864 25.452 15.912 ; - RECT 0.168 16.248 25.452 16.296 ; - RECT 0.168 16.632 25.452 16.680 ; - RECT 0.168 17.016 25.452 17.064 ; - RECT 0.168 17.400 25.452 17.448 ; - RECT 0.168 17.784 25.452 17.832 ; - RECT 0.168 18.168 25.452 18.216 ; - RECT 0.168 18.552 25.452 18.600 ; - RECT 0.168 18.936 25.452 18.984 ; - RECT 0.168 19.320 25.452 19.368 ; - RECT 0.168 19.704 25.452 19.752 ; - RECT 0.168 20.088 25.452 20.136 ; - RECT 0.168 20.472 25.452 20.520 ; - RECT 0.168 20.856 25.452 20.904 ; - RECT 0.168 21.240 25.452 21.288 ; - RECT 0.168 21.624 25.452 21.672 ; - RECT 0.168 22.008 25.452 22.056 ; - RECT 0.168 22.392 25.452 22.440 ; - RECT 0.168 22.776 25.452 22.824 ; - RECT 0.168 23.160 25.452 23.208 ; - RECT 0.168 23.544 25.452 23.592 ; - RECT 0.168 23.928 25.452 23.976 ; - RECT 0.168 24.312 25.452 24.360 ; - RECT 0.168 24.696 25.452 24.744 ; - RECT 0.168 25.080 25.452 25.128 ; - RECT 0.168 25.464 25.452 25.512 ; - RECT 0.168 25.848 25.452 25.896 ; - RECT 0.168 26.232 25.452 26.280 ; - RECT 0.168 26.616 25.452 26.664 ; - RECT 0.168 27.000 25.452 27.048 ; - RECT 0.168 27.384 25.452 27.432 ; - RECT 0.168 27.768 25.452 27.816 ; - RECT 0.168 28.152 25.452 28.200 ; + RECT 0.168 0.312 25.452 0.360 ; + RECT 0.168 0.696 25.452 0.744 ; + RECT 0.168 1.080 25.452 1.128 ; + RECT 0.168 1.464 25.452 1.512 ; + RECT 0.168 1.848 25.452 1.896 ; + RECT 0.168 2.232 25.452 2.280 ; + RECT 0.168 2.616 25.452 2.664 ; + RECT 0.168 3.000 25.452 3.048 ; + RECT 0.168 3.384 25.452 3.432 ; + RECT 0.168 3.768 25.452 3.816 ; + RECT 0.168 4.152 25.452 4.200 ; + RECT 0.168 4.536 25.452 4.584 ; + RECT 0.168 4.920 25.452 4.968 ; + RECT 0.168 5.304 25.452 5.352 ; + RECT 0.168 5.688 25.452 5.736 ; + RECT 0.168 6.072 25.452 6.120 ; + RECT 0.168 6.456 25.452 6.504 ; + RECT 0.168 6.840 25.452 6.888 ; + RECT 0.168 7.224 25.452 7.272 ; + RECT 0.168 7.608 25.452 7.656 ; + RECT 0.168 7.992 25.452 8.040 ; + RECT 0.168 8.376 25.452 8.424 ; + RECT 0.168 8.760 25.452 8.808 ; + RECT 0.168 9.144 25.452 9.192 ; + RECT 0.168 9.528 25.452 9.576 ; + RECT 0.168 9.912 25.452 9.960 ; + RECT 0.168 10.296 25.452 10.344 ; + RECT 0.168 10.680 25.452 10.728 ; + RECT 0.168 11.064 25.452 11.112 ; + RECT 0.168 11.448 25.452 11.496 ; + RECT 0.168 11.832 25.452 11.880 ; + RECT 0.168 12.216 25.452 12.264 ; + RECT 0.168 12.600 25.452 12.648 ; + RECT 0.168 12.984 25.452 13.032 ; + RECT 0.168 13.368 25.452 13.416 ; + RECT 0.168 13.752 25.452 13.800 ; + RECT 0.168 14.136 25.452 14.184 ; + RECT 0.168 14.520 25.452 14.568 ; + RECT 0.168 14.904 25.452 14.952 ; + RECT 0.168 15.288 25.452 15.336 ; + RECT 0.168 15.672 25.452 15.720 ; + RECT 0.168 16.056 25.452 16.104 ; + RECT 0.168 16.440 25.452 16.488 ; + RECT 0.168 16.824 25.452 16.872 ; + RECT 0.168 17.208 25.452 17.256 ; + RECT 0.168 17.592 25.452 17.640 ; + RECT 0.168 17.976 25.452 18.024 ; + RECT 0.168 18.360 25.452 18.408 ; + RECT 0.168 18.744 25.452 18.792 ; + RECT 0.168 19.128 25.452 19.176 ; + RECT 0.168 19.512 25.452 19.560 ; + RECT 0.168 19.896 25.452 19.944 ; + RECT 0.168 20.280 25.452 20.328 ; + RECT 0.168 20.664 25.452 20.712 ; + RECT 0.168 21.048 25.452 21.096 ; + RECT 0.168 21.432 25.452 21.480 ; + RECT 0.168 21.816 25.452 21.864 ; + RECT 0.168 22.200 25.452 22.248 ; + RECT 0.168 22.584 25.452 22.632 ; + RECT 0.168 22.968 25.452 23.016 ; + RECT 0.168 23.352 25.452 23.400 ; + RECT 0.168 23.736 25.452 23.784 ; + RECT 0.168 24.120 25.452 24.168 ; + RECT 0.168 24.504 25.452 24.552 ; + RECT 0.168 24.888 25.452 24.936 ; + RECT 0.168 25.272 25.452 25.320 ; + RECT 0.168 25.656 25.452 25.704 ; + RECT 0.168 26.040 25.452 26.088 ; + RECT 0.168 26.424 25.452 26.472 ; + RECT 0.168 26.808 25.452 26.856 ; + RECT 0.168 27.192 25.452 27.240 ; + RECT 0.168 27.576 25.452 27.624 ; + RECT 0.168 27.960 25.452 28.008 ; + RECT 0.168 28.344 25.452 28.392 ; END END VDD OBS diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_22x60_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_22x60_1r1w.lef index 4dea7985..7ab59a98 100644 --- a/designs/gt2n/NVDLA/sram/lef/fakeram_22x60_1r1w.lef +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_22x60_1r1w.lef @@ -635,75 +635,75 @@ MACRO fakeram_22x60_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.168 0.120 15.498 0.168 ; - RECT 0.168 0.504 15.498 0.552 ; - RECT 0.168 0.888 15.498 0.936 ; - RECT 0.168 1.272 15.498 1.320 ; - RECT 0.168 1.656 15.498 1.704 ; - RECT 0.168 2.040 15.498 2.088 ; - RECT 0.168 2.424 15.498 2.472 ; - RECT 0.168 2.808 15.498 2.856 ; - RECT 0.168 3.192 15.498 3.240 ; - RECT 0.168 3.576 15.498 3.624 ; - RECT 0.168 3.960 15.498 4.008 ; - RECT 0.168 4.344 15.498 4.392 ; - RECT 0.168 4.728 15.498 4.776 ; - RECT 0.168 5.112 15.498 5.160 ; - RECT 0.168 5.496 15.498 5.544 ; - RECT 0.168 5.880 15.498 5.928 ; - RECT 0.168 6.264 15.498 6.312 ; - RECT 0.168 6.648 15.498 6.696 ; - RECT 0.168 7.032 15.498 7.080 ; - RECT 0.168 7.416 15.498 7.464 ; - RECT 0.168 7.800 15.498 7.848 ; - RECT 0.168 8.184 15.498 8.232 ; - RECT 0.168 8.568 15.498 8.616 ; - RECT 0.168 8.952 15.498 9.000 ; - RECT 0.168 9.336 15.498 9.384 ; - RECT 0.168 9.720 15.498 9.768 ; - RECT 0.168 10.104 15.498 10.152 ; - RECT 0.168 10.488 15.498 10.536 ; - RECT 0.168 10.872 15.498 10.920 ; - RECT 0.168 11.256 15.498 11.304 ; - RECT 0.168 11.640 15.498 11.688 ; - RECT 0.168 12.024 15.498 12.072 ; - RECT 0.168 12.408 15.498 12.456 ; - RECT 0.168 12.792 15.498 12.840 ; - RECT 0.168 13.176 15.498 13.224 ; - RECT 0.168 13.560 15.498 13.608 ; - RECT 0.168 13.944 15.498 13.992 ; - RECT 0.168 14.328 15.498 14.376 ; - RECT 0.168 14.712 15.498 14.760 ; - RECT 0.168 15.096 15.498 15.144 ; - RECT 0.168 15.480 15.498 15.528 ; - RECT 0.168 15.864 15.498 15.912 ; - RECT 0.168 16.248 15.498 16.296 ; - RECT 0.168 16.632 15.498 16.680 ; - RECT 0.168 17.016 15.498 17.064 ; - RECT 0.168 17.400 15.498 17.448 ; - RECT 0.168 17.784 15.498 17.832 ; - RECT 0.168 18.168 15.498 18.216 ; - RECT 0.168 18.552 15.498 18.600 ; - RECT 0.168 18.936 15.498 18.984 ; - RECT 0.168 19.320 15.498 19.368 ; - RECT 0.168 19.704 15.498 19.752 ; - RECT 0.168 20.088 15.498 20.136 ; - RECT 0.168 20.472 15.498 20.520 ; - RECT 0.168 20.856 15.498 20.904 ; - RECT 0.168 21.240 15.498 21.288 ; - RECT 0.168 21.624 15.498 21.672 ; - RECT 0.168 22.008 15.498 22.056 ; - RECT 0.168 22.392 15.498 22.440 ; - RECT 0.168 22.776 15.498 22.824 ; - RECT 0.168 23.160 15.498 23.208 ; - RECT 0.168 23.544 15.498 23.592 ; - RECT 0.168 23.928 15.498 23.976 ; - RECT 0.168 24.312 15.498 24.360 ; - RECT 0.168 24.696 15.498 24.744 ; - RECT 0.168 25.080 15.498 25.128 ; - RECT 0.168 25.464 15.498 25.512 ; - RECT 0.168 25.848 15.498 25.896 ; - RECT 0.168 26.232 15.498 26.280 ; + RECT 0.168 0.312 15.498 0.360 ; + RECT 0.168 0.696 15.498 0.744 ; + RECT 0.168 1.080 15.498 1.128 ; + RECT 0.168 1.464 15.498 1.512 ; + RECT 0.168 1.848 15.498 1.896 ; + RECT 0.168 2.232 15.498 2.280 ; + RECT 0.168 2.616 15.498 2.664 ; + RECT 0.168 3.000 15.498 3.048 ; + RECT 0.168 3.384 15.498 3.432 ; + RECT 0.168 3.768 15.498 3.816 ; + RECT 0.168 4.152 15.498 4.200 ; + RECT 0.168 4.536 15.498 4.584 ; + RECT 0.168 4.920 15.498 4.968 ; + RECT 0.168 5.304 15.498 5.352 ; + RECT 0.168 5.688 15.498 5.736 ; + RECT 0.168 6.072 15.498 6.120 ; + RECT 0.168 6.456 15.498 6.504 ; + RECT 0.168 6.840 15.498 6.888 ; + RECT 0.168 7.224 15.498 7.272 ; + RECT 0.168 7.608 15.498 7.656 ; + RECT 0.168 7.992 15.498 8.040 ; + RECT 0.168 8.376 15.498 8.424 ; + RECT 0.168 8.760 15.498 8.808 ; + RECT 0.168 9.144 15.498 9.192 ; + RECT 0.168 9.528 15.498 9.576 ; + RECT 0.168 9.912 15.498 9.960 ; + RECT 0.168 10.296 15.498 10.344 ; + RECT 0.168 10.680 15.498 10.728 ; + RECT 0.168 11.064 15.498 11.112 ; + RECT 0.168 11.448 15.498 11.496 ; + RECT 0.168 11.832 15.498 11.880 ; + RECT 0.168 12.216 15.498 12.264 ; + RECT 0.168 12.600 15.498 12.648 ; + RECT 0.168 12.984 15.498 13.032 ; + RECT 0.168 13.368 15.498 13.416 ; + RECT 0.168 13.752 15.498 13.800 ; + RECT 0.168 14.136 15.498 14.184 ; + RECT 0.168 14.520 15.498 14.568 ; + RECT 0.168 14.904 15.498 14.952 ; + RECT 0.168 15.288 15.498 15.336 ; + RECT 0.168 15.672 15.498 15.720 ; + RECT 0.168 16.056 15.498 16.104 ; + RECT 0.168 16.440 15.498 16.488 ; + RECT 0.168 16.824 15.498 16.872 ; + RECT 0.168 17.208 15.498 17.256 ; + RECT 0.168 17.592 15.498 17.640 ; + RECT 0.168 17.976 15.498 18.024 ; + RECT 0.168 18.360 15.498 18.408 ; + RECT 0.168 18.744 15.498 18.792 ; + RECT 0.168 19.128 15.498 19.176 ; + RECT 0.168 19.512 15.498 19.560 ; + RECT 0.168 19.896 15.498 19.944 ; + RECT 0.168 20.280 15.498 20.328 ; + RECT 0.168 20.664 15.498 20.712 ; + RECT 0.168 21.048 15.498 21.096 ; + RECT 0.168 21.432 15.498 21.480 ; + RECT 0.168 21.816 15.498 21.864 ; + RECT 0.168 22.200 15.498 22.248 ; + RECT 0.168 22.584 15.498 22.632 ; + RECT 0.168 22.968 15.498 23.016 ; + RECT 0.168 23.352 15.498 23.400 ; + RECT 0.168 23.736 15.498 23.784 ; + RECT 0.168 24.120 15.498 24.168 ; + RECT 0.168 24.504 15.498 24.552 ; + RECT 0.168 24.888 15.498 24.936 ; + RECT 0.168 25.272 15.498 25.320 ; + RECT 0.168 25.656 15.498 25.704 ; + RECT 0.168 26.040 15.498 26.088 ; + RECT 0.168 26.424 15.498 26.472 ; END END VDD OBS diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_32x128_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_32x128_1r1w.lef index 13f4c0ce..faecec34 100644 --- a/designs/gt2n/NVDLA/sram/lef/fakeram_32x128_1r1w.lef +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_32x128_1r1w.lef @@ -838,80 +838,80 @@ MACRO fakeram_32x128_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.168 0.120 45.318 0.168 ; - RECT 0.168 0.504 45.318 0.552 ; - RECT 0.168 0.888 45.318 0.936 ; - RECT 0.168 1.272 45.318 1.320 ; - RECT 0.168 1.656 45.318 1.704 ; - RECT 0.168 2.040 45.318 2.088 ; - RECT 0.168 2.424 45.318 2.472 ; - RECT 0.168 2.808 45.318 2.856 ; - RECT 0.168 3.192 45.318 3.240 ; - RECT 0.168 3.576 45.318 3.624 ; - RECT 0.168 3.960 45.318 4.008 ; - RECT 0.168 4.344 45.318 4.392 ; - RECT 0.168 4.728 45.318 4.776 ; - RECT 0.168 5.112 45.318 5.160 ; - RECT 0.168 5.496 45.318 5.544 ; - RECT 0.168 5.880 45.318 5.928 ; - RECT 0.168 6.264 45.318 6.312 ; - RECT 0.168 6.648 45.318 6.696 ; - RECT 0.168 7.032 45.318 7.080 ; - RECT 0.168 7.416 45.318 7.464 ; - RECT 0.168 7.800 45.318 7.848 ; - RECT 0.168 8.184 45.318 8.232 ; - RECT 0.168 8.568 45.318 8.616 ; - RECT 0.168 8.952 45.318 9.000 ; - RECT 0.168 9.336 45.318 9.384 ; - RECT 0.168 9.720 45.318 9.768 ; - RECT 0.168 10.104 45.318 10.152 ; - RECT 0.168 10.488 45.318 10.536 ; - RECT 0.168 10.872 45.318 10.920 ; - RECT 0.168 11.256 45.318 11.304 ; - RECT 0.168 11.640 45.318 11.688 ; - RECT 0.168 12.024 45.318 12.072 ; - RECT 0.168 12.408 45.318 12.456 ; - RECT 0.168 12.792 45.318 12.840 ; - RECT 0.168 13.176 45.318 13.224 ; - RECT 0.168 13.560 45.318 13.608 ; - RECT 0.168 13.944 45.318 13.992 ; - RECT 0.168 14.328 45.318 14.376 ; - RECT 0.168 14.712 45.318 14.760 ; - RECT 0.168 15.096 45.318 15.144 ; - RECT 0.168 15.480 45.318 15.528 ; - RECT 0.168 15.864 45.318 15.912 ; - RECT 0.168 16.248 45.318 16.296 ; - RECT 0.168 16.632 45.318 16.680 ; - RECT 0.168 17.016 45.318 17.064 ; - RECT 0.168 17.400 45.318 17.448 ; - RECT 0.168 17.784 45.318 17.832 ; - RECT 0.168 18.168 45.318 18.216 ; - RECT 0.168 18.552 45.318 18.600 ; - RECT 0.168 18.936 45.318 18.984 ; - RECT 0.168 19.320 45.318 19.368 ; - RECT 0.168 19.704 45.318 19.752 ; - RECT 0.168 20.088 45.318 20.136 ; - RECT 0.168 20.472 45.318 20.520 ; - RECT 0.168 20.856 45.318 20.904 ; - RECT 0.168 21.240 45.318 21.288 ; - RECT 0.168 21.624 45.318 21.672 ; - RECT 0.168 22.008 45.318 22.056 ; - RECT 0.168 22.392 45.318 22.440 ; - RECT 0.168 22.776 45.318 22.824 ; - RECT 0.168 23.160 45.318 23.208 ; - RECT 0.168 23.544 45.318 23.592 ; - RECT 0.168 23.928 45.318 23.976 ; - RECT 0.168 24.312 45.318 24.360 ; - RECT 0.168 24.696 45.318 24.744 ; - RECT 0.168 25.080 45.318 25.128 ; - RECT 0.168 25.464 45.318 25.512 ; - RECT 0.168 25.848 45.318 25.896 ; - RECT 0.168 26.232 45.318 26.280 ; - RECT 0.168 26.616 45.318 26.664 ; - RECT 0.168 27.000 45.318 27.048 ; - RECT 0.168 27.384 45.318 27.432 ; - RECT 0.168 27.768 45.318 27.816 ; - RECT 0.168 28.152 45.318 28.200 ; + RECT 0.168 0.312 45.318 0.360 ; + RECT 0.168 0.696 45.318 0.744 ; + RECT 0.168 1.080 45.318 1.128 ; + RECT 0.168 1.464 45.318 1.512 ; + RECT 0.168 1.848 45.318 1.896 ; + RECT 0.168 2.232 45.318 2.280 ; + RECT 0.168 2.616 45.318 2.664 ; + RECT 0.168 3.000 45.318 3.048 ; + RECT 0.168 3.384 45.318 3.432 ; + RECT 0.168 3.768 45.318 3.816 ; + RECT 0.168 4.152 45.318 4.200 ; + RECT 0.168 4.536 45.318 4.584 ; + RECT 0.168 4.920 45.318 4.968 ; + RECT 0.168 5.304 45.318 5.352 ; + RECT 0.168 5.688 45.318 5.736 ; + RECT 0.168 6.072 45.318 6.120 ; + RECT 0.168 6.456 45.318 6.504 ; + RECT 0.168 6.840 45.318 6.888 ; + RECT 0.168 7.224 45.318 7.272 ; + RECT 0.168 7.608 45.318 7.656 ; + RECT 0.168 7.992 45.318 8.040 ; + RECT 0.168 8.376 45.318 8.424 ; + RECT 0.168 8.760 45.318 8.808 ; + RECT 0.168 9.144 45.318 9.192 ; + RECT 0.168 9.528 45.318 9.576 ; + RECT 0.168 9.912 45.318 9.960 ; + RECT 0.168 10.296 45.318 10.344 ; + RECT 0.168 10.680 45.318 10.728 ; + RECT 0.168 11.064 45.318 11.112 ; + RECT 0.168 11.448 45.318 11.496 ; + RECT 0.168 11.832 45.318 11.880 ; + RECT 0.168 12.216 45.318 12.264 ; + RECT 0.168 12.600 45.318 12.648 ; + RECT 0.168 12.984 45.318 13.032 ; + RECT 0.168 13.368 45.318 13.416 ; + RECT 0.168 13.752 45.318 13.800 ; + RECT 0.168 14.136 45.318 14.184 ; + RECT 0.168 14.520 45.318 14.568 ; + RECT 0.168 14.904 45.318 14.952 ; + RECT 0.168 15.288 45.318 15.336 ; + RECT 0.168 15.672 45.318 15.720 ; + RECT 0.168 16.056 45.318 16.104 ; + RECT 0.168 16.440 45.318 16.488 ; + RECT 0.168 16.824 45.318 16.872 ; + RECT 0.168 17.208 45.318 17.256 ; + RECT 0.168 17.592 45.318 17.640 ; + RECT 0.168 17.976 45.318 18.024 ; + RECT 0.168 18.360 45.318 18.408 ; + RECT 0.168 18.744 45.318 18.792 ; + RECT 0.168 19.128 45.318 19.176 ; + RECT 0.168 19.512 45.318 19.560 ; + RECT 0.168 19.896 45.318 19.944 ; + RECT 0.168 20.280 45.318 20.328 ; + RECT 0.168 20.664 45.318 20.712 ; + RECT 0.168 21.048 45.318 21.096 ; + RECT 0.168 21.432 45.318 21.480 ; + RECT 0.168 21.816 45.318 21.864 ; + RECT 0.168 22.200 45.318 22.248 ; + RECT 0.168 22.584 45.318 22.632 ; + RECT 0.168 22.968 45.318 23.016 ; + RECT 0.168 23.352 45.318 23.400 ; + RECT 0.168 23.736 45.318 23.784 ; + RECT 0.168 24.120 45.318 24.168 ; + RECT 0.168 24.504 45.318 24.552 ; + RECT 0.168 24.888 45.318 24.936 ; + RECT 0.168 25.272 45.318 25.320 ; + RECT 0.168 25.656 45.318 25.704 ; + RECT 0.168 26.040 45.318 26.088 ; + RECT 0.168 26.424 45.318 26.472 ; + RECT 0.168 26.808 45.318 26.856 ; + RECT 0.168 27.192 45.318 27.240 ; + RECT 0.168 27.576 45.318 27.624 ; + RECT 0.168 27.960 45.318 28.008 ; + RECT 0.168 28.344 45.318 28.392 ; END END VDD OBS diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_4x256_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_4x256_1r1w.lef index 49850602..01016c0e 100644 --- a/designs/gt2n/NVDLA/sram/lef/fakeram_4x256_1r1w.lef +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_4x256_1r1w.lef @@ -315,43 +315,43 @@ MACRO fakeram_4x256_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.168 0.120 22.596 0.168 ; - RECT 0.168 0.504 22.596 0.552 ; - RECT 0.168 0.888 22.596 0.936 ; - RECT 0.168 1.272 22.596 1.320 ; - RECT 0.168 1.656 22.596 1.704 ; - RECT 0.168 2.040 22.596 2.088 ; - RECT 0.168 2.424 22.596 2.472 ; - RECT 0.168 2.808 22.596 2.856 ; - RECT 0.168 3.192 22.596 3.240 ; - RECT 0.168 3.576 22.596 3.624 ; - RECT 0.168 3.960 22.596 4.008 ; - RECT 0.168 4.344 22.596 4.392 ; - RECT 0.168 4.728 22.596 4.776 ; - RECT 0.168 5.112 22.596 5.160 ; - RECT 0.168 5.496 22.596 5.544 ; - RECT 0.168 5.880 22.596 5.928 ; - RECT 0.168 6.264 22.596 6.312 ; - RECT 0.168 6.648 22.596 6.696 ; - RECT 0.168 7.032 22.596 7.080 ; - RECT 0.168 7.416 22.596 7.464 ; - RECT 0.168 7.800 22.596 7.848 ; - RECT 0.168 8.184 22.596 8.232 ; - RECT 0.168 8.568 22.596 8.616 ; - RECT 0.168 8.952 22.596 9.000 ; - RECT 0.168 9.336 22.596 9.384 ; - RECT 0.168 9.720 22.596 9.768 ; - RECT 0.168 10.104 22.596 10.152 ; - RECT 0.168 10.488 22.596 10.536 ; - RECT 0.168 10.872 22.596 10.920 ; - RECT 0.168 11.256 22.596 11.304 ; - RECT 0.168 11.640 22.596 11.688 ; - RECT 0.168 12.024 22.596 12.072 ; - RECT 0.168 12.408 22.596 12.456 ; - RECT 0.168 12.792 22.596 12.840 ; - RECT 0.168 13.176 22.596 13.224 ; - RECT 0.168 13.560 22.596 13.608 ; - RECT 0.168 13.944 22.596 13.992 ; + RECT 0.168 0.312 22.596 0.360 ; + RECT 0.168 0.696 22.596 0.744 ; + RECT 0.168 1.080 22.596 1.128 ; + RECT 0.168 1.464 22.596 1.512 ; + RECT 0.168 1.848 22.596 1.896 ; + RECT 0.168 2.232 22.596 2.280 ; + RECT 0.168 2.616 22.596 2.664 ; + RECT 0.168 3.000 22.596 3.048 ; + RECT 0.168 3.384 22.596 3.432 ; + RECT 0.168 3.768 22.596 3.816 ; + RECT 0.168 4.152 22.596 4.200 ; + RECT 0.168 4.536 22.596 4.584 ; + RECT 0.168 4.920 22.596 4.968 ; + RECT 0.168 5.304 22.596 5.352 ; + RECT 0.168 5.688 22.596 5.736 ; + RECT 0.168 6.072 22.596 6.120 ; + RECT 0.168 6.456 22.596 6.504 ; + RECT 0.168 6.840 22.596 6.888 ; + RECT 0.168 7.224 22.596 7.272 ; + RECT 0.168 7.608 22.596 7.656 ; + RECT 0.168 7.992 22.596 8.040 ; + RECT 0.168 8.376 22.596 8.424 ; + RECT 0.168 8.760 22.596 8.808 ; + RECT 0.168 9.144 22.596 9.192 ; + RECT 0.168 9.528 22.596 9.576 ; + RECT 0.168 9.912 22.596 9.960 ; + RECT 0.168 10.296 22.596 10.344 ; + RECT 0.168 10.680 22.596 10.728 ; + RECT 0.168 11.064 22.596 11.112 ; + RECT 0.168 11.448 22.596 11.496 ; + RECT 0.168 11.832 22.596 11.880 ; + RECT 0.168 12.216 22.596 12.264 ; + RECT 0.168 12.600 22.596 12.648 ; + RECT 0.168 12.984 22.596 13.032 ; + RECT 0.168 13.368 22.596 13.416 ; + RECT 0.168 13.752 22.596 13.800 ; + RECT 0.168 14.136 22.596 14.184 ; END END VDD OBS diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_64x256_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_64x256_1r1w.lef index 4e3e6be1..957f756b 100644 --- a/designs/gt2n/NVDLA/sram/lef/fakeram_64x256_1r1w.lef +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_64x256_1r1w.lef @@ -1506,154 +1506,154 @@ MACRO fakeram_64x256_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.168 0.120 90.804 0.168 ; - RECT 0.168 0.504 90.804 0.552 ; - RECT 0.168 0.888 90.804 0.936 ; - RECT 0.168 1.272 90.804 1.320 ; - RECT 0.168 1.656 90.804 1.704 ; - RECT 0.168 2.040 90.804 2.088 ; - RECT 0.168 2.424 90.804 2.472 ; - RECT 0.168 2.808 90.804 2.856 ; - RECT 0.168 3.192 90.804 3.240 ; - RECT 0.168 3.576 90.804 3.624 ; - RECT 0.168 3.960 90.804 4.008 ; - RECT 0.168 4.344 90.804 4.392 ; - RECT 0.168 4.728 90.804 4.776 ; - RECT 0.168 5.112 90.804 5.160 ; - RECT 0.168 5.496 90.804 5.544 ; - RECT 0.168 5.880 90.804 5.928 ; - RECT 0.168 6.264 90.804 6.312 ; - RECT 0.168 6.648 90.804 6.696 ; - RECT 0.168 7.032 90.804 7.080 ; - RECT 0.168 7.416 90.804 7.464 ; - RECT 0.168 7.800 90.804 7.848 ; - RECT 0.168 8.184 90.804 8.232 ; - RECT 0.168 8.568 90.804 8.616 ; - RECT 0.168 8.952 90.804 9.000 ; - RECT 0.168 9.336 90.804 9.384 ; - RECT 0.168 9.720 90.804 9.768 ; - RECT 0.168 10.104 90.804 10.152 ; - RECT 0.168 10.488 90.804 10.536 ; - RECT 0.168 10.872 90.804 10.920 ; - RECT 0.168 11.256 90.804 11.304 ; - RECT 0.168 11.640 90.804 11.688 ; - RECT 0.168 12.024 90.804 12.072 ; - RECT 0.168 12.408 90.804 12.456 ; - RECT 0.168 12.792 90.804 12.840 ; - RECT 0.168 13.176 90.804 13.224 ; - RECT 0.168 13.560 90.804 13.608 ; - RECT 0.168 13.944 90.804 13.992 ; - RECT 0.168 14.328 90.804 14.376 ; - RECT 0.168 14.712 90.804 14.760 ; - RECT 0.168 15.096 90.804 15.144 ; - RECT 0.168 15.480 90.804 15.528 ; - RECT 0.168 15.864 90.804 15.912 ; - RECT 0.168 16.248 90.804 16.296 ; - RECT 0.168 16.632 90.804 16.680 ; - RECT 0.168 17.016 90.804 17.064 ; - RECT 0.168 17.400 90.804 17.448 ; - RECT 0.168 17.784 90.804 17.832 ; - RECT 0.168 18.168 90.804 18.216 ; - RECT 0.168 18.552 90.804 18.600 ; - RECT 0.168 18.936 90.804 18.984 ; - RECT 0.168 19.320 90.804 19.368 ; - RECT 0.168 19.704 90.804 19.752 ; - RECT 0.168 20.088 90.804 20.136 ; - RECT 0.168 20.472 90.804 20.520 ; - RECT 0.168 20.856 90.804 20.904 ; - RECT 0.168 21.240 90.804 21.288 ; - RECT 0.168 21.624 90.804 21.672 ; - RECT 0.168 22.008 90.804 22.056 ; - RECT 0.168 22.392 90.804 22.440 ; - RECT 0.168 22.776 90.804 22.824 ; - RECT 0.168 23.160 90.804 23.208 ; - RECT 0.168 23.544 90.804 23.592 ; - RECT 0.168 23.928 90.804 23.976 ; - RECT 0.168 24.312 90.804 24.360 ; - RECT 0.168 24.696 90.804 24.744 ; - RECT 0.168 25.080 90.804 25.128 ; - RECT 0.168 25.464 90.804 25.512 ; - RECT 0.168 25.848 90.804 25.896 ; - RECT 0.168 26.232 90.804 26.280 ; - RECT 0.168 26.616 90.804 26.664 ; - RECT 0.168 27.000 90.804 27.048 ; - RECT 0.168 27.384 90.804 27.432 ; - RECT 0.168 27.768 90.804 27.816 ; - RECT 0.168 28.152 90.804 28.200 ; - RECT 0.168 28.536 90.804 28.584 ; - RECT 0.168 28.920 90.804 28.968 ; - RECT 0.168 29.304 90.804 29.352 ; - RECT 0.168 29.688 90.804 29.736 ; - RECT 0.168 30.072 90.804 30.120 ; - RECT 0.168 30.456 90.804 30.504 ; - RECT 0.168 30.840 90.804 30.888 ; - RECT 0.168 31.224 90.804 31.272 ; - RECT 0.168 31.608 90.804 31.656 ; - RECT 0.168 31.992 90.804 32.040 ; - RECT 0.168 32.376 90.804 32.424 ; - RECT 0.168 32.760 90.804 32.808 ; - RECT 0.168 33.144 90.804 33.192 ; - RECT 0.168 33.528 90.804 33.576 ; - RECT 0.168 33.912 90.804 33.960 ; - RECT 0.168 34.296 90.804 34.344 ; - RECT 0.168 34.680 90.804 34.728 ; - RECT 0.168 35.064 90.804 35.112 ; - RECT 0.168 35.448 90.804 35.496 ; - RECT 0.168 35.832 90.804 35.880 ; - RECT 0.168 36.216 90.804 36.264 ; - RECT 0.168 36.600 90.804 36.648 ; - RECT 0.168 36.984 90.804 37.032 ; - RECT 0.168 37.368 90.804 37.416 ; - RECT 0.168 37.752 90.804 37.800 ; - RECT 0.168 38.136 90.804 38.184 ; - RECT 0.168 38.520 90.804 38.568 ; - RECT 0.168 38.904 90.804 38.952 ; - RECT 0.168 39.288 90.804 39.336 ; - RECT 0.168 39.672 90.804 39.720 ; - RECT 0.168 40.056 90.804 40.104 ; - RECT 0.168 40.440 90.804 40.488 ; - RECT 0.168 40.824 90.804 40.872 ; - RECT 0.168 41.208 90.804 41.256 ; - RECT 0.168 41.592 90.804 41.640 ; - RECT 0.168 41.976 90.804 42.024 ; - RECT 0.168 42.360 90.804 42.408 ; - RECT 0.168 42.744 90.804 42.792 ; - RECT 0.168 43.128 90.804 43.176 ; - RECT 0.168 43.512 90.804 43.560 ; - RECT 0.168 43.896 90.804 43.944 ; - RECT 0.168 44.280 90.804 44.328 ; - RECT 0.168 44.664 90.804 44.712 ; - RECT 0.168 45.048 90.804 45.096 ; - RECT 0.168 45.432 90.804 45.480 ; - RECT 0.168 45.816 90.804 45.864 ; - RECT 0.168 46.200 90.804 46.248 ; - RECT 0.168 46.584 90.804 46.632 ; - RECT 0.168 46.968 90.804 47.016 ; - RECT 0.168 47.352 90.804 47.400 ; - RECT 0.168 47.736 90.804 47.784 ; - RECT 0.168 48.120 90.804 48.168 ; - RECT 0.168 48.504 90.804 48.552 ; - RECT 0.168 48.888 90.804 48.936 ; - RECT 0.168 49.272 90.804 49.320 ; - RECT 0.168 49.656 90.804 49.704 ; - RECT 0.168 50.040 90.804 50.088 ; - RECT 0.168 50.424 90.804 50.472 ; - RECT 0.168 50.808 90.804 50.856 ; - RECT 0.168 51.192 90.804 51.240 ; - RECT 0.168 51.576 90.804 51.624 ; - RECT 0.168 51.960 90.804 52.008 ; - RECT 0.168 52.344 90.804 52.392 ; - RECT 0.168 52.728 90.804 52.776 ; - RECT 0.168 53.112 90.804 53.160 ; - RECT 0.168 53.496 90.804 53.544 ; - RECT 0.168 53.880 90.804 53.928 ; - RECT 0.168 54.264 90.804 54.312 ; - RECT 0.168 54.648 90.804 54.696 ; - RECT 0.168 55.032 90.804 55.080 ; - RECT 0.168 55.416 90.804 55.464 ; - RECT 0.168 55.800 90.804 55.848 ; - RECT 0.168 56.184 90.804 56.232 ; - RECT 0.168 56.568 90.804 56.616 ; + RECT 0.168 0.312 90.804 0.360 ; + RECT 0.168 0.696 90.804 0.744 ; + RECT 0.168 1.080 90.804 1.128 ; + RECT 0.168 1.464 90.804 1.512 ; + RECT 0.168 1.848 90.804 1.896 ; + RECT 0.168 2.232 90.804 2.280 ; + RECT 0.168 2.616 90.804 2.664 ; + RECT 0.168 3.000 90.804 3.048 ; + RECT 0.168 3.384 90.804 3.432 ; + RECT 0.168 3.768 90.804 3.816 ; + RECT 0.168 4.152 90.804 4.200 ; + RECT 0.168 4.536 90.804 4.584 ; + RECT 0.168 4.920 90.804 4.968 ; + RECT 0.168 5.304 90.804 5.352 ; + RECT 0.168 5.688 90.804 5.736 ; + RECT 0.168 6.072 90.804 6.120 ; + RECT 0.168 6.456 90.804 6.504 ; + RECT 0.168 6.840 90.804 6.888 ; + RECT 0.168 7.224 90.804 7.272 ; + RECT 0.168 7.608 90.804 7.656 ; + RECT 0.168 7.992 90.804 8.040 ; + RECT 0.168 8.376 90.804 8.424 ; + RECT 0.168 8.760 90.804 8.808 ; + RECT 0.168 9.144 90.804 9.192 ; + RECT 0.168 9.528 90.804 9.576 ; + RECT 0.168 9.912 90.804 9.960 ; + RECT 0.168 10.296 90.804 10.344 ; + RECT 0.168 10.680 90.804 10.728 ; + RECT 0.168 11.064 90.804 11.112 ; + RECT 0.168 11.448 90.804 11.496 ; + RECT 0.168 11.832 90.804 11.880 ; + RECT 0.168 12.216 90.804 12.264 ; + RECT 0.168 12.600 90.804 12.648 ; + RECT 0.168 12.984 90.804 13.032 ; + RECT 0.168 13.368 90.804 13.416 ; + RECT 0.168 13.752 90.804 13.800 ; + RECT 0.168 14.136 90.804 14.184 ; + RECT 0.168 14.520 90.804 14.568 ; + RECT 0.168 14.904 90.804 14.952 ; + RECT 0.168 15.288 90.804 15.336 ; + RECT 0.168 15.672 90.804 15.720 ; + RECT 0.168 16.056 90.804 16.104 ; + RECT 0.168 16.440 90.804 16.488 ; + RECT 0.168 16.824 90.804 16.872 ; + RECT 0.168 17.208 90.804 17.256 ; + RECT 0.168 17.592 90.804 17.640 ; + RECT 0.168 17.976 90.804 18.024 ; + RECT 0.168 18.360 90.804 18.408 ; + RECT 0.168 18.744 90.804 18.792 ; + RECT 0.168 19.128 90.804 19.176 ; + RECT 0.168 19.512 90.804 19.560 ; + RECT 0.168 19.896 90.804 19.944 ; + RECT 0.168 20.280 90.804 20.328 ; + RECT 0.168 20.664 90.804 20.712 ; + RECT 0.168 21.048 90.804 21.096 ; + RECT 0.168 21.432 90.804 21.480 ; + RECT 0.168 21.816 90.804 21.864 ; + RECT 0.168 22.200 90.804 22.248 ; + RECT 0.168 22.584 90.804 22.632 ; + RECT 0.168 22.968 90.804 23.016 ; + RECT 0.168 23.352 90.804 23.400 ; + RECT 0.168 23.736 90.804 23.784 ; + RECT 0.168 24.120 90.804 24.168 ; + RECT 0.168 24.504 90.804 24.552 ; + RECT 0.168 24.888 90.804 24.936 ; + RECT 0.168 25.272 90.804 25.320 ; + RECT 0.168 25.656 90.804 25.704 ; + RECT 0.168 26.040 90.804 26.088 ; + RECT 0.168 26.424 90.804 26.472 ; + RECT 0.168 26.808 90.804 26.856 ; + RECT 0.168 27.192 90.804 27.240 ; + RECT 0.168 27.576 90.804 27.624 ; + RECT 0.168 27.960 90.804 28.008 ; + RECT 0.168 28.344 90.804 28.392 ; + RECT 0.168 28.728 90.804 28.776 ; + RECT 0.168 29.112 90.804 29.160 ; + RECT 0.168 29.496 90.804 29.544 ; + RECT 0.168 29.880 90.804 29.928 ; + RECT 0.168 30.264 90.804 30.312 ; + RECT 0.168 30.648 90.804 30.696 ; + RECT 0.168 31.032 90.804 31.080 ; + RECT 0.168 31.416 90.804 31.464 ; + RECT 0.168 31.800 90.804 31.848 ; + RECT 0.168 32.184 90.804 32.232 ; + RECT 0.168 32.568 90.804 32.616 ; + RECT 0.168 32.952 90.804 33.000 ; + RECT 0.168 33.336 90.804 33.384 ; + RECT 0.168 33.720 90.804 33.768 ; + RECT 0.168 34.104 90.804 34.152 ; + RECT 0.168 34.488 90.804 34.536 ; + RECT 0.168 34.872 90.804 34.920 ; + RECT 0.168 35.256 90.804 35.304 ; + RECT 0.168 35.640 90.804 35.688 ; + RECT 0.168 36.024 90.804 36.072 ; + RECT 0.168 36.408 90.804 36.456 ; + RECT 0.168 36.792 90.804 36.840 ; + RECT 0.168 37.176 90.804 37.224 ; + RECT 0.168 37.560 90.804 37.608 ; + RECT 0.168 37.944 90.804 37.992 ; + RECT 0.168 38.328 90.804 38.376 ; + RECT 0.168 38.712 90.804 38.760 ; + RECT 0.168 39.096 90.804 39.144 ; + RECT 0.168 39.480 90.804 39.528 ; + RECT 0.168 39.864 90.804 39.912 ; + RECT 0.168 40.248 90.804 40.296 ; + RECT 0.168 40.632 90.804 40.680 ; + RECT 0.168 41.016 90.804 41.064 ; + RECT 0.168 41.400 90.804 41.448 ; + RECT 0.168 41.784 90.804 41.832 ; + RECT 0.168 42.168 90.804 42.216 ; + RECT 0.168 42.552 90.804 42.600 ; + RECT 0.168 42.936 90.804 42.984 ; + RECT 0.168 43.320 90.804 43.368 ; + RECT 0.168 43.704 90.804 43.752 ; + RECT 0.168 44.088 90.804 44.136 ; + RECT 0.168 44.472 90.804 44.520 ; + RECT 0.168 44.856 90.804 44.904 ; + RECT 0.168 45.240 90.804 45.288 ; + RECT 0.168 45.624 90.804 45.672 ; + RECT 0.168 46.008 90.804 46.056 ; + RECT 0.168 46.392 90.804 46.440 ; + RECT 0.168 46.776 90.804 46.824 ; + RECT 0.168 47.160 90.804 47.208 ; + RECT 0.168 47.544 90.804 47.592 ; + RECT 0.168 47.928 90.804 47.976 ; + RECT 0.168 48.312 90.804 48.360 ; + RECT 0.168 48.696 90.804 48.744 ; + RECT 0.168 49.080 90.804 49.128 ; + RECT 0.168 49.464 90.804 49.512 ; + RECT 0.168 49.848 90.804 49.896 ; + RECT 0.168 50.232 90.804 50.280 ; + RECT 0.168 50.616 90.804 50.664 ; + RECT 0.168 51.000 90.804 51.048 ; + RECT 0.168 51.384 90.804 51.432 ; + RECT 0.168 51.768 90.804 51.816 ; + RECT 0.168 52.152 90.804 52.200 ; + RECT 0.168 52.536 90.804 52.584 ; + RECT 0.168 52.920 90.804 52.968 ; + RECT 0.168 53.304 90.804 53.352 ; + RECT 0.168 53.688 90.804 53.736 ; + RECT 0.168 54.072 90.804 54.120 ; + RECT 0.168 54.456 90.804 54.504 ; + RECT 0.168 54.840 90.804 54.888 ; + RECT 0.168 55.224 90.804 55.272 ; + RECT 0.168 55.608 90.804 55.656 ; + RECT 0.168 55.992 90.804 56.040 ; + RECT 0.168 56.376 90.804 56.424 ; + RECT 0.168 56.760 90.804 56.808 ; END END VDD OBS diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_65x160_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_65x160_1r1w.lef index c68328e3..82361a20 100644 --- a/designs/gt2n/NVDLA/sram/lef/fakeram_65x160_1r1w.lef +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_65x160_1r1w.lef @@ -1561,191 +1561,191 @@ MACRO fakeram_65x160_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.168 0.120 46.032 0.168 ; - RECT 0.168 0.504 46.032 0.552 ; - RECT 0.168 0.888 46.032 0.936 ; - RECT 0.168 1.272 46.032 1.320 ; - RECT 0.168 1.656 46.032 1.704 ; - RECT 0.168 2.040 46.032 2.088 ; - RECT 0.168 2.424 46.032 2.472 ; - RECT 0.168 2.808 46.032 2.856 ; - RECT 0.168 3.192 46.032 3.240 ; - RECT 0.168 3.576 46.032 3.624 ; - RECT 0.168 3.960 46.032 4.008 ; - RECT 0.168 4.344 46.032 4.392 ; - RECT 0.168 4.728 46.032 4.776 ; - RECT 0.168 5.112 46.032 5.160 ; - RECT 0.168 5.496 46.032 5.544 ; - RECT 0.168 5.880 46.032 5.928 ; - RECT 0.168 6.264 46.032 6.312 ; - RECT 0.168 6.648 46.032 6.696 ; - RECT 0.168 7.032 46.032 7.080 ; - RECT 0.168 7.416 46.032 7.464 ; - RECT 0.168 7.800 46.032 7.848 ; - RECT 0.168 8.184 46.032 8.232 ; - RECT 0.168 8.568 46.032 8.616 ; - RECT 0.168 8.952 46.032 9.000 ; - RECT 0.168 9.336 46.032 9.384 ; - RECT 0.168 9.720 46.032 9.768 ; - RECT 0.168 10.104 46.032 10.152 ; - RECT 0.168 10.488 46.032 10.536 ; - RECT 0.168 10.872 46.032 10.920 ; - RECT 0.168 11.256 46.032 11.304 ; - RECT 0.168 11.640 46.032 11.688 ; - RECT 0.168 12.024 46.032 12.072 ; - RECT 0.168 12.408 46.032 12.456 ; - RECT 0.168 12.792 46.032 12.840 ; - RECT 0.168 13.176 46.032 13.224 ; - RECT 0.168 13.560 46.032 13.608 ; - RECT 0.168 13.944 46.032 13.992 ; - RECT 0.168 14.328 46.032 14.376 ; - RECT 0.168 14.712 46.032 14.760 ; - RECT 0.168 15.096 46.032 15.144 ; - RECT 0.168 15.480 46.032 15.528 ; - RECT 0.168 15.864 46.032 15.912 ; - RECT 0.168 16.248 46.032 16.296 ; - RECT 0.168 16.632 46.032 16.680 ; - RECT 0.168 17.016 46.032 17.064 ; - RECT 0.168 17.400 46.032 17.448 ; - RECT 0.168 17.784 46.032 17.832 ; - RECT 0.168 18.168 46.032 18.216 ; - RECT 0.168 18.552 46.032 18.600 ; - RECT 0.168 18.936 46.032 18.984 ; - RECT 0.168 19.320 46.032 19.368 ; - RECT 0.168 19.704 46.032 19.752 ; - RECT 0.168 20.088 46.032 20.136 ; - RECT 0.168 20.472 46.032 20.520 ; - RECT 0.168 20.856 46.032 20.904 ; - RECT 0.168 21.240 46.032 21.288 ; - RECT 0.168 21.624 46.032 21.672 ; - RECT 0.168 22.008 46.032 22.056 ; - RECT 0.168 22.392 46.032 22.440 ; - RECT 0.168 22.776 46.032 22.824 ; - RECT 0.168 23.160 46.032 23.208 ; - RECT 0.168 23.544 46.032 23.592 ; - RECT 0.168 23.928 46.032 23.976 ; - RECT 0.168 24.312 46.032 24.360 ; - RECT 0.168 24.696 46.032 24.744 ; - RECT 0.168 25.080 46.032 25.128 ; - RECT 0.168 25.464 46.032 25.512 ; - RECT 0.168 25.848 46.032 25.896 ; - RECT 0.168 26.232 46.032 26.280 ; - RECT 0.168 26.616 46.032 26.664 ; - RECT 0.168 27.000 46.032 27.048 ; - RECT 0.168 27.384 46.032 27.432 ; - RECT 0.168 27.768 46.032 27.816 ; - RECT 0.168 28.152 46.032 28.200 ; - RECT 0.168 28.536 46.032 28.584 ; - RECT 0.168 28.920 46.032 28.968 ; - RECT 0.168 29.304 46.032 29.352 ; - RECT 0.168 29.688 46.032 29.736 ; - RECT 0.168 30.072 46.032 30.120 ; - RECT 0.168 30.456 46.032 30.504 ; - RECT 0.168 30.840 46.032 30.888 ; - RECT 0.168 31.224 46.032 31.272 ; - RECT 0.168 31.608 46.032 31.656 ; - RECT 0.168 31.992 46.032 32.040 ; - RECT 0.168 32.376 46.032 32.424 ; - RECT 0.168 32.760 46.032 32.808 ; - RECT 0.168 33.144 46.032 33.192 ; - RECT 0.168 33.528 46.032 33.576 ; - RECT 0.168 33.912 46.032 33.960 ; - RECT 0.168 34.296 46.032 34.344 ; - RECT 0.168 34.680 46.032 34.728 ; - RECT 0.168 35.064 46.032 35.112 ; - RECT 0.168 35.448 46.032 35.496 ; - RECT 0.168 35.832 46.032 35.880 ; - RECT 0.168 36.216 46.032 36.264 ; - RECT 0.168 36.600 46.032 36.648 ; - RECT 0.168 36.984 46.032 37.032 ; - RECT 0.168 37.368 46.032 37.416 ; - RECT 0.168 37.752 46.032 37.800 ; - RECT 0.168 38.136 46.032 38.184 ; - RECT 0.168 38.520 46.032 38.568 ; - RECT 0.168 38.904 46.032 38.952 ; - RECT 0.168 39.288 46.032 39.336 ; - RECT 0.168 39.672 46.032 39.720 ; - RECT 0.168 40.056 46.032 40.104 ; - RECT 0.168 40.440 46.032 40.488 ; - RECT 0.168 40.824 46.032 40.872 ; - RECT 0.168 41.208 46.032 41.256 ; - RECT 0.168 41.592 46.032 41.640 ; - RECT 0.168 41.976 46.032 42.024 ; - RECT 0.168 42.360 46.032 42.408 ; - RECT 0.168 42.744 46.032 42.792 ; - RECT 0.168 43.128 46.032 43.176 ; - RECT 0.168 43.512 46.032 43.560 ; - RECT 0.168 43.896 46.032 43.944 ; - RECT 0.168 44.280 46.032 44.328 ; - RECT 0.168 44.664 46.032 44.712 ; - RECT 0.168 45.048 46.032 45.096 ; - RECT 0.168 45.432 46.032 45.480 ; - RECT 0.168 45.816 46.032 45.864 ; - RECT 0.168 46.200 46.032 46.248 ; - RECT 0.168 46.584 46.032 46.632 ; - RECT 0.168 46.968 46.032 47.016 ; - RECT 0.168 47.352 46.032 47.400 ; - RECT 0.168 47.736 46.032 47.784 ; - RECT 0.168 48.120 46.032 48.168 ; - RECT 0.168 48.504 46.032 48.552 ; - RECT 0.168 48.888 46.032 48.936 ; - RECT 0.168 49.272 46.032 49.320 ; - RECT 0.168 49.656 46.032 49.704 ; - RECT 0.168 50.040 46.032 50.088 ; - RECT 0.168 50.424 46.032 50.472 ; - RECT 0.168 50.808 46.032 50.856 ; - RECT 0.168 51.192 46.032 51.240 ; - RECT 0.168 51.576 46.032 51.624 ; - RECT 0.168 51.960 46.032 52.008 ; - RECT 0.168 52.344 46.032 52.392 ; - RECT 0.168 52.728 46.032 52.776 ; - RECT 0.168 53.112 46.032 53.160 ; - RECT 0.168 53.496 46.032 53.544 ; - RECT 0.168 53.880 46.032 53.928 ; - RECT 0.168 54.264 46.032 54.312 ; - RECT 0.168 54.648 46.032 54.696 ; - RECT 0.168 55.032 46.032 55.080 ; - RECT 0.168 55.416 46.032 55.464 ; - RECT 0.168 55.800 46.032 55.848 ; - RECT 0.168 56.184 46.032 56.232 ; - RECT 0.168 56.568 46.032 56.616 ; - RECT 0.168 56.952 46.032 57.000 ; - RECT 0.168 57.336 46.032 57.384 ; - RECT 0.168 57.720 46.032 57.768 ; - RECT 0.168 58.104 46.032 58.152 ; - RECT 0.168 58.488 46.032 58.536 ; - RECT 0.168 58.872 46.032 58.920 ; - RECT 0.168 59.256 46.032 59.304 ; - RECT 0.168 59.640 46.032 59.688 ; - RECT 0.168 60.024 46.032 60.072 ; - RECT 0.168 60.408 46.032 60.456 ; - RECT 0.168 60.792 46.032 60.840 ; - RECT 0.168 61.176 46.032 61.224 ; - RECT 0.168 61.560 46.032 61.608 ; - RECT 0.168 61.944 46.032 61.992 ; - RECT 0.168 62.328 46.032 62.376 ; - RECT 0.168 62.712 46.032 62.760 ; - RECT 0.168 63.096 46.032 63.144 ; - RECT 0.168 63.480 46.032 63.528 ; - RECT 0.168 63.864 46.032 63.912 ; - RECT 0.168 64.248 46.032 64.296 ; - RECT 0.168 64.632 46.032 64.680 ; - RECT 0.168 65.016 46.032 65.064 ; - RECT 0.168 65.400 46.032 65.448 ; - RECT 0.168 65.784 46.032 65.832 ; - RECT 0.168 66.168 46.032 66.216 ; - RECT 0.168 66.552 46.032 66.600 ; - RECT 0.168 66.936 46.032 66.984 ; - RECT 0.168 67.320 46.032 67.368 ; - RECT 0.168 67.704 46.032 67.752 ; - RECT 0.168 68.088 46.032 68.136 ; - RECT 0.168 68.472 46.032 68.520 ; - RECT 0.168 68.856 46.032 68.904 ; - RECT 0.168 69.240 46.032 69.288 ; - RECT 0.168 69.624 46.032 69.672 ; - RECT 0.168 70.008 46.032 70.056 ; - RECT 0.168 70.392 46.032 70.440 ; - RECT 0.168 70.776 46.032 70.824 ; + RECT 0.168 0.312 46.032 0.360 ; + RECT 0.168 0.696 46.032 0.744 ; + RECT 0.168 1.080 46.032 1.128 ; + RECT 0.168 1.464 46.032 1.512 ; + RECT 0.168 1.848 46.032 1.896 ; + RECT 0.168 2.232 46.032 2.280 ; + RECT 0.168 2.616 46.032 2.664 ; + RECT 0.168 3.000 46.032 3.048 ; + RECT 0.168 3.384 46.032 3.432 ; + RECT 0.168 3.768 46.032 3.816 ; + RECT 0.168 4.152 46.032 4.200 ; + RECT 0.168 4.536 46.032 4.584 ; + RECT 0.168 4.920 46.032 4.968 ; + RECT 0.168 5.304 46.032 5.352 ; + RECT 0.168 5.688 46.032 5.736 ; + RECT 0.168 6.072 46.032 6.120 ; + RECT 0.168 6.456 46.032 6.504 ; + RECT 0.168 6.840 46.032 6.888 ; + RECT 0.168 7.224 46.032 7.272 ; + RECT 0.168 7.608 46.032 7.656 ; + RECT 0.168 7.992 46.032 8.040 ; + RECT 0.168 8.376 46.032 8.424 ; + RECT 0.168 8.760 46.032 8.808 ; + RECT 0.168 9.144 46.032 9.192 ; + RECT 0.168 9.528 46.032 9.576 ; + RECT 0.168 9.912 46.032 9.960 ; + RECT 0.168 10.296 46.032 10.344 ; + RECT 0.168 10.680 46.032 10.728 ; + RECT 0.168 11.064 46.032 11.112 ; + RECT 0.168 11.448 46.032 11.496 ; + RECT 0.168 11.832 46.032 11.880 ; + RECT 0.168 12.216 46.032 12.264 ; + RECT 0.168 12.600 46.032 12.648 ; + RECT 0.168 12.984 46.032 13.032 ; + RECT 0.168 13.368 46.032 13.416 ; + RECT 0.168 13.752 46.032 13.800 ; + RECT 0.168 14.136 46.032 14.184 ; + RECT 0.168 14.520 46.032 14.568 ; + RECT 0.168 14.904 46.032 14.952 ; + RECT 0.168 15.288 46.032 15.336 ; + RECT 0.168 15.672 46.032 15.720 ; + RECT 0.168 16.056 46.032 16.104 ; + RECT 0.168 16.440 46.032 16.488 ; + RECT 0.168 16.824 46.032 16.872 ; + RECT 0.168 17.208 46.032 17.256 ; + RECT 0.168 17.592 46.032 17.640 ; + RECT 0.168 17.976 46.032 18.024 ; + RECT 0.168 18.360 46.032 18.408 ; + RECT 0.168 18.744 46.032 18.792 ; + RECT 0.168 19.128 46.032 19.176 ; + RECT 0.168 19.512 46.032 19.560 ; + RECT 0.168 19.896 46.032 19.944 ; + RECT 0.168 20.280 46.032 20.328 ; + RECT 0.168 20.664 46.032 20.712 ; + RECT 0.168 21.048 46.032 21.096 ; + RECT 0.168 21.432 46.032 21.480 ; + RECT 0.168 21.816 46.032 21.864 ; + RECT 0.168 22.200 46.032 22.248 ; + RECT 0.168 22.584 46.032 22.632 ; + RECT 0.168 22.968 46.032 23.016 ; + RECT 0.168 23.352 46.032 23.400 ; + RECT 0.168 23.736 46.032 23.784 ; + RECT 0.168 24.120 46.032 24.168 ; + RECT 0.168 24.504 46.032 24.552 ; + RECT 0.168 24.888 46.032 24.936 ; + RECT 0.168 25.272 46.032 25.320 ; + RECT 0.168 25.656 46.032 25.704 ; + RECT 0.168 26.040 46.032 26.088 ; + RECT 0.168 26.424 46.032 26.472 ; + RECT 0.168 26.808 46.032 26.856 ; + RECT 0.168 27.192 46.032 27.240 ; + RECT 0.168 27.576 46.032 27.624 ; + RECT 0.168 27.960 46.032 28.008 ; + RECT 0.168 28.344 46.032 28.392 ; + RECT 0.168 28.728 46.032 28.776 ; + RECT 0.168 29.112 46.032 29.160 ; + RECT 0.168 29.496 46.032 29.544 ; + RECT 0.168 29.880 46.032 29.928 ; + RECT 0.168 30.264 46.032 30.312 ; + RECT 0.168 30.648 46.032 30.696 ; + RECT 0.168 31.032 46.032 31.080 ; + RECT 0.168 31.416 46.032 31.464 ; + RECT 0.168 31.800 46.032 31.848 ; + RECT 0.168 32.184 46.032 32.232 ; + RECT 0.168 32.568 46.032 32.616 ; + RECT 0.168 32.952 46.032 33.000 ; + RECT 0.168 33.336 46.032 33.384 ; + RECT 0.168 33.720 46.032 33.768 ; + RECT 0.168 34.104 46.032 34.152 ; + RECT 0.168 34.488 46.032 34.536 ; + RECT 0.168 34.872 46.032 34.920 ; + RECT 0.168 35.256 46.032 35.304 ; + RECT 0.168 35.640 46.032 35.688 ; + RECT 0.168 36.024 46.032 36.072 ; + RECT 0.168 36.408 46.032 36.456 ; + RECT 0.168 36.792 46.032 36.840 ; + RECT 0.168 37.176 46.032 37.224 ; + RECT 0.168 37.560 46.032 37.608 ; + RECT 0.168 37.944 46.032 37.992 ; + RECT 0.168 38.328 46.032 38.376 ; + RECT 0.168 38.712 46.032 38.760 ; + RECT 0.168 39.096 46.032 39.144 ; + RECT 0.168 39.480 46.032 39.528 ; + RECT 0.168 39.864 46.032 39.912 ; + RECT 0.168 40.248 46.032 40.296 ; + RECT 0.168 40.632 46.032 40.680 ; + RECT 0.168 41.016 46.032 41.064 ; + RECT 0.168 41.400 46.032 41.448 ; + RECT 0.168 41.784 46.032 41.832 ; + RECT 0.168 42.168 46.032 42.216 ; + RECT 0.168 42.552 46.032 42.600 ; + RECT 0.168 42.936 46.032 42.984 ; + RECT 0.168 43.320 46.032 43.368 ; + RECT 0.168 43.704 46.032 43.752 ; + RECT 0.168 44.088 46.032 44.136 ; + RECT 0.168 44.472 46.032 44.520 ; + RECT 0.168 44.856 46.032 44.904 ; + RECT 0.168 45.240 46.032 45.288 ; + RECT 0.168 45.624 46.032 45.672 ; + RECT 0.168 46.008 46.032 46.056 ; + RECT 0.168 46.392 46.032 46.440 ; + RECT 0.168 46.776 46.032 46.824 ; + RECT 0.168 47.160 46.032 47.208 ; + RECT 0.168 47.544 46.032 47.592 ; + RECT 0.168 47.928 46.032 47.976 ; + RECT 0.168 48.312 46.032 48.360 ; + RECT 0.168 48.696 46.032 48.744 ; + RECT 0.168 49.080 46.032 49.128 ; + RECT 0.168 49.464 46.032 49.512 ; + RECT 0.168 49.848 46.032 49.896 ; + RECT 0.168 50.232 46.032 50.280 ; + RECT 0.168 50.616 46.032 50.664 ; + RECT 0.168 51.000 46.032 51.048 ; + RECT 0.168 51.384 46.032 51.432 ; + RECT 0.168 51.768 46.032 51.816 ; + RECT 0.168 52.152 46.032 52.200 ; + RECT 0.168 52.536 46.032 52.584 ; + RECT 0.168 52.920 46.032 52.968 ; + RECT 0.168 53.304 46.032 53.352 ; + RECT 0.168 53.688 46.032 53.736 ; + RECT 0.168 54.072 46.032 54.120 ; + RECT 0.168 54.456 46.032 54.504 ; + RECT 0.168 54.840 46.032 54.888 ; + RECT 0.168 55.224 46.032 55.272 ; + RECT 0.168 55.608 46.032 55.656 ; + RECT 0.168 55.992 46.032 56.040 ; + RECT 0.168 56.376 46.032 56.424 ; + RECT 0.168 56.760 46.032 56.808 ; + RECT 0.168 57.144 46.032 57.192 ; + RECT 0.168 57.528 46.032 57.576 ; + RECT 0.168 57.912 46.032 57.960 ; + RECT 0.168 58.296 46.032 58.344 ; + RECT 0.168 58.680 46.032 58.728 ; + RECT 0.168 59.064 46.032 59.112 ; + RECT 0.168 59.448 46.032 59.496 ; + RECT 0.168 59.832 46.032 59.880 ; + RECT 0.168 60.216 46.032 60.264 ; + RECT 0.168 60.600 46.032 60.648 ; + RECT 0.168 60.984 46.032 61.032 ; + RECT 0.168 61.368 46.032 61.416 ; + RECT 0.168 61.752 46.032 61.800 ; + RECT 0.168 62.136 46.032 62.184 ; + RECT 0.168 62.520 46.032 62.568 ; + RECT 0.168 62.904 46.032 62.952 ; + RECT 0.168 63.288 46.032 63.336 ; + RECT 0.168 63.672 46.032 63.720 ; + RECT 0.168 64.056 46.032 64.104 ; + RECT 0.168 64.440 46.032 64.488 ; + RECT 0.168 64.824 46.032 64.872 ; + RECT 0.168 65.208 46.032 65.256 ; + RECT 0.168 65.592 46.032 65.640 ; + RECT 0.168 65.976 46.032 66.024 ; + RECT 0.168 66.360 46.032 66.408 ; + RECT 0.168 66.744 46.032 66.792 ; + RECT 0.168 67.128 46.032 67.176 ; + RECT 0.168 67.512 46.032 67.560 ; + RECT 0.168 67.896 46.032 67.944 ; + RECT 0.168 68.280 46.032 68.328 ; + RECT 0.168 68.664 46.032 68.712 ; + RECT 0.168 69.048 46.032 69.096 ; + RECT 0.168 69.432 46.032 69.480 ; + RECT 0.168 69.816 46.032 69.864 ; + RECT 0.168 70.200 46.032 70.248 ; + RECT 0.168 70.584 46.032 70.632 ; + RECT 0.168 70.968 46.032 71.016 ; END END VDD OBS diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_66x64_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_66x64_1r1w.lef index 422e5adf..c278d351 100644 --- a/designs/gt2n/NVDLA/sram/lef/fakeram_66x64_1r1w.lef +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_66x64_1r1w.lef @@ -1432,80 +1432,80 @@ MACRO fakeram_66x64_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.168 0.120 46.746 0.168 ; - RECT 0.168 0.504 46.746 0.552 ; - RECT 0.168 0.888 46.746 0.936 ; - RECT 0.168 1.272 46.746 1.320 ; - RECT 0.168 1.656 46.746 1.704 ; - RECT 0.168 2.040 46.746 2.088 ; - RECT 0.168 2.424 46.746 2.472 ; - RECT 0.168 2.808 46.746 2.856 ; - RECT 0.168 3.192 46.746 3.240 ; - RECT 0.168 3.576 46.746 3.624 ; - RECT 0.168 3.960 46.746 4.008 ; - RECT 0.168 4.344 46.746 4.392 ; - RECT 0.168 4.728 46.746 4.776 ; - RECT 0.168 5.112 46.746 5.160 ; - RECT 0.168 5.496 46.746 5.544 ; - RECT 0.168 5.880 46.746 5.928 ; - RECT 0.168 6.264 46.746 6.312 ; - RECT 0.168 6.648 46.746 6.696 ; - RECT 0.168 7.032 46.746 7.080 ; - RECT 0.168 7.416 46.746 7.464 ; - RECT 0.168 7.800 46.746 7.848 ; - RECT 0.168 8.184 46.746 8.232 ; - RECT 0.168 8.568 46.746 8.616 ; - RECT 0.168 8.952 46.746 9.000 ; - RECT 0.168 9.336 46.746 9.384 ; - RECT 0.168 9.720 46.746 9.768 ; - RECT 0.168 10.104 46.746 10.152 ; - RECT 0.168 10.488 46.746 10.536 ; - RECT 0.168 10.872 46.746 10.920 ; - RECT 0.168 11.256 46.746 11.304 ; - RECT 0.168 11.640 46.746 11.688 ; - RECT 0.168 12.024 46.746 12.072 ; - RECT 0.168 12.408 46.746 12.456 ; - RECT 0.168 12.792 46.746 12.840 ; - RECT 0.168 13.176 46.746 13.224 ; - RECT 0.168 13.560 46.746 13.608 ; - RECT 0.168 13.944 46.746 13.992 ; - RECT 0.168 14.328 46.746 14.376 ; - RECT 0.168 14.712 46.746 14.760 ; - RECT 0.168 15.096 46.746 15.144 ; - RECT 0.168 15.480 46.746 15.528 ; - RECT 0.168 15.864 46.746 15.912 ; - RECT 0.168 16.248 46.746 16.296 ; - RECT 0.168 16.632 46.746 16.680 ; - RECT 0.168 17.016 46.746 17.064 ; - RECT 0.168 17.400 46.746 17.448 ; - RECT 0.168 17.784 46.746 17.832 ; - RECT 0.168 18.168 46.746 18.216 ; - RECT 0.168 18.552 46.746 18.600 ; - RECT 0.168 18.936 46.746 18.984 ; - RECT 0.168 19.320 46.746 19.368 ; - RECT 0.168 19.704 46.746 19.752 ; - RECT 0.168 20.088 46.746 20.136 ; - RECT 0.168 20.472 46.746 20.520 ; - RECT 0.168 20.856 46.746 20.904 ; - RECT 0.168 21.240 46.746 21.288 ; - RECT 0.168 21.624 46.746 21.672 ; - RECT 0.168 22.008 46.746 22.056 ; - RECT 0.168 22.392 46.746 22.440 ; - RECT 0.168 22.776 46.746 22.824 ; - RECT 0.168 23.160 46.746 23.208 ; - RECT 0.168 23.544 46.746 23.592 ; - RECT 0.168 23.928 46.746 23.976 ; - RECT 0.168 24.312 46.746 24.360 ; - RECT 0.168 24.696 46.746 24.744 ; - RECT 0.168 25.080 46.746 25.128 ; - RECT 0.168 25.464 46.746 25.512 ; - RECT 0.168 25.848 46.746 25.896 ; - RECT 0.168 26.232 46.746 26.280 ; - RECT 0.168 26.616 46.746 26.664 ; - RECT 0.168 27.000 46.746 27.048 ; - RECT 0.168 27.384 46.746 27.432 ; - RECT 0.168 27.768 46.746 27.816 ; - RECT 0.168 28.152 46.746 28.200 ; + RECT 0.168 0.312 46.746 0.360 ; + RECT 0.168 0.696 46.746 0.744 ; + RECT 0.168 1.080 46.746 1.128 ; + RECT 0.168 1.464 46.746 1.512 ; + RECT 0.168 1.848 46.746 1.896 ; + RECT 0.168 2.232 46.746 2.280 ; + RECT 0.168 2.616 46.746 2.664 ; + RECT 0.168 3.000 46.746 3.048 ; + RECT 0.168 3.384 46.746 3.432 ; + RECT 0.168 3.768 46.746 3.816 ; + RECT 0.168 4.152 46.746 4.200 ; + RECT 0.168 4.536 46.746 4.584 ; + RECT 0.168 4.920 46.746 4.968 ; + RECT 0.168 5.304 46.746 5.352 ; + RECT 0.168 5.688 46.746 5.736 ; + RECT 0.168 6.072 46.746 6.120 ; + RECT 0.168 6.456 46.746 6.504 ; + RECT 0.168 6.840 46.746 6.888 ; + RECT 0.168 7.224 46.746 7.272 ; + RECT 0.168 7.608 46.746 7.656 ; + RECT 0.168 7.992 46.746 8.040 ; + RECT 0.168 8.376 46.746 8.424 ; + RECT 0.168 8.760 46.746 8.808 ; + RECT 0.168 9.144 46.746 9.192 ; + RECT 0.168 9.528 46.746 9.576 ; + RECT 0.168 9.912 46.746 9.960 ; + RECT 0.168 10.296 46.746 10.344 ; + RECT 0.168 10.680 46.746 10.728 ; + RECT 0.168 11.064 46.746 11.112 ; + RECT 0.168 11.448 46.746 11.496 ; + RECT 0.168 11.832 46.746 11.880 ; + RECT 0.168 12.216 46.746 12.264 ; + RECT 0.168 12.600 46.746 12.648 ; + RECT 0.168 12.984 46.746 13.032 ; + RECT 0.168 13.368 46.746 13.416 ; + RECT 0.168 13.752 46.746 13.800 ; + RECT 0.168 14.136 46.746 14.184 ; + RECT 0.168 14.520 46.746 14.568 ; + RECT 0.168 14.904 46.746 14.952 ; + RECT 0.168 15.288 46.746 15.336 ; + RECT 0.168 15.672 46.746 15.720 ; + RECT 0.168 16.056 46.746 16.104 ; + RECT 0.168 16.440 46.746 16.488 ; + RECT 0.168 16.824 46.746 16.872 ; + RECT 0.168 17.208 46.746 17.256 ; + RECT 0.168 17.592 46.746 17.640 ; + RECT 0.168 17.976 46.746 18.024 ; + RECT 0.168 18.360 46.746 18.408 ; + RECT 0.168 18.744 46.746 18.792 ; + RECT 0.168 19.128 46.746 19.176 ; + RECT 0.168 19.512 46.746 19.560 ; + RECT 0.168 19.896 46.746 19.944 ; + RECT 0.168 20.280 46.746 20.328 ; + RECT 0.168 20.664 46.746 20.712 ; + RECT 0.168 21.048 46.746 21.096 ; + RECT 0.168 21.432 46.746 21.480 ; + RECT 0.168 21.816 46.746 21.864 ; + RECT 0.168 22.200 46.746 22.248 ; + RECT 0.168 22.584 46.746 22.632 ; + RECT 0.168 22.968 46.746 23.016 ; + RECT 0.168 23.352 46.746 23.400 ; + RECT 0.168 23.736 46.746 23.784 ; + RECT 0.168 24.120 46.746 24.168 ; + RECT 0.168 24.504 46.746 24.552 ; + RECT 0.168 24.888 46.746 24.936 ; + RECT 0.168 25.272 46.746 25.320 ; + RECT 0.168 25.656 46.746 25.704 ; + RECT 0.168 26.040 46.746 26.088 ; + RECT 0.168 26.424 46.746 26.472 ; + RECT 0.168 26.808 46.746 26.856 ; + RECT 0.168 27.192 46.746 27.240 ; + RECT 0.168 27.576 46.746 27.624 ; + RECT 0.168 27.960 46.746 28.008 ; + RECT 0.168 28.344 46.746 28.392 ; END END VDD OBS diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_66x80_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_66x80_1r1w.lef index 46d263ca..840c69f9 100644 --- a/designs/gt2n/NVDLA/sram/lef/fakeram_66x80_1r1w.lef +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_66x80_1r1w.lef @@ -1469,99 +1469,98 @@ MACRO fakeram_66x80_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.168 0.120 46.746 0.168 ; - RECT 0.168 0.504 46.746 0.552 ; - RECT 0.168 0.888 46.746 0.936 ; - RECT 0.168 1.272 46.746 1.320 ; - RECT 0.168 1.656 46.746 1.704 ; - RECT 0.168 2.040 46.746 2.088 ; - RECT 0.168 2.424 46.746 2.472 ; - RECT 0.168 2.808 46.746 2.856 ; - RECT 0.168 3.192 46.746 3.240 ; - RECT 0.168 3.576 46.746 3.624 ; - RECT 0.168 3.960 46.746 4.008 ; - RECT 0.168 4.344 46.746 4.392 ; - RECT 0.168 4.728 46.746 4.776 ; - RECT 0.168 5.112 46.746 5.160 ; - RECT 0.168 5.496 46.746 5.544 ; - RECT 0.168 5.880 46.746 5.928 ; - RECT 0.168 6.264 46.746 6.312 ; - RECT 0.168 6.648 46.746 6.696 ; - RECT 0.168 7.032 46.746 7.080 ; - RECT 0.168 7.416 46.746 7.464 ; - RECT 0.168 7.800 46.746 7.848 ; - RECT 0.168 8.184 46.746 8.232 ; - RECT 0.168 8.568 46.746 8.616 ; - RECT 0.168 8.952 46.746 9.000 ; - RECT 0.168 9.336 46.746 9.384 ; - RECT 0.168 9.720 46.746 9.768 ; - RECT 0.168 10.104 46.746 10.152 ; - RECT 0.168 10.488 46.746 10.536 ; - RECT 0.168 10.872 46.746 10.920 ; - RECT 0.168 11.256 46.746 11.304 ; - RECT 0.168 11.640 46.746 11.688 ; - RECT 0.168 12.024 46.746 12.072 ; - RECT 0.168 12.408 46.746 12.456 ; - RECT 0.168 12.792 46.746 12.840 ; - RECT 0.168 13.176 46.746 13.224 ; - RECT 0.168 13.560 46.746 13.608 ; - RECT 0.168 13.944 46.746 13.992 ; - RECT 0.168 14.328 46.746 14.376 ; - RECT 0.168 14.712 46.746 14.760 ; - RECT 0.168 15.096 46.746 15.144 ; - RECT 0.168 15.480 46.746 15.528 ; - RECT 0.168 15.864 46.746 15.912 ; - RECT 0.168 16.248 46.746 16.296 ; - RECT 0.168 16.632 46.746 16.680 ; - RECT 0.168 17.016 46.746 17.064 ; - RECT 0.168 17.400 46.746 17.448 ; - RECT 0.168 17.784 46.746 17.832 ; - RECT 0.168 18.168 46.746 18.216 ; - RECT 0.168 18.552 46.746 18.600 ; - RECT 0.168 18.936 46.746 18.984 ; - RECT 0.168 19.320 46.746 19.368 ; - RECT 0.168 19.704 46.746 19.752 ; - RECT 0.168 20.088 46.746 20.136 ; - RECT 0.168 20.472 46.746 20.520 ; - RECT 0.168 20.856 46.746 20.904 ; - RECT 0.168 21.240 46.746 21.288 ; - RECT 0.168 21.624 46.746 21.672 ; - RECT 0.168 22.008 46.746 22.056 ; - RECT 0.168 22.392 46.746 22.440 ; - RECT 0.168 22.776 46.746 22.824 ; - RECT 0.168 23.160 46.746 23.208 ; - RECT 0.168 23.544 46.746 23.592 ; - RECT 0.168 23.928 46.746 23.976 ; - RECT 0.168 24.312 46.746 24.360 ; - RECT 0.168 24.696 46.746 24.744 ; - RECT 0.168 25.080 46.746 25.128 ; - RECT 0.168 25.464 46.746 25.512 ; - RECT 0.168 25.848 46.746 25.896 ; - RECT 0.168 26.232 46.746 26.280 ; - RECT 0.168 26.616 46.746 26.664 ; - RECT 0.168 27.000 46.746 27.048 ; - RECT 0.168 27.384 46.746 27.432 ; - RECT 0.168 27.768 46.746 27.816 ; - RECT 0.168 28.152 46.746 28.200 ; - RECT 0.168 28.536 46.746 28.584 ; - RECT 0.168 28.920 46.746 28.968 ; - RECT 0.168 29.304 46.746 29.352 ; - RECT 0.168 29.688 46.746 29.736 ; - RECT 0.168 30.072 46.746 30.120 ; - RECT 0.168 30.456 46.746 30.504 ; - RECT 0.168 30.840 46.746 30.888 ; - RECT 0.168 31.224 46.746 31.272 ; - RECT 0.168 31.608 46.746 31.656 ; - RECT 0.168 31.992 46.746 32.040 ; - RECT 0.168 32.376 46.746 32.424 ; - RECT 0.168 32.760 46.746 32.808 ; - RECT 0.168 33.144 46.746 33.192 ; - RECT 0.168 33.528 46.746 33.576 ; - RECT 0.168 33.912 46.746 33.960 ; - RECT 0.168 34.296 46.746 34.344 ; - RECT 0.168 34.680 46.746 34.728 ; - RECT 0.168 35.064 46.746 35.112 ; - RECT 0.168 35.448 46.746 35.496 ; + RECT 0.168 0.312 46.746 0.360 ; + RECT 0.168 0.696 46.746 0.744 ; + RECT 0.168 1.080 46.746 1.128 ; + RECT 0.168 1.464 46.746 1.512 ; + RECT 0.168 1.848 46.746 1.896 ; + RECT 0.168 2.232 46.746 2.280 ; + RECT 0.168 2.616 46.746 2.664 ; + RECT 0.168 3.000 46.746 3.048 ; + RECT 0.168 3.384 46.746 3.432 ; + RECT 0.168 3.768 46.746 3.816 ; + RECT 0.168 4.152 46.746 4.200 ; + RECT 0.168 4.536 46.746 4.584 ; + RECT 0.168 4.920 46.746 4.968 ; + RECT 0.168 5.304 46.746 5.352 ; + RECT 0.168 5.688 46.746 5.736 ; + RECT 0.168 6.072 46.746 6.120 ; + RECT 0.168 6.456 46.746 6.504 ; + RECT 0.168 6.840 46.746 6.888 ; + RECT 0.168 7.224 46.746 7.272 ; + RECT 0.168 7.608 46.746 7.656 ; + RECT 0.168 7.992 46.746 8.040 ; + RECT 0.168 8.376 46.746 8.424 ; + RECT 0.168 8.760 46.746 8.808 ; + RECT 0.168 9.144 46.746 9.192 ; + RECT 0.168 9.528 46.746 9.576 ; + RECT 0.168 9.912 46.746 9.960 ; + RECT 0.168 10.296 46.746 10.344 ; + RECT 0.168 10.680 46.746 10.728 ; + RECT 0.168 11.064 46.746 11.112 ; + RECT 0.168 11.448 46.746 11.496 ; + RECT 0.168 11.832 46.746 11.880 ; + RECT 0.168 12.216 46.746 12.264 ; + RECT 0.168 12.600 46.746 12.648 ; + RECT 0.168 12.984 46.746 13.032 ; + RECT 0.168 13.368 46.746 13.416 ; + RECT 0.168 13.752 46.746 13.800 ; + RECT 0.168 14.136 46.746 14.184 ; + RECT 0.168 14.520 46.746 14.568 ; + RECT 0.168 14.904 46.746 14.952 ; + RECT 0.168 15.288 46.746 15.336 ; + RECT 0.168 15.672 46.746 15.720 ; + RECT 0.168 16.056 46.746 16.104 ; + RECT 0.168 16.440 46.746 16.488 ; + RECT 0.168 16.824 46.746 16.872 ; + RECT 0.168 17.208 46.746 17.256 ; + RECT 0.168 17.592 46.746 17.640 ; + RECT 0.168 17.976 46.746 18.024 ; + RECT 0.168 18.360 46.746 18.408 ; + RECT 0.168 18.744 46.746 18.792 ; + RECT 0.168 19.128 46.746 19.176 ; + RECT 0.168 19.512 46.746 19.560 ; + RECT 0.168 19.896 46.746 19.944 ; + RECT 0.168 20.280 46.746 20.328 ; + RECT 0.168 20.664 46.746 20.712 ; + RECT 0.168 21.048 46.746 21.096 ; + RECT 0.168 21.432 46.746 21.480 ; + RECT 0.168 21.816 46.746 21.864 ; + RECT 0.168 22.200 46.746 22.248 ; + RECT 0.168 22.584 46.746 22.632 ; + RECT 0.168 22.968 46.746 23.016 ; + RECT 0.168 23.352 46.746 23.400 ; + RECT 0.168 23.736 46.746 23.784 ; + RECT 0.168 24.120 46.746 24.168 ; + RECT 0.168 24.504 46.746 24.552 ; + RECT 0.168 24.888 46.746 24.936 ; + RECT 0.168 25.272 46.746 25.320 ; + RECT 0.168 25.656 46.746 25.704 ; + RECT 0.168 26.040 46.746 26.088 ; + RECT 0.168 26.424 46.746 26.472 ; + RECT 0.168 26.808 46.746 26.856 ; + RECT 0.168 27.192 46.746 27.240 ; + RECT 0.168 27.576 46.746 27.624 ; + RECT 0.168 27.960 46.746 28.008 ; + RECT 0.168 28.344 46.746 28.392 ; + RECT 0.168 28.728 46.746 28.776 ; + RECT 0.168 29.112 46.746 29.160 ; + RECT 0.168 29.496 46.746 29.544 ; + RECT 0.168 29.880 46.746 29.928 ; + RECT 0.168 30.264 46.746 30.312 ; + RECT 0.168 30.648 46.746 30.696 ; + RECT 0.168 31.032 46.746 31.080 ; + RECT 0.168 31.416 46.746 31.464 ; + RECT 0.168 31.800 46.746 31.848 ; + RECT 0.168 32.184 46.746 32.232 ; + RECT 0.168 32.568 46.746 32.616 ; + RECT 0.168 32.952 46.746 33.000 ; + RECT 0.168 33.336 46.746 33.384 ; + RECT 0.168 33.720 46.746 33.768 ; + RECT 0.168 34.104 46.746 34.152 ; + RECT 0.168 34.488 46.746 34.536 ; + RECT 0.168 34.872 46.746 34.920 ; + RECT 0.168 35.256 46.746 35.304 ; END END VDD OBS diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_7x256_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_7x256_1r1w.lef index ba83905d..571c01c0 100644 --- a/designs/gt2n/NVDLA/sram/lef/fakeram_7x256_1r1w.lef +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_7x256_1r1w.lef @@ -406,80 +406,80 @@ MACRO fakeram_7x256_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.168 0.120 19.740 0.168 ; - RECT 0.168 0.504 19.740 0.552 ; - RECT 0.168 0.888 19.740 0.936 ; - RECT 0.168 1.272 19.740 1.320 ; - RECT 0.168 1.656 19.740 1.704 ; - RECT 0.168 2.040 19.740 2.088 ; - RECT 0.168 2.424 19.740 2.472 ; - RECT 0.168 2.808 19.740 2.856 ; - RECT 0.168 3.192 19.740 3.240 ; - RECT 0.168 3.576 19.740 3.624 ; - RECT 0.168 3.960 19.740 4.008 ; - RECT 0.168 4.344 19.740 4.392 ; - RECT 0.168 4.728 19.740 4.776 ; - RECT 0.168 5.112 19.740 5.160 ; - RECT 0.168 5.496 19.740 5.544 ; - RECT 0.168 5.880 19.740 5.928 ; - RECT 0.168 6.264 19.740 6.312 ; - RECT 0.168 6.648 19.740 6.696 ; - RECT 0.168 7.032 19.740 7.080 ; - RECT 0.168 7.416 19.740 7.464 ; - RECT 0.168 7.800 19.740 7.848 ; - RECT 0.168 8.184 19.740 8.232 ; - RECT 0.168 8.568 19.740 8.616 ; - RECT 0.168 8.952 19.740 9.000 ; - RECT 0.168 9.336 19.740 9.384 ; - RECT 0.168 9.720 19.740 9.768 ; - RECT 0.168 10.104 19.740 10.152 ; - RECT 0.168 10.488 19.740 10.536 ; - RECT 0.168 10.872 19.740 10.920 ; - RECT 0.168 11.256 19.740 11.304 ; - RECT 0.168 11.640 19.740 11.688 ; - RECT 0.168 12.024 19.740 12.072 ; - RECT 0.168 12.408 19.740 12.456 ; - RECT 0.168 12.792 19.740 12.840 ; - RECT 0.168 13.176 19.740 13.224 ; - RECT 0.168 13.560 19.740 13.608 ; - RECT 0.168 13.944 19.740 13.992 ; - RECT 0.168 14.328 19.740 14.376 ; - RECT 0.168 14.712 19.740 14.760 ; - RECT 0.168 15.096 19.740 15.144 ; - RECT 0.168 15.480 19.740 15.528 ; - RECT 0.168 15.864 19.740 15.912 ; - RECT 0.168 16.248 19.740 16.296 ; - RECT 0.168 16.632 19.740 16.680 ; - RECT 0.168 17.016 19.740 17.064 ; - RECT 0.168 17.400 19.740 17.448 ; - RECT 0.168 17.784 19.740 17.832 ; - RECT 0.168 18.168 19.740 18.216 ; - RECT 0.168 18.552 19.740 18.600 ; - RECT 0.168 18.936 19.740 18.984 ; - RECT 0.168 19.320 19.740 19.368 ; - RECT 0.168 19.704 19.740 19.752 ; - RECT 0.168 20.088 19.740 20.136 ; - RECT 0.168 20.472 19.740 20.520 ; - RECT 0.168 20.856 19.740 20.904 ; - RECT 0.168 21.240 19.740 21.288 ; - RECT 0.168 21.624 19.740 21.672 ; - RECT 0.168 22.008 19.740 22.056 ; - RECT 0.168 22.392 19.740 22.440 ; - RECT 0.168 22.776 19.740 22.824 ; - RECT 0.168 23.160 19.740 23.208 ; - RECT 0.168 23.544 19.740 23.592 ; - RECT 0.168 23.928 19.740 23.976 ; - RECT 0.168 24.312 19.740 24.360 ; - RECT 0.168 24.696 19.740 24.744 ; - RECT 0.168 25.080 19.740 25.128 ; - RECT 0.168 25.464 19.740 25.512 ; - RECT 0.168 25.848 19.740 25.896 ; - RECT 0.168 26.232 19.740 26.280 ; - RECT 0.168 26.616 19.740 26.664 ; - RECT 0.168 27.000 19.740 27.048 ; - RECT 0.168 27.384 19.740 27.432 ; - RECT 0.168 27.768 19.740 27.816 ; - RECT 0.168 28.152 19.740 28.200 ; + RECT 0.168 0.312 19.740 0.360 ; + RECT 0.168 0.696 19.740 0.744 ; + RECT 0.168 1.080 19.740 1.128 ; + RECT 0.168 1.464 19.740 1.512 ; + RECT 0.168 1.848 19.740 1.896 ; + RECT 0.168 2.232 19.740 2.280 ; + RECT 0.168 2.616 19.740 2.664 ; + RECT 0.168 3.000 19.740 3.048 ; + RECT 0.168 3.384 19.740 3.432 ; + RECT 0.168 3.768 19.740 3.816 ; + RECT 0.168 4.152 19.740 4.200 ; + RECT 0.168 4.536 19.740 4.584 ; + RECT 0.168 4.920 19.740 4.968 ; + RECT 0.168 5.304 19.740 5.352 ; + RECT 0.168 5.688 19.740 5.736 ; + RECT 0.168 6.072 19.740 6.120 ; + RECT 0.168 6.456 19.740 6.504 ; + RECT 0.168 6.840 19.740 6.888 ; + RECT 0.168 7.224 19.740 7.272 ; + RECT 0.168 7.608 19.740 7.656 ; + RECT 0.168 7.992 19.740 8.040 ; + RECT 0.168 8.376 19.740 8.424 ; + RECT 0.168 8.760 19.740 8.808 ; + RECT 0.168 9.144 19.740 9.192 ; + RECT 0.168 9.528 19.740 9.576 ; + RECT 0.168 9.912 19.740 9.960 ; + RECT 0.168 10.296 19.740 10.344 ; + RECT 0.168 10.680 19.740 10.728 ; + RECT 0.168 11.064 19.740 11.112 ; + RECT 0.168 11.448 19.740 11.496 ; + RECT 0.168 11.832 19.740 11.880 ; + RECT 0.168 12.216 19.740 12.264 ; + RECT 0.168 12.600 19.740 12.648 ; + RECT 0.168 12.984 19.740 13.032 ; + RECT 0.168 13.368 19.740 13.416 ; + RECT 0.168 13.752 19.740 13.800 ; + RECT 0.168 14.136 19.740 14.184 ; + RECT 0.168 14.520 19.740 14.568 ; + RECT 0.168 14.904 19.740 14.952 ; + RECT 0.168 15.288 19.740 15.336 ; + RECT 0.168 15.672 19.740 15.720 ; + RECT 0.168 16.056 19.740 16.104 ; + RECT 0.168 16.440 19.740 16.488 ; + RECT 0.168 16.824 19.740 16.872 ; + RECT 0.168 17.208 19.740 17.256 ; + RECT 0.168 17.592 19.740 17.640 ; + RECT 0.168 17.976 19.740 18.024 ; + RECT 0.168 18.360 19.740 18.408 ; + RECT 0.168 18.744 19.740 18.792 ; + RECT 0.168 19.128 19.740 19.176 ; + RECT 0.168 19.512 19.740 19.560 ; + RECT 0.168 19.896 19.740 19.944 ; + RECT 0.168 20.280 19.740 20.328 ; + RECT 0.168 20.664 19.740 20.712 ; + RECT 0.168 21.048 19.740 21.096 ; + RECT 0.168 21.432 19.740 21.480 ; + RECT 0.168 21.816 19.740 21.864 ; + RECT 0.168 22.200 19.740 22.248 ; + RECT 0.168 22.584 19.740 22.632 ; + RECT 0.168 22.968 19.740 23.016 ; + RECT 0.168 23.352 19.740 23.400 ; + RECT 0.168 23.736 19.740 23.784 ; + RECT 0.168 24.120 19.740 24.168 ; + RECT 0.168 24.504 19.740 24.552 ; + RECT 0.168 24.888 19.740 24.936 ; + RECT 0.168 25.272 19.740 25.320 ; + RECT 0.168 25.656 19.740 25.704 ; + RECT 0.168 26.040 19.740 26.088 ; + RECT 0.168 26.424 19.740 26.472 ; + RECT 0.168 26.808 19.740 26.856 ; + RECT 0.168 27.192 19.740 27.240 ; + RECT 0.168 27.576 19.740 27.624 ; + RECT 0.168 27.960 19.740 28.008 ; + RECT 0.168 28.344 19.740 28.392 ; END END VDD OBS diff --git a/designs/gt2n/NVDLA/sram/lef/fakeram_8x256_1r1w.lef b/designs/gt2n/NVDLA/sram/lef/fakeram_8x256_1r1w.lef index d8a8c9ee..8220f26a 100644 --- a/designs/gt2n/NVDLA/sram/lef/fakeram_8x256_1r1w.lef +++ b/designs/gt2n/NVDLA/sram/lef/fakeram_8x256_1r1w.lef @@ -424,80 +424,80 @@ MACRO fakeram_8x256_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.168 0.120 22.596 0.168 ; - RECT 0.168 0.504 22.596 0.552 ; - RECT 0.168 0.888 22.596 0.936 ; - RECT 0.168 1.272 22.596 1.320 ; - RECT 0.168 1.656 22.596 1.704 ; - RECT 0.168 2.040 22.596 2.088 ; - RECT 0.168 2.424 22.596 2.472 ; - RECT 0.168 2.808 22.596 2.856 ; - RECT 0.168 3.192 22.596 3.240 ; - RECT 0.168 3.576 22.596 3.624 ; - RECT 0.168 3.960 22.596 4.008 ; - RECT 0.168 4.344 22.596 4.392 ; - RECT 0.168 4.728 22.596 4.776 ; - RECT 0.168 5.112 22.596 5.160 ; - RECT 0.168 5.496 22.596 5.544 ; - RECT 0.168 5.880 22.596 5.928 ; - RECT 0.168 6.264 22.596 6.312 ; - RECT 0.168 6.648 22.596 6.696 ; - RECT 0.168 7.032 22.596 7.080 ; - RECT 0.168 7.416 22.596 7.464 ; - RECT 0.168 7.800 22.596 7.848 ; - RECT 0.168 8.184 22.596 8.232 ; - RECT 0.168 8.568 22.596 8.616 ; - RECT 0.168 8.952 22.596 9.000 ; - RECT 0.168 9.336 22.596 9.384 ; - RECT 0.168 9.720 22.596 9.768 ; - RECT 0.168 10.104 22.596 10.152 ; - RECT 0.168 10.488 22.596 10.536 ; - RECT 0.168 10.872 22.596 10.920 ; - RECT 0.168 11.256 22.596 11.304 ; - RECT 0.168 11.640 22.596 11.688 ; - RECT 0.168 12.024 22.596 12.072 ; - RECT 0.168 12.408 22.596 12.456 ; - RECT 0.168 12.792 22.596 12.840 ; - RECT 0.168 13.176 22.596 13.224 ; - RECT 0.168 13.560 22.596 13.608 ; - RECT 0.168 13.944 22.596 13.992 ; - RECT 0.168 14.328 22.596 14.376 ; - RECT 0.168 14.712 22.596 14.760 ; - RECT 0.168 15.096 22.596 15.144 ; - RECT 0.168 15.480 22.596 15.528 ; - RECT 0.168 15.864 22.596 15.912 ; - RECT 0.168 16.248 22.596 16.296 ; - RECT 0.168 16.632 22.596 16.680 ; - RECT 0.168 17.016 22.596 17.064 ; - RECT 0.168 17.400 22.596 17.448 ; - RECT 0.168 17.784 22.596 17.832 ; - RECT 0.168 18.168 22.596 18.216 ; - RECT 0.168 18.552 22.596 18.600 ; - RECT 0.168 18.936 22.596 18.984 ; - RECT 0.168 19.320 22.596 19.368 ; - RECT 0.168 19.704 22.596 19.752 ; - RECT 0.168 20.088 22.596 20.136 ; - RECT 0.168 20.472 22.596 20.520 ; - RECT 0.168 20.856 22.596 20.904 ; - RECT 0.168 21.240 22.596 21.288 ; - RECT 0.168 21.624 22.596 21.672 ; - RECT 0.168 22.008 22.596 22.056 ; - RECT 0.168 22.392 22.596 22.440 ; - RECT 0.168 22.776 22.596 22.824 ; - RECT 0.168 23.160 22.596 23.208 ; - RECT 0.168 23.544 22.596 23.592 ; - RECT 0.168 23.928 22.596 23.976 ; - RECT 0.168 24.312 22.596 24.360 ; - RECT 0.168 24.696 22.596 24.744 ; - RECT 0.168 25.080 22.596 25.128 ; - RECT 0.168 25.464 22.596 25.512 ; - RECT 0.168 25.848 22.596 25.896 ; - RECT 0.168 26.232 22.596 26.280 ; - RECT 0.168 26.616 22.596 26.664 ; - RECT 0.168 27.000 22.596 27.048 ; - RECT 0.168 27.384 22.596 27.432 ; - RECT 0.168 27.768 22.596 27.816 ; - RECT 0.168 28.152 22.596 28.200 ; + RECT 0.168 0.312 22.596 0.360 ; + RECT 0.168 0.696 22.596 0.744 ; + RECT 0.168 1.080 22.596 1.128 ; + RECT 0.168 1.464 22.596 1.512 ; + RECT 0.168 1.848 22.596 1.896 ; + RECT 0.168 2.232 22.596 2.280 ; + RECT 0.168 2.616 22.596 2.664 ; + RECT 0.168 3.000 22.596 3.048 ; + RECT 0.168 3.384 22.596 3.432 ; + RECT 0.168 3.768 22.596 3.816 ; + RECT 0.168 4.152 22.596 4.200 ; + RECT 0.168 4.536 22.596 4.584 ; + RECT 0.168 4.920 22.596 4.968 ; + RECT 0.168 5.304 22.596 5.352 ; + RECT 0.168 5.688 22.596 5.736 ; + RECT 0.168 6.072 22.596 6.120 ; + RECT 0.168 6.456 22.596 6.504 ; + RECT 0.168 6.840 22.596 6.888 ; + RECT 0.168 7.224 22.596 7.272 ; + RECT 0.168 7.608 22.596 7.656 ; + RECT 0.168 7.992 22.596 8.040 ; + RECT 0.168 8.376 22.596 8.424 ; + RECT 0.168 8.760 22.596 8.808 ; + RECT 0.168 9.144 22.596 9.192 ; + RECT 0.168 9.528 22.596 9.576 ; + RECT 0.168 9.912 22.596 9.960 ; + RECT 0.168 10.296 22.596 10.344 ; + RECT 0.168 10.680 22.596 10.728 ; + RECT 0.168 11.064 22.596 11.112 ; + RECT 0.168 11.448 22.596 11.496 ; + RECT 0.168 11.832 22.596 11.880 ; + RECT 0.168 12.216 22.596 12.264 ; + RECT 0.168 12.600 22.596 12.648 ; + RECT 0.168 12.984 22.596 13.032 ; + RECT 0.168 13.368 22.596 13.416 ; + RECT 0.168 13.752 22.596 13.800 ; + RECT 0.168 14.136 22.596 14.184 ; + RECT 0.168 14.520 22.596 14.568 ; + RECT 0.168 14.904 22.596 14.952 ; + RECT 0.168 15.288 22.596 15.336 ; + RECT 0.168 15.672 22.596 15.720 ; + RECT 0.168 16.056 22.596 16.104 ; + RECT 0.168 16.440 22.596 16.488 ; + RECT 0.168 16.824 22.596 16.872 ; + RECT 0.168 17.208 22.596 17.256 ; + RECT 0.168 17.592 22.596 17.640 ; + RECT 0.168 17.976 22.596 18.024 ; + RECT 0.168 18.360 22.596 18.408 ; + RECT 0.168 18.744 22.596 18.792 ; + RECT 0.168 19.128 22.596 19.176 ; + RECT 0.168 19.512 22.596 19.560 ; + RECT 0.168 19.896 22.596 19.944 ; + RECT 0.168 20.280 22.596 20.328 ; + RECT 0.168 20.664 22.596 20.712 ; + RECT 0.168 21.048 22.596 21.096 ; + RECT 0.168 21.432 22.596 21.480 ; + RECT 0.168 21.816 22.596 21.864 ; + RECT 0.168 22.200 22.596 22.248 ; + RECT 0.168 22.584 22.596 22.632 ; + RECT 0.168 22.968 22.596 23.016 ; + RECT 0.168 23.352 22.596 23.400 ; + RECT 0.168 23.736 22.596 23.784 ; + RECT 0.168 24.120 22.596 24.168 ; + RECT 0.168 24.504 22.596 24.552 ; + RECT 0.168 24.888 22.596 24.936 ; + RECT 0.168 25.272 22.596 25.320 ; + RECT 0.168 25.656 22.596 25.704 ; + RECT 0.168 26.040 22.596 26.088 ; + RECT 0.168 26.424 22.596 26.472 ; + RECT 0.168 26.808 22.596 26.856 ; + RECT 0.168 27.192 22.596 27.240 ; + RECT 0.168 27.576 22.596 27.624 ; + RECT 0.168 27.960 22.596 28.008 ; + RECT 0.168 28.344 22.596 28.392 ; END END VDD OBS diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_11x128_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_11x128_1r1w.lib index 61496ab5..9fd888b8 100644 --- a/designs/gt2n/NVDLA/sram/lib/fakeram_11x128_1r1w.lib +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_11x128_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_11x128_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-08-01 08:31:13Z"; + date : "2026-08-20 05:56:15Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -97,9 +97,9 @@ cell(fakeram_11x128_1r1w) { } pin(r0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_11x128_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -114,9 +114,9 @@ cell(fakeram_11x128_1r1w) { pin(w0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_11x128_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -132,7 +132,7 @@ cell(fakeram_11x128_1r1w) { bus(r0_rd_out) { bus_type : fakeram_11x128_1r1w_DATA; direction : output; - max_capacitance : 0.500; + max_capacitance : 0.0488; memory_read() { address : r0_addr_in; } @@ -142,7 +142,7 @@ cell(fakeram_11x128_1r1w) { timing_sense : non_unate; cell_rise(fakeram_11x128_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ @@ -150,25 +150,25 @@ cell(fakeram_11x128_1r1w) { } cell_fall(fakeram_11x128_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ ) } rise_transition(fakeram_11x128_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } fall_transition(fakeram_11x128_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } } } pin(w0_we_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -176,16 +176,16 @@ cell(fakeram_11x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_11x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -196,16 +196,16 @@ cell(fakeram_11x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_11x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -222,7 +222,7 @@ cell(fakeram_11x128_1r1w) { } pin(r0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -230,16 +230,16 @@ cell(fakeram_11x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_11x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -250,16 +250,16 @@ cell(fakeram_11x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_11x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -276,7 +276,7 @@ cell(fakeram_11x128_1r1w) { } pin(w0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -284,16 +284,16 @@ cell(fakeram_11x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_11x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -304,16 +304,16 @@ cell(fakeram_11x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_11x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -335,7 +335,7 @@ cell(fakeram_11x128_1r1w) { clocked_on : "w0_clk"; } direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -343,16 +343,16 @@ cell(fakeram_11x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_11x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -363,16 +363,16 @@ cell(fakeram_11x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_11x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -402,7 +402,7 @@ cell(fakeram_11x128_1r1w) { bus(r0_addr_in) { bus_type : fakeram_11x128_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -410,16 +410,16 @@ cell(fakeram_11x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_11x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -430,16 +430,16 @@ cell(fakeram_11x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_11x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -457,7 +457,7 @@ cell(fakeram_11x128_1r1w) { bus(w0_addr_in) { bus_type : fakeram_11x128_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -465,16 +465,16 @@ cell(fakeram_11x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_11x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -485,16 +485,16 @@ cell(fakeram_11x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_11x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_14x80_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_14x80_1r1w.lib index 0d4f32dd..5ca0544d 100644 --- a/designs/gt2n/NVDLA/sram/lib/fakeram_14x80_1r1w.lib +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_14x80_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_14x80_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-08-01 08:31:13Z"; + date : "2026-08-20 05:56:15Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -97,9 +97,9 @@ cell(fakeram_14x80_1r1w) { } pin(r0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_14x80_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -114,9 +114,9 @@ cell(fakeram_14x80_1r1w) { pin(w0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_14x80_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -132,7 +132,7 @@ cell(fakeram_14x80_1r1w) { bus(r0_rd_out) { bus_type : fakeram_14x80_1r1w_DATA; direction : output; - max_capacitance : 0.500; + max_capacitance : 0.0488; memory_read() { address : r0_addr_in; } @@ -142,7 +142,7 @@ cell(fakeram_14x80_1r1w) { timing_sense : non_unate; cell_rise(fakeram_14x80_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ @@ -150,25 +150,25 @@ cell(fakeram_14x80_1r1w) { } cell_fall(fakeram_14x80_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ ) } rise_transition(fakeram_14x80_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } fall_transition(fakeram_14x80_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } } } pin(w0_we_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -176,16 +176,16 @@ cell(fakeram_14x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_14x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -196,16 +196,16 @@ cell(fakeram_14x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_14x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -222,7 +222,7 @@ cell(fakeram_14x80_1r1w) { } pin(r0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -230,16 +230,16 @@ cell(fakeram_14x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_14x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -250,16 +250,16 @@ cell(fakeram_14x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_14x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -276,7 +276,7 @@ cell(fakeram_14x80_1r1w) { } pin(w0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -284,16 +284,16 @@ cell(fakeram_14x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_14x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -304,16 +304,16 @@ cell(fakeram_14x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_14x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -335,7 +335,7 @@ cell(fakeram_14x80_1r1w) { clocked_on : "w0_clk"; } direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -343,16 +343,16 @@ cell(fakeram_14x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_14x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -363,16 +363,16 @@ cell(fakeram_14x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_14x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -402,7 +402,7 @@ cell(fakeram_14x80_1r1w) { bus(r0_addr_in) { bus_type : fakeram_14x80_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -410,16 +410,16 @@ cell(fakeram_14x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_14x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -430,16 +430,16 @@ cell(fakeram_14x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_14x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -457,7 +457,7 @@ cell(fakeram_14x80_1r1w) { bus(w0_addr_in) { bus_type : fakeram_14x80_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -465,16 +465,16 @@ cell(fakeram_14x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_14x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -485,16 +485,16 @@ cell(fakeram_14x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_14x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_15x80_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_15x80_1r1w.lib index 3a8be37c..14508725 100644 --- a/designs/gt2n/NVDLA/sram/lib/fakeram_15x80_1r1w.lib +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_15x80_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_15x80_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-08-01 08:31:13Z"; + date : "2026-08-20 05:56:15Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -97,9 +97,9 @@ cell(fakeram_15x80_1r1w) { } pin(r0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_15x80_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -114,9 +114,9 @@ cell(fakeram_15x80_1r1w) { pin(w0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_15x80_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -132,7 +132,7 @@ cell(fakeram_15x80_1r1w) { bus(r0_rd_out) { bus_type : fakeram_15x80_1r1w_DATA; direction : output; - max_capacitance : 0.500; + max_capacitance : 0.0488; memory_read() { address : r0_addr_in; } @@ -142,7 +142,7 @@ cell(fakeram_15x80_1r1w) { timing_sense : non_unate; cell_rise(fakeram_15x80_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ @@ -150,25 +150,25 @@ cell(fakeram_15x80_1r1w) { } cell_fall(fakeram_15x80_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ ) } rise_transition(fakeram_15x80_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } fall_transition(fakeram_15x80_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } } } pin(w0_we_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -176,16 +176,16 @@ cell(fakeram_15x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_15x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -196,16 +196,16 @@ cell(fakeram_15x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_15x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -222,7 +222,7 @@ cell(fakeram_15x80_1r1w) { } pin(r0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -230,16 +230,16 @@ cell(fakeram_15x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_15x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -250,16 +250,16 @@ cell(fakeram_15x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_15x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -276,7 +276,7 @@ cell(fakeram_15x80_1r1w) { } pin(w0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -284,16 +284,16 @@ cell(fakeram_15x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_15x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -304,16 +304,16 @@ cell(fakeram_15x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_15x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -335,7 +335,7 @@ cell(fakeram_15x80_1r1w) { clocked_on : "w0_clk"; } direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -343,16 +343,16 @@ cell(fakeram_15x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_15x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -363,16 +363,16 @@ cell(fakeram_15x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_15x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -402,7 +402,7 @@ cell(fakeram_15x80_1r1w) { bus(r0_addr_in) { bus_type : fakeram_15x80_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -410,16 +410,16 @@ cell(fakeram_15x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_15x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -430,16 +430,16 @@ cell(fakeram_15x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_15x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -457,7 +457,7 @@ cell(fakeram_15x80_1r1w) { bus(w0_addr_in) { bus_type : fakeram_15x80_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -465,16 +465,16 @@ cell(fakeram_15x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_15x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -485,16 +485,16 @@ cell(fakeram_15x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_15x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_16x160_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_16x160_1r1w.lib index 07570b10..a6ab7544 100644 --- a/designs/gt2n/NVDLA/sram/lib/fakeram_16x160_1r1w.lib +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_16x160_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_16x160_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-08-01 08:31:13Z"; + date : "2026-08-20 05:56:15Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -97,9 +97,9 @@ cell(fakeram_16x160_1r1w) { } pin(r0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_16x160_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -114,9 +114,9 @@ cell(fakeram_16x160_1r1w) { pin(w0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_16x160_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -132,7 +132,7 @@ cell(fakeram_16x160_1r1w) { bus(r0_rd_out) { bus_type : fakeram_16x160_1r1w_DATA; direction : output; - max_capacitance : 0.500; + max_capacitance : 0.0488; memory_read() { address : r0_addr_in; } @@ -142,7 +142,7 @@ cell(fakeram_16x160_1r1w) { timing_sense : non_unate; cell_rise(fakeram_16x160_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ @@ -150,25 +150,25 @@ cell(fakeram_16x160_1r1w) { } cell_fall(fakeram_16x160_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ ) } rise_transition(fakeram_16x160_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } fall_transition(fakeram_16x160_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } } } pin(w0_we_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -176,16 +176,16 @@ cell(fakeram_16x160_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_16x160_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -196,16 +196,16 @@ cell(fakeram_16x160_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_16x160_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -222,7 +222,7 @@ cell(fakeram_16x160_1r1w) { } pin(r0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -230,16 +230,16 @@ cell(fakeram_16x160_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_16x160_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -250,16 +250,16 @@ cell(fakeram_16x160_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_16x160_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -276,7 +276,7 @@ cell(fakeram_16x160_1r1w) { } pin(w0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -284,16 +284,16 @@ cell(fakeram_16x160_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_16x160_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -304,16 +304,16 @@ cell(fakeram_16x160_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_16x160_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -335,7 +335,7 @@ cell(fakeram_16x160_1r1w) { clocked_on : "w0_clk"; } direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -343,16 +343,16 @@ cell(fakeram_16x160_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_16x160_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -363,16 +363,16 @@ cell(fakeram_16x160_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_16x160_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -402,7 +402,7 @@ cell(fakeram_16x160_1r1w) { bus(r0_addr_in) { bus_type : fakeram_16x160_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -410,16 +410,16 @@ cell(fakeram_16x160_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_16x160_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -430,16 +430,16 @@ cell(fakeram_16x160_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_16x160_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -457,7 +457,7 @@ cell(fakeram_16x160_1r1w) { bus(w0_addr_in) { bus_type : fakeram_16x160_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -465,16 +465,16 @@ cell(fakeram_16x160_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_16x160_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -485,16 +485,16 @@ cell(fakeram_16x160_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_16x160_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_18x128_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_18x128_1r1w.lib index d7c352e5..88131b94 100644 --- a/designs/gt2n/NVDLA/sram/lib/fakeram_18x128_1r1w.lib +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_18x128_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_18x128_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-08-01 08:31:13Z"; + date : "2026-08-20 05:56:15Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -97,9 +97,9 @@ cell(fakeram_18x128_1r1w) { } pin(r0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_18x128_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -114,9 +114,9 @@ cell(fakeram_18x128_1r1w) { pin(w0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_18x128_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -132,7 +132,7 @@ cell(fakeram_18x128_1r1w) { bus(r0_rd_out) { bus_type : fakeram_18x128_1r1w_DATA; direction : output; - max_capacitance : 0.500; + max_capacitance : 0.0488; memory_read() { address : r0_addr_in; } @@ -142,7 +142,7 @@ cell(fakeram_18x128_1r1w) { timing_sense : non_unate; cell_rise(fakeram_18x128_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ @@ -150,25 +150,25 @@ cell(fakeram_18x128_1r1w) { } cell_fall(fakeram_18x128_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ ) } rise_transition(fakeram_18x128_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } fall_transition(fakeram_18x128_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } } } pin(w0_we_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -176,16 +176,16 @@ cell(fakeram_18x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_18x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -196,16 +196,16 @@ cell(fakeram_18x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_18x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -222,7 +222,7 @@ cell(fakeram_18x128_1r1w) { } pin(r0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -230,16 +230,16 @@ cell(fakeram_18x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_18x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -250,16 +250,16 @@ cell(fakeram_18x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_18x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -276,7 +276,7 @@ cell(fakeram_18x128_1r1w) { } pin(w0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -284,16 +284,16 @@ cell(fakeram_18x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_18x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -304,16 +304,16 @@ cell(fakeram_18x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_18x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -335,7 +335,7 @@ cell(fakeram_18x128_1r1w) { clocked_on : "w0_clk"; } direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -343,16 +343,16 @@ cell(fakeram_18x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_18x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -363,16 +363,16 @@ cell(fakeram_18x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_18x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -402,7 +402,7 @@ cell(fakeram_18x128_1r1w) { bus(r0_addr_in) { bus_type : fakeram_18x128_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -410,16 +410,16 @@ cell(fakeram_18x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_18x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -430,16 +430,16 @@ cell(fakeram_18x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_18x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -457,7 +457,7 @@ cell(fakeram_18x128_1r1w) { bus(w0_addr_in) { bus_type : fakeram_18x128_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -465,16 +465,16 @@ cell(fakeram_18x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_18x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -485,16 +485,16 @@ cell(fakeram_18x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_18x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_22x60_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_22x60_1r1w.lib index e14adfbc..cfb87dc8 100644 --- a/designs/gt2n/NVDLA/sram/lib/fakeram_22x60_1r1w.lib +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_22x60_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_22x60_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-08-01 08:31:13Z"; + date : "2026-08-20 05:56:15Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -97,9 +97,9 @@ cell(fakeram_22x60_1r1w) { } pin(r0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_22x60_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -114,9 +114,9 @@ cell(fakeram_22x60_1r1w) { pin(w0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_22x60_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -132,7 +132,7 @@ cell(fakeram_22x60_1r1w) { bus(r0_rd_out) { bus_type : fakeram_22x60_1r1w_DATA; direction : output; - max_capacitance : 0.500; + max_capacitance : 0.0488; memory_read() { address : r0_addr_in; } @@ -142,7 +142,7 @@ cell(fakeram_22x60_1r1w) { timing_sense : non_unate; cell_rise(fakeram_22x60_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ @@ -150,25 +150,25 @@ cell(fakeram_22x60_1r1w) { } cell_fall(fakeram_22x60_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ ) } rise_transition(fakeram_22x60_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } fall_transition(fakeram_22x60_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } } } pin(w0_we_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -176,16 +176,16 @@ cell(fakeram_22x60_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_22x60_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -196,16 +196,16 @@ cell(fakeram_22x60_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_22x60_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -222,7 +222,7 @@ cell(fakeram_22x60_1r1w) { } pin(r0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -230,16 +230,16 @@ cell(fakeram_22x60_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_22x60_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -250,16 +250,16 @@ cell(fakeram_22x60_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_22x60_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -276,7 +276,7 @@ cell(fakeram_22x60_1r1w) { } pin(w0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -284,16 +284,16 @@ cell(fakeram_22x60_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_22x60_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -304,16 +304,16 @@ cell(fakeram_22x60_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_22x60_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -335,7 +335,7 @@ cell(fakeram_22x60_1r1w) { clocked_on : "w0_clk"; } direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -343,16 +343,16 @@ cell(fakeram_22x60_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_22x60_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -363,16 +363,16 @@ cell(fakeram_22x60_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_22x60_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -402,7 +402,7 @@ cell(fakeram_22x60_1r1w) { bus(r0_addr_in) { bus_type : fakeram_22x60_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -410,16 +410,16 @@ cell(fakeram_22x60_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_22x60_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -430,16 +430,16 @@ cell(fakeram_22x60_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_22x60_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -457,7 +457,7 @@ cell(fakeram_22x60_1r1w) { bus(w0_addr_in) { bus_type : fakeram_22x60_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -465,16 +465,16 @@ cell(fakeram_22x60_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_22x60_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -485,16 +485,16 @@ cell(fakeram_22x60_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_22x60_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_32x128_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_32x128_1r1w.lib index 3bf4b402..bb5b8e3a 100644 --- a/designs/gt2n/NVDLA/sram/lib/fakeram_32x128_1r1w.lib +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_32x128_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_32x128_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-08-01 08:31:13Z"; + date : "2026-08-20 05:56:15Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -97,9 +97,9 @@ cell(fakeram_32x128_1r1w) { } pin(r0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_32x128_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -114,9 +114,9 @@ cell(fakeram_32x128_1r1w) { pin(w0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_32x128_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -132,7 +132,7 @@ cell(fakeram_32x128_1r1w) { bus(r0_rd_out) { bus_type : fakeram_32x128_1r1w_DATA; direction : output; - max_capacitance : 0.500; + max_capacitance : 0.0488; memory_read() { address : r0_addr_in; } @@ -142,7 +142,7 @@ cell(fakeram_32x128_1r1w) { timing_sense : non_unate; cell_rise(fakeram_32x128_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ @@ -150,25 +150,25 @@ cell(fakeram_32x128_1r1w) { } cell_fall(fakeram_32x128_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ ) } rise_transition(fakeram_32x128_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } fall_transition(fakeram_32x128_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } } } pin(w0_we_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -176,16 +176,16 @@ cell(fakeram_32x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_32x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -196,16 +196,16 @@ cell(fakeram_32x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_32x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -222,7 +222,7 @@ cell(fakeram_32x128_1r1w) { } pin(r0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -230,16 +230,16 @@ cell(fakeram_32x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_32x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -250,16 +250,16 @@ cell(fakeram_32x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_32x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -276,7 +276,7 @@ cell(fakeram_32x128_1r1w) { } pin(w0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -284,16 +284,16 @@ cell(fakeram_32x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_32x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -304,16 +304,16 @@ cell(fakeram_32x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_32x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -335,7 +335,7 @@ cell(fakeram_32x128_1r1w) { clocked_on : "w0_clk"; } direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -343,16 +343,16 @@ cell(fakeram_32x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_32x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -363,16 +363,16 @@ cell(fakeram_32x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_32x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -402,7 +402,7 @@ cell(fakeram_32x128_1r1w) { bus(r0_addr_in) { bus_type : fakeram_32x128_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -410,16 +410,16 @@ cell(fakeram_32x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_32x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -430,16 +430,16 @@ cell(fakeram_32x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_32x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -457,7 +457,7 @@ cell(fakeram_32x128_1r1w) { bus(w0_addr_in) { bus_type : fakeram_32x128_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -465,16 +465,16 @@ cell(fakeram_32x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_32x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -485,16 +485,16 @@ cell(fakeram_32x128_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_32x128_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_4x256_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_4x256_1r1w.lib index 01274137..e77946b0 100644 --- a/designs/gt2n/NVDLA/sram/lib/fakeram_4x256_1r1w.lib +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_4x256_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_4x256_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-08-01 08:31:13Z"; + date : "2026-08-20 05:56:15Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -97,9 +97,9 @@ cell(fakeram_4x256_1r1w) { } pin(r0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_4x256_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -114,9 +114,9 @@ cell(fakeram_4x256_1r1w) { pin(w0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_4x256_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -132,7 +132,7 @@ cell(fakeram_4x256_1r1w) { bus(r0_rd_out) { bus_type : fakeram_4x256_1r1w_DATA; direction : output; - max_capacitance : 0.500; + max_capacitance : 0.0488; memory_read() { address : r0_addr_in; } @@ -142,7 +142,7 @@ cell(fakeram_4x256_1r1w) { timing_sense : non_unate; cell_rise(fakeram_4x256_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ @@ -150,25 +150,25 @@ cell(fakeram_4x256_1r1w) { } cell_fall(fakeram_4x256_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ ) } rise_transition(fakeram_4x256_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } fall_transition(fakeram_4x256_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } } } pin(w0_we_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -176,16 +176,16 @@ cell(fakeram_4x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -196,16 +196,16 @@ cell(fakeram_4x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -222,7 +222,7 @@ cell(fakeram_4x256_1r1w) { } pin(r0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -230,16 +230,16 @@ cell(fakeram_4x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -250,16 +250,16 @@ cell(fakeram_4x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -276,7 +276,7 @@ cell(fakeram_4x256_1r1w) { } pin(w0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -284,16 +284,16 @@ cell(fakeram_4x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -304,16 +304,16 @@ cell(fakeram_4x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -335,7 +335,7 @@ cell(fakeram_4x256_1r1w) { clocked_on : "w0_clk"; } direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -343,16 +343,16 @@ cell(fakeram_4x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -363,16 +363,16 @@ cell(fakeram_4x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -402,7 +402,7 @@ cell(fakeram_4x256_1r1w) { bus(r0_addr_in) { bus_type : fakeram_4x256_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -410,16 +410,16 @@ cell(fakeram_4x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -430,16 +430,16 @@ cell(fakeram_4x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -457,7 +457,7 @@ cell(fakeram_4x256_1r1w) { bus(w0_addr_in) { bus_type : fakeram_4x256_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -465,16 +465,16 @@ cell(fakeram_4x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -485,16 +485,16 @@ cell(fakeram_4x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_64x256_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_64x256_1r1w.lib index 127bf539..be83d18f 100644 --- a/designs/gt2n/NVDLA/sram/lib/fakeram_64x256_1r1w.lib +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_64x256_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_64x256_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-08-01 08:31:13Z"; + date : "2026-08-20 05:56:15Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -97,9 +97,9 @@ cell(fakeram_64x256_1r1w) { } pin(r0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_64x256_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -114,9 +114,9 @@ cell(fakeram_64x256_1r1w) { pin(w0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_64x256_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -132,7 +132,7 @@ cell(fakeram_64x256_1r1w) { bus(r0_rd_out) { bus_type : fakeram_64x256_1r1w_DATA; direction : output; - max_capacitance : 0.500; + max_capacitance : 0.0488; memory_read() { address : r0_addr_in; } @@ -142,7 +142,7 @@ cell(fakeram_64x256_1r1w) { timing_sense : non_unate; cell_rise(fakeram_64x256_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ @@ -150,25 +150,25 @@ cell(fakeram_64x256_1r1w) { } cell_fall(fakeram_64x256_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ ) } rise_transition(fakeram_64x256_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } fall_transition(fakeram_64x256_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } } } pin(w0_we_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -176,16 +176,16 @@ cell(fakeram_64x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_64x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -196,16 +196,16 @@ cell(fakeram_64x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_64x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -222,7 +222,7 @@ cell(fakeram_64x256_1r1w) { } pin(r0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -230,16 +230,16 @@ cell(fakeram_64x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_64x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -250,16 +250,16 @@ cell(fakeram_64x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_64x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -276,7 +276,7 @@ cell(fakeram_64x256_1r1w) { } pin(w0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -284,16 +284,16 @@ cell(fakeram_64x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_64x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -304,16 +304,16 @@ cell(fakeram_64x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_64x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -335,7 +335,7 @@ cell(fakeram_64x256_1r1w) { clocked_on : "w0_clk"; } direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -343,16 +343,16 @@ cell(fakeram_64x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_64x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -363,16 +363,16 @@ cell(fakeram_64x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_64x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -402,7 +402,7 @@ cell(fakeram_64x256_1r1w) { bus(r0_addr_in) { bus_type : fakeram_64x256_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -410,16 +410,16 @@ cell(fakeram_64x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_64x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -430,16 +430,16 @@ cell(fakeram_64x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_64x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -457,7 +457,7 @@ cell(fakeram_64x256_1r1w) { bus(w0_addr_in) { bus_type : fakeram_64x256_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -465,16 +465,16 @@ cell(fakeram_64x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_64x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -485,16 +485,16 @@ cell(fakeram_64x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_64x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_65x160_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_65x160_1r1w.lib index 8293c213..1aac1375 100644 --- a/designs/gt2n/NVDLA/sram/lib/fakeram_65x160_1r1w.lib +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_65x160_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_65x160_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-08-01 08:31:13Z"; + date : "2026-08-20 05:56:15Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -97,9 +97,9 @@ cell(fakeram_65x160_1r1w) { } pin(r0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_65x160_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -114,9 +114,9 @@ cell(fakeram_65x160_1r1w) { pin(w0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_65x160_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -132,7 +132,7 @@ cell(fakeram_65x160_1r1w) { bus(r0_rd_out) { bus_type : fakeram_65x160_1r1w_DATA; direction : output; - max_capacitance : 0.500; + max_capacitance : 0.0488; memory_read() { address : r0_addr_in; } @@ -142,7 +142,7 @@ cell(fakeram_65x160_1r1w) { timing_sense : non_unate; cell_rise(fakeram_65x160_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ @@ -150,25 +150,25 @@ cell(fakeram_65x160_1r1w) { } cell_fall(fakeram_65x160_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ ) } rise_transition(fakeram_65x160_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } fall_transition(fakeram_65x160_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } } } pin(w0_we_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -176,16 +176,16 @@ cell(fakeram_65x160_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_65x160_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -196,16 +196,16 @@ cell(fakeram_65x160_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_65x160_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -222,7 +222,7 @@ cell(fakeram_65x160_1r1w) { } pin(r0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -230,16 +230,16 @@ cell(fakeram_65x160_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_65x160_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -250,16 +250,16 @@ cell(fakeram_65x160_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_65x160_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -276,7 +276,7 @@ cell(fakeram_65x160_1r1w) { } pin(w0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -284,16 +284,16 @@ cell(fakeram_65x160_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_65x160_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -304,16 +304,16 @@ cell(fakeram_65x160_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_65x160_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -335,7 +335,7 @@ cell(fakeram_65x160_1r1w) { clocked_on : "w0_clk"; } direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -343,16 +343,16 @@ cell(fakeram_65x160_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_65x160_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -363,16 +363,16 @@ cell(fakeram_65x160_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_65x160_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -402,7 +402,7 @@ cell(fakeram_65x160_1r1w) { bus(r0_addr_in) { bus_type : fakeram_65x160_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -410,16 +410,16 @@ cell(fakeram_65x160_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_65x160_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -430,16 +430,16 @@ cell(fakeram_65x160_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_65x160_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -457,7 +457,7 @@ cell(fakeram_65x160_1r1w) { bus(w0_addr_in) { bus_type : fakeram_65x160_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -465,16 +465,16 @@ cell(fakeram_65x160_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_65x160_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -485,16 +485,16 @@ cell(fakeram_65x160_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_65x160_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_66x64_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_66x64_1r1w.lib index bf2d5af9..45f87942 100644 --- a/designs/gt2n/NVDLA/sram/lib/fakeram_66x64_1r1w.lib +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_66x64_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_66x64_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-08-01 08:31:13Z"; + date : "2026-08-20 05:56:15Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -97,9 +97,9 @@ cell(fakeram_66x64_1r1w) { } pin(r0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_66x64_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -114,9 +114,9 @@ cell(fakeram_66x64_1r1w) { pin(w0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_66x64_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -132,7 +132,7 @@ cell(fakeram_66x64_1r1w) { bus(r0_rd_out) { bus_type : fakeram_66x64_1r1w_DATA; direction : output; - max_capacitance : 0.500; + max_capacitance : 0.0488; memory_read() { address : r0_addr_in; } @@ -142,7 +142,7 @@ cell(fakeram_66x64_1r1w) { timing_sense : non_unate; cell_rise(fakeram_66x64_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ @@ -150,25 +150,25 @@ cell(fakeram_66x64_1r1w) { } cell_fall(fakeram_66x64_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ ) } rise_transition(fakeram_66x64_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } fall_transition(fakeram_66x64_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } } } pin(w0_we_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -176,16 +176,16 @@ cell(fakeram_66x64_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_66x64_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -196,16 +196,16 @@ cell(fakeram_66x64_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_66x64_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -222,7 +222,7 @@ cell(fakeram_66x64_1r1w) { } pin(r0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -230,16 +230,16 @@ cell(fakeram_66x64_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_66x64_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -250,16 +250,16 @@ cell(fakeram_66x64_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_66x64_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -276,7 +276,7 @@ cell(fakeram_66x64_1r1w) { } pin(w0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -284,16 +284,16 @@ cell(fakeram_66x64_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_66x64_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -304,16 +304,16 @@ cell(fakeram_66x64_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_66x64_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -335,7 +335,7 @@ cell(fakeram_66x64_1r1w) { clocked_on : "w0_clk"; } direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -343,16 +343,16 @@ cell(fakeram_66x64_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_66x64_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -363,16 +363,16 @@ cell(fakeram_66x64_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_66x64_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -402,7 +402,7 @@ cell(fakeram_66x64_1r1w) { bus(r0_addr_in) { bus_type : fakeram_66x64_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -410,16 +410,16 @@ cell(fakeram_66x64_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_66x64_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -430,16 +430,16 @@ cell(fakeram_66x64_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_66x64_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -457,7 +457,7 @@ cell(fakeram_66x64_1r1w) { bus(w0_addr_in) { bus_type : fakeram_66x64_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -465,16 +465,16 @@ cell(fakeram_66x64_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_66x64_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -485,16 +485,16 @@ cell(fakeram_66x64_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_66x64_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_66x80_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_66x80_1r1w.lib index 41a9d343..5d04ef8a 100644 --- a/designs/gt2n/NVDLA/sram/lib/fakeram_66x80_1r1w.lib +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_66x80_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_66x80_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-08-01 08:31:13Z"; + date : "2026-08-20 05:56:15Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -97,9 +97,9 @@ cell(fakeram_66x80_1r1w) { } pin(r0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_66x80_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -114,9 +114,9 @@ cell(fakeram_66x80_1r1w) { pin(w0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_66x80_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -132,7 +132,7 @@ cell(fakeram_66x80_1r1w) { bus(r0_rd_out) { bus_type : fakeram_66x80_1r1w_DATA; direction : output; - max_capacitance : 0.500; + max_capacitance : 0.0488; memory_read() { address : r0_addr_in; } @@ -142,7 +142,7 @@ cell(fakeram_66x80_1r1w) { timing_sense : non_unate; cell_rise(fakeram_66x80_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ @@ -150,25 +150,25 @@ cell(fakeram_66x80_1r1w) { } cell_fall(fakeram_66x80_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ ) } rise_transition(fakeram_66x80_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } fall_transition(fakeram_66x80_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } } } pin(w0_we_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -176,16 +176,16 @@ cell(fakeram_66x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_66x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -196,16 +196,16 @@ cell(fakeram_66x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_66x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -222,7 +222,7 @@ cell(fakeram_66x80_1r1w) { } pin(r0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -230,16 +230,16 @@ cell(fakeram_66x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_66x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -250,16 +250,16 @@ cell(fakeram_66x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_66x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -276,7 +276,7 @@ cell(fakeram_66x80_1r1w) { } pin(w0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -284,16 +284,16 @@ cell(fakeram_66x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_66x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -304,16 +304,16 @@ cell(fakeram_66x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_66x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -335,7 +335,7 @@ cell(fakeram_66x80_1r1w) { clocked_on : "w0_clk"; } direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -343,16 +343,16 @@ cell(fakeram_66x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_66x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -363,16 +363,16 @@ cell(fakeram_66x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_66x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -402,7 +402,7 @@ cell(fakeram_66x80_1r1w) { bus(r0_addr_in) { bus_type : fakeram_66x80_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -410,16 +410,16 @@ cell(fakeram_66x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_66x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -430,16 +430,16 @@ cell(fakeram_66x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_66x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -457,7 +457,7 @@ cell(fakeram_66x80_1r1w) { bus(w0_addr_in) { bus_type : fakeram_66x80_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -465,16 +465,16 @@ cell(fakeram_66x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_66x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -485,16 +485,16 @@ cell(fakeram_66x80_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_66x80_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_7x256_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_7x256_1r1w.lib index f155b648..08f037e5 100644 --- a/designs/gt2n/NVDLA/sram/lib/fakeram_7x256_1r1w.lib +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_7x256_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_7x256_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-08-01 08:31:13Z"; + date : "2026-08-20 05:56:15Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -97,9 +97,9 @@ cell(fakeram_7x256_1r1w) { } pin(r0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_7x256_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -114,9 +114,9 @@ cell(fakeram_7x256_1r1w) { pin(w0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_7x256_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -132,7 +132,7 @@ cell(fakeram_7x256_1r1w) { bus(r0_rd_out) { bus_type : fakeram_7x256_1r1w_DATA; direction : output; - max_capacitance : 0.500; + max_capacitance : 0.0488; memory_read() { address : r0_addr_in; } @@ -142,7 +142,7 @@ cell(fakeram_7x256_1r1w) { timing_sense : non_unate; cell_rise(fakeram_7x256_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ @@ -150,25 +150,25 @@ cell(fakeram_7x256_1r1w) { } cell_fall(fakeram_7x256_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ ) } rise_transition(fakeram_7x256_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } fall_transition(fakeram_7x256_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } } } pin(w0_we_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -176,16 +176,16 @@ cell(fakeram_7x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_7x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -196,16 +196,16 @@ cell(fakeram_7x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_7x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -222,7 +222,7 @@ cell(fakeram_7x256_1r1w) { } pin(r0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -230,16 +230,16 @@ cell(fakeram_7x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_7x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -250,16 +250,16 @@ cell(fakeram_7x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_7x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -276,7 +276,7 @@ cell(fakeram_7x256_1r1w) { } pin(w0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -284,16 +284,16 @@ cell(fakeram_7x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_7x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -304,16 +304,16 @@ cell(fakeram_7x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_7x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -335,7 +335,7 @@ cell(fakeram_7x256_1r1w) { clocked_on : "w0_clk"; } direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -343,16 +343,16 @@ cell(fakeram_7x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_7x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -363,16 +363,16 @@ cell(fakeram_7x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_7x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -402,7 +402,7 @@ cell(fakeram_7x256_1r1w) { bus(r0_addr_in) { bus_type : fakeram_7x256_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -410,16 +410,16 @@ cell(fakeram_7x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_7x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -430,16 +430,16 @@ cell(fakeram_7x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_7x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -457,7 +457,7 @@ cell(fakeram_7x256_1r1w) { bus(w0_addr_in) { bus_type : fakeram_7x256_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -465,16 +465,16 @@ cell(fakeram_7x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_7x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -485,16 +485,16 @@ cell(fakeram_7x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_7x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } diff --git a/designs/gt2n/NVDLA/sram/lib/fakeram_8x256_1r1w.lib b/designs/gt2n/NVDLA/sram/lib/fakeram_8x256_1r1w.lib index 115b0a53..d6f94caf 100644 --- a/designs/gt2n/NVDLA/sram/lib/fakeram_8x256_1r1w.lib +++ b/designs/gt2n/NVDLA/sram/lib/fakeram_8x256_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_8x256_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-08-01 08:31:13Z"; + date : "2026-08-20 05:56:15Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -97,9 +97,9 @@ cell(fakeram_8x256_1r1w) { } pin(r0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_8x256_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -114,9 +114,9 @@ cell(fakeram_8x256_1r1w) { pin(w0_clk) { direction : input; - capacitance : 0.025; + capacitance : 0.00244; clock : true; - min_period : 0.075 ; + min_period : 0.143 ; internal_power(){ rise_power(fakeram_8x256_1r1w_energy_template_clkslew) { index_1 ("0.005, 0.125"); @@ -132,7 +132,7 @@ cell(fakeram_8x256_1r1w) { bus(r0_rd_out) { bus_type : fakeram_8x256_1r1w_DATA; direction : output; - max_capacitance : 0.500; + max_capacitance : 0.0488; memory_read() { address : r0_addr_in; } @@ -142,7 +142,7 @@ cell(fakeram_8x256_1r1w) { timing_sense : non_unate; cell_rise(fakeram_8x256_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ @@ -150,25 +150,25 @@ cell(fakeram_8x256_1r1w) { } cell_fall(fakeram_8x256_1r1w_mem_out_delay_template) { index_1 ("0.005, 0.125"); - index_2 ("0.005, 0.500"); + index_2 ("0.000488, 0.0488"); values ( \ "0.200, 0.200", \ "0.200, 0.200" \ ) } rise_transition(fakeram_8x256_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } fall_transition(fakeram_8x256_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); + index_1 ("0.000488, 0.0488"); values ("0.005, 0.125") } } } pin(w0_we_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -176,16 +176,16 @@ cell(fakeram_8x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_8x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -196,16 +196,16 @@ cell(fakeram_8x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_8x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -222,7 +222,7 @@ cell(fakeram_8x256_1r1w) { } pin(r0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -230,16 +230,16 @@ cell(fakeram_8x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_8x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -250,16 +250,16 @@ cell(fakeram_8x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_8x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -276,7 +276,7 @@ cell(fakeram_8x256_1r1w) { } pin(w0_ce_in) { direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -284,16 +284,16 @@ cell(fakeram_8x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_8x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -304,16 +304,16 @@ cell(fakeram_8x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_8x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -335,7 +335,7 @@ cell(fakeram_8x256_1r1w) { clocked_on : "w0_clk"; } direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -343,16 +343,16 @@ cell(fakeram_8x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_8x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -363,16 +363,16 @@ cell(fakeram_8x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_8x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -402,7 +402,7 @@ cell(fakeram_8x256_1r1w) { bus(r0_addr_in) { bus_type : fakeram_8x256_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : r0_clk; timing_type : setup_rising ; @@ -410,16 +410,16 @@ cell(fakeram_8x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_8x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -430,16 +430,16 @@ cell(fakeram_8x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_8x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -457,7 +457,7 @@ cell(fakeram_8x256_1r1w) { bus(w0_addr_in) { bus_type : fakeram_8x256_1r1w_ADDRESS; direction : input; - capacitance : 0.005; + capacitance : 0.000488; timing() { related_pin : w0_clk; timing_type : setup_rising ; @@ -465,16 +465,16 @@ cell(fakeram_8x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_8x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } @@ -485,16 +485,16 @@ cell(fakeram_8x256_1r1w) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } fall_constraint(fakeram_8x256_1r1w_constraint_template) { index_1 ("0.005, 0.125"); index_2 ("0.005, 0.125"); values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ + "0.007, 0.007", \ + "0.007, 0.007" \ ) } } diff --git a/designs/gt2n/floonoc/BUILD.bazel b/designs/gt2n/floonoc/BUILD.bazel index ad1e8130..68dc048d 100644 --- a/designs/gt2n/floonoc/BUILD.bazel +++ b/designs/gt2n/floonoc/BUILD.bazel @@ -17,9 +17,7 @@ hightide_design( # Die sized for logic density; io.tcl's pin placement is die-size-parametric # (queries ord::get_die_area at build time), so no manual re-tuning needed # when resizing. Pin-fit floor: 1598 × M3_pitch 0.028 + 2×end_margin(5) = - # 54.7 µm minimum die edge — far below the size used here. See - # scratch_logs/floonoc_gt2n/floonoc_gt2n_qor_comparison.md for the - # utilization/clock tightening sweep that landed on this config. + # 54.7 µm minimum die edge — far below the size used here. "DIE_AREA": "0 0 80 80", "CORE_AREA": "6 6 74 74", "MAX_ROUTING_LAYER": "M11", diff --git a/designs/gt2n/floonoc/io.tcl b/designs/gt2n/floonoc/io.tcl index 590e44a3..6bcc9233 100644 --- a/designs/gt2n/floonoc/io.tcl +++ b/designs/gt2n/floonoc/io.tcl @@ -33,9 +33,9 @@ # ver_offset = WIDTH/2 = 0.007 um (center of first x-track) # ver_pitch = 0.028 um # -# Pin-fit check (129×129 die, end_margin 5.0 um each side → 119 um effective edge): -# top/bottom (M3 vertical, 1598 gaps): 1598 × 0.028 = 44.744 um < 119 um ✓ -# left/right (M2 horizontal, 1598 gaps): 1598 × 0.024 = 38.352 um < 119 um ✓ +# Pin-fit check (80×80 die, end_margin 5.0 um each side → 70 um effective edge): +# top/bottom (M3 vertical, 1598 gaps): 1598 × 0.028 = 44.744 um < 70 um ✓ +# left/right (M2 horizontal, 1598 gaps): 1598 × 0.024 = 38.352 um < 70 um ✓ # # PSM-0069 note: edge_margin is kept at 5.0 um (no sky130hd-style reduction needed). # The gt2n PDN is entirely backside: BPR followpins → BM1 → BM2, with only diff --git a/designs/src/NVDLA/DECISIONS.md b/designs/src/NVDLA/DECISIONS.md index f515650c..ebf2372d 100644 --- a/designs/src/NVDLA/DECISIONS.md +++ b/designs/src/NVDLA/DECISIONS.md @@ -102,18 +102,17 @@ The FF stubs are emitted by `designs/src/NVDLA/dev/gen_ff_rams.py` into `designs ### Configuration - **partition_a** (no macros, FF-array SRAMs): `CORE_UTILIZATION=80`, `PLACE_DENSITY=0.88`, `MAX_ROUTING_LAYER=M11`, `MIN_CLK_ROUTING_LAYER=M4`, `HOLD_SLACK_MARGIN=20`, `SYNTH_MEMORY_MAX_BITS=8192` (4352-bit FF instance trips the ORFS default 4096 cap). Clock: 895 ps (Fmax 1.12 GHz). Die area 4506 µm². -- **partition_c** (65 SRAM macro instances, 2 macro types: `64x256`/`11x128`): `DIE_AREA="0 0 855.792 716.928"`, `CORE_AREA="1.008 1.008 854.784 715.808"`, `MAX_ROUTING_LAYER=M11`, `MIN_CLK_ROUTING_LAYER=M6`, `MACRO_BLOCKAGE_HALO=0.5`. Clock: 1300 ps, achieved Fmax 635.80 MHz. -- **partition_m** (no SRAM macros): `CORE_UTILIZATION=82`, `PLACE_DENSITY=0.87`, `MAX_ROUTING_LAYER=M11`, `MIN_CLK_ROUTING_LAYER=M4`. Clock: 660 ps (Fmax 1.52 GHz). Die area 1334 µm². -- **partition_o** (17 SRAM macro instances, 8 macro types): `CORE_UTILIZATION=46`, `MAX_ROUTING_LAYER=M11`, `MIN_CLK_ROUTING_LAYER=M4`, `MACRO_PLACE_HALO="8 8"`, `HOLD_SLACK_MARGIN=40`. Multi-clock: `nvdla_core_clk` (2270 ps, Fmax 440 MHz) + `nvdla_falcon_clk` tracked at the NVIDIA reference core:falcon ratio (1.25). Die area 54218 µm². -- **partition_p** (6 SRAM macro instances, 4 macro types): `CORE_UTILIZATION=45`, `MAX_ROUTING_LAYER=M11`, `MIN_CLK_ROUTING_LAYER=M6`, `MACRO_PLACE_HALO="5 5"`, `MACRO_BLOCKAGE_HALO=0.5`, `HOLD_SLACK_MARGIN=50`. Clock: 1433 ps (Fmax 698 MHz). Die area 33257 µm². +- **partition_c** (65 SRAM macro instances, 2 macro types: `64x256`/`11x128`): `DIE_AREA="0 0 855.792 716.928"`, `CORE_AREA="1.008 1.008 854.784 715.808"`, `MAX_ROUTING_LAYER=M11`, `MIN_CLK_ROUTING_LAYER=M6`, `MACRO_BLOCKAGE_HALO=0.5`. Clock: 1300 ps, achieved Fmax 673.54 MHz. +- **partition_m** (no SRAM macros): `CORE_UTILIZATION=82`, `PLACE_DENSITY=0.87`, `MAX_ROUTING_LAYER=M11`, `MIN_CLK_ROUTING_LAYER=M4`, `HOLD_SLACK_MARGIN=5`. Clock: 660 ps (Fmax 1.68 GHz). Die area 1334 µm². +- **partition_o** (17 SRAM macro instances, 8 macro types): `CORE_UTILIZATION=46`, `MAX_ROUTING_LAYER=M11`, `MIN_CLK_ROUTING_LAYER=M4`, `MACRO_PLACE_HALO="8 8"`, `HOLD_SLACK_MARGIN=40`. Multi-clock: `nvdla_core_clk` (2270 ps, Fmax 467.90 MHz) + `nvdla_falcon_clk` (2838 ps, Fmax 1736.15 MHz), tracked at the NVIDIA reference core:falcon ratio (1.25). Die area 54218 µm². +- **partition_p** (6 SRAM macro instances, 4 macro types): `CORE_UTILIZATION=45`, `MAX_ROUTING_LAYER=M11`, `MIN_CLK_ROUTING_LAYER=M6`, `MACRO_PLACE_HALO="5 5"`, `MACRO_BLOCKAGE_HALO=0.5`, `HOLD_SLACK_MARGIN=50`. Clock: 1635 ps (Fmax 630.47 MHz). Die area 33257 µm². - `TNS_END_PERCENT=100` on all five. ### Decisions - **asap7 is not a reliable reference for gt2n targets**: gt2n's per-square sheet resistance is dramatically higher than asap7's even at layers with near-identical pitch — e.g. M4 (0.042µm gt2n vs 0.048µm asap7, only ~12.5% apart) is 3.506 Ω/□ on gt2n vs 0.433 Ω/□ on asap7, an 8.1x gap that pitch differences can't explain. This isn't a material story either — gt2n uses ruthenium at the lower layers specifically because it scales better than copper at nanoscale linewidths, so a real process should look relatively *better* here, not 8x worse. The more plausible explanation is that asap7, an older predictive/academic PDK, is simply optimistic on interconnect resistance relative to what a real advanced-node process delivers. Fmax/area achieved on asap7 for the same RTL should not be treated as a dependable target for gt2n. - **FakeRAM cfg**: partitions c/o/p share `fakeram_gt2n.cfg` (14 SRAM macro configs). -- **partition_c**: uses a hand-placed 8×8 SRAM bank grid (`macro_placement.tcl`) and applies an inter-partition I/O delay credit post-CTS (`pre_grt.tcl`) to more realistically model the clock-network latency that boundary signals would see if the partitions were connected as one die. -- **partition_o / partition_p**: several inter-partition boundary signals are zero-logic passthroughs of primary inputs with no on-chip source register in the standalone per-partition build, so the blanket `set_input_delay` under-budgets their true minimum arrival. Both partitions add scoped `-min` overrides on those specific signals in `constraint.sdc`. +- **partition_c**: uses a hand-placed 8×8 SRAM bank grid (`macro_placement.tcl`). `constraint.sdc` sets a blanket input delay (`clk_period * 0.2`) and a fixed −1950 ps output delay credit, modeling the clock-network latency boundary signals would see if the partitions were connected as one die; `pre_grt.tcl` overrides the input delay post-CTS with 1950 ps, since that value exceeds the clock period and would disrupt placement/CTS if applied any earlier. The internal reset synchronizer's async-reset false-paths in `constraint.sdc` match on `q`/`d0`, regs declared directly in NVDLA's `p_SSYNC2DO_C_PP.v` primitive, and error loudly if either net is missing. +- **partition_o / partition_p**: several inter-partition boundary signals are zero-logic passthroughs of primary inputs with no on-chip source register in the standalone per-partition build, so the blanket `set_input_delay` under-budgets their true minimum arrival. Both partitions add scoped `-min` and matching `-max` overrides (kept equal, consistent with the zero-window blanket delay used elsewhere in these SDCs) on those specific signals in `constraint.sdc`. ### Known issues / open questions -- **partition_o**: minor hold violations (8, worst −58.34 ps). -- **partition_c**: incremental hold repair at global routing did not converge within ~18h (run setup-only instead) — may close with more time. +- **partition_c**: 75 setup violations (WNS −184.68 ps) and 2497 hold violations (WNS −529.52 ps) at the 1300 ps target; incremental hold repair at global routing does not converge within ~18h (setup-only repair used instead) — may close further with more time. diff --git a/designs/src/lfsr/DECISIONS.md b/designs/src/lfsr/DECISIONS.md index 6e23b706..893031e4 100644 --- a/designs/src/lfsr/DECISIONS.md +++ b/designs/src/lfsr/DECISIONS.md @@ -78,7 +78,7 @@ The three RTL files are no longer a git submodule + checked-in vendored copy. Th - **bsg_fakeram bump**: gt2n analytical bitcell/timing/pin-layer support. - Reaches `_final` with WNS = 0, 0 DRC violations. Congestion never exceeded ~25% usage on any layer. - **No antenna cells**: gt2n PDK ships no antenna filler cells. GRT-0246 ("no antenna cell found in the design library") fires on every gt2n build — benign; the router uses wire-jumping to resolve antenna violations, reaching 0 antenna DRC violations in the final report. -- **Backside PDN**: gt2n uses BSPDN (BPR followpins → BM1 → BM2 stripes, entirely on the backside stack). Signal layers M1–M13 carry no power. No `pdn.tcl` override is needed for std-cell-only designs — `platforms/gt2n/pdn.cfg` handles BSPDN correctly out of the box. +- **Backside PDN**: gt2n uses BSPDN (BPR followpins → BM1 → BM2 stripes, entirely on the backside stack). Signal layers M1–M13 carry no power. No `pdn.tcl` override is needed for std-cell-only designs — `platforms/gt2n/pdn.tcl` handles BSPDN correctly out of the box. ### Known issues / open questions - None. diff --git a/tools/bsg_fakeram b/tools/bsg_fakeram index d7a0c2e0..2db2c320 160000 --- a/tools/bsg_fakeram +++ b/tools/bsg_fakeram @@ -1 +1 @@ -Subproject commit d7a0c2e099648e6f2290675433240b64ec8832ca +Subproject commit 2db2c32022c9493aba3dda7b9b4d6aad0144538b