diff --git a/docs_src/dslx_std.md b/docs_src/dslx_std.md index 93b8c477ea..6db55e760f 100644 --- a/docs_src/dslx_std.md +++ b/docs_src/dslx_std.md @@ -774,20 +774,42 @@ fn main(x: u32) -> u32 { source (i.e., iverilog). See [google/xls#436](https://github.com/google/xls/issues/436). -The `cover!` built-in tracks how often some condition is satisfied. It desugars -into SystemVerilog cover points. Its signature is: +The `cover!` built-in tracks how often some condition is satisfied. In generated +SystemVerilog it is emitted as a named concurrent `cover property` sampled on +the positive edge of the module clock, of the form: + +``` +