From d21122511f9064b30f4b3a65d0ca09596da0e320 Mon Sep 17 00:00:00 2001 From: hippi345 <13539685+hippi345@users.noreply.github.com> Date: Sat, 17 Oct 2026 01:17:04 +0000 Subject: [PATCH] docs: clarify DSLX cover! as SystemVerilog cover property Document that cover! emits a concurrent cover property in generated SystemVerilog, describe assertion-based coverage, and link related coverage issues. --- docs_src/dslx_std.md | 34 ++++++++++++++++++++++++++++------ 1 file changed, 28 insertions(+), 6 deletions(-) diff --git a/docs_src/dslx_std.md b/docs_src/dslx_std.md index 93b8c477ea..49c650a53d 100644 --- a/docs_src/dslx_std.md +++ b/docs_src/dslx_std.md @@ -774,8 +774,17 @@ fn main(x: u32) -> u32 { source (i.e., iverilog). See [google/xls#436](https://github.com/google/xls/issues/436). -The `cover!` built-in tracks how often some condition is satisfied. It desugars -into SystemVerilog cover points. Its signature is: +The `cover!` built-in tracks how often some condition is satisfied. In generated +SystemVerilog it is emitted as a named concurrent `cover property` sampled on +the positive edge of the module clock, of the form: + +``` +