From 18bdabf8f7e2580c29e399b8de8900c7c1050954 Mon Sep 17 00:00:00 2001 From: Darren Kulp Date: Fri, 2 Jul 2021 15:34:25 -0400 Subject: [PATCH 1/5] Remove changelog entry obsoleted by another one Although it is true that CI support was added for non-x86 architectures, inluding in #36, the Travis-CI implementation of that CI was subsequently removed (#72), so it does not make sense to notate the addition in the Changelog for v0.9.8. --- Changelog.md | 1 - 1 file changed, 1 deletion(-) diff --git a/Changelog.md b/Changelog.md index 0d36b5180..1149d7964 100644 --- a/Changelog.md +++ b/Changelog.md @@ -17,7 +17,6 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 ### Added - Enabled many compiler warnings under Clang and GCC - Introduced a stream-based abstraction layer for filesystem operations -- Enabled CI jobs for additional architectures (arm64, ppc64le, s390x) - Defined the overshifting behavior for the `@` operator - Defined the tenyr assembly grammar in ABNF (#60) - Set up continuous integration using GitHub Actions (#66, #67, #68, #69, #70, #71) From 0584ffd341dba8af3874065c0b55147ae1fd6c90 Mon Sep 17 00:00:00 2001 From: Darren Kulp Date: Fri, 2 Jul 2021 14:31:55 -0400 Subject: [PATCH 2/5] Address bit-width lints from Verilator --- hw/verilog/top.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/verilog/top.v b/hw/verilog/top.v index ff99db8b7..72f2fadb4 100644 --- a/hw/verilog/top.v +++ b/hw/verilog/top.v @@ -70,7 +70,7 @@ module Tenyr( `ifdef SERIAL // TODO write a hardware-compatible serial device ; rename to eliminate `Sim` - SimWrap_simserial #(.BASE(12'h20), .SIZE(2)) serial( + SimWrap_simserial #(.BASE(32'h20), .SIZE(2)) serial( .clk ( clk_core ), .reset ( reset ), .enable ( s_stbcyc ), .rw ( s_wen ), .addr ( s_adr ), .data ( s_ddn ) ); From 70ca174393604ed4cfd4a2108fb8c42fa5e90581 Mon Sep 17 00:00:00 2001 From: Darren Kulp Date: Fri, 2 Jul 2021 14:48:25 -0400 Subject: [PATCH 3/5] Strength the `@` test a bit The amount of entropy tested by the `@` op-test is pretty low, and I have observed on multiple occasions the test passing even when the hardware is not doing its job. The current commit strengthens the randomization test a bit. An even stronger test might ensure that a sole one or zero in a word of zeros or ones is being extracted successfully. --- test/op/at.tas | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/test/op/at.tas b/test/op/at.tas index 0ed35824f..9231653bf 100644 --- a/test/op/at.tas +++ b/test/op/at.tas @@ -1,6 +1,12 @@ C <- [(@args + (0 + 0x1000))] D <- [(@args + (1 + 0x1000))] +# For each instruction type, we test straightforwardly first, and then test +# again after inverting the randomly-generated inputs. +J <- ~C +K <- ~D + D <- D & 31 # overshifting is tested separately +K <- K & 31 # passing until proven broken B <- -1 @@ -13,6 +19,14 @@ E <- E == 1 I <- I == E B <- B & I +I <- J @ K +# test type 0 +E <- J >>> K +E <- E & 1 +E <- E == 1 +I <- I == E +B <- B & I + I <- C @ 3 # test type 1 E <- C >>> 3 @@ -21,6 +35,14 @@ E <- E == 1 I <- I == E B <- B & I +I <- J @ 3 +# test type 1 +E <- J >>> 3 +E <- E & 1 +E <- E == 1 +I <- I == E +B <- B & I + I <- 0x7ef @ D # test type 2 E <- 0x7ef >>> D @@ -29,5 +51,13 @@ E <- E == 1 I <- I == E B <- B & I +I <- 0x7ef @ K +# test type 2 +E <- 0x7ef >>> K +E <- E & 1 +E <- E == 1 +I <- I == E +B <- B & I + illegal From 9c73e7b203ad25384f76a8fb9c5b8cdd2e30343b Mon Sep 17 00:00:00 2001 From: Darren Kulp Date: Fri, 2 Jul 2021 14:52:01 -0400 Subject: [PATCH 4/5] Inline the now-trivial Bit function The purpose of the Bit function, as it was introduced in commit eda7dc4871670e0904a730a7d6ff66e05898028d, was to keep columnar alignment for readability. As of commit f98aba7760018e2edf33956ec2c5dae3ffdb3bbe, the contained expression shrank significantly, but could not be inlined directly since its result width was too wide. Now I recognize that I should have been using bit-indexing instead of bit-shifting anyway, and the silly function can be removed entirely. As a happy side-effect, this change addresses a bit-width lint noted by Verilator. --- hw/verilog/tenyr.v | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/hw/verilog/tenyr.v b/hw/verilog/tenyr.v index d1c261066..d39b6598c 100644 --- a/hw/verilog/tenyr.v +++ b/hw/verilog/tenyr.v @@ -56,10 +56,6 @@ module Exec(input clk, en, output reg done, output reg[31:0] valZ, reg[3:0] rop; reg add, act, staged; - function Bit(input[31:0] rA, rB); - Bit = rA >> rB; - endfunction - always @(posedge clk) begin { rop , valZ , rA , rB , rC , done , add , act , staged } <= { op , rZ , valA , valB , valC , add , act , staged , en } ; @@ -70,7 +66,7 @@ module Exec(input clk, en, output reg done, output reg[31:0] valZ, 4'h3: rY <= (rA >>> rB) ; 4'hb: rY <= (rA >> rB ); 4'h4: rY <= (rA + rB) ; 4'hc: rY <= (rA - rB ); 4'h5: rY <= (rA * rB) ; 4'hd: rY <= (rA << rB ); - 4'h6: rY <= {32{rA == rB}}; 4'he: rY <= {32{Bit(rA, rB)}}; + 4'h6: rY <= {32{rA == rB}}; 4'he: rY <= {32{rA [rB] }}; 4'h7: rY <= {32{rA < rB}}; 4'hf: rY <= {32{rA >= rB }}; endcase if (act) rZ <= rY + rC; From 2e75e7f9373fd631e683014f160d9b788d08ab69 Mon Sep 17 00:00:00 2001 From: Darren Kulp Date: Fri, 2 Jul 2021 14:58:45 -0400 Subject: [PATCH 5/5] Address missing-pin lints from Verilator --- hw/verilog/top.v | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/hw/verilog/top.v b/hw/verilog/top.v index 72f2fadb4..d54e3d17f 100644 --- a/hw/verilog/top.v +++ b/hw/verilog/top.v @@ -22,7 +22,8 @@ module Tenyr( tenyr_mainclock clocks( .clk_in ( clk ), .clk_core ( clk_core ), - .reset ( reset ), .clk_vga ( clk_vga ) + .reset ( reset ), .clk_vga ( clk_vga ), + .locked ( ) ); Core core( @@ -51,13 +52,13 @@ module Tenyr( TwoPortRAM #(.LOADH(1), .LOADFILE(LOADFILE), .INIT(0), .PBITS(32), .ABITS(RAMABITS), .OFFSET(`RESETVECTOR) ) ram( - .clka ( clk_core ), .clkb ( 1'b0 ), - .ena ( r_stb ), .enb ( 1'b0 ), - .acka ( r_ack ), - .wea ( r_wen ), - .addra ( r_adr ), - .dina ( r_ddn ), - .douta ( r_dup ) + .clka ( clk_core ), .clkb ( '0 ), + .ena ( r_stb ), .enb ( '0 ), + .acka ( r_ack ), .ackb ( ), + .wea ( r_wen ), .web ( '0 ), + .addra ( r_adr ), .addrb ( '0 ), + .dina ( r_ddn ), .dinb ( '0 ), + .douta ( r_dup ), .doutb ( ) ); // ----------------------------------------------------------------------------- @@ -153,8 +154,10 @@ module Tenyr( .wbs_cyc_o ({ o_cyc, g_cyc, v_cyc, s_cyc, r_cyc, x_cyc }), // unused ports - .wbm_cti_i ( 3'bz ), - .wbm_bte_i ( 2'bz ) + .wbm_cti_i ( '0 ), + .wbm_bte_i ( '0 ), + .wbs_cti_o ( ), + .wbs_bte_o ( ) ); endmodule