diff --git a/.gitignore b/.gitignore
index 24ecd3f..32d4ccc 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,3 +1,6 @@
+```markdown
+Pocket-LLM/compiler/README.md
+doc/ARCHITECTURE.md
 ```
 # Logs and temp files
 *.log
diff --git a/Pocket-LLM/compiler/README.md b/Pocket-LLM/compiler/README.md
index d0b2d7b..4a47ca1 100644
--- a/Pocket-LLM/compiler/README.md
+++ b/Pocket-LLM/compiler/README.md
@@ -20,18 +20,18 @@ The Pocket-LLM compiler bridges the gap between large language models and hardwa
 |    4096)                                 |
 |  - Float32 precision                     |
 +------------------------------------------+
-                    |
-                    | Weight extraction
-                    v
+                     |
+                     | Weight extraction
+                     v
 +------------------------------------------+
 |  OCCP Compiler (this directory)          |
 |  - Tiling (4096x4096 -> 2x2 blocks)      |
 |  - Quantization (Float32 -> INT8)        |
 |  - Binary serialization                  |
 +------------------------------------------+
-                    |
-                    | compiled_model.bin
-                    v
+                     |
+                     | compiled_model.bin
+                     v
 +------------------------------------------+
 |  OCCP Hardware Bridge (C Driver)         |
 |  - Streams tiles to silicon              |
@@ -50,7 +50,7 @@ The Pocket-LLM compiler bridges the gap between large language models and hardwa
 ## Files
 
 | File | Purpose |
-|------|---------|
+|------|----------|
 | `occp_compiler.py` | Main compiler implementation |
 | `README.md` | This documentation file |
 
diff --git a/doc/ARCHITECTURE.md b/doc/ARCHITECTURE.md
index d6f93fa..52c0619 100644
--- a/doc/ARCHITECTURE.md
+++ b/doc/ARCHITECTURE.md
@@ -41,6 +41,7 @@ The compilation artifacts from **Pocket-LLM** directly feed into the core hardwa
                                                  +---------------------------+
 ```
 
+For the low-level silicon implementation and C-Driver specifications, please refer to the main repository: [Open-Cognitive-Core](https://github.com/mathcode220-math/open-cognitive-core).
 For the low-level silicon implementation and C-Driver specifications, please refer to the main repository: [Pocket-LLM](https://github.com/mathcode220-math/-Pocket-LLM-).
 
 ## System Architecture
@@ -50,10 +51,10 @@ For the low-level silicon implementation and C-Driver specifications, please ref
 |                     AXI4-Lite Control Bus                         |
 |  (RISC-V / CPU Control Interface)                                |
 +------------------------------------------------------------------+
-                              |
-        +---------------------+---------------------+
-        |                                           |
-        v                                           v
+                               |
+         +---------------------+---------------------+
+         |                                           |
+         v                                           v
 +-------------------+                   +-------------------+
 |   HDC Subsystem   |                   |   ML Subsystem    |
 |                   |                   |                   |
@@ -69,15 +70,15 @@ For the low-level silicon implementation and C-Driver specifications, please ref
 |  +-------------+  |                   |  +-------------+  |
 |                   |                   |        |          |
 +-------------------+                   |        v          |
-                                        |  +-------------+  |
-                                        |  | ReLU        |  |
-                                        |  +-------------+  |
-                                        |        |          |
-                                        |        v          |
-                                        |  +-------------+  |
-                                        |  | Softmax     |  |
-                                        |  +-------------+  |
-                                        +-------------------+
+                                         |  +-------------+  |
+                                         |  | ReLU        |  |
+                                         |  +-------------+  |
+                                         |        |          |
+                                         |        v          |
+                                         |  +-------------+  |
+                                         |  | Softmax     |  |
+                                         |  +-------------+  |
+                                         +-------------------+
 ```
 
 ## Module Descriptions
diff --git a/sim/Makefile b/sim/Makefile
index 373047d..440b928 100644
--- a/sim/Makefile
+++ b/sim/Makefile
@@ -39,41 +39,41 @@ XSIM_FLAGS := -nolog -norecompile
 all: verilator
 
 verilator: $(BUILD_DIR)/V$(TOP_MODULE)
-@echo "✓ Simulation binary ready: $(BUILD_DIR)/V$(TOP_MODULE)"
+	@echo "✓ Simulation binary ready: $(BUILD_DIR)/V$(TOP_MODULE)"
 
 $(BUILD_DIR)/V$(TOP_MODULE): $(RTL_SRCS) $(TB_SRCS)
-@mkdir -p $(BUILD_DIR)
-verilator $(VERILATOR_FLAGS) \
-$(RTL_SRCS) $(TB_SRCS)
-$(MAKE) -C $(OBJ_DIR) -f V$(TOP_MODULE).mk
+	@mkdir -p $(BUILD_DIR)
+	verilator $(VERILATOR_FLAGS) \
+	$(RTL_SRCS) $(TB_SRCS)
+	$(MAKE) -C $(OBJ_DIR) -f V$(TOP_MODULE).mk
 
 run-verilator: $(BUILD_DIR)/V$(TOP_MODULE)
-$(BUILD_DIR)/V$(TOP_MODULE)
+	$(BUILD_DIR)/V$(TOP_MODULE)
 
 xsim: 
-@echo "Compiling with XSIM (Vivado)..."
-xvlog $(RTL_SRCS) $(TB_SRCS)
-xelab $(XSIM_FLAGS) $(TOP_MODULE)
-xsim $(TOP_MODULE) $(XSIM_FLAGS)
+	@echo "Compiling with XSIM (Vivado...)"
+	xvlog $(RTL_SRCS) $(TB_SRCS)
+	xelab $(XSIM_FLAGS) $(TOP_MODULE)
+	xsim $(TOP_MODULE) $(XSIM_FLAGS)
 
 clean:
-rm -rf $(BUILD_DIR) *.log *.jou xelab.* xsim.dir/ *.wdb
+	rm -rf $(BUILD_DIR) *.log *.jou xelab.* xsim.dir/ *.wdb
 
 help:
-@echo "Open Cognitive Core Project - Build System"
-@echo "============================================="
-@echo ""
-@echo "Usage:"
-@echo "  make              - Build with Verilator (default)"
-@echo "  make verilator    - Build with Verilator"
-@echo "  make xsim         - Build with XSIM (Vivado)"
-@echo "  make run-verilator - Run Verilator simulation"
-@echo "  make clean        - Remove build artifacts"
-@echo ""
-@echo "Environment Variables:"
-@echo "  SIM=<tool>        - Select simulator (verilator|xsim)"
-@echo "  TOP_MODULE=<name> - Top module for simulation"
-@echo ""
-@echo "Examples:"
-@echo "  make TOP_MODULE=tb_softmax"
-@echo "  make xsim TOP_MODULE=tb_axi4_lite"
+	@echo "Open Cognitive Core Project - Build System"
+	@echo "============================================="
+	@echo ""
+	@echo "Usage:"
+	@echo "  make              - Build with Verilator (default)"
+	@echo "  make verilator    - Build with Verilator"
+	@echo "  make xsim         - Build with XSIM (Vivado)"
+	@echo "  make run-verilator - Run Verilator simulation"
+	@echo "  make clean        - Remove build artifacts"
+	@echo ""
+	@echo "Environment Variables:"
+	@echo "  SIM=<tool>        - Select simulator (verilator|xsim)"
+	@echo "  TOP_MODULE=<name> - Top module for simulation"
+	@echo ""
+	@echo "Examples:"
+	@echo "  make TOP_MODULE=tb_softmax"
+	@echo "  make xsim TOP_MODULE=tb_axi4_lite"
diff --git a/sw/README.md b/sw/README.md
index 1d53edf..7a672d0 100644
--- a/sw/README.md
+++ b/sw/README.md
@@ -19,18 +19,18 @@ The OCCP co-processor is designed in SystemVerilog and communicates via the **AX
 |  - Model weights                         |
 |  - Inference requests                    |
 +------------------------------------------+
-                    |
-                    | float matrices
-                    v
+                     |
+                     | float matrices
+                     v
 +------------------------------------------+
 |  OCCP Bridge API (this directory)        |
 |  - occp_init()                           |
 |  - occp_dispatch_matrix_multiply()       |
 |  - occp_reset()                          |
 +------------------------------------------+
-                    |
-                    | AXI4-Lite transactions
-                    v
+                     |
+                     | AXI4-Lite transactions
+                     v
 +------------------------------------------+
 |  OCCP Silicon Co-Processor (../rtl/)     |
 |  - axi4_lite_core_ctrl.sv                |
@@ -42,7 +42,7 @@ The OCCP co-processor is designed in SystemVerilog and communicates via the **AX
 ## Files
 
 | File | Purpose |
-|------|---------|
+|------|----------|
 | `occp_bridge.h` | Public API header with register definitions |
 | `occp_bridge.c` | Driver implementation with simulation support |
 | `Makefile` | Build system for compilation and testing |