From 18ded4951279b81a065e32895eeb7679026449d9 Mon Sep 17 00:00:00 2001 From: Ram Sargar Date: Mon, 28 Sep 2026 18:08:53 +0530 Subject: [PATCH 1/8] Revert "QCLINUX: arm64: dts: qcom: lemans: Add RTSS Mailbox device tree overlay" This reverts commit f9e0c595ae6b2cf49eb01626284000621aea0fa7. The original overlay accessed the APSS TCSR mutex/status registers via direct memory-mapped reg ranges and shipped RTSS as a standalone lemans-rtss-mb.dtso overlay. Upstream review feedback on this design requires: - Accessing the TCSR registers via a syscon phandle instead of a direct reg-mapped node. - Folding the RTSS mailbox node into the shared lemans-staging.dtso overlay instead of a separate, RTSS-only DTBO. The following commits reintroduce this support using that syscon-based, staging-overlay design. Signed-off-by: Ram Sargar --- arch/arm64/boot/dts/qcom/Makefile | 1 - arch/arm64/boot/dts/qcom/lemans-rtss-mb.dtso | 65 -------------------- 2 files changed, 66 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/lemans-rtss-mb.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 45f7c4449ae94..4f531ebe2f792 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -541,7 +541,6 @@ dtb-$(CONFIG_ARCH_QCOM) += lemans-camx-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-staging.dtbo -dtb-$(CONFIG_ARCH_QCOM) += lemans-rtss-mb.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-staging.dtbo monaco-evk-camx-dtbs := monaco-evk.dtb monaco-evk-camx.dtbo diff --git a/arch/arm64/boot/dts/qcom/lemans-rtss-mb.dtso b/arch/arm64/boot/dts/qcom/lemans-rtss-mb.dtso deleted file mode 100644 index b1d8996c9ea8b..0000000000000 --- a/arch/arm64/boot/dts/qcom/lemans-rtss-mb.dtso +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -/dts-v1/; -/plugin/; - -#include -#include -#include - -&soc { - ipcc_computeL1: qcom,ipcc@488000 { - compatible = "qcom,ipcc"; - reg = <0x0 0x00488000 0x0 0x1000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - #mbox-cells = <2>; - num_mbox_chans = <5>; - }; - - rtss_mailbox: rtss-mailbox@1ffe02c { - compatible = "qcom,rtss-mailbox"; - reg = <0x0 0x01ffe02c 0x0 0x10>, - <0x0 0x01ffd018 0x0 0x10>, - <0x0 0x17c0000c 0x0 0x04>; - mboxes = <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x2>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS1 0x3>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x4>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x5>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x6>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x7>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS2 0x8>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS1 0x9>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS2 0xa>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS1 0xb>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0xc>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0xd>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS1 0xe>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS2 0xf>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS3 0x10>; - memory-region = <&sail_mailbox_mem>, - <&sail_ota_mem>; - interrupt-parent = <&ipcc_computeL1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - rtss-handshake-delay = <50000>; - status = "okay"; - }; -}; From dba6eddf543bfaa0ddf8837515359676b65de618 Mon Sep 17 00:00:00 2001 From: Ram Sargar Date: Mon, 28 Sep 2026 18:09:24 +0530 Subject: [PATCH 2/8] Revert "QCLINUX: arm64: dts: qcom: Monaco: Add RTSS Mailbox device tree overlay" This reverts commit 5c6149c05f6ce5a14a7c10fe4bc8d54fdb05ea88. Same as the lemans overlay, the original Monaco overlay accessed the APSS TCSR mutex/status registers via direct memory-mapped reg ranges and shipped RTSS as a standalone monaco-rtss-mb.dtso overlay. Upstream review feedback on this design requires: - Accessing the TCSR registers via a syscon phandle instead of a direct reg-mapped node. - Folding the RTSS mailbox node into the shared monaco-staging.dtso overlay instead of a separate, RTSS-only DTBO. The following commits reintroduce this support using that syscon-based, staging-overlay design. Signed-off-by: Ram Sargar --- arch/arm64/boot/dts/qcom/Makefile | 1 - arch/arm64/boot/dts/qcom/monaco-rtss-mb.dtso | 65 -------------------- 2 files changed, 66 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/monaco-rtss-mb.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 4f531ebe2f792..5d32b06cf2d7a 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -553,7 +553,6 @@ monaco-camx-el2-dtbs := monaco-evk-el2.dtb monaco-evk-camx.dtbo monaco-camx-el2. dtb-$(CONFIG_ARCH_QCOM) += monaco-camx-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-staging.dtbo -dtb-$(CONFIG_ARCH_QCOM) += monaco-rtss-mb.dtbo dtb-$(CONFIG_ARCH_QCOM) += monaco-staging.dtbo diff --git a/arch/arm64/boot/dts/qcom/monaco-rtss-mb.dtso b/arch/arm64/boot/dts/qcom/monaco-rtss-mb.dtso deleted file mode 100644 index b1d8996c9ea8b..0000000000000 --- a/arch/arm64/boot/dts/qcom/monaco-rtss-mb.dtso +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -/dts-v1/; -/plugin/; - -#include -#include -#include - -&soc { - ipcc_computeL1: qcom,ipcc@488000 { - compatible = "qcom,ipcc"; - reg = <0x0 0x00488000 0x0 0x1000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - #mbox-cells = <2>; - num_mbox_chans = <5>; - }; - - rtss_mailbox: rtss-mailbox@1ffe02c { - compatible = "qcom,rtss-mailbox"; - reg = <0x0 0x01ffe02c 0x0 0x10>, - <0x0 0x01ffd018 0x0 0x10>, - <0x0 0x17c0000c 0x0 0x04>; - mboxes = <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x2>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS1 0x3>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x4>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x5>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x6>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x7>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS2 0x8>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS1 0x9>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS2 0xa>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS1 0xb>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0xc>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0xd>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS1 0xe>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS2 0xf>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS3 0x10>; - memory-region = <&sail_mailbox_mem>, - <&sail_ota_mem>; - interrupt-parent = <&ipcc_computeL1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - rtss-handshake-delay = <50000>; - status = "okay"; - }; -}; From 2bf291cb69c69de2472c60491f99dfb8ccbe43ae Mon Sep 17 00:00:00 2001 From: Ram Sargar Date: Fri, 18 Sep 2026 05:17:35 +0530 Subject: [PATCH 3/8] QCLINUX: dt-bindings: mfd: Add qcom,apsshm-shared-intu schema Add DT schema for the Qualcomm APSS Shared Memory Interrupt Notification Unit (apsshm-shared-intu) syscon block. This block is used to trigger doorbell interrupts that notify special event notifications to one or more subsystems such as RTSS. Signed-off-by: Ram Sargar (cherry picked from commit bc4441b6380a5cba921bffa9d376d0aca754abc4) --- .../bindings/mfd/qcom,apsshm-shared-intu.yaml | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/qcom,apsshm-shared-intu.yaml diff --git a/Documentation/devicetree/bindings/mfd/qcom,apsshm-shared-intu.yaml b/Documentation/devicetree/bindings/mfd/qcom,apsshm-shared-intu.yaml new file mode 100644 index 0000000000000..6178be887c4b7 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/qcom,apsshm-shared-intu.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/qcom,apsshm-shared-intu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm APSS Shared Memory Interrupt Notification Unit registers + +maintainers: + - Ram Sargar + +description: + A block of SoC-level APSS HM CSR registers used to trigger doorbells that + notify special event notifications to one or more subsystems within SOC. + +properties: + compatible: + items: + - enum: + - qcom,sa8775p-apsshm-shared-intu + - qcom,qcs8300-apsshm-shared-intu + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + apsshm_shared_intu: syscon@17c00000 { + compatible = "qcom,sa8775p-apsshm-shared-intu", "syscon"; + reg = <0x0 0x17c00000 0x0 0x38>; + }; From 3189e4fbf8054405c40ec414069178c05ef75d41 Mon Sep 17 00:00:00 2001 From: Ram Sargar Date: Thu, 10 Sep 2026 02:51:28 +0530 Subject: [PATCH 4/8] QCLINUX: dt-bindings: mailbox: Add qcom,rtss-mailbox schema Add the DT schema for the RTSS mailbox, which exposes a shared-memory and IPCC doorbell channel between the application processor and the RTSS subsystem, and manages the boot/suspend handshake with RTSS. Signed-off-by: Ram Sargar (cherry picked from commit 746c85e2b945cda030f5f10041cc6d6643b3c740) --- .../bindings/mailbox/qcom,rtss-mailbox.yaml | 99 +++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/qcom,rtss-mailbox.yaml diff --git a/Documentation/devicetree/bindings/mailbox/qcom,rtss-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/qcom,rtss-mailbox.yaml new file mode 100644 index 0000000000000..f223dc91eb392 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/qcom,rtss-mailbox.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/qcom,rtss-mailbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. RTSS Mailbox + +maintainers: + - Ram Sargar + +description: + The RTSS mailbox exposes a shared-memory and IPCC doorbell channel between + the application processor and the RTSS subsystem, and manages handshake + with the RTSS subsystem to handle different milestones in mission mode. + +properties: + compatible: + items: + - enum: + - qcom,sa8775p-rtss-mailbox + - qcom,qcs8300-rtss-mailbox + - const: qcom,rtss-mailbox + + qcom,syscon-tcsr-req: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the TCSR syscon node + - description: offset of the RTSS request register from the syscon base + description: + Reference to the TCSR syscon node and register offset used to write + the boot/suspend handshake magic that RTSS reads. + + qcom,syscon-tcsr-resp: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the TCSR syscon node + - description: offset of the RTSS response register from the syscon base + description: + Reference to the TCSR syscon node and register offset used to read + back the handshake magic RTSS acknowledges with. + + qcom,syscon-ipc: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the APSS shared IPC syscon node + - description: offset of the IPC trigger register from the syscon base + description: + Reference to the syscon node and register offset used to trigger the + IPC interrupt that notifies RTSS a TCSR handshake register was updated. + + mboxes: + description: + IPCC mailbox channels used to send interrupts to the RTSS-facing IPCC + client/signal pairs. + + interrupts-extended: + description: + IPCC channels used to receive interrupts from the RTSS-facing IPCC + client/signal pairs. + + memory-region: + items: + - description: reserved-memory carveout for the RTSS mailbox descriptor region + - description: reserved-memory carveout for the OTA region + description: + Reference to the reserved-memory regions used for the mailbox + descriptor and for OTA. + +required: + - compatible + - qcom,syscon-tcsr-req + - qcom,syscon-tcsr-resp + - qcom,syscon-ipc + - mboxes + - interrupts-extended + - memory-region + +additionalProperties: false + +examples: + - | + #include + #include + + rtss-ipcc-mailbox { + compatible = "qcom,sa8775p-rtss-mailbox", "qcom,rtss-mailbox"; + qcom,syscon-tcsr-req = <&tcsr 0x3e02c>; + qcom,syscon-tcsr-resp = <&tcsr 0x3d018>; + qcom,syscon-ipc = <&apsshm_shared_intu 0xc>; + mboxes = <&ipcc1 IPCC_CLIENT_RTSS0 0x2>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x3>; + interrupts-extended = <&ipcc1 IPCC_CLIENT_RTSS0 0x2 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x3 IRQ_TYPE_EDGE_RISING>; + memory-region = <&sail_mailbox_mem>, <&sail_ota_mem>; + }; From 71ebbdaf920973dbee487b849380d52970a29996 Mon Sep 17 00:00:00 2001 From: Ram Sargar Date: Thu, 10 Sep 2026 02:47:17 +0530 Subject: [PATCH 5/8] QCLINUX: arm64: dts: qcom: lemans: Add IPCC and syscon nodes for RTSS Mailbox Add ipcc1-4 mailbox nodes, widen the tcsr syscon's reg range to cover both TCSR request/response registers, and add the apss_shared_ipc syscon node for the Lemans platform. These back the syscon/mbox phandle references used by the Lemans RTSS mailbox node (qcom,rtss-mailbox). Signed-off-by: Ram Sargar (cherry picked from commit 495968715f30bf12e50ea71adf1b7db9ffd3c750) --- arch/arm64/boot/dts/qcom/lemans.dtsi | 43 +++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 8f74aeb579d7c..2c74b29bd41c0 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -1112,6 +1112,42 @@ #mbox-cells = <2>; }; + ipcc1: mailbox@488000 { + compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; + reg = <0x0 0x00488000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + ipcc2: mailbox@4a1000 { + compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; + reg = <0x0 0x004a1000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + ipcc3: mailbox@4a2000 { + compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; + reg = <0x0 0x004a2000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + ipcc4: mailbox@4a3000 { + compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; + reg = <0x0 0x004a3000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + qfprom: efuse@784000 { compatible = "qcom,sa8775p-qfprom", "qcom,qfprom"; reg = <0x0 0x00784000 0x0 0x3000>; @@ -4446,7 +4482,7 @@ tcsr: syscon@1fc0000 { compatible = "qcom,sa8775p-tcsr", "syscon"; - reg = <0x0 0x1fc0000 0x0 0x30000>; + reg = <0x0 0x1fc0000 0x0 0x40000>; }; gpu: gpu@3d00000 { @@ -6824,6 +6860,11 @@ redistributor-stride = <0x0 0x20000>; }; + apsshm_shared_intu: syscon@17c00000 { + compatible = "qcom,sa8775p-apsshm-shared-intu", "syscon"; + reg = <0x0 0x17c00000 0x0 0x38>; + }; + watchdog@17c10000 { compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt"; reg = <0x0 0x17c10000 0x0 0x1000>; From b131cab1befaba68999bc28225dd8d7d56207312 Mon Sep 17 00:00:00 2001 From: Ram Sargar Date: Thu, 10 Sep 2026 02:49:11 +0530 Subject: [PATCH 6/8] QCLINUX: arm64: dts: qcom: lemans-staging: Add rtss-mailbox node Add the rtss_mailbox overlay node for the Lemans platform, using ipcc1-ipcc4 and the tcsr/apss_shared_ipc syscon nodes. Place it under &soc, alongside the other simple-bus child nodes in this file. Signed-off-by: Ram Sargar (cherry picked from commit ffc450f489ed42d2c383ccd419c0757398ee8d23) --- arch/arm64/boot/dts/qcom/lemans-staging.dtso | 41 ++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-staging.dtso b/arch/arm64/boot/dts/qcom/lemans-staging.dtso index d09d8dba42a37..c458b9d17b992 100644 --- a/arch/arm64/boot/dts/qcom/lemans-staging.dtso +++ b/arch/arm64/boot/dts/qcom/lemans-staging.dtso @@ -8,9 +8,50 @@ /dts-v1/; /plugin/; #include +#include #include +#include &soc { + rtss_mailbox: rtss-ipcc-mailbox { + compatible = "qcom,sa8775p-rtss-mailbox", "qcom,rtss-mailbox"; + qcom,syscon-tcsr-req = <&tcsr 0x3e02c>; + qcom,syscon-tcsr-resp = <&tcsr 0x3d018>; + qcom,syscon-ipc = <&apsshm_shared_intu 0xc>; + mboxes = <&ipcc1 IPCC_CLIENT_RTSS0 0x2>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x3>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x4>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x5>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x6>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x7>, + <&ipcc1 IPCC_CLIENT_RTSS2 0x8>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x9>, + <&ipcc1 IPCC_CLIENT_RTSS2 0xa>, + <&ipcc1 IPCC_CLIENT_RTSS1 0xb>, + <&ipcc1 IPCC_CLIENT_RTSS0 0xc>, + <&ipcc1 IPCC_CLIENT_RTSS0 0xd>, + <&ipcc1 IPCC_CLIENT_RTSS1 0xe>, + <&ipcc1 IPCC_CLIENT_RTSS2 0xf>, + <&ipcc1 IPCC_CLIENT_RTSS3 0x10>; + interrupts-extended = <&ipcc1 IPCC_CLIENT_RTSS0 0x2 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x3 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x4 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x5 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x6 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x7 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS2 0x8 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x9 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS2 0xa IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS1 0xb IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0xc IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0xd IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS1 0xe IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS2 0xf IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS3 0x10 IRQ_TYPE_EDGE_RISING>; + memory-region = <&sail_mailbox_mem>, + <&sail_ota_mem>; + }; + tgu@4b0e000 { compatible = "qcom,tgu", "arm,primecell"; reg = <0x0 0x4b0e000 0x0 0x1000>; From 8b1c15a8ef1b4b36ef2c4f873900f5a1c9d05bc4 Mon Sep 17 00:00:00 2001 From: Ram Sargar Date: Thu, 10 Sep 2026 02:50:00 +0530 Subject: [PATCH 7/8] QCLINUX: arm64: dts: qcom: monaco: Add IPCC, syscon, and memory nodes for RTSS Mailbox Add ipcc1-4 mailbox nodes, widen the tcsr syscon's reg range to cover both TCSR request/response registers, and add the apss_shared_ipc syscon node for the Monaco platform. These back the syscon/mbox phandle references used by the Monaco RTSS mailbox node (qcom,rtss-mailbox). Reserve the memory regions used by the SAIL/RTSS subsystem for its TZ mailbox, shared-memory mailbox, and OTA buffer on Monaco. These regions back the memory-region references used by the Monaco RTSS mailbox node. Signed-off-by: Ram Sargar (cherry picked from commit e8cda0f46a9713e3dc91280f8aff212b610f9311) --- arch/arm64/boot/dts/qcom/monaco.dtsi | 58 +++++++++++++++++++++++++++- 1 file changed, 57 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index c51b7d429c36e..071ed465db61b 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -793,6 +793,21 @@ hwlocks = <&tcsr_mutex 3>; }; + tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 { + reg = <0x0 0x90c00000 0x0 0x100000>; + no-map; + }; + + sail_mailbox_mem: sail-ss@90d00000 { + reg = <0x0 0x90d00000 0x0 0x100000>; + no-map; + }; + + sail_ota_mem: sail-ss@90e00000 { + reg = <0x0 0x90e00000 0x0 0x300000>; + no-map; + }; + gunyah_md_mem: gunyah-md-region@91a80000 { reg = <0x0 0x91a80000 0x0 0x80000>; no-map; @@ -964,6 +979,42 @@ #mbox-cells = <2>; }; + ipcc1: mailbox@488000 { + compatible = "qcom,qcs8300-ipcc", "qcom,ipcc"; + reg = <0x0 0x00488000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + ipcc2: mailbox@4a1000 { + compatible = "qcom,qcs8300-ipcc", "qcom,ipcc"; + reg = <0x0 0x004a1000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + ipcc3: mailbox@4a2000 { + compatible = "qcom,qcs8300-ipcc", "qcom,ipcc"; + reg = <0x0 0x004a2000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + ipcc4: mailbox@4a3000 { + compatible = "qcom,qcs8300-ipcc", "qcom,ipcc"; + reg = <0x0 0x004a3000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + qfprom: efuse@784000 { compatible = "qcom,qcs8300-qfprom", "qcom,qfprom"; reg = <0x0 0x00784000 0x0 0x2410>; @@ -2747,7 +2798,7 @@ tcsr: syscon@1fc0000 { compatible = "qcom,qcs8300-tcsr", "syscon"; - reg = <0x0 0x1fc0000 0x0 0x30000>; + reg = <0x0 0x1fc0000 0x0 0x40000>; }; remoteproc_adsp: remoteproc@3000000 { @@ -7364,6 +7415,11 @@ redistributor-stride = <0x0 0x20000>; }; + apsshm_shared_intu: syscon@17c00000 { + compatible = "qcom,qcs8300-apsshm-shared-intu", "syscon"; + reg = <0x0 0x17c00000 0x0 0x38>; + }; + watchdog@17c10000 { compatible = "qcom,apss-wdt-qcs8300", "qcom,kpss-wdt"; reg = <0x0 0x17c10000 0x0 0x1000>; From 96841104b8c7f5563b58f1713281bc388641e877 Mon Sep 17 00:00:00 2001 From: Ram Sargar Date: Thu, 10 Sep 2026 02:51:04 +0530 Subject: [PATCH 8/8] QCLINUX: arm64: dts: qcom: monaco-staging: Add rtss-mailbox node Add the rtss_mailbox overlay node for the Monaco platform, mirroring the Lemans RTSS mailbox node. Place it under &soc, alongside the other simple-bus child nodes in this file. Signed-off-by: Ram Sargar (cherry picked from commit 3ae6ea8d823ba9fa2764b762323d9318921c52d1) --- arch/arm64/boot/dts/qcom/monaco-staging.dtso | 42 ++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-staging.dtso b/arch/arm64/boot/dts/qcom/monaco-staging.dtso index fc44741b8caab..ad3c0662cd561 100644 --- a/arch/arm64/boot/dts/qcom/monaco-staging.dtso +++ b/arch/arm64/boot/dts/qcom/monaco-staging.dtso @@ -7,8 +7,50 @@ /dts-v1/; /plugin/; +#include +#include +#include &soc { + rtss_mailbox: rtss-ipcc-mailbox { + compatible = "qcom,qcs8300-rtss-mailbox", "qcom,rtss-mailbox"; + qcom,syscon-tcsr-req = <&tcsr 0x3e02c>; + qcom,syscon-tcsr-resp = <&tcsr 0x3d018>; + qcom,syscon-ipc = <&apsshm_shared_intu 0xc>; + mboxes = <&ipcc1 IPCC_CLIENT_RTSS0 0x2>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x3>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x4>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x5>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x6>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x7>, + <&ipcc1 IPCC_CLIENT_RTSS2 0x8>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x9>, + <&ipcc1 IPCC_CLIENT_RTSS2 0xa>, + <&ipcc1 IPCC_CLIENT_RTSS1 0xb>, + <&ipcc1 IPCC_CLIENT_RTSS0 0xc>, + <&ipcc1 IPCC_CLIENT_RTSS0 0xd>, + <&ipcc1 IPCC_CLIENT_RTSS1 0xe>, + <&ipcc1 IPCC_CLIENT_RTSS2 0xf>, + <&ipcc1 IPCC_CLIENT_RTSS3 0x10>; + interrupts-extended = <&ipcc1 IPCC_CLIENT_RTSS0 0x2 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x3 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x4 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x5 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x6 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x7 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS2 0x8 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x9 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS2 0xa IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS1 0xb IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0xc IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0xd IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS1 0xe IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS2 0xf IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS3 0x10 IRQ_TYPE_EDGE_RISING>; + memory-region = <&sail_mailbox_mem>, + <&sail_ota_mem>; + }; + tgu@4b0e000 { compatible = "qcom,tgu", "arm,primecell"; reg = <0x0 0x4b0e000 0x0 0x1000>;