From 63067476d89e5690d46edd2d5744dbab1652822f Mon Sep 17 00:00:00 2001 From: CUB3D Date: Mon, 30 Mar 2026 14:36:10 +0000 Subject: [PATCH 1/8] Add missing registers --- packages/aarch64-cpu/src/registers.rs | 14 +++ .../aarch64-cpu/src/registers/accdata_el1.rs | 35 +++++++ .../src/registers/actlrmask_el1.rs | 28 ++++++ .../src/registers/actlrmask_el2.rs | 28 ++++++ .../aarch64-cpu/src/registers/afsr0_el2.rs | 30 ++++++ .../aarch64-cpu/src/registers/afsr0_el3.rs | 30 ++++++ .../aarch64-cpu/src/registers/ccsidr2_el1.rs | 28 ++++++ .../src/registers/id_aa64pfr1_el1.rs | 94 ++++++++++++++++++- .../aarch64-cpu/src/registers/tpidr_el3.rs | 28 ++++++ 9 files changed, 314 insertions(+), 1 deletion(-) create mode 100644 packages/aarch64-cpu/src/registers/accdata_el1.rs create mode 100644 packages/aarch64-cpu/src/registers/actlrmask_el1.rs create mode 100644 packages/aarch64-cpu/src/registers/actlrmask_el2.rs create mode 100644 packages/aarch64-cpu/src/registers/afsr0_el2.rs create mode 100644 packages/aarch64-cpu/src/registers/afsr0_el3.rs create mode 100644 packages/aarch64-cpu/src/registers/ccsidr2_el1.rs create mode 100644 packages/aarch64-cpu/src/registers/tpidr_el3.rs diff --git a/packages/aarch64-cpu/src/registers.rs b/packages/aarch64-cpu/src/registers.rs index bd57723..c89a12e 100644 --- a/packages/aarch64-cpu/src/registers.rs +++ b/packages/aarch64-cpu/src/registers.rs @@ -5,10 +5,15 @@ #[macro_use] mod macros; +mod accdata_el1; mod actlr_el1; mod actlr_el2; mod actlr_el3; +mod actlrmask_el1; +mod actlrmask_el2; mod afsr0_el1; +mod afsr0_el2; +mod afsr0_el3; mod afsr1_el1; mod aidr_el1; mod amair_el1; @@ -23,6 +28,7 @@ mod apiakeylo_el1; mod apibkeyhi_el1; mod apibkeylo_el1; mod ccsidr_el1; +mod ccsidr2_el1; mod clidr_el1; mod cntfrq_el0; mod cnthctl_el2; @@ -164,6 +170,7 @@ mod tcr_el2; mod tpidr_el0; mod tpidr_el1; mod tpidr_el2; +mod tpidr_el3; mod tpidrro_el0; mod ttbr0_el1; mod ttbr0_el2; @@ -175,10 +182,15 @@ mod vmpidr_el2; mod vtcr_el2; mod vttbr_el2; +pub use accdata_el1::ACCDATA_EL1; pub use actlr_el1::ACTLR_EL1; pub use actlr_el2::ACTLR_EL2; pub use actlr_el3::ACTLR_EL3; +pub use actlrmask_el1::ACTLRMASK_EL1; +pub use actlrmask_el2::ACTLRMASK_EL2; pub use afsr0_el1::AFSR0_EL1; +pub use afsr0_el2::AFSR0_EL2; +pub use afsr0_el3::AFSR0_EL3; pub use afsr1_el1::AFSR1_EL1; pub use aidr_el1::AIDR_EL1; pub use amair_el1::AMAIR_EL1; @@ -193,6 +205,7 @@ pub use apiakeylo_el1::APIAKEYLO_EL1; pub use apibkeyhi_el1::APIBKEYHI_EL1; pub use apibkeylo_el1::APIBKEYLO_EL1; pub use ccsidr_el1::CCSIDR_EL1; +pub use ccsidr2_el1::CCSIDR2_EL1; pub use clidr_el1::CLIDR_EL1; pub use cntfrq_el0::CNTFRQ_EL0; pub use cnthctl_el2::CNTHCTL_EL2; @@ -334,6 +347,7 @@ pub use tcr_el2::TCR_EL2; pub use tpidr_el0::TPIDR_EL0; pub use tpidr_el1::TPIDR_EL1; pub use tpidr_el2::TPIDR_EL2; +pub use tpidr_el3::TPIDR_EL3; pub use tpidrro_el0::TPIDRRO_EL0; pub use ttbr0_el1::TTBR0_EL1; pub use ttbr0_el2::TTBR0_EL2; diff --git a/packages/aarch64-cpu/src/registers/accdata_el1.rs b/packages/aarch64-cpu/src/registers/accdata_el1.rs new file mode 100644 index 0000000..308269c --- /dev/null +++ b/packages/aarch64-cpu/src/registers/accdata_el1.rs @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2018-2026 by the author(s) +// +// Author(s): +// - Callum Thomson + +//! Accelerator Data - EL1 + +use tock_registers::interfaces::{Readable, Writeable}; +use tock_registers::register_bitfields; + +pub struct Reg; + +register_bitfields! {u64, + pub ACCDATA_EL1 [ + ACCDATA OFFSET(0) NUMBITS(32) [], + ] +} + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ACCDATA_EL1", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ACCDATA_EL1", "x"); +} + +pub const ACCDATA_EL1: Reg = Reg; diff --git a/packages/aarch64-cpu/src/registers/actlrmask_el1.rs b/packages/aarch64-cpu/src/registers/actlrmask_el1.rs new file mode 100644 index 0000000..05080c3 --- /dev/null +++ b/packages/aarch64-cpu/src/registers/actlrmask_el1.rs @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2018-2026 by the author(s) +// +// Author(s): +// - Callum Thomson + +//! Auxiliary Control Masking Register - EL1 + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ACTLRMASK_EL1", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ACTLRMASK_EL1", "x"); +} + +pub const ACTLRMASK_EL1: Reg = Reg; diff --git a/packages/aarch64-cpu/src/registers/actlrmask_el2.rs b/packages/aarch64-cpu/src/registers/actlrmask_el2.rs new file mode 100644 index 0000000..636d532 --- /dev/null +++ b/packages/aarch64-cpu/src/registers/actlrmask_el2.rs @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2018-2026 by the author(s) +// +// Author(s): +// - Callum Thomson + +//! Auxiliary Control Masking Register - EL1 + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ACTLRMASK_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ACTLRMASK_EL2", "x"); +} + +pub const ACTLRMASK_EL2: Reg = Reg; diff --git a/packages/aarch64-cpu/src/registers/afsr0_el2.rs b/packages/aarch64-cpu/src/registers/afsr0_el2.rs new file mode 100644 index 0000000..7afc13e --- /dev/null +++ b/packages/aarch64-cpu/src/registers/afsr0_el2.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2026 by the author(s) +// +// Author(s): +// - Callum Thomson + +//! Auxiliary Fault Status Register 0 - EL2 +//! +//! Provides IMPLEMENTATION DEFINED fault status information for synchronous aborts that are taken to EL2. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "AFSR0_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "AFSR0_EL2", "x"); +} + +pub const AFSR0_EL2: Reg = Reg {}; diff --git a/packages/aarch64-cpu/src/registers/afsr0_el3.rs b/packages/aarch64-cpu/src/registers/afsr0_el3.rs new file mode 100644 index 0000000..82b408f --- /dev/null +++ b/packages/aarch64-cpu/src/registers/afsr0_el3.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2026 by the author(s) +// +// Author(s): +// - Callum Thomson + +//! Auxiliary Fault Status Register 0 - EL3 +//! +//! Provides IMPLEMENTATION DEFINED fault status information for synchronous aborts that are taken to EL3. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "AFSR0_EL3", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "AFSR0_EL3", "x"); +} + +pub const AFSR0_EL3: Reg = Reg {}; diff --git a/packages/aarch64-cpu/src/registers/ccsidr2_el1.rs b/packages/aarch64-cpu/src/registers/ccsidr2_el1.rs new file mode 100644 index 0000000..7a62477 --- /dev/null +++ b/packages/aarch64-cpu/src/registers/ccsidr2_el1.rs @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2018-2026 by the author(s) +// +// Author(s): +// - Callum Thomson + +//! Current Cache Size ID Register 2 - EL1 + +use tock_registers::interfaces::Readable; +use tock_registers::register_bitfields; + +pub struct Reg; + +register_bitfields! {u64, + pub CCSIDR2_EL1 [ + NumSets OFFSET(0) NUMBITS(24) [], + ] +} + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "CCSIDR2_EL1", "x"); +} + +pub const CCSIDR2_EL1: Reg = Reg; diff --git a/packages/aarch64-cpu/src/registers/id_aa64pfr1_el1.rs b/packages/aarch64-cpu/src/registers/id_aa64pfr1_el1.rs index e4fd1bc..129f5fa 100644 --- a/packages/aarch64-cpu/src/registers/id_aa64pfr1_el1.rs +++ b/packages/aarch64-cpu/src/registers/id_aa64pfr1_el1.rs @@ -4,6 +4,7 @@ // // Author(s): // - Sangwan Kwon +// - Callum Thomson //! AArch64 Processor Feature Register 1 - EL1 //! @@ -13,8 +14,99 @@ use tock_registers::{interfaces::Readable, register_bitfields}; register_bitfields! {u64, pub ID_AA64PFR1_EL1 [ + /// Support for physical fault address registers + PFAR OFFSET(60) NUMBITS(4) [ + NotImplemented = 0b0000, + Implemented = 0b0001, + ], + + /// Support for error routing extensions + DF2 OFFSET(56) NUMBITS(4) [ + NotImplemented = 0b0000, + Implemented = 0b0001, + ], + + /// Support for additional MTE tag check modes + MTEX OFFSET(52) NUMBITS(4) [ + NotSupported = 0b0000, + Supported = 0b0001, + ], + + /// Support for Translation Hardening Extension + THE OFFSET(48) NUMBITS(4) [ + NotImplemented = 0b0000, + Implemented = 0b0001, + ], + + /// Support for Guarded Control Stack + GCS OFFSET(44) NUMBITS(4) [ + NotImplemented = 0b0000, + Implemented = 0b0001, + ], + + /// Support for Asynchronous reporting of a Tag Check Fault + MTE_frac OFFSET(40) NUMBITS(4) [ + Supported = 0b0000, + NotSupported = 0b1111, + ], + + /// Non-maskable Interrupt + NMI OFFSET(36) NUMBITS(4) [ + NotSupported = 0b0000, + Supported = 0b0001, + ], + + /// CSV2 fractional field + CSV2_frac OFFSET(32) NUMBITS(4) [ + Undisclosed = 0b0000, + Partial = 0b0001, + Implemented = 0b0010, + ], + + /// Random Number trap to EL3 + RNDR_trap OFFSET(28) NUMBITS(4) [ + NotSupported = 0b0000, + Supported = 0b0001, + ], + + /// Scalable Matrix Extension + SME OFFSET(24) NUMBITS(4) [ + NotImplemented = 0b0000, + Implemented = 0b0001, + ], + + /// Minor version number for the MPAM Extension + MPAM_frac OFFSET(16) NUMBITS(4) [ + MinorVersion0 = 0b0000, + MinorVersion1 = 0b0001, + ], + + /// RAS Extension fractional field + RAS_frac OFFSET(12) NUMBITS(4) [ + Implmented = 0b0000, + ImplmentedExtraRegisters = 0b0001, + ], + /// Support for the Memory Tagging Extension. - MTE OFFSET(8) NUMBITS(4) [], + MTE OFFSET(8) NUMBITS(4) [ + NotImplemented = 0b0000, + InstructionOnly = 0b0001, + InstructionOnlyOptionalAsync = 0b0010, + InstructionMandatoryAsync = 0b0011, + ], + + /// Speculative Store Bypassing controls + SSBS OFFSET(4) NUMBITS(4) [ + NoMechanism = 0b0000, + SSBSOnly = 0b0001, + SSBSWithMsrAndMrs = 0b0010, + ], + + /// Branch Target Identification + BT OFFSET(0) NUMBITS(4) [ + NotImplemented = 0b0000, + Implemented = 0b0001, + ], ] } diff --git a/packages/aarch64-cpu/src/registers/tpidr_el3.rs b/packages/aarch64-cpu/src/registers/tpidr_el3.rs new file mode 100644 index 0000000..c35a709 --- /dev/null +++ b/packages/aarch64-cpu/src/registers/tpidr_el3.rs @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2018-2026 by the author(s) +// +// Author(s): +// - Callum Thomson + +//! Software Thread ID Register - EL3 + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "TPIDR_EL3", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "TPIDR_EL3", "x"); +} + +pub const TPIDR_EL3: Reg = Reg; From 08bab003fdea8f17c11e2403162da373e3f26626 Mon Sep 17 00:00:00 2001 From: CUB3D Date: Mon, 30 Mar 2026 18:00:12 +0000 Subject: [PATCH 2/8] Add hacr_el2 --- packages/aarch64-cpu/src/registers.rs | 2 ++ .../aarch64-cpu/src/registers/hacr_el2.rs | 28 +++++++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 packages/aarch64-cpu/src/registers/hacr_el2.rs diff --git a/packages/aarch64-cpu/src/registers.rs b/packages/aarch64-cpu/src/registers.rs index c89a12e..8b5cd3d 100644 --- a/packages/aarch64-cpu/src/registers.rs +++ b/packages/aarch64-cpu/src/registers.rs @@ -68,6 +68,7 @@ mod far_el1; mod far_el2; mod far_el3; mod fp; +mod hacr_el2; mod hafgrtr_el2; mod hcr_el2; mod hdfgrtr_el2; @@ -245,6 +246,7 @@ pub use far_el1::FAR_EL1; pub use far_el2::FAR_EL2; pub use far_el3::FAR_EL3; pub use fp::FP; +pub use hacr_el2::HACR_EL2; pub use hafgrtr_el2::HAFGRTR_EL2; pub use hcr_el2::HCR_EL2; pub use hdfgrtr_el2::HDFGRTR_EL2; diff --git a/packages/aarch64-cpu/src/registers/hacr_el2.rs b/packages/aarch64-cpu/src/registers/hacr_el2.rs new file mode 100644 index 0000000..11475ff --- /dev/null +++ b/packages/aarch64-cpu/src/registers/hacr_el2.rs @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2018-2026 by the author(s) +// +// Author(s): +// - Callum Thomson + +//! Hypervisor Auxiliary Control Register - EL1 + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "HACR_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "HACR_EL2", "x"); +} + +pub const HACR_EL2: Reg = Reg; From 920cfcaf36143bf39f79d47ed1ec438038df8d89 Mon Sep 17 00:00:00 2001 From: CUB3D Date: Thu, 2 Apr 2026 02:50:29 +0100 Subject: [PATCH 3/8] Add OSDLR_EL1 --- packages/aarch64-cpu/src/registers.rs | 2 + .../aarch64-cpu/src/registers/osdlr_el1.rs | 39 +++++++++++++++++++ 2 files changed, 41 insertions(+) create mode 100644 packages/aarch64-cpu/src/registers/osdlr_el1.rs diff --git a/packages/aarch64-cpu/src/registers.rs b/packages/aarch64-cpu/src/registers.rs index 8b5cd3d..069ceed 100644 --- a/packages/aarch64-cpu/src/registers.rs +++ b/packages/aarch64-cpu/src/registers.rs @@ -135,6 +135,7 @@ mod mpuir_el2; mod mvfr0_el1; mod mvfr1_el1; mod mvfr2_el1; +mod osdlr_el1; mod oslar_el1; mod par_el1; mod pmuserenr_el0; @@ -313,6 +314,7 @@ pub use mpuir_el2::MPUIR_EL2; pub use mvfr0_el1::MVFR0_EL1; pub use mvfr1_el1::MVFR1_EL1; pub use mvfr2_el1::MVFR2_EL1; +pub use osdlr_el1::OSDLR_EL1; pub use oslar_el1::OSLAR_EL1; pub use par_el1::PAR_EL1; pub use pmuserenr_el0::PMUSERENR_EL0; diff --git a/packages/aarch64-cpu/src/registers/osdlr_el1.rs b/packages/aarch64-cpu/src/registers/osdlr_el1.rs new file mode 100644 index 0000000..5d67e0d --- /dev/null +++ b/packages/aarch64-cpu/src/registers/osdlr_el1.rs @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2018-2026 by the author(s) +// +// Author(s): +// - Callum Thomson + +//! OS Double Lock Register - EL1 + +use tock_registers::interfaces::{Readable, Writeable}; +use tock_registers::register_bitfields; + +pub struct Reg; + +register_bitfields! {u64, + pub OSDLR_EL1 [ + /// OS Double Lock control bit + DLK OFFSET(0) NUMBITS(1) [ + Unlocked = 0, + Locked = 1 + ] + ] +} + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "OSDLR_EL1", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "OSDLR_EL1", "x"); +} + +pub const OSDLR_EL1: Reg = Reg; \ No newline at end of file From 703da138e79363e0e95224ddc10debefcefd1e9e Mon Sep 17 00:00:00 2001 From: CUB3D Date: Thu, 2 Apr 2026 02:51:23 +0100 Subject: [PATCH 4/8] Update ID_AA64DFR1_EL1 --- .../src/registers/id_aa64dfr1_el1.rs | 62 ++++++++++++++++++- 1 file changed, 60 insertions(+), 2 deletions(-) diff --git a/packages/aarch64-cpu/src/registers/id_aa64dfr1_el1.rs b/packages/aarch64-cpu/src/registers/id_aa64dfr1_el1.rs index d8aa670..f22d6d9 100644 --- a/packages/aarch64-cpu/src/registers/id_aa64dfr1_el1.rs +++ b/packages/aarch64-cpu/src/registers/id_aa64dfr1_el1.rs @@ -1,18 +1,76 @@ // SPDX-License-Identifier: Apache-2.0 OR MIT // -// Copyright (c) 2024 by the author(s) +// Copyright (c) 2018-2026 by the author(s) // // Author(s): // - Sangwan Kwon +// - Callum Thomson //! AArch64 Debug Feature Register 1 - EL1 //! //! Provides top level information about the debug system in AArch64. use tock_registers::interfaces::Readable; +use tock_registers::register_bitfields; pub struct Reg; +register_bitfields! {u64, + pub ID_AA64DFR1_EL1 [ + /// Number of breakpoint that support address linking, minus 1 + ABL_CMPs OFFSET(56) NUMBITS(8) [], + + /// Behaviour of the cycle counter when event counting is frozen by a Statistical Profiling management event + DPFZS OFFSET(52) NUMBITS(4) [ + NeverAffected = 0b0000, + FrozenByFZS = 0b0001, + ], + + /// Exception Based event profiling + EBEP OFFSET(48) NUMBITS(4) [ + NotImplemented = 0b0000, + Implemented = 0b0001, + ], + + /// Instrumentation Trace Extension + ITE OFFSET(44) NUMBITS(4) [ + NotImplemented = 0b0000, + Implemented = 0b0001, + ], + + /// Address Breakpoint Linking Extension + ABLE OFFSET(40) NUMBITS(4) [ + NotImplmented = 0b0000, + Implmented = 0b0001, + ], + + /// PMU fixed-function instruction counter + PMICNTR OFFSET(36) NUMBITS(4) [ + NotImplmented = 0b0000, + Implmented = 0b0001, + ], + + /// System PMU extension + SPMU OFFSET(32) NUMBITS(4) [ + NotImplemented = 0b0000, + Implmented = 0b0001, + ImplmentedWithSPMZR = 0b0010, + ], + + /// Context-aware breakpoints + CTX_CMPs OFFSET(24) NUMBITS(8) [], + + /// Watchpoints + WRPs OFFSET(16) NUMBITS(8) [], + + /// Breakpoints + BRPs OFFSET(8) NUMBITS(8) [], + + /// System PMU ID + SYSPMUID OFFSET(0) NUMBITS(8) [], + ] +} + impl Readable for Reg { type T = u64; type R = (); @@ -20,4 +78,4 @@ impl Readable for Reg { sys_coproc_read_raw!(u64, "ID_AA64DFR1_EL1", "x"); } -pub const ID_AA64DFR1_EL1: Reg = Reg {}; +pub const ID_AA64DFR1_EL1: Reg = Reg; \ No newline at end of file From 2b6761dfda709d0f38175f89d1b4e3b8c14c4e52 Mon Sep 17 00:00:00 2001 From: CUB3D Date: Thu, 2 Apr 2026 06:44:48 +0100 Subject: [PATCH 5/8] Fmt --- packages/aarch64-cpu/src/registers.rs | 4 ++-- packages/aarch64-cpu/src/registers/id_aa64dfr1_el1.rs | 2 +- packages/aarch64-cpu/src/registers/osdlr_el1.rs | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/packages/aarch64-cpu/src/registers.rs b/packages/aarch64-cpu/src/registers.rs index 069ceed..9e10f73 100644 --- a/packages/aarch64-cpu/src/registers.rs +++ b/packages/aarch64-cpu/src/registers.rs @@ -27,8 +27,8 @@ mod apiakeyhi_el1; mod apiakeylo_el1; mod apibkeyhi_el1; mod apibkeylo_el1; -mod ccsidr_el1; mod ccsidr2_el1; +mod ccsidr_el1; mod clidr_el1; mod cntfrq_el0; mod cnthctl_el2; @@ -206,8 +206,8 @@ pub use apiakeyhi_el1::APIAKEYHI_EL1; pub use apiakeylo_el1::APIAKEYLO_EL1; pub use apibkeyhi_el1::APIBKEYHI_EL1; pub use apibkeylo_el1::APIBKEYLO_EL1; -pub use ccsidr_el1::CCSIDR_EL1; pub use ccsidr2_el1::CCSIDR2_EL1; +pub use ccsidr_el1::CCSIDR_EL1; pub use clidr_el1::CLIDR_EL1; pub use cntfrq_el0::CNTFRQ_EL0; pub use cnthctl_el2::CNTHCTL_EL2; diff --git a/packages/aarch64-cpu/src/registers/id_aa64dfr1_el1.rs b/packages/aarch64-cpu/src/registers/id_aa64dfr1_el1.rs index f22d6d9..58fb65d 100644 --- a/packages/aarch64-cpu/src/registers/id_aa64dfr1_el1.rs +++ b/packages/aarch64-cpu/src/registers/id_aa64dfr1_el1.rs @@ -78,4 +78,4 @@ impl Readable for Reg { sys_coproc_read_raw!(u64, "ID_AA64DFR1_EL1", "x"); } -pub const ID_AA64DFR1_EL1: Reg = Reg; \ No newline at end of file +pub const ID_AA64DFR1_EL1: Reg = Reg; diff --git a/packages/aarch64-cpu/src/registers/osdlr_el1.rs b/packages/aarch64-cpu/src/registers/osdlr_el1.rs index 5d67e0d..fbe6d72 100644 --- a/packages/aarch64-cpu/src/registers/osdlr_el1.rs +++ b/packages/aarch64-cpu/src/registers/osdlr_el1.rs @@ -36,4 +36,4 @@ impl Writeable for Reg { sys_coproc_write_raw!(u64, "OSDLR_EL1", "x"); } -pub const OSDLR_EL1: Reg = Reg; \ No newline at end of file +pub const OSDLR_EL1: Reg = Reg; From e4d23eeeb07325df4134e53b941d13e7988eed77 Mon Sep 17 00:00:00 2001 From: CUB3D Date: Thu, 2 Apr 2026 10:57:24 +0000 Subject: [PATCH 6/8] Add id_aa64isar2_el1, id_aa64isar3_el1 and missing fields in id_aa64dfr0_el1 --- packages/aarch64-cpu/src/registers.rs | 4 + .../src/registers/id_aa64dfr0_el1.rs | 31 +++++ .../src/registers/id_aa64isar2_el1.rs | 128 ++++++++++++++++++ .../src/registers/id_aa64isar3_el1.rs | 100 ++++++++++++++ 4 files changed, 263 insertions(+) create mode 100644 packages/aarch64-cpu/src/registers/id_aa64isar2_el1.rs create mode 100644 packages/aarch64-cpu/src/registers/id_aa64isar3_el1.rs diff --git a/packages/aarch64-cpu/src/registers.rs b/packages/aarch64-cpu/src/registers.rs index 9e10f73..43f1c99 100644 --- a/packages/aarch64-cpu/src/registers.rs +++ b/packages/aarch64-cpu/src/registers.rs @@ -113,6 +113,8 @@ mod id_aa64dfr0_el1; mod id_aa64dfr1_el1; mod id_aa64isar0_el1; mod id_aa64isar1_el1; +mod id_aa64isar2_el1; +mod id_aa64isar3_el1; mod id_aa64mmfr0_el1; mod id_aa64mmfr1_el1; mod id_aa64mmfr2_el1; @@ -292,6 +294,8 @@ pub use id_aa64dfr0_el1::ID_AA64DFR0_EL1; pub use id_aa64dfr1_el1::ID_AA64DFR1_EL1; pub use id_aa64isar0_el1::ID_AA64ISAR0_EL1; pub use id_aa64isar1_el1::ID_AA64ISAR1_EL1; +pub use id_aa64isar2_el1::ID_AA64ISAR2_EL1; +pub use id_aa64isar3_el1::ID_AA64ISAR3_EL1; pub use id_aa64mmfr0_el1::ID_AA64MMFR0_EL1; pub use id_aa64mmfr1_el1::ID_AA64MMFR1_EL1; pub use id_aa64mmfr2_el1::ID_AA64MMFR2_EL1; diff --git a/packages/aarch64-cpu/src/registers/id_aa64dfr0_el1.rs b/packages/aarch64-cpu/src/registers/id_aa64dfr0_el1.rs index 57bbe46..fe06e5c 100644 --- a/packages/aarch64-cpu/src/registers/id_aa64dfr0_el1.rs +++ b/packages/aarch64-cpu/src/registers/id_aa64dfr0_el1.rs @@ -13,6 +13,19 @@ use tock_registers::{interfaces::Readable, register_bitfields}; register_bitfields! {u64, pub ID_AA64DFR0_EL1 [ + + /// Zero PMU event counters for Guest + HPMN0 OFFSET(60) NUMBITS(4) [ + Unpredictable = 0b0000, + Defined = 0b00001, + ], + + /// Trace Buffer External Mode Extension + ExtTrcBuff OFFSET(56) NUMBITS(4) [ + NotImplemented = 0b0000, + Implemented = 0b00001, + ], + /// Branch Record Buffer Extension. /// /// - 0000 Branch Record Buffer Extension not implemented. @@ -65,15 +78,33 @@ register_bitfields! {u64, Implemented = 0b0001, ], + /// OS Double Lock implemented + DoubleLock OFFSET(36) NUMBITS(4) [ + Implemented = 0b0000, + NotImplemented = 0b1111, + ], + /// Statistical Profiling Extension version. PMSVer OFFSET(32) NUMBITS(4) [], /// Number of context-aware breakpoints, minus 1. CTX_CMPs OFFSET(28) NUMBITS(4) [], + /// Synchronous-exception-based event profiling + SEBEP OFFSET(24) NUMBITS(4) [ + NotImplemented = 0b0000, + Implemented = 0b00001, + ], + /// Number of watchpoints, minus 1. WRPs OFFSET(20) NUMBITS(4) [], + /// PMU Snapshot extension + PMSS OFFSET(16) NUMBITS(4) [ + NotImplemented = 0b0000, + Implemented = 0b00001, + ], + /// Number of breakpoints, minus 1. BRPs OFFSET(12) NUMBITS(4) [], diff --git a/packages/aarch64-cpu/src/registers/id_aa64isar2_el1.rs b/packages/aarch64-cpu/src/registers/id_aa64isar2_el1.rs new file mode 100644 index 0000000..8f3edb2 --- /dev/null +++ b/packages/aarch64-cpu/src/registers/id_aa64isar2_el1.rs @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2018-2026 by the author(s) +// +// Author(s): +// - Callum Thomson + +//! AArch64 Instruction Set Attribute Register 2 - EL1 + +use tock_registers::interfaces::Readable; +use tock_registers::register_bitfields; + +pub struct Reg; + +register_bitfields! {u64, + pub ID_AA64ISAR2_EL1 [ + /// Indicates support for address translation instructions that perform stage 1 translation without checking stage 1 permissions + ATS1A OFFSET(60) NUMBITS(4) [ + NotImplmented = 0b0000, + Implmented = 0b0001, + ], + + /// Indicates support for advanced SIMD and SVE2 lookup instruction + LUT OFFSET(56) NUMBITS(4) [ + NotImplemented = 0b0000, + Implemented = 0b0001, + ], + + /// Support for common short sequence compression instructions + CSSC OFFSET(52) NUMBITS(4) [ + NotImplemented = 0b0000, + MinMaxAbsCnt = 0b0001, + MinMaxAbsCntCB = 0b0010, + ], + + /// RPRFM hint instruction + RPRFM OFFSET(48) NUMBITS(4) [ + NotImplmented = 0b0000, + Implmented = 0b0001, + ], + + /// Indicates support for producer-consumer data placement hints + PCDPHINT OFFSET(44) NUMBITS(4) [ + NotImplmented = 0b0000, + Implemented = 0b0001, + ], + + /// Indicates whether PRFM instruction support a system level cache option + PRFMSLC OFFSET(40) NUMBITS(4) [ + NotSupported = 0b0000, + Supported = 0b0001, + ], + + /// Indicates support for system instructions that can take 128-bit inputs + SYSINSTR_128 OFFSET(36) NUMBITS(4) [ + NotImplmented = 0b0000, + Implmented = 0b0001, + ], + + /// Indicates support for instructions to access 128-bit system registers + SYSREG_128 OFFSET(32) NUMBITS(4) [ + NotSupported = 0b0000, + Supported = 0b0001, + ], + + /// Indicates support for the CLRBHB instruction + CLRBHB OFFSET(28) NUMBITS(4) [ + NotImplmented = 0b0000, + Implmented = 0b0001, + ], + + /// Indicates which bit is used to determine the size of the PAC field + PAC_frac OFFSET(24) NUMBITS(4) [ + DependsOnAddressTagging = 0b0000, + Fixed = 0b0001, + ], + + /// Support for the BC instruction + BC OFFSET(20) NUMBITS(4) [ + NotImplmented = 0b0000, + Implmented = 0b0001, + ], + + /// Support for Memory Copy and Memory Set instructions + MOPS OFFSET(16) NUMBITS(4) [ + NotImplmented = 0b0000, + Implmented = 0b0001, + ], + + /// Indicates support for QARMA3 for address authentication + APA3 OFFSET(12) NUMBITS(4) [ + NotImplemented = 0b0000, + ImplementedNoEPACNoPAuth2 = 0b0001, + ImplementedWithEPACNoPAuth2 = 0b0010, + ImplementedWithEPACAndPauth2 = 0b0011, + ImplementedNoEPACWithPAuthAndPFAC = 0b0100, + ImplementedNoEPACWithPAuth2FPACAndFPACCOMBINE = 0b0101, + ImplementedWithSignedLR = 0b0110, + ], + + /// Indicates support for QARMA3 for generic code authentication + GPA3 OFFSET(8) NUMBITS(4) [ + NotImplmented = 0b0000, + Implmented = 0b0001, + ], + + /// Support for 12 bits of mantissa in single-precision reciprocal and reciprocal square root instructions + RPRES OFFSET(4) NUMBITS(4) [ + Mantissa8Bit = 0b0000, + Mantissa12Bit = 0b0001, + ], + + /// Support for WFET and WFIT instructions + WFxT OFFSET(0) NUMBITS(4) [ + NotSupported = 0b0000, + Supported = 0b0010, + ], + ] +} + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ID_AA64ISAR2_EL1", "x"); +} + +pub const ID_AA64ISAR2_EL1: Reg = Reg; diff --git a/packages/aarch64-cpu/src/registers/id_aa64isar3_el1.rs b/packages/aarch64-cpu/src/registers/id_aa64isar3_el1.rs new file mode 100644 index 0000000..58cc406 --- /dev/null +++ b/packages/aarch64-cpu/src/registers/id_aa64isar3_el1.rs @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2018-2026 by the author(s) +// +// Author(s): +// - Callum Thomson + +//! AArch64 Instruction Set Attribute Register 3- EL1 + +use tock_registers::interfaces::Readable; +use tock_registers::register_bitfields; + +pub struct Reg; + +register_bitfields! {u64, + pub ID_AA64ISAR3_EL1 [ + /// Support for `LDAP`, `LDAPP` and `STLP` instructions + LSCP OFFSET(44) NUMBITS(4) [ + NotImplemented = 0b0000, + Implemented = 0b0001, + ], + + /// Support for `SHUH` and `STCPH` + LSCSHINT OFFSET(40) NUMBITS(4) [ + NotImplemented = 0b0000, + Implemented = 0b0001, + ], + + /// Support for `DC ZGBVA` and `DC GBVA`` + MTETC OFFSET(36) NUMBITS(4) [ + NotImplemented = 0b0000, + Implemented = 0b0001, + ], + + /// Indicates support for independant control of EL0 PAC and disabling BTI landing pad on PAC instructions + PAC_frac2 OFFSET(32) NUMBITS(4) [ + NotImplemented = 0b0000, + Implemented = 0b0001, + ], + + /// Indicates support for some floating-point and integer conversion instructions + FPRCVT OFFSET(28) NUMBITS(4) [ + NotImplemented = 0b0000, + Implemented = 0b0001, + ], + + /// Support for some unprivileged load and store instructions + LSUI OFFSET(24) NUMBITS(4) [ + NotImplemented = 0b0000, + Implemented = 0b0001, + ], + + /// Indicates support for `DC CIVAOC` and `DC CVAOC` + OCCMO OFFSET(20) NUMBITS(4) [ + NotImplemented = 0b0000, + Implemented = 0b0001, + ], + + /// Indicates support for some atomic floating-point in-memory instructions + LSFE OFFSET(16) NUMBITS(4) [ + NotImplemented = 0b0000, + Implemented = 0b0001, + ], + + /// Indicates the implementation of PSTATE.PACM + PACM OFFSET(12) NUMBITS(4) [ + NotSupported = 0b0000, + Trivial = 0b0001, + Full = 0b0010, + ], + + /// Support for TLBI VMALL for Dirty state + TLBIW OFFSET(8) NUMBITS(4) [ + NotSupported = 0b0000, + Supported = 0b0001, + ], + + /// Support for SIMD instructions that compute maximum and minimum absolute values + FAMINMAX OFFSET(4) NUMBITS(4) [ + NotImplemented = 0b0000, + Implemented = 0b0001, + ], + + /// Support for Checked Pointer Arithmetic instructions + CPA OFFSET(0) NUMBITS(4) [ + NotImplemented = 0b0000, + Implemented = 0b0001, + ImplementedCanBeEnabled = 0b0010, + ], + ] +} + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ID_AA64ISAR3_EL1", "x"); +} + +pub const ID_AA64ISAR3_EL1: Reg = Reg; From 0aba3afd8cb242b6fe87bddb853e09b7178786ee Mon Sep 17 00:00:00 2001 From: CUB3D Date: Thu, 2 Apr 2026 16:16:25 +0000 Subject: [PATCH 7/8] Add id_aa64isar2_el1 --- .../aarch64-cpu/src/registers/id_aa64isar2_el1.rs | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/packages/aarch64-cpu/src/registers/id_aa64isar2_el1.rs b/packages/aarch64-cpu/src/registers/id_aa64isar2_el1.rs index 8f3edb2..faa2eb4 100644 --- a/packages/aarch64-cpu/src/registers/id_aa64isar2_el1.rs +++ b/packages/aarch64-cpu/src/registers/id_aa64isar2_el1.rs @@ -35,13 +35,13 @@ register_bitfields! {u64, /// RPRFM hint instruction RPRFM OFFSET(48) NUMBITS(4) [ - NotImplmented = 0b0000, + NotImplemented = 0b0000, Implmented = 0b0001, ], /// Indicates support for producer-consumer data placement hints PCDPHINT OFFSET(44) NUMBITS(4) [ - NotImplmented = 0b0000, + NotImplemented = 0b0000, Implemented = 0b0001, ], @@ -53,7 +53,7 @@ register_bitfields! {u64, /// Indicates support for system instructions that can take 128-bit inputs SYSINSTR_128 OFFSET(36) NUMBITS(4) [ - NotImplmented = 0b0000, + NotImplemented = 0b0000, Implmented = 0b0001, ], @@ -65,7 +65,7 @@ register_bitfields! {u64, /// Indicates support for the CLRBHB instruction CLRBHB OFFSET(28) NUMBITS(4) [ - NotImplmented = 0b0000, + NotImplemented = 0b0000, Implmented = 0b0001, ], @@ -77,13 +77,13 @@ register_bitfields! {u64, /// Support for the BC instruction BC OFFSET(20) NUMBITS(4) [ - NotImplmented = 0b0000, + NotImplemented = 0b0000, Implmented = 0b0001, ], /// Support for Memory Copy and Memory Set instructions MOPS OFFSET(16) NUMBITS(4) [ - NotImplmented = 0b0000, + NotImplemented = 0b0000, Implmented = 0b0001, ], @@ -100,7 +100,7 @@ register_bitfields! {u64, /// Indicates support for QARMA3 for generic code authentication GPA3 OFFSET(8) NUMBITS(4) [ - NotImplmented = 0b0000, + NotImplemented = 0b0000, Implmented = 0b0001, ], From d05eba70bf0bc7cb99193c2ee191952823ba5393 Mon Sep 17 00:00:00 2001 From: CUB3D Date: Thu, 8 Oct 2026 22:25:16 +0100 Subject: [PATCH 8/8] Changes from review --- .../aarch64-cpu/src/registers/actlrmask_el2.rs | 2 +- .../aarch64-cpu/src/registers/ccsidr2_el1.rs | 2 +- packages/aarch64-cpu/src/registers/hacr_el2.rs | 2 +- .../src/registers/id_aa64dfr1_el1.rs | 16 ++++++++-------- .../src/registers/id_aa64isar2_el1.rs | 18 +++++++++--------- .../src/registers/id_aa64isar3_el1.rs | 8 ++++---- .../src/registers/id_aa64pfr1_el1.rs | 4 ++-- .../aarch64-cpu/src/registers/osdlr_el1.rs | 4 ++-- 8 files changed, 28 insertions(+), 28 deletions(-) diff --git a/packages/aarch64-cpu/src/registers/actlrmask_el2.rs b/packages/aarch64-cpu/src/registers/actlrmask_el2.rs index 636d532..4defff4 100644 --- a/packages/aarch64-cpu/src/registers/actlrmask_el2.rs +++ b/packages/aarch64-cpu/src/registers/actlrmask_el2.rs @@ -5,7 +5,7 @@ // Author(s): // - Callum Thomson -//! Auxiliary Control Masking Register - EL1 +//! Auxiliary Control Masking Register - EL2 use tock_registers::interfaces::{Readable, Writeable}; diff --git a/packages/aarch64-cpu/src/registers/ccsidr2_el1.rs b/packages/aarch64-cpu/src/registers/ccsidr2_el1.rs index 7a62477..40ec9d8 100644 --- a/packages/aarch64-cpu/src/registers/ccsidr2_el1.rs +++ b/packages/aarch64-cpu/src/registers/ccsidr2_el1.rs @@ -20,7 +20,7 @@ register_bitfields! {u64, impl Readable for Reg { type T = u64; - type R = (); + type R = CCSIDR2_EL1::Register; sys_coproc_read_raw!(u64, "CCSIDR2_EL1", "x"); } diff --git a/packages/aarch64-cpu/src/registers/hacr_el2.rs b/packages/aarch64-cpu/src/registers/hacr_el2.rs index 11475ff..bada12b 100644 --- a/packages/aarch64-cpu/src/registers/hacr_el2.rs +++ b/packages/aarch64-cpu/src/registers/hacr_el2.rs @@ -5,7 +5,7 @@ // Author(s): // - Callum Thomson -//! Hypervisor Auxiliary Control Register - EL1 +//! Hypervisor Auxiliary Control Register - EL2 use tock_registers::interfaces::{Readable, Writeable}; diff --git a/packages/aarch64-cpu/src/registers/id_aa64dfr1_el1.rs b/packages/aarch64-cpu/src/registers/id_aa64dfr1_el1.rs index 58fb65d..224ac3d 100644 --- a/packages/aarch64-cpu/src/registers/id_aa64dfr1_el1.rs +++ b/packages/aarch64-cpu/src/registers/id_aa64dfr1_el1.rs @@ -17,7 +17,7 @@ pub struct Reg; register_bitfields! {u64, pub ID_AA64DFR1_EL1 [ - /// Number of breakpoint that support address linking, minus 1 + /// Number of breakpoints that support address linking, minus 1 ABL_CMPs OFFSET(56) NUMBITS(8) [], /// Behaviour of the cycle counter when event counting is frozen by a Statistical Profiling management event @@ -40,21 +40,21 @@ register_bitfields! {u64, /// Address Breakpoint Linking Extension ABLE OFFSET(40) NUMBITS(4) [ - NotImplmented = 0b0000, - Implmented = 0b0001, + NotImplemented = 0b0000, + Implemented = 0b0001, ], /// PMU fixed-function instruction counter PMICNTR OFFSET(36) NUMBITS(4) [ - NotImplmented = 0b0000, - Implmented = 0b0001, + NotImplemented = 0b0000, + Implemented = 0b0001, ], /// System PMU extension SPMU OFFSET(32) NUMBITS(4) [ NotImplemented = 0b0000, - Implmented = 0b0001, - ImplmentedWithSPMZR = 0b0010, + Implemented = 0b0001, + ImplementedWithSPMZR = 0b0010, ], /// Context-aware breakpoints @@ -73,7 +73,7 @@ register_bitfields! {u64, impl Readable for Reg { type T = u64; - type R = (); + type R = ID_AA64DFR1_EL1::Register; sys_coproc_read_raw!(u64, "ID_AA64DFR1_EL1", "x"); } diff --git a/packages/aarch64-cpu/src/registers/id_aa64isar2_el1.rs b/packages/aarch64-cpu/src/registers/id_aa64isar2_el1.rs index faa2eb4..d697880 100644 --- a/packages/aarch64-cpu/src/registers/id_aa64isar2_el1.rs +++ b/packages/aarch64-cpu/src/registers/id_aa64isar2_el1.rs @@ -16,8 +16,8 @@ register_bitfields! {u64, pub ID_AA64ISAR2_EL1 [ /// Indicates support for address translation instructions that perform stage 1 translation without checking stage 1 permissions ATS1A OFFSET(60) NUMBITS(4) [ - NotImplmented = 0b0000, - Implmented = 0b0001, + NotImplemented = 0b0000, + Implemented = 0b0001, ], /// Indicates support for advanced SIMD and SVE2 lookup instruction @@ -36,7 +36,7 @@ register_bitfields! {u64, /// RPRFM hint instruction RPRFM OFFSET(48) NUMBITS(4) [ NotImplemented = 0b0000, - Implmented = 0b0001, + Implemented = 0b0001, ], /// Indicates support for producer-consumer data placement hints @@ -54,7 +54,7 @@ register_bitfields! {u64, /// Indicates support for system instructions that can take 128-bit inputs SYSINSTR_128 OFFSET(36) NUMBITS(4) [ NotImplemented = 0b0000, - Implmented = 0b0001, + Implemented = 0b0001, ], /// Indicates support for instructions to access 128-bit system registers @@ -66,7 +66,7 @@ register_bitfields! {u64, /// Indicates support for the CLRBHB instruction CLRBHB OFFSET(28) NUMBITS(4) [ NotImplemented = 0b0000, - Implmented = 0b0001, + Implemented = 0b0001, ], /// Indicates which bit is used to determine the size of the PAC field @@ -78,13 +78,13 @@ register_bitfields! {u64, /// Support for the BC instruction BC OFFSET(20) NUMBITS(4) [ NotImplemented = 0b0000, - Implmented = 0b0001, + Implemented = 0b0001, ], /// Support for Memory Copy and Memory Set instructions MOPS OFFSET(16) NUMBITS(4) [ NotImplemented = 0b0000, - Implmented = 0b0001, + Implemented = 0b0001, ], /// Indicates support for QARMA3 for address authentication @@ -101,7 +101,7 @@ register_bitfields! {u64, /// Indicates support for QARMA3 for generic code authentication GPA3 OFFSET(8) NUMBITS(4) [ NotImplemented = 0b0000, - Implmented = 0b0001, + Implemented = 0b0001, ], /// Support for 12 bits of mantissa in single-precision reciprocal and reciprocal square root instructions @@ -120,7 +120,7 @@ register_bitfields! {u64, impl Readable for Reg { type T = u64; - type R = (); + type R = ID_AA64ISAR2_EL1::Register; sys_coproc_read_raw!(u64, "ID_AA64ISAR2_EL1", "x"); } diff --git a/packages/aarch64-cpu/src/registers/id_aa64isar3_el1.rs b/packages/aarch64-cpu/src/registers/id_aa64isar3_el1.rs index 58cc406..f645714 100644 --- a/packages/aarch64-cpu/src/registers/id_aa64isar3_el1.rs +++ b/packages/aarch64-cpu/src/registers/id_aa64isar3_el1.rs @@ -5,7 +5,7 @@ // Author(s): // - Callum Thomson -//! AArch64 Instruction Set Attribute Register 3- EL1 +//! AArch64 Instruction Set Attribute Register 3 - EL1 use tock_registers::interfaces::Readable; use tock_registers::register_bitfields; @@ -26,13 +26,13 @@ register_bitfields! {u64, Implemented = 0b0001, ], - /// Support for `DC ZGBVA` and `DC GBVA`` + /// Support for `DC ZGBVA` and `DC GBVA` MTETC OFFSET(36) NUMBITS(4) [ NotImplemented = 0b0000, Implemented = 0b0001, ], - /// Indicates support for independant control of EL0 PAC and disabling BTI landing pad on PAC instructions + /// Indicates support for independent control of EL0 PAC and disabling BTI landing pad on PAC instructions PAC_frac2 OFFSET(32) NUMBITS(4) [ NotImplemented = 0b0000, Implemented = 0b0001, @@ -92,7 +92,7 @@ register_bitfields! {u64, impl Readable for Reg { type T = u64; - type R = (); + type R = ID_AA64ISAR3_EL1::Register; sys_coproc_read_raw!(u64, "ID_AA64ISAR3_EL1", "x"); } diff --git a/packages/aarch64-cpu/src/registers/id_aa64pfr1_el1.rs b/packages/aarch64-cpu/src/registers/id_aa64pfr1_el1.rs index 129f5fa..47f53dc 100644 --- a/packages/aarch64-cpu/src/registers/id_aa64pfr1_el1.rs +++ b/packages/aarch64-cpu/src/registers/id_aa64pfr1_el1.rs @@ -83,8 +83,8 @@ register_bitfields! {u64, /// RAS Extension fractional field RAS_frac OFFSET(12) NUMBITS(4) [ - Implmented = 0b0000, - ImplmentedExtraRegisters = 0b0001, + Implemented = 0b0000, + ImplementedExtraRegisters = 0b0001, ], /// Support for the Memory Tagging Extension. diff --git a/packages/aarch64-cpu/src/registers/osdlr_el1.rs b/packages/aarch64-cpu/src/registers/osdlr_el1.rs index fbe6d72..4cb6bbb 100644 --- a/packages/aarch64-cpu/src/registers/osdlr_el1.rs +++ b/packages/aarch64-cpu/src/registers/osdlr_el1.rs @@ -24,14 +24,14 @@ register_bitfields! {u64, impl Readable for Reg { type T = u64; - type R = (); + type R = OSDLR_EL1::Register; sys_coproc_read_raw!(u64, "OSDLR_EL1", "x"); } impl Writeable for Reg { type T = u64; - type R = (); + type R = OSDLR_EL1::Register; sys_coproc_write_raw!(u64, "OSDLR_EL1", "x"); }