From 0892094317b8a823f3a038b996c0886c48627c1d Mon Sep 17 00:00:00 2001
From: Thomas <thomas.giudici@proton.me>
Date: Sun, 1 Nov 2026 08:36:07 +0000
Subject: [PATCH] Fix randomx_get_flags not reporting hardware AES on RISC-V

---
 src/aes_hash_rv64_zvkned.cpp | 18 ++++++++++++++++++
 src/intrin_portable.h        | 13 +++++++++++--
 src/tests/tests.cpp          |  7 ++++++-
 3 files changed, 35 insertions(+), 3 deletions(-)

diff --git a/src/aes_hash_rv64_zvkned.cpp b/src/aes_hash_rv64_zvkned.cpp
index abb0dff5..7f4a9c99 100644
--- a/src/aes_hash_rv64_zvkned.cpp
+++ b/src/aes_hash_rv64_zvkned.cpp
@@ -30,12 +30,30 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "aes_hash.hpp"
 #include "randomx.h"
 #include "blake2/endian.h"
+#include "intrin_portable.h"
 
 #include <riscv_vector.h>
 
 static FORCE_INLINE vuint32m1_t aesenc_zvkned(vuint32m1_t a, vuint32m1_t b) { return __riscv_vaesem_vv_u32m1(a, b, 8); }
 static FORCE_INLINE vuint32m1_t aesdec_zvkned(vuint32m1_t a, vuint32m1_t b, vuint32m1_t zero) { return __riscv_vxor_vv_u32m1(__riscv_vaesdm_vv_u32m1(a, zero, 8), b, 8); }
 
+rx_vec_i128 rx_aesenc_vec_i128(rx_vec_i128 v, rx_vec_i128 rkey)
+{
+	const vuint32m1_t a = __riscv_vle32_v_u32m1(v.u32, 4);
+	const vuint32m1_t k = __riscv_vle32_v_u32m1(rkey.u32, 4);
+	__riscv_vse32_v_u32m1(v.u32, __riscv_vaesem_vv_u32m1(a, k, 4), 4);
+	return v;
+}
+
+rx_vec_i128 rx_aesdec_vec_i128(rx_vec_i128 v, rx_vec_i128 rkey)
+{
+	const vuint32m1_t a = __riscv_vle32_v_u32m1(v.u32, 4);
+	const vuint32m1_t k = __riscv_vle32_v_u32m1(rkey.u32, 4);
+	const vuint32m1_t zero = {};
+	__riscv_vse32_v_u32m1(v.u32, __riscv_vxor_vv_u32m1(__riscv_vaesdm_vv_u32m1(a, zero, 4), k, 4), 4);
+	return v;
+}
+
 static constexpr uint32_t AES_HASH_1R_STATE02[8] = { 0x92b52c0d, 0x9fa856de, 0xcc82db47, 0xd7983aad, 0x6a770017, 0xae62c7d0, 0x5079506b, 0xe8a07ce4 };
 static constexpr uint32_t AES_HASH_1R_STATE13[8] = { 0x338d996e, 0x15c7b798, 0xf59e125a, 0xace78057, 0x630a240c, 0x07ad828d, 0x79a10005, 0x7e994948 };
 
diff --git a/src/intrin_portable.h b/src/intrin_portable.h
index 1bf7452a..7ff36676 100644
--- a/src/intrin_portable.h
+++ b/src/intrin_portable.h
@@ -772,13 +772,22 @@ FORCE_INLINE rx_vec_f128 rx_cvt_packed_int_vec_f128(const void* addr) {
 	return x;
 }
 
+#ifdef __riscv
+rx_vec_i128 rx_aesenc_vec_i128(rx_vec_i128 v, rx_vec_i128 rkey);
+rx_vec_i128 rx_aesdec_vec_i128(rx_vec_i128 v, rx_vec_i128 rkey);
+
+#define HAVE_AES 1
+#endif
+
 #define RANDOMX_DEFAULT_FENV
 
 #endif
 
-#ifndef HAVE_AES
-static const char* platformError = "Platform doesn't support hardware AES";
+#if !defined(HAVE_AES) || defined(__riscv)
+static const char* const platformError = "Platform doesn't support hardware AES";
+#endif
 
+#ifndef HAVE_AES
 #include <stdexcept>
 
 FORCE_INLINE rx_vec_i128 rx_aesenc_vec_i128(rx_vec_i128 v, rx_vec_i128 rkey) {
diff --git a/src/tests/tests.cpp b/src/tests/tests.cpp
index 7e91a43d..9664cfaa 100644
--- a/src/tests/tests.cpp
+++ b/src/tests/tests.cpp
@@ -1250,7 +1250,12 @@ int main() {
 		}
 	});
 
-	runTest("Hardware AES not supported", !HAVE_AES && !randomx::cpu.hasAes(), []() {
+#ifdef __riscv
+	constexpr bool hardAesCheckedAtRuntime = true;
+#else
+	constexpr bool hardAesCheckedAtRuntime = !HAVE_AES;
+#endif
+	runTest("Hardware AES not supported", hardAesCheckedAtRuntime && !randomx::cpu.hasAes(), []() {
 		assert(randomx_create_vm(RANDOMX_FLAG_HARD_AES, cache, nullptr) == nullptr);
 	});