arm64: dts: aspeed: shrink eDAF reserved region to 32MB - #319
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arm64: dts: aspeed: shrink eDAF reserved region to 32MB#319ankitaprasad2206 wants to merge 1 commit into
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rajaganeshr
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Sep 8, 2026
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| edaf0: eadf0-memory@428000000 { | ||
| reg = <0x4 0x28000000 0x0 0x4000000>; | ||
| reg = <0x4 0x28000000 0x0 0x2000000>; |
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Our DTS should override this node. The dtsi comes from Aspeed, and we usually don’t change it.
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Replace flash-edaf-tgt-addr phandles with a 64-bit target address so Mix-mode eDAF can program ESPI_CH3_EDAF_TADDR from DT. Keep Aspeed ast2700-reserved-mem.dtsi at the vendor 64MB edaf0 default. Override &edaf0 to 32MB in AMD board DTS so the reserved-memory size matches flash-edaf-size and the programmed translation mask. Tested - Tested on Morocco - Host boots and SOL logs are available Signed-off-by: Ankita Prasad <ankprasa@amd.com>
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amd-knieman
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Sep 8, 2026
| dev_err(dev, "cannot get eDAF memory region\n"); | ||
| return -ENODEV; | ||
| } | ||
| rc = of_property_read_u64(dev->of_node, "flash-edaf-tgt-addr", |
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Any particular reason for having this to allow for the old(flash-edaf-tgt-addr and flash-edaf-size) and new style (edaf0 with reg?
AspeedTech-BMC@1b160bb
New style should do the exact same thing.
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// Using the new way of
&edaf0 {
reg = <0x1 0x80000000 0x0 0x2000000>;
};
// Should be equivalent to
&espi0 {
...
flash-edaf-tgt-addr = <0x1 0x80000000>;
flash-edaf-size = <0x0 0x2000000>;
};
rajaganeshr
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Sep 9, 2026
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Resize edaf0 from 0x4000000 to 0x2000000 so the reserved-memory size matches flash-edaf-size and the programmed translation mask.
Tested