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fix(gic): use correct distributor registers for ESPI enable and routing - #653
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chetan-rathore merged 1 commit intoOct 23, 2026
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Extended SPI (ESPI) support in the GICv3 driver had two register addressing bugs: 1. v3_enable_extended_interrupt_source() wrote to GICD_ICENABLERE (Clear-Enable) instead of GICD_ISENABLERE (Set-Enable). As a result, attempting to enable an ESPI source would clear/disable it. Define GICD_ISENABLERE (0x1200) in acs_gic.h and write to it when enabling ESPI. 2. v3_route_extended_interrupt() programmed GICD_IROUTERn (0x6000, legacy SPI range) and did not subtract EXTENDED_SPI_START_INTID (4096) from int_id, writing to an incorrect offset well past the distributor routing space. Route ESPIs through GICD_IROUTERnE (0x8000) using the 0-based ESPI index (int_id - EXTENDED_SPI_START_INTID). Fixes ARM-software#605 Signed-off-by: La1itchauhan <chauhanlalitofficial@gmail.com>
chetan-rathore
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Oct 23, 2026
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Thanks @La1itchauhan for the contribution. |
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Summary
This PR fixes two distributor register addressing bugs in the GICv3 driver when handling Extended SPIs (ESPIs, INTIDs 4096..5119):
v3_enable_extended_interrupt_source()previously wrote toGICD_ICENABLERE(Clear-Enable, offset0x1400) instead ofGICD_ISENABLERE(Set-Enable, offset0x1200), unintentionally clearing/disabling the interrupt. Added#define GICD_ISENABLERE 0x1200toval/include/acs_gic.hand updated the driver to write toGICD_ISENABLERE.v3_route_extended_interrupt()previously usedGICD_IROUTERn(0x6000, intended only for standard SPIs up to INTID 1019) and multipliedint_id * 8directly without subtractingEXTENDED_SPI_START_INTID(4096), writing to an invalid out-of-bounds offset (0xE000). Corrected to useGICD_IROUTERnE(0x8000) indexed by(int_id - EXTENDED_SPI_START_INTID) * 8U.Fixes #605
Test Plan
GICD_ISENABLERE<n>:0x1200 + (4 * n)GICD_ICENABLERE<n>:0x1400 + (4 * n)GICD_IROUTER<n>E:0x8000 + (8 * n)val/driver/gic/v3/gic_v3_extended.cunderqemu-aarch64:enable ESPI 4133 (ISENABLERE)-> wrote offset0x1204(want0x1204) [PASS]disable ESPI 4133 (ICENABLERE)-> wrote offset0x1404(want0x1404) [PASS]route first ESPI 4096-> wrote offset0x8000(want0x8000) [PASS]route ESPI 4101-> wrote offset0x8028(want0x8028) [PASS]route last ESPI 5119-> wrote offset0x9ff8(want0x9ff8) [PASS]all checks passedI am a human contributor and I fully understand, reviewed, and verified the code and architectural offsets being submitted.
An AI coding assistant was used to help cross-reference the Arm IHI 0069 register map and format the unit test harness under my direction.