⚙️ FPGA Engineer · 🧠 Computer Architecture · 🔧 Compiler Engineer
FPGA Acceleration & EDA · RISC-V Processor & Security · HLS / MLIR Synthesis
📍 Beijing, China · 🎓 Beijing University of Technology
我是一名横跨硬件 / 体系结构 / 编译器三层计算栈的研究者，专注于高效能计算系统与开源 EDA 方法论。
Working across three layers of the computing stack — from silicon to toolchains:
| ⚙️ FPGA Engineer | 高性能加速器、HLS 设计流程、时序收敛与板级验证 |
| 🧠 Computer Architecture | RISC-V 处理器、安全核心、片上互联与内存系统 |
| 🔧 Compiler Engineer | 硬件综合、基于 MLIR 的优化、面向加速器的代码生成 |
- 🚀 Task-parallel HLS compilation for FPGA accelerators — TAPA
| Domain | Tools & Skills |
|---|---|
| 🧩 Hardware / FPGA | Verilog · SystemVerilog · Chisel · Vivado · Vitis HLS · Quartus · Verilator |
| 🧠 Architecture | RISC-V · AXI / AMBA · CPU & SoC design · on-chip interconnect |
| 🔧 Compilers / EDA | MLIR · LLVM · HLS · Yosys · OpenROAD · TAPA · XLS |
| 💻 Languages / Tools | C++ · Python · CMake · Shell · Git · Linux |
| Project | Description |
|---|---|
| TAPA | 将 TAPA（task-parallel HLS 编译器）移植到 V80 |
| XLS | 将 XLS（加速硬件综合）移植到其他 FPGA 工具链 |