data(cpu): fill process node and L3 cache for 84 AMD CPUs - #135
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84 AMD records gain 136 previously-null fields (process_node 84, l3_cache_mb 52) from the Wikipedia Athlon/Athlon 64/Phenom/FX/Sempron/ Turion list pages. Two source quirks had to be handled before anything was written: - These tables state the clock in MHz on some pages and GHz on others, so the value is normalised before it is compared (1500 -> 1.5). Without that the cross-check rejected every Sempron row. - One page (Athlon II) was caught filing a TDP figure in the L3 column -- it proposed "L3 = 65 MB" for a 65 W part and "100 MB" for a 100 W part, and a 4.0 GHz turbo for chips that have no turbo at all. Its row-derived values are therefore discarded entirely; only the node, which comes from the section heading rather than the row, is kept from that page. Values are additionally checked against the set of real cache capacities, and a turbo clock must exceed the base clock by a sane margin. The usual confirm-before-write rule still applies (base clock within 0.05 GHz, TDP within 1 W): 332 rows matched a record, 176 passed. Refs #1
Regenerates site/public/v1/cpus for the 84 records changed in the previous commit, with the engine at the pinned submodule commit. Only the pages whose content actually differs are committed; 7,871 timestamp-only pages are not. Refs #1
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…kipped Recovers records that the merged batches (#132-#135) left untouched because of three separate mismatches in how the pages name things, not because the data was unavailable: - model codes are not always digit-first (Core 2 uses E6600, Atom uses N270), and the table parser required a leading digit; - the Atom page is built entirely from {{cpulist}} templates and had never been run through that parser; - the Opteron page lists a bare model-number column with no branding column, so the family name now comes from the page itself. Same confirm-before-write rule as before (base clock within 0.05 GHz, TDP within 1 W, L3 must be a real capacity and must not equal the row's TDP): 1,610 rows parsed, 1,053 matched a record, 885 passed, 210 still had a gap to fill. Verified against known parts: Clarkdale i5-6xx/i3-5xx 32 nm, Haswell i7-4770R 22 nm, Broadwell i7-5775R 14 nm, Atom 330/D410 45 nm, Atom D2500 32 nm, Opteron Shanghai 6 MB L3. Older families whose rows failed the cross-check (Core 2 E-series, Atom N270, early Opteron) were left empty rather than guessed. Refs #1
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What
84 AMD records gain 136 previously-null fields —
process_node84,l3_cache_mb52 — from the Wikipedia Athlon / Athlon 64 / Phenom / FX / Sempron / Turion list pages.Running total across #132–#134 and this PR: CPU
process_node24% → 55%,l3_cache_mb19% → 54%.This batch is small on purpose
769 rows parsed, 332 matched a record, 176 passed the cross-check, and only 84 records had a gap left to fill (the rest were already covered by the earlier batches). AMD's list pages are far less uniform than Intel's, and two problems had to be solved before writing anything:
1. Mixed clock units. Some pages state the clock in MHz, others in GHz. Sempron rows read
1500against our1.5, so every one of them failed the cross-check. Normalising the unit turned that page from 1 trusted row into 30.2. A page that files TDP as cache. The Athlon II page proposed:
…plus a 4.0 GHz turbo for parts that have no turbo. Its columns are misaligned, so every row-derived value from that page is discarded; only
process_node, which comes from the section heading rather than the row, is kept.Guards added
After the guards the proposed values are 2/4/6/8 MB caches and 130/90/65/45/32 nm nodes — all real for these parts. All 7 source pages were HTTP-verified; every written record cites the specific page.
python -m app.validate→ Data validation passed. Dump refreshed for the 84 changed pages only.Closes #1