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harsh-patil28/README.md

Hi 👋, I'm Harsh Patil

ASIC Physical Design Engineer

harsh-patil28

  • ASIC Physical Design Engineer with 1.5+ years of experience

  • Hands-on experience in Synthesis, Physical Design, STA and Physical Verification

  • Experienced in block-level ASIC implementation from RTL to GDS

  • Hands-on with Cadence Genus, Innovus, Tempus and Siemens Tessent

  • Knowledge of TCL scripting

  • Experience with 22nm, 28nm and 45nm technologies

  • Strong interest in ASIC Physical Design and VLSI implementation

  • 📫 How to reach me harshp1832@gmail.com

  • 👨‍💻 All of my projects are available at https://github.com/Harsh-patil28

Connect with me:

harsh-patil-4170a3264 engineering enigma

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