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Kalana304
Downsampling_Processor
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Downsampling_Processor
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Verilog HDL of a downsampling processor
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Results
Results
db
db
greybox_tmp
greybox_tmp
incremental_db
incremental_db
simulation
simulation
work
work
1.UART - image transmit working.rar
1.UART - image transmit working.rar
1_Encoder.py
1_Encoder.py
2_Encoder.py
2_Encoder.py
3_Encoder.py
3_Encoder.py
C_ram.qip
C_ram.qip
C_ram.v
C_ram.v
C_ram_bb.v
C_ram_bb.v
Const_Mem.mif
Const_Mem.mif
Const_Mem.mif.bak
Const_Mem.mif.bak
DE2-115_PIN_ASSIGNMENTS.pdf
DE2-115_PIN_ASSIGNMENTS.pdf
DataEncoder.py
DataEncoder.py
Data_Mem.mif
Data_Mem.mif
Encoder.py
Encoder.py
Image.jpg
Image.jpg
ImageDecoder.py
ImageDecoder.py
ImageEncoder.py
ImageEncoder.py
Inst_mem.mem
Inst_mem.mem
Inst_mem_test.mem
Inst_mem_test.mem
InstructionEncoder.py
InstructionEncoder.py
Ironman.jpg
Ironman.jpg
Loadable_test.cr.mti
Loadable_test.cr.mti
Loadable_test.mpf
Loadable_test.mpf
Pocessor Design Report.pdf
Pocessor Design Report.pdf
Processor.v
Processor.v
Processor.v.bak
Processor.v.bak
Processor_test_1.cr.mti
Processor_test_1.cr.mti
Processor_test_1.mpf
Processor_test_1.mpf
ReadBus.v
ReadBus.v
ReadBus.v.bak
ReadBus.v.bak
Recieved_Memory.hex
Recieved_Memory.hex
Recieved_Memory_1.hex
Recieved_Memory_1.hex
Recieved_Memory_2.hex
Recieved_Memory_2.hex
Recieved_Memory_3.hex
Recieved_Memory_3.hex
ac.v
ac.v
ac.v.bak
ac.v.bak
alu.v
alu.v
alu.v.bak
alu.v.bak
controller.v
controller.v
controller.v.bak
controller.v.bak
coun.v
coun.v
coun.v.bak
coun.v.bak
cram.v
cram.v
cram.v.bak
cram.v.bak
decoder.v
decoder.v
decoder.v.bak
decoder.v.bak
dram.qip
dram.qip
dram.v
dram.v
dram_bb.v
dram_bb.v
dstr.v
dstr.v
dstr.v.bak
dstr.v.bak
ir.v
ir.v
ir.v.bak
ir.v.bak
iram.v
iram.v
iram.v.bak
iram.v.bak
main_controller.v
main_controller.v
main_controller.v.bak
main_controller.v.bak
mar.v
mar.v
mar.v.bak
mar.v.bak
pc.v
pc.v
pc.v.bak
pc.v.bak
reg1.v
reg1.v
reg1.v.bak
reg1.v.bak
reg2.v
reg2.v
reg2.v.bak
reg2.v.bak
reg3.v
reg3.v
reg3.v.bak
reg3.v.bak
reloaded_test.cr.mti
reloaded_test.cr.mti
reloaded_test.mpf
reloaded_test.mpf
slowclock.v
slowclock.v
slowclock.v.bak
slowclock.v.bak
sor.v
sor.v
sor.v.bak
sor.v.bak
tb.v
tb.v
tb.v.bak
tb.v.bak
tb2.cr.mti
tb2.cr.mti
tb2.mpf
tb2.mpf
tb3.cr.mti
tb3.cr.mti
tb3.mpf
tb3.mpf
top_processor.asm.rpt
top_processor.asm.rpt
top_processor.cdf
top_processor.cdf
top_processor.done
top_processor.done
top_processor.fit.rpt
top_processor.fit.rpt
top_processor.fit.smsg
top_processor.fit.smsg
top_processor.fit.summary
top_processor.fit.summary
top_processor.flow.rpt
top_processor.flow.rpt
top_processor.jdi
top_processor.jdi
top_processor.map.rpt
top_processor.map.rpt
top_processor.map.smsg
top_processor.map.smsg
top_processor.map.summary
top_processor.map.summary
top_processor.pin
top_processor.pin
top_processor.qpf
top_processor.qpf
top_processor.qsf
top_processor.qsf
top_processor.qws
top_processor.qws
top_processor.sld
top_processor.sld
View all files
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Verilog HDL of a downsampling processor
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