Skip to content

fix(mir-lower): stabilize shared pointer union storage - #1335

Open
YunusMutlu wants to merge 1 commit into
NVIDIA:mainfrom
YunusMutlu:fix/union-shared-pointer-storage
Open

YunusMutlu wants to merge 1 commit into
NVIDIA:mainfrom
YunusMutlu:fix/union-shared-pointer-storage

Conversation

@YunusMutlu

Copy link
Copy Markdown
Contributor

Fixes #1334

Summary

Fix union lowering for shared-memory pointer fields whose physical width depends on the selected backend data layout. Under modern NVVM (p3:32), an AS3 pointer could previously become a 32-bit store into union storage that was subsequently read through an 8-byte field. This change uses the existing target-stable storage machinery for union fields and converts between semantic and physical representations at union insert/extract boundaries.

Changes

  • Use target-stable physical storage for union fields containing shared-memory pointers, recursively rewriting AS3 pointer leaves to generic pointers.
  • Preserve the existing semantic pointer compatibility checks before selecting the physical storage representation.
  • Convert values between semantic and target-stable representations when inserting into and extracting from union storage.
  • Validate that the target-stable representation preserves the field's expected size and alignment.
  • Bound array-expanded shared-pointer rewrites to 16 leaves to avoid unbounded extract/cast/insert expansion.
  • Add regression coverage for:
    • direct shared-pointer union fields;
    • shared pointers nested inside structs;
    • target-stable shared-pointer storage selection;
    • the array rewrite bound and rejection above the bound.

Testing

  • just check passes (the local mirror of CI: fmt, clippy, tests, guards, docs)
  • cargo oxide run union_aggregate passes on sm_86 (union_aggregate: PASS)
  • New example added (not applicable; regression coverage is in mir-lower tests)

Additional verification:

  • cargo test -p mir-lower passes.
  • git diff --check passes.
  • Reproduced Shared-memory pointer union can emit a partial 32-bit store under p3:32 #1334 on clean upstream/main at ec4aa479 when compiling for sm_120.
  • Verified the unfixed optimized IR reduces the shared-pointer union write to a 32-bit store under the modern p3:32 layout.
  • Verified the fixed path uses a target-stable generic-pointer representation and produces a full 64-bit store for the same case.
  • Verified the existing union_aggregate runtime example still passes on sm_86 hardware.

Checklist

  • All commits signed off (git commit -s)
  • SPDX headers on new source files (N/A; no new source files)

@nihalpasham nihalpasham added the cuda-oxide SIMT programming model: rustc backend, cargo oxide, cuda-device, cuda-host, book label Oct 11, 2026
Fixes NVIDIA#1334

Signed-off-by: Yunus Mutlu <mutluyunus708@gmail.com>
@YunusMutlu
YunusMutlu force-pushed the fix/union-shared-pointer-storage branch from 20339f7 to b6ad993 Compare October 13, 2026 10:59
@copy-pr-bot

copy-pr-bot Bot commented Oct 13, 2026

Copy link
Copy Markdown

This pull request requires additional validation before any workflows can run on NVIDIA's runners.

Pull request vetters can view their responsibilities here.

Contributors can view more details about this message here.

This branch has not been deployed

No deployments
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

cuda-oxide SIMT programming model: rustc backend, cargo oxide, cuda-device, cuda-host, book

Projects

None yet

Development

Successfully merging this pull request may close these issues.

Shared-memory pointer union can emit a partial 32-bit store under p3:32

3 participants