Issues

• Verilog attributes not kept when verilog is generated

  Nic30/hdlConvertor#206 · Filter by author fjullien opened on Sep 18, 2025
  3

• HDLConverter - Project Issue in parsing assign statement

  Nic30/hdlConvertor#198 · Filter by author nitinhariharan opened on Mar 13, 2025

• Package and Interface level information is missing

  Nic30/hdlConvertor#196 · Filter by author nitinhariharan opened on Mar 10, 2025
  2

• Prebuilt Binary Release to PyPi

  Nic30/hdlConvertor#187 · Filter by author khwong-c opened on Jan 5, 2024 · v2.4
  16

• (System)Verilog parallel_case attribute is not supported

  Nic30/hdlConvertor#185 · Filter by author KatCe opened on Oct 17, 2023
  1

• Using updated SV/Verilog, VHDL Grammars

  Nic30/hdlConvertor#178 · Filter by author AmeyaVS opened on Apr 17, 2023
  2

• Updating Git Submodules For Tests

  Nic30/hdlConvertor#177 · Filter by author AmeyaVS opened on Apr 16, 2023
  1

• Verilog2017 - unpacked array converted as packed

  Nic30/hdlConvertor#169 · Filter by author diffore opened on Jun 14, 2022
  2

• Convert VHDL package to Verilog or SV

  Nic30/hdlConvertor#168 · Filter by author jabate-anova opened on Apr 5, 2022
  3

• incorrect Position

  Nic30/hdlConvertor#166 · Filter by author Thomasb81 opened on Feb 5, 2022
  6

• Preprocessor - expose complete parser?

  Nic30/hdlConvertor#165 · Filter by author the-moog opened on Dec 24, 2021
  12

• Handling extraneous commas (SystemVerilog)

  Nic30/hdlConvertor#163 · Filter by author the-moog opened on Nov 26, 2021
  1

• Replace scikit-build/cmake with mesonpep517/meson (potential drop of python2.7 support)

  Nic30/hdlConvertor#162 · Filter by author Nic30 opened on Nov 20, 2021
  1

• SystemVerilog import package - doesn't seem to do anything?

  Nic30/hdlConvertor#149 · Filter by author flemish4 opened on Jan 26, 2021
  8

• VHDL: proper tests for comment parsing

  Nic30/hdlConvertor#148 · Filter by author Nic30 opened on Jan 22, 2021

• VHDL: Arrays of unbounded elements not working correctly.

  Nic30/hdlConvertor#141 · Filter by author mewais opened on Oct 10, 2020

• VHDL: Slicing and range attributes incorrectly identified as function calls.

  Nic30/hdlConvertor#140 · Filter by author mewais opened on Oct 7, 2020
  13

• Package Instantiation in VHDL

  Nic30/hdlConvertor#136 · Filter by author mewais opened on Aug 27, 2020
  2

• Add file name to CodePosition

  Nic30/hdlConvertor#134 · Filter by author tictacmenthe opened on Aug 26, 2020
  5

• BLIF support

  Nic30/hdlConvertor#132 · Filter by author mewais opened on Jul 27, 2020
  7

• notebooks with examples

  Nic30/hdlConvertor#131 · Filter by author Nic30 opened on Jun 19, 2020

• Optional compiler directives

  Nic30/hdlConvertor#99 · Filter by author Thomasb81 opened on Nov 24, 2019
  1

• Elaboration?

  Nic30/hdlConvertor#96 · Filter by author hs-apotell opened on Nov 14, 2019
  19

• Support for static library build

  Nic30/hdlConvertor#95 · Filter by author hs-apotell opened on Nov 14, 2019
  5

• finish the integration with sv-tests

  Nic30/hdlConvertor#92 · Filter by author Nic30 opened on Nov 13, 2019
  1