[phix33]

On every PowerPC language, a lwarx/stwcx. retry loop decompiles as a loop
instead of as one atomic update. In the output below, v1 is never assigned,
so the store and the loop exit both depend on an uninitialized value.

printf '\tlwarx 9,0,3\n\taddi 9,9,1\n\tstwcx. 9,0,3\n\tbne- .-12\n\tblr\n' > atomic.s
powerpc-linux-gnu-as atomic.s -o atomic.o
powerpc-linux-gnu-ld -Ttext=0x10000 -e 0x10000 atomic.o -o atomic.elf
kuna decompile atomic.elf 0x10000 --addr

void sub_10000(int *a0)
{
  char v1; // reserve
  unsigned char v2; // cr0
  
  do {
    if (v1) {
      *a0 = storeWordConditionalIndexed(*a0 + 1,0,a0);
      v2 = 2;
    }
  } while (!(bool)(v2 >> 1 & 1));
}

With the fix this is *a0 = storeWordConditionalIndexed(*a0 + 1,0,a0);.
Compiled __atomic_fetch_add, compare-exchange, exchange and spinlock code
shows the same pattern.

Fix

• stwcx. and stdcx. skip their store while RESERVE is 0, but lwarx in
  ppc_instructions.sinc had its reservation setup commented out, with a
  misspelled register name. It now sets RESERVE, RESERVE_LENGTH and
  RESERVE_ADDRESS, as the ISA lwarx does.
• That constructor fixes the hint bit at 0, so for ordinary encodings it is
  chosen over the ISA one in the ISA languages too. All 23 PowerPC languages
  were affected, and all now produce the single conditional store.

Tests

• tests/stages/kuna-ppc-lwarx-reservation.xml: the loop above on
  PowerPC:BE:32:default. It passes 0/2 without the fix and 2/2 with it.
• kuna-sleigh ppc_lwarx_reservation: lwarx writes all three reservation
  registers on generic 32- and 64-bit, e500 and ISA languages. It fails on the
  unpatched specs.
• The datatest corpus is unchanged (675/675). No other stage expectation moved.