ARM: dts: hi3536dv100: give the hibvt i2c controller its interrupt

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Same change as #94 (hisilicon-hi3516cv500), for hi3536dv100.dtsi. Its one hibvt I2C node, i2c@120c0000, has no interrupts property, so i2c-hibvt polls.

The problem

In polling mode a transfer that never completes spins udelay(50) up to 0x10000 times, 3.28 s, on the SoC's only core, before wait idle timeout. An NVR has nothing on that bus.

On a lab Hi3536DV100 NVR, one full ipctool report issued 38 such transfers:

• the board stopped answering ping and ssh for about two minutes;
• carrier stayed up, and a ping loop on the NVR itself managed one iteration every ~13 s.

(ipctool no longer probes for a sensor on this chip: OpenIPC/ipctool#250. Any other I2C user still pays the polling cost.)

The fix

interrupts = <0 10 4>: the Hi3536DV100 data sheet's interrupt table gives I2C as bit 42, which is SPI 10. Nothing else in this dtsi uses SPI 10.

Tested

• The interrupt line, on the NVR (stock kernel, read-only to the GIC):

  • devmem 0x120c00e4 32 0x1fff (the controller's INTR_EN) makes GICD_ISPENDR1 (0x10301204) read 0x00000400, i.e. bit 10 = ID 42 pending.
  • Writing 0 back clears it.

• Interrupt mode on hardware: the cv500 change in ARM: dts: hi3516cv500/hi3516dv300: give the hibvt i2c controllers their interrupts #94 ran on a Hi3516AV300, where the sensor works over I2C and failed transfers come back by interrupt in 10 ms.

• Booted on the NVR: I flashed this branch's DTB onto the NVR's own kernel (its flash zImage with only the appended DTB replaced, which differs by this one line). Then I restored the original kernel afterwards (MD5 verified).

  • /proc/interrupts shows 120c0000.i2c at GIC 42.
  • 38 transfers to the empty bus took 39.7 s: about 1.04 s each, the driver's 1-second completion timeout, spent sleeping, ending in tx timeout. Before, it was 3.3 s each of busy-waiting.
  • A ping loop on the NVR recorded 316/316 replies over 70 s while they ran. The board stays responsive, where before it froze for about two minutes.

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PR Summary by Qodo

ARM: hi3536dv100: assign the hibvt I2C controller interrupt

🐞 Bug fix 🕐 Less than 10 minutes

AI Description

• Assign GIC SPI 10 to the Hi3536DV100 hibvt I2C controller, enabling interrupt-driven transfers.
• Avoid CPU-blocking polling on failed transfers; hardware testing confirmed the NVR stays
 responsive.

Diagram

graph TD
  D["I2C DT node"] --> H["hibvt driver"] --> G["GIC SPI 10"] --> W["Completion wakeup"]
  H --> W

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High-Level Assessment

Adding the missing interrupt to the device tree is the appropriate fix: the existing driver already supports interrupt-driven transfers, so changing its polling logic is unnecessary.

Files changed (1) +1 / -0

Bug fix (1) +1 / -0

hi3536dv100.dtsiAssign SPI 10 to the hibvt I2C controller +1/-0

Assign SPI 10 to the hibvt I2C controller

• Adds 'interrupts = <0 10 4>' to 'i2c@120c0000', allowing the existing hibvt driver to use interrupt mode rather than polling when the controller is enabled.

arch/arm/boot/dts/hi3536dv100.dtsi

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Code Review by Qodo

🐞 Bugs (0) 📘 Rule violations (0) 📎 Requirement gaps (0)

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