PeakRDL provides an "external" register attribute that creates a req/ack protocol interface for the register reads. However, reads on registers implemented as "external" are causing a reboot loop on the ADALM-Pluto device which uses the Zynq-Z7010 FPGA. Presumably the AXI4Lite bus is "unhappy" with some aspect of the register read using the req/ack protocol. Perhaps this is because of the wait-states required until the ack is received to complete the AXI read transaction.
The task is to debug the AXI interface when using external registers to determine the root cause of the reboot loop.
PeakRDL provides an "external" register attribute that creates a req/ack protocol interface for the register reads. However, reads on registers implemented as "external" are causing a reboot loop on the ADALM-Pluto device which uses the Zynq-Z7010 FPGA. Presumably the AXI4Lite bus is "unhappy" with some aspect of the register read using the req/ack protocol. Perhaps this is because of the wait-states required until the ack is received to complete the AXI read transaction.
The task is to debug the AXI interface when using external registers to determine the root cause of the reboot loop.