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3b35c96
Bonsai 2 27B (PTQ1_0) on Intel Arc B580: SYCL + Vulkan performance work
Torchit1 Sep 26, 2026
e0b174d
sycl: PQ2_0 weights on the TernSYCL XMX path too (GGML_SYCL_PTQ1_T2)
Torchit1 Sep 27, 2026
6836929
sycl: PTQ1 T2 path only on Xe2+ GPUs, fall back with a warning elsewhere
Torchit1 Sep 27, 2026
48ffc2e
sycl/ternsycl: 64-bit surface base address on Windows
Torchit1 Sep 27, 2026
c8e3bfc
sycl: GGML_SYCL_PTQ1_T2_TILE lab knob for the TernSYCL large-M tile (…
Torchit1 Sep 27, 2026
af00847
sycl: two-pass top-k for long rows (GGML_SYCL_TOPK_OLD=1 restores the…
Torchit1 Sep 27, 2026
cd93812
sycl: q4_0 decode attention on XMX via s8 x s4 DPAS (opt-in GGML_SYCL…
Torchit1 Sep 27, 2026
fa64caa
sycl: MKL flash-attention softmax, one work-group per query row
Torchit1 Sep 27, 2026
bf5feb2
sycl: GGML_SYCL_MMVQ_CHUNK_MAX, largest batch run as MMVQ column chunks
Torchit1 Sep 27, 2026
82d8626
sycl: oneDNN / MKL flash attention only for packed interleaved K/V
Torchit1 Sep 27, 2026
4210fca
sycl: XMX decode attention only on Xe2+, fall back with a warning els…
Torchit1 Sep 27, 2026
03f06b0
sycl: XMX q4_0 decode attention for Gemma 4 (head 512 x GQA 16 global…
Torchit1 Sep 27, 2026
76067c4
sycl: reordered q4_0 small-batch GEMM on XMX via s8 x s4 DPAS (opt-in…
Torchit1 Sep 28, 2026
22d436f
sycl: large T2 prompt batches through oneDNN's int8 GEMM (GGML_SYCL_T…
Torchit1 Sep 28, 2026
837ba6b
SYCL decode attention: SLM-staged K/V tiles for 1 query token, one-wa…
Torchit1 Oct 2, 2026
0f16f1d
SYCL: s8 x s4 DPAS as inline vISA instead of the intel_sub_group_i8_i…
Torchit1 Oct 3, 2026
9d262b5
SYCL: no IGC builtins left (TernSYCL main, f16 DPAS via vISA), device…
Torchit1 Oct 3, 2026
1bb8282
SYCL decode attention: default DPAS cap 32 -> 256 query tokens
Torchit1 Oct 3, 2026
1d3b194
SYCL decode attention: 5-token query chunks for MTP verifies
Torchit1 Oct 3, 2026
53744cc
lab: runtime-switchable SYCL tuning knobs (GGML_SYCL_KNOBS_FILE); LLA…
Torchit1 Oct 3, 2026
7ab9e58
sycl: T2 quantized-activation cache + fused Hadamard rotate/quantize
Torchit1 Oct 3, 2026
846c033
sycl: fuse residual add + RMS norm into the T2 rotate/quantize kernel
Torchit1 Oct 3, 2026
975a359
sycl: vendored TernSYCL -> 8b0ae42, drop the -fp-model=precise override
Torchit1 Oct 4, 2026
1f16921
sycl: lab knob GGML_SYCL_T2_ZERO_WEIGHTS (zeroes T2 weights to profil…
Torchit1 Oct 5, 2026
870f3c8
sycl: lab instrumentation - host token timing (GGML_SYCL_HOST_TIMING)…
Torchit1 Oct 5, 2026
204450d
sycl: fuse the DeltaNet conv chain for one-token decode (GGML_SYCL_CO…
Torchit1 Oct 5, 2026
c44f996
sycl: fuse the DeltaNet gate block (GGML_SYCL_DN_GATES)
Torchit1 Oct 5, 2026
b7a7af1
sycl: same-input T2 mat-vecs in one launch (GGML_SYCL_T2_MULTI)
Torchit1 Oct 5, 2026
6fe6440
sycl: fold FFN SwiGLU and the DeltaNet pre-norm into the T2 rotation
Torchit1 Oct 5, 2026
7a650fc
sycl: per-batch-size GemmMT tile for T2 (small tile up to 32 rows); G…
Torchit1 Oct 5, 2026
3c5fdcd
sycl: decode attention prefetches the next phase's key rows (GGML_SYC…
Torchit1 Oct 5, 2026
1fe355a
tests: arctune fusion tests for the SYCL fusions; fusion guard fixes
Torchit1 Oct 5, 2026
844a387
ptq1-t2: GGML_SYCL_PTQ1_T2_TUNED per-shape GEMV tile table (plumbing,…
Torchit1 Oct 9, 2026
86134e0
ptq1-t2: GGML_SYCL_PTQ1_T2_TUNED table from the B580 GEMV sweep (bit-…
Torchit1 Oct 9, 2026
26cd716
ptq1-t2: tuned GEMV tiles on by default on a B580 (GGML_SYCL_PTQ1_T2_…
Torchit1 Oct 9, 2026
174e85d
sycl: default to the legacy Level Zero adapter unless SYCL_UR_USE_LEV…
Torchit1 Oct 10, 2026
58e4b0b
sycl: tuned Q6_K mat-vec and fused Q6_K gate+up+SWIGLU for the MTP dr…
Torchit1 Oct 10, 2026
6cc6323
sycl fattn-dec: transposed 2D block loads for the DPAS kernel's lane …
Torchit1 Oct 10, 2026
82aad28
sycl fattn-dec: 256-register file for the DPAS decode kernel at 3+ qu…
Torchit1 Oct 10, 2026
b7c8d8c
sycl: one in-place layout owner for PQ2_0/PTQ1_0 weights
bri-prism Oct 13, 2026
888d75e
sycl: drop PQ2_0/PTQ1_0 duplicates left by the arc-b580 merge
bri-prism Oct 13, 2026
9485154
sycl: Xe3 defaults to the MMVQ reorder for PQ2_0/PTQ1_0 and to XMX de…
bri-prism Oct 13, 2026
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9 changes: 9 additions & 0 deletions common/speculative.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -3490,6 +3490,15 @@ common_params common_base_params_to_speculative(const common_params & params) {
result.cache_type_k = params_spec.cache_type_k;
result.cache_type_v = params_spec.cache_type_v;

// ARC-LAB: the draft context inherits the target's physical batch (2048 on the Arc server = a 784 MiB compute
// buffer for an MTP layer that drafts 1-3 tokens); its prompt catch-up already runs in n_ubatch chunks.
if (const char * ub = getenv("LLAMA_ARG_SPEC_DRAFT_UBATCH")) {
const int32_t n = atoi(ub);
if (n > 0 && n < result.n_ubatch) {
result.n_ubatch = n;
}
}

// the K-cache mean-center bias is calibrated for the target model
// (per-head/channel K layout); the draft model has a different K
// geometry, so it must not inherit the bias
Expand Down
9 changes: 9 additions & 0 deletions ggml/src/ggml-sycl/CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -105,6 +105,15 @@ endif()

target_compile_options(ggml-sycl PRIVATE "-Wno-narrowing")

# ARC-LAB: one device image per kernel. The Xe2 XMX kernels (DPAS) then only get JIT-compiled when they are first launched,
# so a GPU without DPAS (Xe-LP, Gen9) never compiles them; with one image per source file, compiling any kernel of
# fattn-dec / mmvq / ptq1-t2 built the DPAS ones too and the shader compiler crashed (UHD 630). OFF = compiler default.
option(GGML_SYCL_DEVICE_CODE_SPLIT_PER_KERNEL "ggml: SYCL device code split per kernel" ON)
if (GGML_SYCL_DEVICE_CODE_SPLIT_PER_KERNEL)
target_compile_options(ggml-sycl PRIVATE "-fsycl-device-code-split=per_kernel")
target_link_options(ggml-sycl PRIVATE "-fsycl-device-code-split=per_kernel")
endif()

message(STATUS "GGML_SYCL_SUPPORT_LEVEL_ZERO_API ${GGML_SYCL_SUPPORT_LEVEL_ZERO_API}")
if (GGML_SYCL_SUPPORT_LEVEL_ZERO_API)
# Link against Level Zero loader for direct device memory allocation.
Expand Down
9 changes: 9 additions & 0 deletions ggml/src/ggml-sycl/common.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -60,6 +60,8 @@ void ggml_sycl_host_free(void* ptr);

extern int g_ggml_sycl_debug;
extern int g_ggml_sycl_enable_optimize;
extern int g_ggml_sycl_quant_f16_gemm;
extern int g_ggml_sycl_quant_s4_gemm;
extern int g_ggml_sycl_enable_fusion;
extern int g_ggml_sycl_enable_esimd;
extern int g_ggml_sycl_prioritize_dmmv;
Expand Down Expand Up @@ -225,6 +227,7 @@ inline dpct::err0 ggml_sycl_set_device(const int device) try {
struct optimize_feature {
bool reorder=false;
bool xmx_pq2=false; // PQ2_0 rewritten into the XMX layout (pq2_xmx.hpp); only that path can read it
bool t2=false; // ARC-LAB: PTQ1_0 repacked to the TernSYCL 2-bit layout (ptq1-t2.cpp)
};

struct sycl_device_info {
Expand Down Expand Up @@ -1041,4 +1044,10 @@ static __dpct_inline__ float ggml_sycl_ue4m3_to_fp32(uint8_t x) {
return raw * 0.5f;
}

// ARC-LAB lab knobs: integer tuning switches read through here can be changed while the process runs. With
// GGML_SYCL_KNOBS_FILE=<path> set, the file (NAME=VALUE lines) is re-read at the start of a graph compute when its
// mtime changes and its values override the environment; without it, each knob is read from the environment once.
int ggml_sycl_knob(const char * name, int def);
void ggml_sycl_knobs_refresh();

#endif // GGML_SYCL_COMMON_HPP
17 changes: 17 additions & 0 deletions ggml/src/ggml-sycl/concat.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -94,6 +94,23 @@ template <typename T>
static void concat_T_sycl(const T *x, const T *y, T *dst,
int ne00, int ne01, int ne02, int ne0, int ne1,
int ne2, int dim, queue_ptr stream) {
if (dim == 0 && ne0 < SYCL_CONCAT_BLOCK_SIZE) {
// ARC-LAB: narrow rows (delta-net conv state: 3 + 1 columns x 10240 channels) launched one work-group of 256 per
// row with 4 active lanes (12.5 us per call on the B580); one lane per element instead.
const int total = ne0 * ne1 * ne2;
const int nblk = (total + SYCL_CONCAT_BLOCK_SIZE - 1) / SYCL_CONCAT_BLOCK_SIZE;
stream->parallel_for(sycl::nd_range<1>(nblk * SYCL_CONCAT_BLOCK_SIZE, SYCL_CONCAT_BLOCK_SIZE),
[=](sycl::nd_item<1> it) {
const int i = it.get_global_id(0);
if (i >= total) {
return;
}
const int i0 = i % ne0;
const int row = i / ne0; // i1 + i2 * ne1
dst[i] = i0 < ne00 ? x[row * ne00 + i0] : y[row * (ne0 - ne00) + i0 - ne00];
});
return;
}
int num_blocks = (ne0 + SYCL_CONCAT_BLOCK_SIZE - 1) / SYCL_CONCAT_BLOCK_SIZE;
sycl::range<3> gridDim(ne2, ne1, num_blocks);
switch (dim) {
Expand Down
118 changes: 114 additions & 4 deletions ggml/src/ggml-sycl/convert.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -170,6 +170,35 @@ static void dequantize_row_q4_0_sycl_reorder(const void *vx, dst_t *y, const int

}

template <typename dst_t>
static void dequantize_row_pq2_0_sycl_reorder(const void * vx, dst_t * y, const int64_t k, dpct::queue_ptr stream) {
GGML_ASSERT(k % QK_PQ2_0 == 0);
const uint8_t * qs = (const uint8_t *) vx;
const sycl::half * d = (const sycl::half *) (qs + k / 4);
stream->parallel_for(sycl::range<1>(k / 4), [=](sycl::id<1> i) {
const float dv = d[i / (QK_PQ2_0 / 4)];
const uint8_t q = qs[i];
#pragma unroll
for (int j = 0; j < 4; ++j) {
y[i * 4 + j] = (float) (((q >> (2 * j)) & 3) - 1) * dv;
}
});
}

template <typename dst_t>
static void dequantize_row_ptq1_0_sycl_reorder(const void * vx, dst_t * y, const int64_t k, dpct::queue_ptr stream) {
GGML_ASSERT(k % QK_PTQ1_0 == 0);
const int64_t nb = k / QK_PTQ1_0;
const uint8_t * qs = (const uint8_t *) vx;
const uint8_t * qh = qs + nb * 24;
const sycl::half * d = (const sycl::half *) (qs + nb * 26);
stream->parallel_for(sycl::range<1>(k), [=](sycl::id<1> id) {
const int64_t i = id[0];
const int64_t ib = i / QK_PTQ1_0;
y[i] = (float) (ptq1_0_trit(qs + ib * 24, qh + ib * 2, (int) (i % QK_PTQ1_0)) - 1) * (float) d[ib];
});
}

template <typename dst_t>
static void dequantize_row_q8_0_sycl_reorder(const void *vx, dst_t *y, const int64_t k,
dpct::queue_ptr stream) {
Expand Down Expand Up @@ -657,12 +686,20 @@ to_fp16_sycl_t ggml_get_to_fp16_sycl(ggml_type type, ggml_tensor * dst) {
switch (type) {
case GGML_TYPE_Q1_0:
return dequantize_block_sycl<QK1_0, QR1_0, dequantize_q1_0>;
case GGML_TYPE_Q2_0:
return dequantize_block_sycl<QK2_0, QR2_0, dequantize_q2_0>;
case GGML_TYPE_PTQ1_0:
if (dst->src[0]->extra &&
((ggml_tensor_extra_gpu *) dst->src[0]->extra)->optimized_feature.reorder) {
return dequantize_row_ptq1_0_sycl_reorder;
}
return dequantize_block_sycl<QK_PTQ1_0, QR_PTQ1_0, dequantize_ptq1_0>;
case GGML_TYPE_PQ2_0:
if (dst->src[0]->extra &&
((ggml_tensor_extra_gpu *) dst->src[0]->extra)->optimized_feature.reorder) {
return dequantize_row_pq2_0_sycl_reorder;
}
return dequantize_block_sycl<QK_PQ2_0, QR_PQ2_0, dequantize_pq2_0>;
case GGML_TYPE_Q2_0:
return dequantize_block_sycl<QK2_0, QR2_0, dequantize_q2_0>;
case GGML_TYPE_Q4_0:
if (dst->src[0]->extra &&
((ggml_tensor_extra_gpu*)dst->src[0]->extra)->optimized_feature.reorder) {
Expand Down Expand Up @@ -751,12 +788,20 @@ to_fp32_sycl_t ggml_get_to_fp32_sycl(ggml_type type, ggml_tensor *dst) {
switch (type) {
case GGML_TYPE_Q1_0:
return dequantize_block_sycl<QK1_0, QR1_0, dequantize_q1_0>;
case GGML_TYPE_Q2_0:
return dequantize_block_sycl<QK2_0, QR2_0, dequantize_q2_0>;
case GGML_TYPE_PTQ1_0:
if (dst->src[0]->extra &&
((ggml_tensor_extra_gpu *) dst->src[0]->extra)->optimized_feature.reorder) {
return dequantize_row_ptq1_0_sycl_reorder;
}
return dequantize_block_sycl<QK_PTQ1_0, QR_PTQ1_0, dequantize_ptq1_0>;
case GGML_TYPE_PQ2_0:
if (dst->src[0]->extra &&
((ggml_tensor_extra_gpu *) dst->src[0]->extra)->optimized_feature.reorder) {
return dequantize_row_pq2_0_sycl_reorder;
}
return dequantize_block_sycl<QK_PQ2_0, QR_PQ2_0, dequantize_pq2_0>;
case GGML_TYPE_Q2_0:
return dequantize_block_sycl<QK2_0, QR2_0, dequantize_q2_0>;
case GGML_TYPE_Q4_0:
if (dst->src[0]->extra &&
((ggml_tensor_extra_gpu*)dst->src[0]->extra)->optimized_feature.reorder) {
Expand Down Expand Up @@ -887,3 +932,68 @@ to_fp16_nc_sycl_t ggml_get_to_fp16_nc_sycl(ggml_type type) {
return nullptr;
}
}

void ggml_sycl_quant_to_s4(ggml_type type, bool reordered, const void * vx, uint8_t * w4, float * scales,
int64_t nrows, int64_t ncols, dpct::queue_ptr stream) {
GGML_ASSERT(type == GGML_TYPE_PQ2_0 || type == GGML_TYPE_PTQ1_0);
GGML_ASSERT(ncols % 128 == 0);
const int64_t nb = nrows * ncols / 128;
const uint8_t * base = (const uint8_t *) vx;
const bool ptq = type == GGML_TYPE_PTQ1_0;
// one work item = 8 elements = one uint32 of s4
stream->parallel_for(sycl::range<1>(nb * 16), [=](sycl::id<1> id) {
const int64_t ib = id[0] / 16;
const int c = (int) (id[0] % 16);
int v[8];
sycl::half d;
if (ptq) {
const uint8_t * qs;
const uint8_t * qh;
if (reordered) {
qs = base + ib * 24;
qh = base + nb * 24 + ib * 2;
d = ((const sycl::half *) (base + nb * 26))[ib];
} else {
const block_ptq1_0 * x = (const block_ptq1_0 *) vx + ib;
qs = x->qs;
qh = x->qh;
d = x->d;
}
// trit t of byte b = ((b * 3^t) mod 256) * 3 >> 8
constexpr uint32_t pow3[5] = { 1, 3, 9, 27, 81 };
if (c < 10) { // elements t*16 + m, 8 consecutive m
const uint32_t p = pow3[c / 2];
const int m = (c % 2) * 8;
#pragma unroll
for (int i = 0; i < 8; ++i) v[i] = (int) ((((qs[m + i] * p) & 0xFF) * 3) >> 8) - 1;
} else if (c < 15) { // elements 80 + t*8 + m, m = 0..7
const uint32_t p = pow3[c - 10];
#pragma unroll
for (int i = 0; i < 8; ++i) v[i] = (int) ((((qs[16 + i] * p) & 0xFF) * 3) >> 8) - 1;
} else { // elements 120 + t*2 + h
#pragma unroll
for (int i = 0; i < 8; ++i) v[i] = (int) ((((qh[i % 2] * pow3[i / 2]) & 0xFF) * 3) >> 8) - 1;
}
} else {
const uint8_t * qs;
if (reordered) {
qs = base + ib * 32;
d = ((const sycl::half *) (base + nb * 32))[ib];
} else {
const block_pq2_0 * x = (const block_pq2_0 *) vx + ib;
qs = x->qs;
d = x->d;
}
#pragma unroll
for (int i = 0; i < 8; ++i) v[i] = ((qs[2 * c + i / 4] >> (2 * (i % 4))) & 3) - 1;
}
uint32_t out = 0;
#pragma unroll
for (int i = 0; i < 8; ++i) out |= (uint32_t) (v[i] & 0xF) << (4 * i);
((uint32_t *) w4)[id[0]] = out;
if (c == 0) {
const int64_t bpr = ncols / 128;
scales[(ib % bpr) * nrows + ib / bpr] = d; // [group][row]
}
});
}
5 changes: 5 additions & 0 deletions ggml/src/ggml-sycl/convert.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,11 @@ typedef to_t_sycl_t<float> to_fp32_sycl_t;
typedef to_t_sycl_t<sycl::half> to_fp16_sycl_t;

to_fp16_sycl_t ggml_get_to_fp16_sycl(ggml_type type, ggml_tensor * dst);

// PQ2_0 / PTQ1_0 rows -> packed s4 (low nibble = even element) + f32 scales laid out [group][row].
// All their values (-1..2) are exact in s4.
void ggml_sycl_quant_to_s4(ggml_type type, bool reordered, const void * vx, uint8_t * w4, float * scales,
int64_t nrows, int64_t ncols, dpct::queue_ptr stream);
to_fp32_sycl_t ggml_get_to_fp32_sycl(ggml_type type, ggml_tensor * dst);

#ifdef GGML_SYCL_HAS_BF16
Expand Down
20 changes: 20 additions & 0 deletions ggml/src/ggml-sycl/dequantize.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -47,6 +47,26 @@ static __dpct_inline__ void dequantize_q2_0(const void *vx, const int64_t ib,
#endif // GGML_SYCL_F16
}

// Trit of element e (0..127) in a PTQ1_0 block: 16 bytes x 5, 8 bytes x 5, then 2 qh bytes x 4.
static __dpct_inline__ int ptq1_0_trit(const uint8_t * qs, const uint8_t * qh, const int e) {
uint32_t v;
int t;
if (e < 80) {
v = qs[e % 16];
t = e / 16;
} else if (e < 120) {
v = qs[16 + (e - 80) % 8];
t = (e - 80) / 8;
} else {
v = qh[(e - 120) % 2];
t = (e - 120) / 2;
}
for (int i = 0; i < t; ++i) {
v = (v * 3) & 0xFF;
}
return (int) ((v * 3) >> 8);
}

static __dpct_inline__ void dequantize_q4_0(const void *vx, const int64_t ib,
const int iqs, dfloat2 &v) {
const block_q4_0 * x = (const block_q4_0 *) vx;
Expand Down
38 changes: 36 additions & 2 deletions ggml/src/ggml-sycl/dmmv.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -238,6 +238,34 @@ static void convert_mul_mat_vec_f16_sycl(const void *vx, const dfloat *y,
}

#ifdef GGML_SYCL_DMMV_HAS_BF16
// ARC-LAB: small-output bf16 mat-vec (Bonsai's delta-net gate projections: 48 x 5120, 96 calls per token).
// The generic dequantize_mul_mat_vec gives each row one sub-group, so 48 rows used 48 sub-groups and reached
// ~25 GB/s on the B580 (~20 us per call). Here each row gets a 256-wide work-group that splits K, loads 8 bf16
// at a time and reduces over the group.
static void bf16_gemv_rowsplit_sycl(const void * vx, const dfloat * y, float * dst, const int ncols,
const int nrows, dpct::queue_ptr stream) {
constexpr int WG = 256;
stream->parallel_for(
sycl::nd_range<1>(sycl::range<1>((size_t) nrows * WG), sycl::range<1>(WG)),
[=](sycl::nd_item<1> it) [[sycl::reqd_sub_group_size(WARP_SIZE)]] {
const int row = it.get_group(0);
const int tid = it.get_local_id(0);
const uint16_t * x = (const uint16_t *) vx + (size_t) row * ncols;
float sum = 0.0f;
for (int i = tid * 8; i < ncols; i += WG * 8) {
const sycl::vec<uint16_t, 8> w = *(const sycl::vec<uint16_t, 8> *) (x + i);
#pragma unroll
for (int j = 0; j < 8; ++j) {
sum += sycl::bit_cast<float>((uint32_t) w[j] << 16) * (float) y[i + j];
}
}
sum = sycl::reduce_over_group(it.get_group(), sum, sycl::plus<float>());
if (tid == 0) {
dst[row] = sum;
}
});
}

static void convert_mul_mat_vec_bf16_sycl(const void *vx, const dfloat *y,
float *dst, const int ncols,
const int nrows,
Expand Down Expand Up @@ -2209,9 +2237,15 @@ void ggml_sycl_op_dequantize_mul_mat_vec(
convert_mul_mat_vec_f16_sycl(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream);
break;
#ifdef GGML_SYCL_DMMV_HAS_BF16
case GGML_TYPE_BF16:
convert_mul_mat_vec_bf16_sycl(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream);
case GGML_TYPE_BF16: {
static const bool rowsplit = getenv("GGML_SYCL_BF16_ROWSPLIT_OFF") == nullptr;
if (rowsplit && row_diff <= 512 && ne00 % 8 == 0 && ((uintptr_t) src0_dd_i % 16) == 0) {
bf16_gemv_rowsplit_sycl(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream);
} else {
convert_mul_mat_vec_bf16_sycl(src0_dd_i, src1_dfloat, dst_dd_i, ne00, row_diff, stream);
}
break;
}
#endif
default:
printf("ggml_sycl_op_dequantize_mul_mat_vec unsupported GGML_TYPE %d\n", src0->type);
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