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1. RTL-Design-And-Synthesis-Using-Sky130 RTL-Design-And-Synthesis-Using-Sky130 Public

   RTL Design and ASIC synthesis workshop using Verilog, Yosys, GTKWave, and SKY130 open-source PDK. Includes RTL simulation, synthesis, Gate-Level Simulation (GLS), optimization techniques, waveform …

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2. HDLbits-verilog HDLbits-verilog Public

   Verilog/SystemVerilog practice from HDLBits

   Verilog 1