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two_transistor_interdigitized and common_centroid_ab_ba consume the multiplier's inter-finger top-metal ports (*sd_top_met_*), which no other registered cell touches. Without coverage here a change to inter_finger_topmet breaks them silently. Lands after the two fixes above so the new cells start green. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
…e devices The tapring was placed before the gate/drain routes existed, so evaluate_bbox saw only the transistors. The ring ended up ~1um clear of the devices while the routes reach ~1.84um above them, leaving a met2 route 0.25um from the ring's met2 rail -- gf180 M2.2a requires 0.28um. Moving the ring placement after all routing makes evaluate_bbox see the real extent. No change to the ring's construction, only when it is built. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
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Branch:
placement-helper-ci-coverage→main· 2 commitstwo_transistor_interdigitizedandcommon_centroid_ab_bahad no DRC or LVScoverage. They are also the only consumers of the multiplier's inter-finger
top-metal ports (
*sd_top_met_*), so a change tointer_finger_topmetcouldbreak them silently. This adds them to the CI matrix — and the first run found a
real bug.
The bug the coverage found
common_centroid_ab_bafails gf180 DRC with 4× M2.2a (min metal2 spacing,0.28 µm), symmetric top and bottom:
The guard ring was sized off the bbox before any routing existed:
At that point
comcentroidholds only the four placed FETs. The routing is addedafterwards and reaches ~1.84 µm above them, well past the 1 µm padding:
0.25 µm where 0.28 is required, short by 0.03. The asymmetry is why it fired on
one side only. Note
get_grule("met2")["min_separation"]is 0.3 in glayout'sgf180 rules — stricter than the deck — so nothing was computing too small a
spacing; the routing simply wasn't accounted for.
Fix: place the guard ring after all routing, so
evaluate_bboxsees the realextent. No magic numbers, and it stays correct if the routing changes.
Impact
common_centroid_ab_bagf180 DRC: 4 violations → pass; sky130 still passescommon_centroid_ab_bagrows 1.48 µm in y (15.59 → 17.07, widthunchanged). Its only consumers,
diff_pairanddiff_pair_ibias, areexactly unchanged at 23.56 × 19.32 and 20.00 × 43.08 — their own outer
rings already cleared it, and both still pass DRC and LVS on both PDKs.
Coverage caveats
common_centroid_ab_bagets DRC only. It setsinfo["route_genid"]but neverinfo['netlist'], so LVS skips it (cells without inputs). Worth adding later.two_transistor_interdigitizedgets both, and passes both — but its LVS onlypasses with the
.subcktfix in the LVS-harness PR. Land that one first,or gf180 LVS here reports "inconclusive".
🤖 Generated with Claude Code
https://claude.ai/code/session_01RExJUxLyBEHcQRb6GprVSL