[jeffhsu3]

Branch: met1-defaults → main · 3 commits · changes every cell's geometry

Two default flips in primitives/fet.py, plus the cells that hardcoded the old
value:

• nmos/pmos: tie_layers ("met2","met1") → ("met1","met1")
  (and the same in fvf, current_mirror, transmission_gate,
  two_nfet_interdigitized, two_pfet_interdigitized)
• multiplier: inter_finger_topmet "met2" → "met1"

The second is the larger one. Every source/drain region was being brought all the
way up to met2 whether or not it needed to reach a rail — the rails' own vias
already alternate (source rail lands on even S/D positions, drain rail on odd,
via sdvia_extension = big_extension if finger % 2 else ...). The code already
knew better in one place: dummy devices are built with
inter_finger_topmet="met1" (fet.py:339).

Measured

Identical commits, only the defaults differing:

	metal area	vias
gf180	8708.8 → 7362.8 µm² (−15.5%)	5786 → 2888 (−50%)
sky130	7051.1 → 6421.9 µm² (−8.9%)	8761 → 3335 (−62%)

Per cell on gf180: transmission_gate −30.8% metal and 58 → 6 vias, both current
mirrors −24.0%, flipped_voltage_follower −22.3%, low_voltage_cmirror −21.5%
with 486 → 102 vias, opamp −16.7% and 4076 → 2198 vias.

Verification

Full DRC + LVS, both PDKs, on this branch off main:

• 18 cells pass per PDK; no new failures.
• The only reds are the two opamp LVS failures that main already has:
  gf180's MIM-option bug (fixed by the LVS-harness PR) and sky130's Magic
  PMOS-bulk mis-extraction. Both verified pre-existing by reverting and re-running.

The two placement helpers that consume the inter-finger top-metal ports were
checked explicitly, since they are the only code that touches them:
two_transistor_interdigitized still passes DRC on both PDKs, and
common_centroid_ab_ba's gf180 DRC result is bit-identical before and after
(same 4 M2.2a in the same places — that is the separate bug fixed in the
placement-helper PR, neither caused nor fixed by this change).

Their routing turned out to be layer-agnostic: two_transistor_interdigitized
derives its route layer from the port itself
(pdk.layer_to_glayer(...ports["row0_col0_rightsd_top_met_N"].layer)), and
common_centroid_ab_ba takes glayer1 from the drain rail, not the
inter-finger array.

Reviewer notes

• This changes the GDS of every cell in the library. Worth landing after the
  LVS-harness and placement-helper PRs so the baseline is green first.
• Also included: a code cleanup of macro_two_transistor_interdigitized
  (independent of the defaults; happy to split it out if preferred).
• inter_finger_topmet is still a parameter — pass "met2" for a layout that
  needs the old stack.

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