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1. he-soc he-soc Public

   Forked from Rodolfo-Pellizzoni-Lab/he-soc

   This is the multicore AlSaqr-variant of the PULP he-soc platform. It has a coherent interconnect based on the AXI4 ACE protocol, called Culsans.

   SystemVerilog

2. hades-v-plus hades-v-plus Public

   Extended RISC-V soft core for the Basys3 FPGA — RV32IM + Zba + Zicsr/Zifencei/Zicntr on a 5-stage in-order pipeline with a bimodal branch predictor. Built on the TU Graz HaDes-V open educational re…

   SystemVerilog