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…eeds
asap7/tinyRocket force-converts tag_array through ADDITIONAL_MEMORIES,
because the RTL gives that wrapper no behavioral body: it instantiates
a tag_array_ext the sources never define. Detection finds memories by
their inferred $mem_v2 cells and tag_array has none, so the override is
taken whole (schema.merge: "it must then carry pins and geometry itself
to be emittable"). It carried only name, idiomatic and reason, and
gen_memories stopped in validate_emittable:
schema.SchemaError: memory tag_array: no pins
The override now carries what the module boundary in
freechips.rocketchip.system.TinyConfig.v says: one read-write port,
rows 4 (addr_w 2), bits 25, and the six RW0 pins, no mask.
schema_test.py gains TinyRocketTagArrayTest: the override taken whole
is emittable, and its pins equal the tag_array module's ports read from
the RTL, so the data cannot drift from the design. Both fail before
this change.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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Code Review
This pull request updates the tag_array memory definition in tag_array.memories with detailed properties and pins, and introduces a unit test in schema_test.py to verify that the override is emittable and matches the RTL. The review feedback suggests making the Verilog module header parser in the test helper more robust by stripping leading whitespace before checking for the module declaration and closing parenthesis.
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🔍 QoR checkMetrics reflect the PR merge build — i.e. what will land on the target branch. Commit 62 design(s) checked — 0 with regression(s), 0 without a comparable baseline. |
maliberty
approved these changes
Sep 26, 2026
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Why
This is to stop AI squirrel chasing: a checked-in design file that fails its own format's contract sends an agent (or a human) hunting in the flow for a bug that is in the data.
What
asap7/tinyRocketforce-convertstag_arraythroughADDITIONAL_MEMORIES, because the RTL gives that wrapper no behavioral body: it instantiates atag_array_extthe sources never define. Detection finds memories by their inferred$mem_v2cells andtag_arrayhas none, so the override is taken whole (schema.merge: "it must then carry pins and geometry itself to be emittable"). It carried only name, idiomatic and reason, sogen_memoriesstops invalidate_emittable:Fix
The override carries what the module boundary in
freechips.rocketchip.system.TinyConfig.vsays: one read-write port, rows 4 (addr_w2), bits 25, and the sixRW0pins, no mask.Test
flow/scripts/memories/schema_test.pygainsTinyRocketTagArrayTest:tag_arraymodule's ports read from the RTL, so the data cannot drift from the design.Both fail before this change; the memories tests pass after. Note that CI does not run
flow/scripts/memories/*_test.pytoday.🤖 Generated with Claude Code