syn: reject combinational loops in synthesize

[maliberty]

Summary

The elaborator lowers latches (e.g. a latch-based clock gate) to feedback muxes. syn cuts such a loop with a loop_breaker and then optimizes it as combinational logic, which does not preserve the state the loop holds. On nangate45/ibex the enable of prim_clock_gating dropped out entirely, leaving AND2(clk_i, clk) -> clk. CTS's LatencyBalancer::computeSinkArrivalRecur then recursed around that loop until the stack overflowed (a segfault in 4_1_cts).

synthesize now checks for combinational loops after the full bitblast and fails with SYN-0080, naming nets on each loop (SYN-0079), instead of silently producing a wrong netlist.

• Loops are found as strongly connected components of a per-pin dependency graph, so word-level false loops (e.g. feedback through an adder) are not reported.
• A liberty cell output depends only on the inputs in its function/three_state expression or with a combinational/tristate timing arc to it. An output with neither (such as a fakeram read port) breaks the loop, matching how Yosys treats such cells as opaque.
• New comb_loop regression test covers a word-level false loop, a loop through a RAM macro, a multi-output cell with independent paths (all accepted), and a loop through one pin of a partially opaque cell and a latch clock gate (both rejected).

Running the check across all ORFS designs: every design that uses syn upstream (SYNTH_USE_SYN = 1) still passes. Designs containing real latches now fail at synthesis rather than producing a broken netlist: ibex (all platforms), picorv32 ((* full_case *) is not honored by the elaborator), bp_quad and mempool_group. None of these use syn upstream.

[gemini-code-assist]

Code Review

This pull request introduces a combinational loop detection mechanism (checkCombinationalLoops) to the synthesis flow, which identifies and rejects designs containing combinational loops (such as inferred latches) using Tarjan's strongly connected components algorithm. Feedback on the implementation suggests fixing the net name indexing for vectors declared in descending order to prevent incorrect names in warnings, and falling back to printing net IDs for unnamed nets to improve debuggability.

[maliberty]

@povik FYI