dbSta: keep top ports on local nets through child feedthroughs

[AbhinavChoudhary24167]

When a child module feeds its input through to its output, the reader can attach both top ports to the output's module net. For example, top(ti, to) instantiating a wrapper around assign lo = li leaves both BTerms on modnet to, although the child input remains bound to ti. Preserving input aliases then emits assign to = ti alongside the child's output driver, breaking hierarchy conformance.

Verilog2db::makeModNetsForSubmodule uses the terminals of the exact parent net to find top BTerms. The previous connectedPinIterator traversed child feedthroughs and reconnected ports from other local nets. This correction retains local module connections and flattened physical connectivity. The reader regression covers nested bus feedthroughs and an intentional local top-level alias.

This is the integration companion to OpenSTA #420, whose head is pinned here. Four buffer-insertion goldens include the required input assignments. Repaired flat and hierarchy fixtures use the normal structural and equivalence assertions after their obsolete expected-failure entries are removed.

Validation:

• Head CI build 2 and merge CI build 2 pass on 5386453d3a.
• The complete Bazel test suite passes in both builds, including the reader regression and hierarchy structural/equivalence tests.
• Each suite reports 4,451 tests passing, zero failures, and four unchanged GPU skips; cached results are included. All 22 previously failing hierarchy targets have passing verdicts in both builds, and all 14 flow tests pass.
• All 11 hierarchy fixtures promoted by the final expectation update independently pass native roundtrips, the unchanged assignment checker, and Yosys equivalence with functional Liberty models.
• DCO and documentation checks pass.

Every one of the 436 failing Bazel targets reported by OpenSTA PR-420 build 2 has an explicit passing verdict in both of this PR's corrected CI builds. Those failures comprised 214 hierarchy structural targets, 220 conformance targets, and two buffer-insertion targets. OpenSTA #420's pipeline still selects unmodified OpenROAD master; incorporating this companion is required before that original integration check can validate the repaired combination.

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[gemini-code-assist]

Code Review

This pull request modifies Verilog2db::makeModNetsForSubmodule in dbReadVerilog.cc to use NetTermIterator instead of NetConnectedPinIterator when connecting top-level bterms. This ensures that only terminals on the local net belonging to the top module are traversed, preventing child feedthroughs from reconnecting unrelated ports. Additionally, a new test case is introduced to verify this behavior, several tests are removed from the expected failures list, and the subproject src/sta is updated. As there are no review comments provided, I have no further feedback to offer.