Add gt2n platform: lfsr, sha3, minimax, floonoc, NVDLA

CLAUDE.md

@@ -144,6 +144,7 @@ Designs in this repo carry workarounds for upstream tool bugs. Update this table
 | **GRT-0183 heap underflow in `repair_antennas`** — `updateRouteGridsLayer` in `FastRoute.cpp` modified the routing grids vector in-place; when two jumpers were inserted on the same net at adjacent positions, their promoted endpoints merged into a single same-layer chain. `releaseNetResources` then decremented a `uint16_t` usage counter for an edge that was never incremented, wrapping to 65535. Triggered by sky130hd's high post-DRT antenna violation count (→ many diodes + jumpers, high probability of adjacent jumpers on the same net). | sky130hd NVDLA `partition_c` (baseline floorplan) | Local patch `patches/openroad-grt-0183-fix.patch` (upstream PR #10743, merged 2026-06-24). Remove once OR pin advances past 2026-06-24. | (this PR) | [OpenROAD#10156](https://github.com/The-OpenROAD-Project/OpenROAD/issues/10156), [#10273](https://github.com/The-OpenROAD-Project/OpenROAD/issues/10273) |
 | **OpenSTA `write_sdc` instance-name corruption** (new in OpenROAD 299f3015) — expanding a wildcard `set_false_path -to [get_pin */SETN]` / `*/RESETN` writes corrupted (invalid-UTF-8) instance names into `1_synth.sdc`; Tcl 9's strict UTF-8 then hard-fails floorplan reading it (`error reading "fileN": invalid or incomplete multibyte`) | NVDLA `partition_m` (asap7/sky130hd), `partition_c` (asap7/nangate45) | Remove the two redundant `-to [get_pin */SETN\|/RESETN]` async-reset false-paths from `constraint.sdc` (reset sources are already `-from` false-pathed and the reset nets are `set_ideal_network`, so no real timed path is lost) | (this PR) | None filed yet |
 | **bsg_fakeram `wd_in` LEF direction** — `generate_lef.py` set pin `DIRECTION` by physical die side, not function, so the upper half of every write-data bus was `OUTPUT` in LEF while Liberty said `input`; OpenROAD PnR shorted half of each `wd_in` bus → unroutable GRT-0116 (cnn-sky130hd net: 1964 iterms / 512 bogus drivers) | every fakeram design's pre-`c83ecb4` LEF (Section A + B); all prior `_final` passes invalid | Fork fix `c83ecb4` (submodule bumped `044c02b9`); regenerate all macros via `tools/regenerate_sram.sh` / `tools/reconstruct_cfg_from_lef.py`; vortex's 6 unsizable macros → FF-fallback | `c83ecb4` / `044c02b9` | Pre-existing in fork since `0e1b3c00` (Oct 2025); fixed in VLSIDA/bsg_fakeram |
+| **bsg_fakeram snap-grid key mismatch** — cfg files set `snap_width_nm`/`snap_height_nm` (snake_case), but `class_process.py` only reads `snapWidth_nm`/`snapHeight_nm` (camelCase) and silently falls back to a 1 nm grid on a miss, so the intended platform site-grid snap never applies. Confirmed on committed asap7 LEF (`fakeram_64x256_1r1w`: `SIZE 107.137 BY 66.961` — divides evenly by 0.001 µm, not by the intended 0.190/1.400 µm grid) | **Every asap7 fakeram cfg in the repo** (NVDLA, cnn, coralnpu, NyuziProcessor, vortex, ternip, bp_processor, liteeth, litepci, eyeriss, snitch_cluster) — all use the wrong snake_case keys. nangate45/sky130hd cfgs are unaffected (correctly use camelCase). Suspected contributor to asap7 macro designs with unresolved timing/congestion (not yet confirmed) | Fixed so far only for gt2n `NVDLA` cfgs (this PR) — renamed keys, regenerated via `tools/regenerate_sram.sh`, confirmed macros now land on-grid. **asap7 cfgs across the suite not yet fixed or regenerated** — flagged for follow-up, no designs rebuilt against this yet | (this PR, gt2n only) | None filed yet |
 | **CTS-0105** false skip — yosys hierarchical synthesis output port buffers arrive in ODB with `dbSourceType::TIMING` instead of `NETLIST`; CTS skips them as pre-existing clock buffers and leaves the clock net unbuffered | asap7 NyuziProcessor; asap7/nangate45/sky130hd `bp_quad`, `bp_uno` | `PRE_CTS_TCL` script resets affected buffers' `dbSourceType` from `TIMING` → `NETLIST` before CTS runs | `81b0ed4b` | [OpenROAD#10177](https://github.com/The-OpenROAD-Project/OpenROAD/issues/10177) |
 | **MPL-0040** — `rtl_macro_placer` annealing failure on certain macro clusters | asap7 `bp_quad` (pipe_fma cluster), asap7 `cnn` | Hand-place fakeram macros in left-edge columns at FIRM status via `macros.tcl` so RTLMP only sees pre-placed macros; for cnn also drop `CORE_UTILIZATION` 65→60 | `09542e19` | [OpenROAD#9985](https://github.com/The-OpenROAD-Project/OpenROAD/issues/9985) |
 | **ODB-1200** in `repair_timing` — `InsertBufferBeforeLoads` iterates a stale load list and aborts the flow with `Load pin '...' is not connected to net '...'`. Triggered by the resizer's `SplitLoadMove` step in CTS-time repair_timing | asap7 `liteeth`; sky130hd `NyuziProcessor`; asap7 `NyuziProcessor` (surfaced post-wd_in-fix); asap7 `bp_quad`; asap7 `gemmini` | Most designs: `SKIP_CTS_REPAIR_TIMING = 1` (skips the whole repair pass; route still does its own hold-repair). Gemmini: drop `split_load` from `SETUP_MOVE_SEQUENCE` (`"unbuffer,sizeup,swap,buffer,clone"`) — keeps the rest of repair_timing working (try this first). asap7 `NyuziProcessor`: split_load-drop did **not** clear it (ODB-1200 recurred via another move) → escalated to the full `SKIP_CTS_REPAIR_TIMING = 1` | `87829fdb` | [HighTide#75](https://github.com/VLSIDA/HighTide/issues/75) |

MODULE.bazel

@@ -56,6 +56,8 @@ archive_override(
     patch_strip = 1,
     patches = [
         "//patches:0036-fix-bazel-orfs-bazel_dep-non-dev-for-load-visibility.patch",
+        "//patches:orfs-gt2n-flow-build.patch",
+        "//patches:orfs-no-rcx-spef-stub.patch",
     ],
     strip_prefix = "OpenROAD-flow-scripts-fb65d5b487d2afd443fc1892330f622c776a57ac",
     urls = ["https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/archive/fb65d5b487d2afd443fc1892330f622c776a57ac.tar.gz"],

defs.bzl

@@ -5,6 +5,7 @@ load("@bazel-orfs//:openroad.bzl", "orfs_flow", "orfs_run")
 # PDK label mapping per platform
 PDKS = {
     "asap7": "@orfs//flow:asap7",
+    "gt2n": "@orfs//flow:gt2n",
     "nangate45": "@orfs//flow:nangate45",
     "sky130hd": "@orfs//flow:sky130hd",
 }

designs/gt2n/NVDLA/BUILD.bazel

@@ -0,0 +1,68 @@
+package(default_visibility = ["//designs/gt2n/NVDLA:__subpackages__"])
+
+# partition_p: 16x160, 65x160, 14x80, 66x80 (all stay as macros).
+filegroup(
+    name = "sram_lefs_p",
+    srcs = [
+        "sram/lef/fakeram_16x160_1r1w.lef",
+        "sram/lef/fakeram_65x160_1r1w.lef",
+        "sram/lef/fakeram_14x80_1r1w.lef",
+        "sram/lef/fakeram_66x80_1r1w.lef",
+    ],
+)
+
+filegroup(
+    name = "sram_libs_p",
+    srcs = [
+        "sram/lib/fakeram_16x160_1r1w.lib",
+        "sram/lib/fakeram_65x160_1r1w.lib",
+        "sram/lib/fakeram_14x80_1r1w.lib",
+        "sram/lib/fakeram_66x80_1r1w.lib",
+    ],
+)
+
+# partition_o: 18x128, 8x256, 4x256, 7x256, 66x64, 15x80, 22x60, 32x128 (all stay as macros).
+filegroup(
+    name = "sram_lefs_o",
+    srcs = [
+        "sram/lef/fakeram_18x128_1r1w.lef",
+        "sram/lef/fakeram_8x256_1r1w.lef",
+        "sram/lef/fakeram_4x256_1r1w.lef",
+        "sram/lef/fakeram_7x256_1r1w.lef",
+        "sram/lef/fakeram_66x64_1r1w.lef",
+        "sram/lef/fakeram_15x80_1r1w.lef",
+        "sram/lef/fakeram_22x60_1r1w.lef",
+        "sram/lef/fakeram_32x128_1r1w.lef",
+    ],
+)
+
+filegroup(
+    name = "sram_libs_o",
+    srcs = [
+        "sram/lib/fakeram_18x128_1r1w.lib",
+        "sram/lib/fakeram_8x256_1r1w.lib",
+        "sram/lib/fakeram_4x256_1r1w.lib",
+        "sram/lib/fakeram_7x256_1r1w.lib",
+        "sram/lib/fakeram_66x64_1r1w.lib",
+        "sram/lib/fakeram_15x80_1r1w.lib",
+        "sram/lib/fakeram_22x60_1r1w.lib",
+        "sram/lib/fakeram_32x128_1r1w.lib",
+    ],
+)
+
+# partition_c: 64x256, 11x128 (both stay as macros).
+filegroup(
+    name = "sram_lefs_c",
+    srcs = [
+        "sram/lef/fakeram_64x256_1r1w.lef",
+        "sram/lef/fakeram_11x128_1r1w.lef",
+    ],
+)
+
+filegroup(
+    name = "sram_libs_c",
+    srcs = [
+        "sram/lib/fakeram_64x256_1r1w.lib",
+        "sram/lib/fakeram_11x128_1r1w.lib",
+    ],
+)

designs/gt2n/NVDLA/partition_a/BUILD.bazel

@@ -0,0 +1,28 @@
+load("//:defs.bzl", "hightide_design")
+
+# partition_a has no FakeRAM macros (both SRAMs are FF arrays).
+hightide_design(
+    name = "partition_a",
+    top = "NV_NVDLA_partition_a",
+    platform = "gt2n",
+    verilog_files = ["//designs/src/NVDLA:rtl"],
+    sources = {
+        "SDC_FILE": [":constraint.sdc"],
+        "PRE_CTS_TCL": [":pre_cts.tcl"],
+    },
+    stage_data = {"synth": ["//designs/src/NVDLA:include"]},
+    arguments = {
+        "SYNTH_HIERARCHICAL": "1",
+        "VERILOG_INCLUDE_DIRS": "bazel-out/k8-fastbuild/bin/designs/src/NVDLA/vmod/include bazel-out/k8-fastbuild/bin/designs/src/NVDLA/vmod/vlibs",
+        # 272x16 + 256x16 FF arrays (4352 + 4096 bits) — the 4352-bit
+        # instance trips the ORFS default 4096 cap (same as every
+        # other platform's partition_a).
+        "SYNTH_MEMORY_MAX_BITS": "8192",
+        "CORE_UTILIZATION": "80",
+        "PLACE_DENSITY": "0.88",
+        "MAX_ROUTING_LAYER": "M11",
+        "MIN_CLK_ROUTING_LAYER": "M4",
+        "TNS_END_PERCENT": "100",
+        "HOLD_SLACK_MARGIN": "20",
+    },
+)

designs/gt2n/NVDLA/partition_a/constraint.sdc

@@ -0,0 +1,31 @@
+current_design NV_NVDLA_partition_a
+
+set clk_name nvdla_core_clk
+set clk_period 895
+set clk_io_pct 0.2
+
+set clk_port [get_ports $clk_name]
+
+create_clock -name $clk_name -period $clk_period -waveform [list 0 [expr $clk_period / 2]] $clk_port
+set_clock_transition -rise -min 0.1 [get_clocks $clk_name]
+set_clock_transition -rise -max 0.1 [get_clocks $clk_name]
+set_clock_transition -fall -min 0.1 [get_clocks $clk_name]
+set_clock_transition -fall -max 0.1 [get_clocks $clk_name]
+
+set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+
+set_input_delay  [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
+
+set_ideal_network [get_ports direct_reset_]
+set_ideal_network [get_ports dla_reset_rstn]
+set_ideal_network -no_propagate [get_nets nvdla_core_rstn]
+set_ideal_network [get_ports test_mode]
+
+set_false_path -from [get_ports direct_reset_]
+set_false_path -from [get_ports dla_reset_rstn]
+set_false_path -from [get_ports test_mode]
+set_false_path -from [get_ports pwrbus_ram_pd*]
+set_false_path -from [get_ports tmc2slcg_disable_clock_gating]
+set_false_path -from [get_ports global_clk_ovr_on]
+set_false_path -from [get_ports nvdla_clk_ovr_on]

designs/gt2n/NVDLA/partition_a/pre_cts.tcl

@@ -0,0 +1,2 @@
+# to match MIN_CLK_ROUTING_LAYER=M4.
+set_wire_rc -clock -layer M4

designs/gt2n/NVDLA/partition_c/BUILD.bazel

@@ -0,0 +1,28 @@
+load("//:defs.bzl", "hightide_design")
+
+hightide_design(
+    name = "partition_c",
+    top = "NV_NVDLA_partition_c",
+    platform = "gt2n",
+    verilog_files = ["//designs/src/NVDLA:rtl"],
+    sources = {
+        "SDC_FILE": [":constraint.sdc"],
+        "ADDITIONAL_LEFS": ["//designs/gt2n/NVDLA:sram_lefs_c"],
+        "ADDITIONAL_LIBS": ["//designs/gt2n/NVDLA:sram_libs_c"],
+        "PRE_CTS_TCL": [":pre_cts.tcl"],
+        "PRE_GLOBAL_ROUTE_TCL": [":pre_grt.tcl"],
+        "MACRO_PLACEMENT_TCL": [":macro_placement.tcl"],
+    },
+    stage_data = {"synth": ["//designs/src/NVDLA:include"]},
+    arguments = {
+        "SYNTH_HIERARCHICAL": "1",
+        "VERILOG_INCLUDE_DIRS": "bazel-out/k8-fastbuild/bin/designs/src/NVDLA/vmod/include bazel-out/k8-fastbuild/bin/designs/src/NVDLA/vmod/vlibs",
+        "DIE_AREA": "0 0 855.792 716.928",
+        "CORE_AREA": "1.008 1.008 854.784 715.808",
+        "MAX_ROUTING_LAYER": "M11",
+        # Macro heavy designs appear to benefit from raising the minimum clock routing layer to M6 on gt2n
+        "MIN_CLK_ROUTING_LAYER": "M6",
+        "MACRO_BLOCKAGE_HALO": "0.5",
+        "TNS_END_PERCENT": "100",
+    },
+)

designs/gt2n/NVDLA/partition_c/constraint.sdc

@@ -0,0 +1,63 @@
+current_design NV_NVDLA_partition_c
+
+set clk_name nvdla_core_clk
+set clk_period 1300
+set clk_io_pct 0.2
+
+set clk_port [get_ports $clk_name]
+
+create_clock -name $clk_name -period $clk_period -waveform [list 0 [expr $clk_period / 2]] $clk_port
+
+set_clock_transition -rise -min 0.1 [get_clocks $clk_name]
+set_clock_transition -rise -max 0.1 [get_clocks $clk_name]
+set_clock_transition -fall -min 0.1 [get_clocks $clk_name]
+set_clock_transition -fall -max 0.1 [get_clocks $clk_name]
+
+set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+
+# Blanket delay so synth/floorplan/place/CTS see a real input constraint; pre_grt.tcl
+# overrides this post-CTS with the true (period-exceeding) cross-partition delay.
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+
+# Delay credit more realistically models the capture-side clock insertion latency of whatever
+# receives this partition's boundary outputs, since all partitions are intended as a single die.
+# Fixed at -1950 ps -- approximately half of the worst clock network latency observed in this
+# partition.
+set_output_delay -1950 -clock $clk_name [all_outputs]
+
+set_ideal_network [get_ports global_clk_ovr_on]
+set_ideal_network [get_ports test_mode]
+set_ideal_network [get_ports direct_reset_]
+set_ideal_network [get_ports dla_reset_rstn]
+set_ideal_network [get_ports nvdla_core_clk]
+set_ideal_network [get_ports nvdla_clk_ovr_on]
+set_ideal_network [get_ports tmc2slcg_disable_clock_gating]
+set_ideal_network [get_ports pwrbus_ram_pd*]
+set_ideal_network [get_nets nvdla_core_rstn]
+
+set_false_path -from [get_ports direct_reset_]
+set_false_path -from [get_ports dla_reset_rstn]
+set_false_path -from [get_ports test_mode]
+set_false_path -from [get_ports pwrbus_ram_pd*]
+set_false_path -from [get_ports tmc2slcg_disable_clock_gating]
+set_false_path -from [get_ports global_clk_ovr_on]
+set_false_path -from [get_ports nvdla_clk_ovr_on]
+
+# -through [get_nets ...] on q/d0 -- regs declared directly in NVDLA's p_SSYNC2DO_C_PP.v
+# primitive, not synthesis-tool-internal names, so this stays valid across yosys versions.
+# Errors loudly if a toolchain change ever makes either net disappear, instead of silently
+# dropping the false-path and reintroducing recovery/removal violations on this reset's fanout.
+foreach reset_sync_net {
+    u_partition_c_reset.sync_reset_synced_rstn.NV_GENERIC_CELL.q
+    u_partition_c_reset.sync_reset_synced_rstn.NV_GENERIC_CELL.d0
+} {
+  set net [get_nets $reset_sync_net]
+  if {[llength $net] == 0} {
+    error "constraint.sdc: reset synchronizer net $reset_sync_net not found -- update this false-path"
+  }
+  set_false_path -through $net
+}
+
+set_max_fanout 128 [current_design]
+
+set_wire_load_mode enclosed