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1. 32-bit-Signed-Vedic-Multiplier 32-bit-Signed-Vedic-Multiplier Public

   A 32-bit Signed Vedic Multiplier created using Verilog HDL utilising Vedic Mathematic Sutras formed using Carry Lookahead Adders as the basic building blocks.

   Verilog 5 2

2. Chess-Clock Chess-Clock Public

   A two player digital chess clock controller used to keep track of time in hrs:mins:sec taken by each player while making their respective move during the passage of the game.

   2

3. Oven-FSM-RTL-to-GDS-II-design-using-Qflow Oven-FSM-RTL-to-GDS-II-design-using-Qflow Public

   RTL to GDS II flow for a custom "Oven FSM" ASIC design utilising Qflow, an Open Source Physical Design toolchain.

   Verilog 2

4. 4bit-RCA-180nm-Layout 4bit-RCA-180nm-Layout Public

   Layout of 4bit Ripple Carry Adder formed using CMOS logic in gpdk180nm technology node done in Cadence Virtuoso with no DRC and LVS errors.

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5. 4bitRCA180nm 4bitRCA180nm Public

   Performance Analysis of a 4-bit Ripple Carry Adder (RCA) formed using Static CMOS, Transmission Gate, NMOS Pass Transistor Logic at gpdk 180nm Technology node.

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6. Digitalclock12Hr Digitalclock12Hr Public

   A 12 Hour Digital Clock Implemented on Nexys4 DDR FPGA board using Verilog HDL.

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