Solutions Architect at FuriosaAI, with a background in Electrical Engineering and Physics from Sogang University.

I am interested in understanding how AI systems behave beyond theoretical compute performance - particularly how many hierarchy, data movement, interconnects, and system architecture determine real-world performance.

My background spans FPGA-based AI accelerator design, embedded systems, and system-level performance analysis. I enjoy identifying bottlenecks across hardware and software boundaries and understanding how individual components interact as a compute system.

Designed and analyzed an INT8 systolic-array accelerator on a Xilinx Zynq SoC targeting MobileNetV2 workloads.

• Implemented a Verilog-based systolic array architecture and AXI DMA-based HW-SW interface
• Achieved high compute efficiency (~38× theoretical speedup), but observed limited end-to-end performance (~2.4×)
• Developed a runtime analysis framework with cycle-level instrumentation and Roofline modeling
• Identified that system performance was fundamentally limited by memory bandwidth and host-side overhead (memory/host-bound)
• Quantified the relationship between arithmetic intensity and performance scaling
• Explored INT8 quantization (PTQ and selective QAT), analyzing trade-offs between model accuracy and hardware efficiency

This project emphasized that system performance is not determined by compute throughput alone, but by the interaction between computation, memory, and data movement.

Developed an interrupt-driven embedded system on STM32F103RB.

• Designed a modular firmware architecture integrating GPIO, ADC (DMA), USART, and timers
• Implemented a state-machine-based control system for real-time interaction
• Used DMA-based ADC sampling for non-blocking data acquisition
• Built a dual-board communication system using USART

This project strengthened my understanding of how software interacts with hardware in real-time systems.

• AI systems & Inference Infrastructure
• System-Level Performance Analysis
• Hardware-Software Co-Design
• Memory Hierarchy & Data Movement
• PCIe, NUMA & System Interconnects
• AI Accelerators & Heterogeneous Computing