Computer Engineer out of UIUC (BS '25, hardware systems). I build systems like processors, FPGAs, embedded and the tooling/testbenches that proves they work.
Currently: finishing an open-source RV32I core in Verilator, and looking for RTL design, DV, embedded: hardware roles.
📫 basmalik1@gmail.com · LinkedIn
Microarchitecture. A Tomasulo-style out-of-order RISC-V core (RV32I + RV32M) — multi-stage front end with instruction caching, fetch, decode/rename, and dispatch; reservation-station scheduling across ALU/MUL/DIV/branch/memory units; a reorder buffer enforcing in-order retirement over out-of-order execution.
Verification. Constrained-random SystemVerilog testbenches, waveform-driven debug in Synopsys
VCS and Verdi, timing-closure validation. Open-source flow too: Yosys + Verilator + GTKWave + a Make/Python
harness in riscv-cpu.
Bare metal. monolithic-x86-kernel — a monolithic x86 kernel in C.
Paging-based virtual memory, interrupt-driven I/O through the Intel 8259 PIC, syscall-mediated
user/kernel transitions, a simple filesystem. Boots under QEMU via GRUB, debugged with GDB.
FPGA. duck-hunt-fpga — the 1984 game rebuilt in
SystemVerilog on an Intel DE10-Lite. FSM-driven game state, hand-written PS/2 mouse and keyboard
drivers, VGA output with validated timing constraints.
Embedded. esp32-iot-telemetry — an ESP32-S3
that measures its own die temperature, WiFi RSSI, and heap, and serves a React dashboard straight
out of flash.
SystemVerilog RISC-V x86 C C++ Python
Synopsys VCS Verdi Verilator GTKWave Intel Quartus Prime GDB QEMU Git Linux