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feat(sv)!: support packed unions, scoped locals and named calls - #1211
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Also preserve X/Z constant casts and bind unpacked-array parameter patterns in the caller scope. Re-enable the matching Veryl-to-SV regressions and add shared lexical-scope coverage.
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Keep fill literals and arithmetic in their assignment context, and include DPI prototypes in named-call signatures. Add shared regressions and retain the observed Icarus array-parameter limitation. Update only the newly passing packed-union conformance expectation.
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The only conflict is the retained Icarus evidence report, where both sides appended reviewed failures to the same list. - Keep both appends: master's `$printtimescale` exclusions and this branch's `hierarchy::parameter_patterns_*` exclusions, raising `compile_error` from 81 to 87 and the case count from 97 to 103. - Give the four pattern rows the schema-3 metadata (`stronger_than_sv`, `tags`, `tag_reasons`) that the report writer always emits, so they match the neighbouring retained rows and a fresh run instead of only the older schema-2 leftovers. - The exclusion table, the aggregate limitations evidence and the case catalogue merged without conflict; no reviewed failure or coverage contract changed beyond that union. The merged row set is exactly the union of both parents' rows.
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Summary
Veryl-emitted RTL containing packed unions, shadowed procedural locals, named calls, X/Z constant casts or array-parameter patterns now compiles and simulates through the SystemVerilog frontend.
unsigned'(byte'(X))in constant initializers with four-state parameter values, including conversion of X/Z to zero.Re-enable the corresponding Veryl-to-SV regressions, add portable lexical-scope cases, and update the English/Japanese support guides.
Compatibility: public
ast::Expr::Call,ir::Expr::CallandStmtBase::Callgainarg_order; expression-callargschange fromVec<Expr>toVec<Option<Expr>>to represent omitted actuals. Downstream constructors and exhaustive field patterns must account for these changes.Expression and statement calls support ANSI argument defaults under IEEE 1800-2023 13.5.3. Named calls with procedural effects in selection indices and packed union assignment patterns remain unsupported.
Closes #440.
Closes #445.
Closes #1187.
Closes #1188.
Closes #1189.
Scope relative to other PRs
Includes master
0c62248fe. Mixed-interface behavior (#1204), unpacked-dimension queries (#1171), and the clock/DSE changes are inherited from that merged base and covered by the integration checks. Timed testbench execution and removing thesystemverilogfeature gate remain separate work; #1191 and #1192 remain open.Validation
celox/sv-dpiand both external-adapter features.$printtimescalesupport adds a pass without relaxing the baseline.intpattern sign extension disagrees with IEEE 1800-2023 10.9/6.11.3/6.20.2. A standalone probe confirms it zero-extends the pattern directly but sign-extends through anintvariable/cast. Named constant/query and generate-signature cases pass; dynamic-default scope remains its separately reviewed disagreement under 13.5.3.All local builds use the locked Nix environment and managed default
target/. Routine successful simulator results and proof manifests were not regenerated.Latest head
8c82448ac: CI and lydite both succeeded. Every selected check passes; platform skips follow the existing PR job-selection policy. All seven review threads are resolved, and GitHub reports the PR mergeable with a clean merge state.