Pinned Loading

1. RISCV-RV32IM-Processor RISCV-RV32IM-Processor Public

   6-stage pipelined RV32IM processor in SystemVerilog, closing timing at 100 MHz on Artix-7 after evolving from a 5-stage design capped at 64 MHz. Pipelined hardware multiplier, iterative divider, M-…

   SystemVerilog 1

2. CrickHit CrickHit Public

   Real-time cricket batting game on the TI MSPM0G3507 (ARM Cortex-M0+) with triple-ISR architecture, custom KiCad PCB, 5-bit DAC audio, and 3D-printed enclosure. Built for ECE 319H at UT Austin.

   C 1

3. RISCV-Pipeline-Research RISCV-Pipeline-Research Public

   RISC-V pipeline research: RV32IM soft core, branch prediction (SGF), FPGA experiments + paper

   SystemVerilog 3

4. ssWaterFlowing/Analog-PID-Controller ssWaterFlowing/Analog-PID-Controller Public

   HTML

5. BuckConverter BuckConverter Public

   High-efficiency power conversion circuit that steps down a higher input voltage to a lower output voltage for a load. Unlike simple methods such as resistor dividers, which dissipate energy as heat…

6. Advanced_TrafficLightControl_System Advanced_TrafficLightControl_System Public

   12-state Moore FSM four-way traffic light controller in Verilog HDL with protected left turns, all-red safety interlocks, and 100MHz-to-1Hz clock divider. Deployed on Basys 3 (Artix-7).

   Verilog 1