All pull requests

Pull requests

• Verilog preprocessor: `include via macro expansion

  Verilog
  #2330·kroening opened Nov 5, 2026Collaborator·

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• Netlist: avoid stack overflow on long chains of definitions

  engines
  #2322·kroening opened Oct 31, 2026Collaborator·

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  1

• Verilog: linear growth for loops over arrays of structs

  Verilog
  #2319·yvizel opened Oct 29, 2026Collaborator·

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  14

• Verilog: type of dynamic arrays

  Verilog
  #2301·tautschnig opened Oct 27, 2026Collaborator·3/3·

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  5

• Verilog: RTL construction with system functions of type integer

  #2300·tautschnig opened Oct 27, 2026Collaborator·2/3·

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  3

• Verilog: liveness-based driver check, dual write ports, free undriven net bits

  Verilog
  #2266·kroening opened Oct 13, 2026Collaborator·

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  1

• Verilog: reject continuous assignment to variables in Verilog and variables on inout ports

  Verilog
  #2265·kroening opened Oct 13, 2026Collaborator·

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  3

• Verilog: local declarations vs. wildcard imports, package variable initializers

  Verilog
  #2262·kroening opened Oct 13, 2026Collaborator·

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  1

• Verilog: while/repeat, always_latch, latch inference in RTL construction

  Verilog
  #2254·kroening opened Oct 13, 2026Collaborator·

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  1

• Verilog: name complex expressions that are read back in RTL construction

  Verilog
  #2216·kroening opened Oct 5, 2026Collaborator·

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  1

  2

• Verilog: interface port members are aliases of the bound instance's members

  Verilog
  #2190·tautschnig opened Sep 28, 2026Collaborator·4/4·

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  1

• Verilog: interface ports take the parameters of the bound instance

  Verilog
  #2186·tautschnig opened Sep 28, 2026Collaborator·3/4·

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  7

• Verilog: regression test for genvar-indexed instance port connections

  Verilog
  #2163·kroening opened Sep 25, 2026Collaborator·

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• Verilog: upward name referencing

  Verilog
  #2129·kroening opened Sep 14, 2026Collaborator·5 tasks done·

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  1

  2

• Verilog: import of tasks/functions in interfaces and modports

  Verilog
  #2115·kroening opened Aug 21, 2026Collaborator·

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• Verilog: hierarchical references into named generate blocks

  Verilog
  #2101·kroening opened Aug 12, 2026Collaborator·

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• Verilog: assignments between unpacked arrays of equivalent types

  Verilog
  #2100·kroening opened Aug 12, 2026Collaborator·

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• Verilog: loop-local genvar scoping

  Verilog
  #2091·kroening opened Aug 12, 2026Collaborator·

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  2

• Verilog: parse packages before the files that import them

  Verilog
  #2082·kroening opened Aug 11, 2026Collaborator·

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• New IC3: compare SAT backends on HWMCC17

  engines
  #2066·kroening opened Aug 9, 2026Collaborator·

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• Do not review

  #2064·kroening opened Aug 9, 2026Collaborator·

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• Verilog: accept struct/array/union as constant expressions

  Verilog
  #2059·kroening opened Aug 1, 2026Collaborator·

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  1

• Verilog: fold Verilog-specific constructs when propagating constants in synthesis

  Verilog
  #2053·kroening opened Jul 23, 2026Collaborator·

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• Verilog: synthesize the module instance hierarchy monolithically

  Verilog
  #2040·kroening opened Jul 21, 2026Collaborator·5 tasks done·

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  5

• new IC3: recycle frame solvers after 2000 queries

  engines
  #2020·kroening opened Jul 16, 2026Collaborator·2 tasks done·

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  1