[tboinovski1]

Overview

Add support for f16/f32 CONV2D to Hexagon backend.

Additional information

Tested on v73, v75 and v81 Android and v81 WoS devices.

test-backend-ops: 1021/1021 tests passed

Requirements

• I have read and agree with the contributing guidelines
• AI usage disclosure: Yes, to brainstorm and test the implementation.

@max-krasnyansky

[max-krasnyansky]

@tboinovski1 let's rebase with the latest master (opfusion rework).

Most of the dma usage look synchronous (push a bunch -> flush queue, then compute).
The trace events that are supposed to track HVX/HMX work overlap with the dmas (ie there are dma push/pop between trace start/stop) that will confuse the stats and makes the tracing confusing.
Also I see a lot flush queue calls. That generally tells me that the pipeline is not quite right.
We typically want a clean push(N), push(N+1), pop(N), compute(N), push(N+2), pop(N+1), compute(N+1),... kind of pipeline if the output is using dma as well then we use dummy (nrows=0) transactions to start the pipeline and then again just use clean push/pop/.. sequence.

[tboinovski1]

@max-krasnyansky as requested rebased to latest master.

Regarding:

• Flushes: the mid-loop flushes are gone. Only one flush per thread at the end of each phase is left.
• Pipeline:
  • Activation staging now runs push(N), push(N+1), pop(N), compute(N), push(N+2).
  • Weight packing now waits with an exact pop rather than a flush. It isn't double-buffered because it runs once per block of row tiles; I tried double-buffering and measured no gain on the HMX paths.
• Traces: HMX events now cover only the compute. The duplicate manual DMA events are gone.
• Removed the HVX paths which were used originally as scaffolding during bringup.