Issues

• Evaluate dart:developer.CreationLocation for optional source-provenance capture

  intel/rohd#737 · Filter by author desmonddak opened on Oct 13, 2026

• Design shared synthesis extensibility for backend-specific leaf implementations

  intel/rohd#735 · Filter by author desmonddak opened on Oct 12, 2026

• Inline fully packed child array outputs into split destinations

  enhancement
  intel/rohd#734 · Filter by author mkorbel1 opened on Oct 5, 2026

• Suggestion: warn/document Sequential's resetValues with a non-constant value + asyncReset (CD/SDN timing hazard pattern)

  intel/rohd#728 · Filter by author caflore1 opened on Sep 30, 2026
  1

• ROHD linter

  enhancement
  intel/rohd#713 · Filter by author desmonddak opened on Sep 9, 2026

• Recursion bug due to module.build() connection tracing

  bug
  intel/rohd#709 · Filter by author desmonddak opened on Sep 6, 2026

• Discarded wires remain subscribed to simulator lifecycle events and progressively degrade tick performance

  bug
  intel/rohd#708 · Filter by author pmjobin opened on Sep 6, 2026
  1

• Using Dart/Flutter URIs for resources

  enhancement
  intel/rohd#684 · Filter by author desmonddak opened on Jul 16, 2026

• filelist generation for SystemVerilog

  enhancement
  intel/rohd#683 · Filter by author desmonddak opened on Jul 16, 2026

• Generate code coverage preview as part of GitHub pages

  enhancement
  intel/rohd#647 · Filter by author maifeeulasad opened on Jan 20, 2026

• Better handling for LogicStructures in Pipelines

  enhancement
  intel/rohd#632 · Filter by author mkorbel1 opened on Oct 31, 2025
  1

• Allow assignment merging in SystemVerilog between packed arrays and non-arrays when legal

  enhancement
  intel/rohd#619 · Filter by author mkorbel1 opened on Aug 25, 2025

• A type-safe mechanism to connect PairInterfaces

  enhancement
  intel/rohd#613 · Filter by author mkorbel1 opened on Jul 21, 2025

• SystemVerilog.definitionParameters does not enforce uniqueness with other names

  bug
  intel/rohd#611 · Filter by author mkorbel1 opened on Jul 17, 2025

• Module.uniqueInstanceName not enforced as reserved name in Synth stack

  bug
  intel/rohd#610 · Filter by author mkorbel1 opened on Jul 17, 2025

• Expose references to primitive inputs

  enhancement
  intel/rohd#609 · Filter by author mkorbel1 opened on Jul 15, 2025
  1

• abs() produces a complex name

  enhancement
  intel/rohd#608 · Filter by author desmonddak opened on Jul 12, 2025
  1

• Dynamically renameable ports during code generation

  enhancement
  intel/rohd#600 · Filter by author mkorbel1 opened on Jun 26, 2025

• Rename "swizzle" to "concat"

  enhancement
  intel/rohd#597 · Filter by author mkorbel1 opened on Jun 24, 2025
  1

• Add @protected onto execute on Conditionals

  bug
  intel/rohd#596 · Filter by author mkorbel1 opened on Jun 10, 2025

• Warn when Simulator runs but no events have been registered

  enhancement
  intel/rohd#595 · Filter by author mkorbel1 opened on Jun 10, 2025

• Generation of structs and enums in output SystemVerilog

  enhancement
  intel/rohd#594 · Filter by author mkorbel1 opened on May 22, 2025
  3

• LogicValue radixString code should allow for prefix-free strings

  enhancement
  intel/rohd#591 · Filter by author desmonddak opened on Mar 26, 2025

• Add documentation to User Guide for automations like flop, cases, mux, etc.

  documentationenhancementhelp wanted
  intel/rohd#577 · Filter by author awmoore-intel opened on Mar 5, 2025

• WaveDumper outputs empty file when test() {expect()} fails

  bug
  intel/rohd#574 · Filter by author awmoore-intel opened on Feb 26, 2025
  1