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The arm32 header put the testcase buffer in r10, which TSFFS reads as the index selector, so HARNESS_START was ignored with 'index is not configured'. HARNESS_STOP left r10 untouched. Align arm32 with aarch64: index in r10, args in r9/r8/r7, add *_INDEX macros, and add missing aarch64 clobbers.
Wenzel
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6 open issues
Usingpush/popinside inline asm is unsafe here because it temporarily movesspand writes… · Newenv!(\"CARGO_TARGET_TMPDIR\")is evaluated at compile time and will fail compilation if that env… · Newenv!(\"CARGO_TARGET_TMPDIR\")is evaluated at compile time and will fail compilation if that env… · New This can panic or slice out-of-bounds if aSTT_FUNCsymbol is undefined/special (st_shndxlike… · New This can panic or slice out-of-bounds if aSTT_FUNCsymbol is undefined/special (st_shndxlike… · New Dropping the unsigned suffix changes the constant’s type to (signed)int, which can trigger… · New
What changed in this PR
Fixes the ARM32 harness ABI by ensuring the magic index is passed in r10 (and arguments in r9/r8/r7) to match what src/arch/arm.rs expects, and adds an integration test that verifies the generated ARM32 harness code without requiring an ARM Simics model.
Changes:
- Update ARM32 harness macros to pass
DEFAULT_INDEXinr10and add*_INDEXmacro variants. - Fix AArch64 harness inline-asm clobbers for
__orr_extended3/__orr_extended4. - Add a new Rust test that cross-compiles harness macros for ARM32 and validates register values via disassembly and constant propagation.
| File | Description |
|---|---|
| tests/arm32_harness_abi_latest.rs | Adds a cross-compile + disassembly-based ABI test for ARM32 harness macros/register placement. |
| harness/tsffs.h | Regenerates umbrella header to reflect ARM32 macro ABI fixes and AArch64 clobber updates. |
| harness/tsffs-gcc-arm32.h | Fixes ARM32 register assignment (index in r10) and introduces *_INDEX harness macros. |
| harness/tsffs-gcc-aarch64.h | Adds missing x8/x7 clobbers for correctness under optimization. |
| harness/test.c | Stops skipping _INDEX harness tests on ARM now that ARM32 supports them. |
Review effort: Lite
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| #define __orr_extended4(value, arg0, arg1, arg2, arg3) \ | ||
| __asm__ __volatile__( \ | ||
| "mov r10, %0; mov r9, %1; mov r8, %2; mov r7, %3; " \ | ||
| "push {r7}; mov r10, %0; mov r9, %1; mov r8, %2; mov r7, %3; " \ | ||
| "orr r" __tostring(value) ", r" __tostring(value) ", r" __tostring( \ | ||
| value) \ | ||
| value) "; pop {r7}" \ | ||
| : \ | ||
| : "r"(arg0), "r"(arg1), "r"(arg2), "r"(arg3) \ | ||
| : "r10", "r9", "r8", "r7"); | ||
|
|
||
| /// Magic value defined by SIMICS as the "leaf" value of a CPUID instruction | ||
| /// that is treated as a magic instruction. | ||
| #define MAGIC (0x4711U) | ||
| : "r"((unsigned int)arg0), "r"((unsigned int)arg1), \ | ||
| "r"((unsigned int)arg2), "r"((unsigned int)arg3) \ | ||
| : "r10", "r9", "r8"); |
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| let manifest_dir = PathBuf::from(env!("CARGO_MANIFEST_DIR")); | ||
| let out_dir = PathBuf::from(env!("CARGO_TARGET_TMPDIR")).join("arm32_harness_abi"); |
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| let status = Command::new("clang") | ||
| .args([ | ||
| "-target", | ||
| "arm-unknown-linux-gnueabi", | ||
| "-marm", | ||
| "-mfloat-abi=soft", | ||
| "-O2", | ||
| ]) |
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| let name = elf | ||
| .strtab | ||
| .get_at(sym.st_name) | ||
| .ok_or_else(|| anyhow!("bad symbol name"))?; | ||
| let section = &elf.section_headers[sym.st_shndx]; | ||
| let start = (section.sh_offset + sym.st_value) as usize; | ||
| functions.insert(name, &bytes[start..start + sym.st_size as usize]); |
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| let section = &elf.section_headers[sym.st_shndx]; | ||
| let start = (section.sh_offset + sym.st_value) as usize; | ||
| functions.insert(name, &bytes[start..start + sym.st_size as usize]); |
| /// support multiple start and stop indices, which defaults to 0 if not | ||
| /// specified. | ||
| #define DEFAULT_INDEX (0x0000U) | ||
| #define DEFAULT_INDEX (0x0000) |
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Wenzel due to an error
October 28, 2026 11:25
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Fixes #245.
Summary
src/arch/arm.rsreads the magic index fromr10and arguments fromr9/r8/r7. The arm32 harness put the testcase buffer inr10and never set an index, so every start/stop was rejected withindex is not configured(index2129111884=0x7ee7ab4c, the reporter's stack buffer; seemov sl, r7beforeorr r1,r1,r1in their disassembly). #217 fixed the aarch64 registers but not arm32.harness/tsffs-gcc-arm32.h: ported from the aarch64 header (same macro set and register order).__orr_extended4saves/restoresr7instead of clobbering it (Thumb frame pointer).harness/tsffs-gcc-aarch64.h: add missingx8/x7clobbers to__orr_extended3/__orr_extended4.harness/tsffs.h: regenerated withbuild.sh;harness/test.cno longer skips the*_INDEXtests on arm.tests/arm32_harness_abi_latest.rs: new test. Public Simics has no ARM CPU model, so it compiles everyHARNESS_*macro withclang -target arm-unknown-linux-gnueabi -O2, decodes each function withgoblin+yaxpeax-arm(existing deps), constant-propagates up to the magicorr rN,rN,rN, and asserts the magic number,r10index, andr9/r8/r7arguments.Evidence
_INDEXmacros only):HARNESS_START_INDEXetc. undeclared.test test_arm32_harness_abi_latest ... okAlso:
cargo build -r,cargo clippy --test arm32_harness_abi_latest -- -D warnings, andharness/build.shpass (Simics 7.70.0). Thumb-O0build ofharness/test.cemits no warnings.Merge Danger
Door: two-way
Blast Radius: arm32 harness users
Targets must be rebuilt with the new header; the TSFFS module is unchanged. Not run end to end in Simics on an ARM target (no public ARM package). Thumb-mode encoding of the
orrmagic instruction was not verified against Simics.