Skip to content
View intisar-int's full-sized avatar
🙂
innalillah!
🙂
innalillah!
2 followers · 0 following

Block or report intisar-int

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Content in all repositories owned by your account will be closed.
Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
intisar-int/README.md

Hi, I'm Ahmad 👋

EEE Student · Electronics · Teacher · Founder

Profile views

🧑‍💻 About me

  • 🎓 EEE (Electronics major) at BRAC University, Bangladesh. Graduating around Feb 2027
  • 🏫 Teaching Math & Science at Iqra Model School and College since 2019
  • 🚀 Founder of Wallchemy, an LED wall panel decor brand in Dhaka
  • 🤝 Senior Executive at BUEEC and Secretary of Operations at BURT
  • 🔬 Currently exploring: ALU design, RISC-V, FPGA/VHDL, and swarm robotics

🛠️ Tech & Tools

VHDL MATLAB Simulink Arduino Python Git Proteus FPGA

📌 Featured Projects

Project What it is
alu-16bit-vhdl 16-bit ALU in VHDL
riscv-rv32i-5stage RISC-V RV32I 5-stage pipeline
EEE383 Seismic Alert System Dual-sensor earthquake alert system
quake-in-a-circuit Earthquake detection circuit
evm-atmega32-voting-machine Electronic voting machine on ATmega32
bitconveyor-siso16 16-bit serial-in serial-out register
lab-electrical-layout-bnbc Lab electrical layout (BNBC)
portfolio My personal portfolio website

📊 GitHub Stats

Stats Top Langs

Streak

🤝 Let's connect

Facebook

Building circuits, teaching minds, starting things. ⚡

Popular repositories Loading

  1. bitconveyor-siso16 bitconveyor-siso16 Public

    16-bit bidirectional shift register with parallel load in Verilog. Verified with a self-checking testbench, fitted in Quartus and synthesized in Cadence Genus at slow and fast PVT corners to compar…

    Python 1

  2. portfolio portfolio Public

    Portfolio website of Intisar Ahmad

    HTML 1

  3. alu-16bit-vhdl alu-16bit-vhdl Public

    16-bit ALU in VHDL with FSM Booth multiplier, restoring divider, flag unit and built-in self-test. Simulated with GHDL, synthesized for Artix-7.

    VHDL

  4. EEE383-Dual-Sensor-Seismic-Alert-System EEE383-Dual-Sensor-Seismic-Alert-System Public

    Dual-sensor hybrid seismic alert system: piezo and MPU-6050 sensing on ESP32 with RMS and FFT detection and ESP-NOW alerts. Two custom PCBs, firmware, MATLAB and Proteus validation.

    C++

  5. evm-atmega32-voting-machine evm-atmega32-voting-machine Public

    Secure electronic voting machine on the ATmega32 with keypad, buttons and LCD. CodeVisionAVR C firmware, Proteus 8 simulation.

    C

  6. lab-electrical-layout-bnbc lab-electrical-layout-bnbc Public

    Electrical service design of the LASSET laboratory (Room 12B-16L): three layouts, BNBC 2020 load calculations and an independent protection audit. AutoCAD drawings with Python calculation checks.

    Python