Address some Verilog lints and weaknesses

Changelog.md

@@ -17,7 +17,6 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ### Added
 - Enabled many compiler warnings under Clang and GCC
 - Introduced a stream-based abstraction layer for filesystem operations
-- Enabled CI jobs for additional architectures (arm64, ppc64le, s390x)
 - Defined the overshifting behavior for the `@` operator
 - Defined the tenyr assembly grammar in ABNF (#60)
 - Set up continuous integration using GitHub Actions (#66, #67, #68, #69, #70, #71)

hw/verilog/tenyr.v

@@ -56,10 +56,6 @@ module Exec(input clk, en, output reg done, output reg[31:0] valZ,
     reg[3:0] rop;
     reg add, act, staged;
 
-    function Bit(input[31:0] rA, rB);
-        Bit = rA >> rB;
-    endfunction
-
     always @(posedge clk) begin
         { rop , valZ , rA   , rB   , rC   , done , add , act    , staged } <=
         { op  , rZ   , valA , valB , valC , add  , act , staged , en     } ;
@@ -70,7 +66,7 @@ module Exec(input clk, en, output reg done, output reg[31:0] valZ,
             4'h3: rY <=    (rA >>> rB) ; 4'hb: rY <=    (rA  >> rB  );
             4'h4: rY <=    (rA  +  rB) ; 4'hc: rY <=    (rA  -  rB  );
             4'h5: rY <=    (rA  *  rB) ; 4'hd: rY <=    (rA  << rB  );
-            4'h6: rY <= {32{rA ==  rB}}; 4'he: rY <= {32{Bit(rA, rB)}};
+            4'h6: rY <= {32{rA ==  rB}}; 4'he: rY <= {32{rA    [rB] }};
             4'h7: rY <= {32{rA  <  rB}}; 4'hf: rY <= {32{rA  >= rB  }};
         endcase
         if (act) rZ <= rY + rC;

hw/verilog/top.v

@@ -22,7 +22,8 @@ module Tenyr(
 
     tenyr_mainclock clocks(
         .clk_in ( clk   ), .clk_core ( clk_core ),
-        .reset  ( reset ), .clk_vga  ( clk_vga  )
+        .reset  ( reset ), .clk_vga  ( clk_vga  ),
+        .locked (       )
     );
 
     Core core(
@@ -51,13 +52,13 @@ module Tenyr(
     TwoPortRAM #(.LOADH(1), .LOADFILE(LOADFILE), .INIT(0),
         .PBITS(32), .ABITS(RAMABITS), .OFFSET(`RESETVECTOR)
     ) ram(
-        .clka  ( clk_core ), .clkb ( 1'b0 ),
-        .ena   ( r_stb    ), .enb  ( 1'b0 ),
-        .acka  ( r_ack    ),
-        .wea   ( r_wen    ),
-        .addra ( r_adr    ),
-        .dina  ( r_ddn    ),
-        .douta ( r_dup    )
+        .clka  ( clk_core ), .clkb  ( '0 ),
+        .ena   ( r_stb    ), .enb   ( '0 ),
+        .acka  ( r_ack    ), .ackb  (    ),
+        .wea   ( r_wen    ), .web   ( '0 ),
+        .addra ( r_adr    ), .addrb ( '0 ),
+        .dina  ( r_ddn    ), .dinb  ( '0 ),
+        .douta ( r_dup    ), .doutb (    )
     );
 
 // -----------------------------------------------------------------------------
@@ -70,7 +71,7 @@ module Tenyr(
 
 `ifdef SERIAL
     // TODO write a hardware-compatible serial device ; rename to eliminate `Sim`
-    SimWrap_simserial #(.BASE(12'h20), .SIZE(2)) serial(
+    SimWrap_simserial #(.BASE(32'h20), .SIZE(2)) serial(
         .clk ( clk_core ), .reset ( reset ), .enable ( s_stbcyc ),
         .rw  ( s_wen    ), .addr  ( s_adr ), .data   ( s_ddn    )
     );
@@ -153,8 +154,10 @@ module Tenyr(
         .wbs_cyc_o ({ o_cyc, g_cyc, v_cyc, s_cyc, r_cyc, x_cyc }),
 
         // unused ports
-        .wbm_cti_i ( 3'bz ),
-        .wbm_bte_i ( 2'bz )
+        .wbm_cti_i ( '0 ),
+        .wbm_bte_i ( '0 ),
+        .wbs_cti_o (    ),
+        .wbs_bte_o (    )
     );
 
 endmodule

test/op/at.tas

@@ -1,6 +1,12 @@
 C <- [(@args + (0 + 0x1000))]
 D <- [(@args + (1 + 0x1000))]
+# For each instruction type, we test straightforwardly first, and then test
+# again after inverting the randomly-generated inputs.
+J <- ~C
+K <- ~D
+
 D <- D & 31 # overshifting is tested separately
+K <- K & 31
 
 # passing until proven broken
 B <- -1
@@ -13,6 +19,14 @@ E <- E == 1
 I <- I == E
 B <- B & I
 
+I <- J @ K
+# test type 0
+E <- J >>> K
+E <- E & 1
+E <- E == 1
+I <- I == E
+B <- B & I
+
 I <- C @ 3
 # test type 1
 E <- C >>> 3
@@ -21,6 +35,14 @@ E <- E == 1
 I <- I == E
 B <- B & I
 
+I <- J @ 3
+# test type 1
+E <- J >>> 3
+E <- E & 1
+E <- E == 1
+I <- I == E
+B <- B & I
+
 I <- 0x7ef @ D
 # test type 2
 E <- 0x7ef >>> D
@@ -29,5 +51,13 @@ E <- E == 1
 I <- I == E
 B <- B & I
 
+I <- 0x7ef @ K
+# test type 2
+E <- 0x7ef >>> K
+E <- E & 1
+E <- E == 1
+I <- I == E
+B <- B & I
+
 illegal