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Write floating-point arithmetic, FMA, comparison and conversion results directly to the destination where source registers can be preserved. Remove redundant temporary copies and use vector-register alias checks in narrowing conversions. (cherry picked from commit c8d4ac5) Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
Write move, broadcast, insert, extract and shuffle results directly to the destination when the source lanes are no longer needed. Keep the XMM VSHUFPD single-shuffle path when both sources are the same register. (cherry picked from commit c0084ea) Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
Use copies and lane inserts for constant VBLENDPD and VBLENDPS masks. Write XMM VBLENDVPD results directly to the destination. For XMM VBLENDPD with dest equal to src2, retain the selected dest lanes and insert only the lanes from src1. This removes the temporary result and its copies. (cherry picked from commit ef2925a) Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
Remove intermediate copies from vector logic, shifts, packing, horizontal arithmetic, multiply-accumulate, carry-less multiply and SAD translation. Keep temporaries where overlapping sources or shift semantics require them. (cherry picked from commit b61cb01) Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
Write XMM VPANDN results directly and remove duplicate YMM VPBROADCASTQ inserts. Skip the src1 copy in VRCPSS and VRSQRTSS when dest is src1. For XMM VPBLENDD, select a base source and insert only the required words instead of building a vector mask. Reuse dest when it already holds a source, and load memory operands even when the mask selects no memory lanes. Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
Use reduced-flag generation for VCOMISS, VCOMISD, VUCOMISS and VUCOMISD. Load memory operands and perform the floating comparison even when its flags are unused, so flag elimination retains faults and invalid operations. Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
Mark VPTEST, VTESTPS and VTESTPD as writing all six arithmetic flags. Generate only the needed ZF and CF results and required constant flags, using conditional moves instead of branches around flag writes. Load operands before eliminating unused flags so memory faults are retained. Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
Fuse adjacent VPTEST, VTESTPS or VTESTPD with JE, JNE, JB, JAE, JBE or JA. Use the vector test conditions directly instead of reading EFLAGS back. Write any live flags before leaving the block. Use ordinary translation for two-successor TU blocks and when the pattern option or LASX is disabled. Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
When imm[3:2] is clear and all native traps are masked, use one fixed-direction round for both the result and exception status. Remove the preliminary round and the FCSR save/mask/restore sequence from this path. Use the existing sequence when traps are enabled, precision is suppressed or MXCSR selects the rounding direction. Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
When dest is src1 in VADDSD, VSUBSD, VMULSD or VDIVSD, insert the computed low double into dest. Its high double already contains the required src1 bits, so the temporary shuffle and full-register copy are unnecessary. Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
Check native exception enables before fixed-direction rounding. When all traps are masked, round without first disabling them in FCSR. With precision suppression, retain the unordered comparison and FCSR restore to preserve invalid status without adding inexact status. Otherwise, one round supplies both the result and exception status. Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
Compute the low subtraction and high addition with scalar operations, then interleave their results. This replaces seven core instructions with five and avoids arithmetic on unused elements. Read both sources before writing dest so overlapping registers remain valid. Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
For fixed rounds with precision suppression, skip the FCSR save/restore when native traps are masked and inexact is already set. Round once, then perform the unordered comparison to produce the final cause bits. Use the existing sequence when inexact is clear, traps are enabled or MXCSR selects the rounding direction. Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
For eligible 64-bit base-plus-displacement addresses, add the rounded high part to the base and keep the signed low 12 bits in the memory instruction. This removes an ORI from address generation when the high part fits signed32. Exclude indexed, segmented, RIP-relative and narrow-address forms. Keep 80-bit x87 operands on the old path because their second access adds eight to the returned displacement. Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
Signal recovery reads tb->s_data->ir1 even though recovered TBs may have no IR1 list or share storage with another TB. A guest fault can then cause a nested host fault or report the wrong guest address. Store the delayed CMP/TEST/BT operation, width and TEST alias information in the per-instruction search table. Recover flags from saved host operands without reading temporary translation data, and activate the recovery record only after the comparison completes. Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
XV.PICKVE.W already zeroes bits 255:32 of the VMOVSS destination. Cancel its pending upper-half clear instead of scheduling another clear. Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
The LASX sequences for VMOVD XMM destinations already write the full physical register and zero its upper bits. Cancel the pending upper-half clear instead of emitting an extra XV.PERMI.Q. Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
When VPERM2F128 or VPERM2I128 has identical sources and selects the low 128-bit half for both result halves, use XVREPLVE0.Q instead of a copy followed by XVPERMI.Q. Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
For immediate low nibbles 0x0 and 0xf, use XVREPL128VEI.D to duplicate the selected double in each 128-bit half. This replaces the generic shuffle and avoids its dependency on the previous destination value. Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
When the low two immediate bits are 0x0 or 0x3, use VREPLVEI.D to duplicate the selected double. This replaces the generic shuffle and avoids its dependency on the previous destination value. Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
Move the source into a temporary vector register, count its bits with VPCNT.D and move the low result back. This replaces the fixed-width loop that counts one bit per iteration. Keep the existing 16/32/64-bit destination writes and flag generation. Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
When dest is src1, insert the selected 128-bit lane directly into dest instead of copying src1 to a temporary and copying the result back. Reuse the alias handling shared with VINSERTI128. Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
A high-lane insert reads only src1's low 128 bits and replaces its high half. Skip materializing src1's pending high-half clear and load it as XMM. Continue to materialize src2 before reading it. Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
The memory operand is eight bytes, but translation loads 16 bytes before broadcasting the low double. A valid page-end operand can therefore fault. Use XVLDREPL.D when the displacement is a multiple of eight. Otherwise, load one double with FLD.D and replicate it. Keep the page check at eight bytes. Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
Insert the converted low double directly into dest when it is src1. The high double already holds the required source bits, so the temporary shuffle and full-register copy are unnecessary. Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
Handle three-register VMOVSD aliases directly. Identical sources need only a copy when dest differs; dest equal to src2 needs only src1's high double inserted. For other cases, merge the source lanes directly in dest instead of copying a temporary result back. Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
For effective immediates 0x0 and 0xf, use XVILVL.D or XVILVH.D to produce the result directly. For 0x3 and 0xc, combine the two interleaves with one XVPERMI.Q. This avoids the generic two-temporary shuffle sequence. Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
Insert the converted low double directly into dest when it is src1. Its high double already contains the required source bits, so the result shuffle and full-register copy are unnecessary. Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
Apply the VINSERTF128 high-insert handling to VINSERTI128. A high insert replaces src1's upper half, so read only its low half and skip its pending upper-half clear. Keep src2 materialization and low-insert handling.
A fused UCOMISD/SETA store uses the comparison's instruction boundary. If the store faults, the signal context reports the comparison PC instead of the SETA PC. Translate memory SETA separately and retain all comparison flags for its fault context.
SETA reads only CF and ZF, but a later page fault can expose every comparison flag to a signal handler. Keep the full flag write for adjacent VUCOMISD and SETA even when ordinary flag analysis marks other flags dead.
Share the adjacent register SETA path between UCOMISD and VUCOMISD. Use one quiet greater-than comparison when no flags need to survive. Discard flags only when a retained register ADD, SUB or CMP overwrites all of them in the same block with no possible fault in between. Otherwise, keep all flags for faults and successors. Perform the floating comparison before writing flags so an invalid-operation trap sees the previous state. Reuse CF and ZF to compute PF when this removes a floating comparison.
When dest differs from src1, write the comparison mask directly to dest and merge src1's high double there. This removes a temporary result and its copy. Keep the temporary when dest is src1 because its high double is still needed after the comparison.
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Summary / 变更说明
Validation / 验证
ninja -C build-avx-opt-3-tests -j8 latx-x86_64passed at7f6d3c02394.Checklist / 检查项
CONTRIBUTING.md. / 我已阅读CONTRIBUTING.md。git commit -s). /每个提交都包含 DCO 签署（
git commit -s）。are not applicable. /
我已提供相关构建或测试结果，或说明了不适用的原因。