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Update from task 416aaebf-5441-47ed-920b-d4bfaf3f2540 #7

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8e3c28c
Update gitignore and enhance documentation for Pocket-LLM project
qwen-intl Sep 4, 2026
0a7cb0d
Update gitignore and documentation files
qwen-intl Sep 4, 2026
9d94d94
Resolve merge conflicts from main branch
mathcode220-math Sep 4, 2026
65b7501
Fix: Remove markdown conflict markers and resolve merge properly
mathcode220-math Sep 4, 2026
f8d979b
Update documentation and ignore files for Pocket-LLM compiler
qwen-intl Sep 4, 2026
1d8632b
merge remote cross-project-documentation-sync-f2540 to align history
qwen-intl Sep 4, 2026
025e349
Merge branch 'main' into cross-project-documentation-sync-f2540
mathcode220-math Sep 4, 2026
928dbf3
fix(sim/Makefile): use tabs for recipe lines to fix make 'missing sep…
mathcode220-math Sep 4, 2026
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3 changes: 3 additions & 0 deletions .gitignore
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Original file line number Diff line number Diff line change
@@ -1,3 +1,6 @@
```markdown
Pocket-LLM/compiler/README.md
doc/ARCHITECTURE.md
```
# Logs and temp files
*.log
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14 changes: 7 additions & 7 deletions Pocket-LLM/compiler/README.md
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Expand Up @@ -20,18 +20,18 @@ The Pocket-LLM compiler bridges the gap between large language models and hardwa
| 4096) |
| - Float32 precision |
+------------------------------------------+
|
| Weight extraction
v
|
| Weight extraction
v
+------------------------------------------+
| OCCP Compiler (this directory) |
| - Tiling (4096x4096 -> 2x2 blocks) |
| - Quantization (Float32 -> INT8) |
| - Binary serialization |
+------------------------------------------+
|
| compiled_model.bin
v
|
| compiled_model.bin
v
+------------------------------------------+
| OCCP Hardware Bridge (C Driver) |
| - Streams tiles to silicon |
Expand All @@ -50,7 +50,7 @@ The Pocket-LLM compiler bridges the gap between large language models and hardwa
## Files

| File | Purpose |
|------|---------|
|------|----------|
| `occp_compiler.py` | Main compiler implementation |
| `README.md` | This documentation file |

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27 changes: 14 additions & 13 deletions doc/ARCHITECTURE.md
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Expand Up @@ -41,6 +41,7 @@ The compilation artifacts from **Pocket-LLM** directly feed into the core hardwa
+---------------------------+
```

For the low-level silicon implementation and C-Driver specifications, please refer to the main repository: [Open-Cognitive-Core](https://github.com/mathcode220-math/open-cognitive-core).
For the low-level silicon implementation and C-Driver specifications, please refer to the main repository: [Pocket-LLM](https://github.com/mathcode220-math/-Pocket-LLM-).

## System Architecture
Expand All @@ -50,10 +51,10 @@ For the low-level silicon implementation and C-Driver specifications, please ref
| AXI4-Lite Control Bus |
| (RISC-V / CPU Control Interface) |
+------------------------------------------------------------------+
|
+---------------------+---------------------+
| |
v v
|
+---------------------+---------------------+
| |
v v
+-------------------+ +-------------------+
| HDC Subsystem | | ML Subsystem |
| | | |
Expand All @@ -69,15 +70,15 @@ For the low-level silicon implementation and C-Driver specifications, please ref
| +-------------+ | | +-------------+ |
| | | | |
+-------------------+ | v |
| +-------------+ |
| | ReLU | |
| +-------------+ |
| | |
| v |
| +-------------+ |
| | Softmax | |
| +-------------+ |
+-------------------+
| +-------------+ |
| | ReLU | |
| +-------------+ |
| | |
| v |
| +-------------+ |
| | Softmax | |
| +-------------+ |
+-------------------+
```

## Module Descriptions
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56 changes: 28 additions & 28 deletions sim/Makefile
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Expand Up @@ -39,41 +39,41 @@ XSIM_FLAGS := -nolog -norecompile
all: verilator

verilator: $(BUILD_DIR)/V$(TOP_MODULE)
@echo "✓ Simulation binary ready: $(BUILD_DIR)/V$(TOP_MODULE)"
@echo "✓ Simulation binary ready: $(BUILD_DIR)/V$(TOP_MODULE)"

$(BUILD_DIR)/V$(TOP_MODULE): $(RTL_SRCS) $(TB_SRCS)
@mkdir -p $(BUILD_DIR)
verilator $(VERILATOR_FLAGS) \
$(RTL_SRCS) $(TB_SRCS)
$(MAKE) -C $(OBJ_DIR) -f V$(TOP_MODULE).mk
@mkdir -p $(BUILD_DIR)
verilator $(VERILATOR_FLAGS) \
$(RTL_SRCS) $(TB_SRCS)
$(MAKE) -C $(OBJ_DIR) -f V$(TOP_MODULE).mk

run-verilator: $(BUILD_DIR)/V$(TOP_MODULE)
$(BUILD_DIR)/V$(TOP_MODULE)
$(BUILD_DIR)/V$(TOP_MODULE)

xsim:
@echo "Compiling with XSIM (Vivado)..."
xvlog $(RTL_SRCS) $(TB_SRCS)
xelab $(XSIM_FLAGS) $(TOP_MODULE)
xsim $(TOP_MODULE) $(XSIM_FLAGS)
@echo "Compiling with XSIM (Vivado...)"
xvlog $(RTL_SRCS) $(TB_SRCS)
xelab $(XSIM_FLAGS) $(TOP_MODULE)
xsim $(TOP_MODULE) $(XSIM_FLAGS)

clean:
rm -rf $(BUILD_DIR) *.log *.jou xelab.* xsim.dir/ *.wdb
rm -rf $(BUILD_DIR) *.log *.jou xelab.* xsim.dir/ *.wdb

help:
@echo "Open Cognitive Core Project - Build System"
@echo "============================================="
@echo ""
@echo "Usage:"
@echo " make - Build with Verilator (default)"
@echo " make verilator - Build with Verilator"
@echo " make xsim - Build with XSIM (Vivado)"
@echo " make run-verilator - Run Verilator simulation"
@echo " make clean - Remove build artifacts"
@echo ""
@echo "Environment Variables:"
@echo " SIM=<tool> - Select simulator (verilator|xsim)"
@echo " TOP_MODULE=<name> - Top module for simulation"
@echo ""
@echo "Examples:"
@echo " make TOP_MODULE=tb_softmax"
@echo " make xsim TOP_MODULE=tb_axi4_lite"
@echo "Open Cognitive Core Project - Build System"
@echo "============================================="
@echo ""
@echo "Usage:"
@echo " make - Build with Verilator (default)"
@echo " make verilator - Build with Verilator"
@echo " make xsim - Build with XSIM (Vivado)"
@echo " make run-verilator - Run Verilator simulation"
@echo " make clean - Remove build artifacts"
@echo ""
@echo "Environment Variables:"
@echo " SIM=<tool> - Select simulator (verilator|xsim)"
@echo " TOP_MODULE=<name> - Top module for simulation"
@echo ""
@echo "Examples:"
@echo " make TOP_MODULE=tb_softmax"
@echo " make xsim TOP_MODULE=tb_axi4_lite"
14 changes: 7 additions & 7 deletions sw/README.md
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Expand Up @@ -19,18 +19,18 @@ The OCCP co-processor is designed in SystemVerilog and communicates via the **AX
| - Model weights |
| - Inference requests |
+------------------------------------------+
|
| float matrices
v
|
| float matrices
v
+------------------------------------------+
| OCCP Bridge API (this directory) |
| - occp_init() |
| - occp_dispatch_matrix_multiply() |
| - occp_reset() |
+------------------------------------------+
|
| AXI4-Lite transactions
v
|
| AXI4-Lite transactions
v
+------------------------------------------+
| OCCP Silicon Co-Processor (../rtl/) |
| - axi4_lite_core_ctrl.sv |
Expand All @@ -42,7 +42,7 @@ The OCCP co-processor is designed in SystemVerilog and communicates via the **AX
## Files

| File | Purpose |
|------|---------|
|------|----------|
| `occp_bridge.h` | Public API header with register definitions |
| `occp_bridge.c` | Driver implementation with simulation support |
| `Makefile` | Build system for compilation and testing |
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