RTL / CPU Design Engineer working on RISC-V CPU microarchitecture and hardware security.
- ๐ง Contributed 6 merged ISA extensions to the OpenHW Group CVA6 RISC-V core โ see my merged PRs
- ๐ MS in Digital & Embedded Systems, researching hardware security for autonomous vehicles
- ๐ฑ Interested in CPU design, ASIC design, and SoC architecture
- ๐ซ Reach me on LinkedIn

