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tg-full-adder-cmos
tg-full-adder-cmos Public"1-bit full adder using transmission gate logic — Cadence Virtuoso, GPDK 0.18µm, 14.3% transistor reduction vs standard CMOS
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fpga-hardware-puf
fpga-hardware-puf PublicFPGA-based Hardware PUF implementation on Shrike FPGA using Verilog, SPN architecture, UART & SHA-256 for secure device authentication.
Tcl 1
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PCB_Design
PCB_Design PublicHardware design submissions: 3S Li-ion charger, PCB design, and Arduino control system
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CanSat-ISL
CanSat-ISL Public2-layer PCB Avionics design for CanSat mission with STM32, IMU, GPS, Altimeter & OpenRocket simulation
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