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Add Qualcomm Shikra and Nord Ethernet support to tech/net/eth - #1910

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Mohd Ayaan Anwar (ayaan-anwar) merged 19 commits into
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ayaan-anwar:nord_shikra_ethernet_patches
Sep 25, 2026
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Add Qualcomm Shikra and Nord Ethernet support to tech/net/eth#1910
Mohd Ayaan Anwar (ayaan-anwar) merged 19 commits into
qualcomm-linux:tech/net/ethfrom
ayaan-anwar:nord_shikra_ethernet_patches

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@ayaan-anwar Mohd Ayaan Anwar (ayaan-anwar) commented Sep 25, 2026 •
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This PR:

  • Adds Shikra ETHQOS bindings and platform support.
  • Fixes RGMII-ID DLL bypass handling.
  • Adds per-platform NOC clock and OPP voting.
  • Adds Qualcomm Nord XPCS and USXGMII Clause 37 autonegotiation support.
  • Integrates DW25GMAC into stmmac.
  • Adds Nord ETHQOS, external PCS, and custom XGMAC register layouts.
  • Carries one Qualcomm-specific DW25GMAC patch marked PENDING.

The Shikra series is in v2. For Nord, all changes apart from DW25GMAC fixes have been posted as well.
The last DW25GMAC patches has a tight dependency on:

Therefore, the final patch remains PENDING.

CRs-Fixed: 4688350

@ayaan-anwar
FROMLIST: dt-bindings: net: qcom,ethqos: add qcom,shikra-ethqos compa…
c4bb90b 
…tible

Shikra's EMAC requires two additional clocks for NOC interconnect
access (axi-noc, pcie-tile-axi-noc) beyond the standard four, and an
OPP table with required-opps to vote VDD_CX to SVS when the NOC clocks
are enabled.

Add qcom,shikra-ethqos to the compatible enum and use an if/else
block to constrain Shikra to exactly six clocks and require
operating-points-v2, while leaving existing compatibles unchanged.

Add the relevant compatible to the binding document for snps,dwmac as
well.

Link: https://lore.kernel.org/netdev/20260908-shikra_ethernet-v2-3-bbe3389d0652@oss.qualcomm.com/
Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
@ayaan-anwar
FROMLIST: net: stmmac: qcom-ethqos: convert ethqos_rgmii_macro_init()…
fc6ede7 
… to void

The return value is never checked by its sole caller and the speed
validation duplicates a check higher up the call stack.  Convert to
void and remove the dead code.

Link: https://lore.kernel.org/netdev/20260908-shikra_ethernet-v2-4-bbe3389d0652@oss.qualcomm.com/
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
@ayaan-anwar
FROMLIST: net: stmmac: qcom-ethqos: fix RGMII_ID mode to use DLL bypass
10db493 
When "rgmii-id" is selected the PHY supplies both TX and RX delays, so
the MAC must not add its own. The driver currently falls through to the
generic DLL initialisation path which programs it to add a delay.

Power down the DLL and set DDR bypass mode for RGMII_ID, then program
the IO_MACRO via a new ethqos_rgmii_id_macro_init() helper. Also fix
ethqos_set_clk_tx_rate() to not double the clock rate in bypass mode at
100M/10M, and remove RGMII_ID from the phase-shift suppression in
ethqos_rgmii_macro_init() since RGMII_ID no longer reaches that path.

Link: https://lore.kernel.org/netdev/20260908-shikra_ethernet-v2-5-bbe3389d0652@oss.qualcomm.com/
Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
@ayaan-anwar
FROMLIST: net: stmmac: qcom-ethqos: warn about legacy RGMII PHY modes
73ce514 
The qcom-ethqos driver is moving towards using "rgmii-id" together
with PHY-provided delays. However, existing DTBs use "rgmii" and
"rgmii-txid" and must remain supported for backwards compatibility.

Warn when either of these legacy PHY modes is used to encourage users
to migrate to updated DTBs using "rgmii-id".

Link: https://lore.kernel.org/netdev/20260908-shikra_ethernet-v2-6-bbe3389d0652@oss.qualcomm.com/
Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
@ayaan-anwar
FROMLIST: net: stmmac: qcom-ethqos: set initial RGMII link clock to l…
34b202d 
…owest speed

On probe the RGMII link clock is initialised at SPEED_1000, which
translates to a 250 MHz source clock even when no PHY link is present,
drawing unnecessary power.

Initialise at SPEED_10 instead; fix_mac_speed updates the rate once
a link is established.

Link: https://lore.kernel.org/netdev/20260908-shikra_ethernet-v2-7-bbe3389d0652@oss.qualcomm.com/
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
@ayaan-anwar
FROMLIST: net: stmmac: qcom-ethqos: add per-platform NOC clock voting
9af9aab 
Some SoCs gate the EMAC's path to the System NOC behind dedicated clocks
that must be enabled before the DMA can reach memory. Add
ethqos_noc_clk_cfg and the corresponding fields in the driver-data and
runtime structs so each compatible can declare its own set with per-clock
rates.  The clocks are acquired during probe and enabled/disabled
alongside the existing link clock in ethqos_clks_config().

No functional change for existing compatibles. This will help us when
we add support for Shikra.

Link: https://lore.kernel.org/netdev/20260908-shikra_ethernet-v2-8-bbe3389d0652@oss.qualcomm.com/
Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
@ayaan-anwar
FROMLIST: net: stmmac: qcom-ethqos: add Shikra EMAC support
daafeff 
Shikra integrates two Qualcomm ETHQOS controllers based on the Synopsys
GMAC IP, similar to previous platforms.  Register qcom,shikra-ethqos
backed by a new shikra_data descriptor that enables the three NOC clocks
required for DMA memory access (axi-noc, pcie-tile-axi-noc, stmmaceth)
all at 120 MHz, and the 36-bit DMA address width.

As part of the NOC clock voting logic, the qcom-ethqos glue driver takes
a second enable reference on the "stmmaceth" clock, which is already
enabled by the stmmac core. All three clocks in shikra_noc_clks[] must
run at 120 MHz for NOC access, and managing "stmmaceth" through the same
clk_bulk path keeps the rate-setting and enable/disable together.

Link: https://lore.kernel.org/netdev/20260908-shikra_ethernet-v2-9-bbe3389d0652@oss.qualcomm.com/
Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
@ayaan-anwar
FROMLIST: dt-bindings: net: pcs: add Qualcomm Nord XPCS
2de3a36 
Document the Qualcomm Nord integrated DesignWare XPCS compatible. The
XPCS resides in an Ethernet power domain and requires its CSR clock for
register access, so require the clock and power-domain resources for
this compatible.

Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-1-4b1c682af70f@oss.qualcomm.com/
Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
@ayaan-anwar
FROMLIST: net: pcs: xpcs: add USXGMII Clause 37 autoneg support
9a004e2 
Add the Clause 37 USXGMII configuration and state handling required by
XPCS variants which use Clause 37 framing for USXGMII.

Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-2-4b1c682af70f@oss.qualcomm.com/
Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
@ayaan-anwar
FROMLIST: net: pcs: xpcs: add custom platform register accessors
9edea6d 
Some XPCS integrations do not expose the standard direct or indirect
register layout. Allow the platform driver to use optional register read
and write callbacks for both Clause 22 and Clause 45 accesses, while
retaining the existing access paths when no callbacks are supplied.

Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-3-4b1c682af70f@oss.qualcomm.com/
Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
@ayaan-anwar
FROMLIST: net: pcs: xpcs: add Qualcomm Nord platform support
c67a4ed 
Qualcomm Nord exposes the DesignWare XPCS register blocks through
separate direct-MMIO windows instead of the standard contiguous
MMD/register layout. Add accessors that translate MMD accesses to the
Nord windows:

  MMD 3 (PCS), standard registers: SR_XS at 0x0000
  MMD 3 (PCS), vendor registers:   VR_XS at 0x2000
  MMD 1 (PMA/PMD):                  SR_PMA at 0x3000
  MMD 31 (VEND2), standard regs:    SR_MII at 0x4000
  MMD 31 (VEND2), vendor registers: VR_MII at 0x5000

Each register uses a 32-bit MMIO stride. The vendor bit is removed from
the register index before calculating a vendor-window offset.

Select these accessors using the Nord synthetic XPCS ID, allow its
smaller direct-MMIO resource, and add the Nord USXGMII Clause 37
compatibility.

Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-4-4b1c682af70f@oss.qualcomm.com/
Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
@ayaan-anwar
FROMLIST: net: pcs: xpcs: initialize runtime PM as suspended
4eab623 
xpcs_plat_init_clk() acquires the optional CSR clock but does not
prepare or enable it. Marking the device runtime-active at that point
makes the PM core assume that the hardware is already powered.

On Nord, once the XPCS CSR clock was described, the first
pm_runtime_resume_and_get() accessed XPCS registers without invoking
runtime_resume() to enable the clock. The matching runtime put then
invoked runtime_suspend() and attempted to disable a clock which was
never enabled, producing an already-disabled clock warning.

Initialize the runtime-PM state as suspended instead. The first
register access now runs the resume callback and enables the CSR clock,
while the subsequent suspend callback performs the matching disable.
Check and propagate the state-transition error as part of probe.

Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-5-4b1c682af70f@oss.qualcomm.com/
Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Jitendra Vegiraju @ayaan-anwar
FROMLIST: net: stmmac: Add DW25GMAC support in stmmac core driver
ba01aeb 
The DW25GMAC introduced a new DMA architecture called Hyper-DMA (HDMA) for
virtualization scalability. This is realized by decoupling physical DMA
channels(PDMA) from potentially large number of virtual DMA channels(VDMA).
The VDMAs provide software abstraction to driver that map to PDMAs for
frame transmission and reception.
Since 25GMAC is a derivative of XGMAC, majority of IP is common to both.

To add support for the HDMA in 25GMAC, a new instance of dma_ops,
dw25gmac400_dma_ops is introduced.
To support the current needs, a simple one-to-one mapping of dw25gmac's
logical VDMA (channel) to TC to PDMAs is used. Most of the other dma
operation functions in existing dwxgamc2_dma.c file are reused whereever
applicable.
Added setup function for DW25GMAC's stmmac_hwif_entry in stmmac core.

Link: https://lore.kernel.org/netdev/20260402213629.1996133-2-jitendra.vegiraju@broadcom.com/
Signed-off-by: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Jitendra Vegiraju @ayaan-anwar
FROMLIST: net: stmmac: Integrate dw25gmac into hwif handling
49a6e85 
Integrate dw25gmac support into stmmac hardware interface handling.
Added a new entry to the stmmac_hw table in hwif.c.

Link: https://lore.kernel.org/netdev/20260402213629.1996133-3-jitendra.vegiraju@broadcom.com/
Signed-off-by: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
@ayaan-anwar
FROMLIST: dt-bindings: net: qcom,ethqos: add Qualcomm Nord
cc2278e 
Qualcomm Nord integrates two ETHQOS controllers based on the Synopsys
DesignWare XGMAC IP. Each controller has five clocks, one power domain,
and ten SMMU stream mappings.

Due to a hardware quirk, PCS link-up depends on the EEE clock being
enabled.

Add the Nord compatible to the common DWMAC schema exceptions used by
Qualcomm ETHQOS platforms.

Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-6-4b1c682af70f@oss.qualcomm.com/
Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
@ayaan-anwar
FROMLIST: net: stmmac: support custom XGMAC register layouts
b06cf04 
Some XGMAC integrations place their MTL queues and DMA channels at
different offsets from the standard register layout. Allow platform
data to override these addresses while retaining the standard layout by
default.

This follows the approach used by commit 33719b5 ("net: stmmac:
dwmac4: Allow platforms to specify some DMA/MTL offsets"). Qualcomm
XGMAC hardware similarly uses differently aligned queue and channel
registers.

Also allow platforms to override the timestamp register base.

Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-7-4b1c682af70f@oss.qualcomm.com/
Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
@ayaan-anwar
FROMLIST: net: stmmac: qcom-ethqos: support external PCS
e38e452 
Select the XPCS instance initialized by stmmac when firmware provides
a pcs-handle. Reject interfaces that are not supported by the selected
PCS.

Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-8-4b1c682af70f@oss.qualcomm.com/
Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
@ayaan-anwar
FROMLIST: net: stmmac: add Qualcomm Nord ETHQOS support
632ab93 
Qualcomm Nord provides two ETHQOS controllers based on the Synopsys
DesignWare XGMAC IP. Add their register layout, wrapper configuration
for USXGMII, EEE clock handling required for PCS link-up, and
platform-specific SGMII loopback control.

Link: ttps://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-9-4b1c682af70f@oss.qualcomm.com/
Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
@ayaan-anwar
PENDING: net: stmmac: QCOM DW25GMAC fixes
7bc8ed9 
Qualcomm Nord requires DW25GMAC HDMA channels to wait for CSR
initialization, mappings for channels not exposed to Linux, and
independent VDMA and PDMA traffic-class maps.

This patch is tightly coupled with the following ongoing series from
Broadcom adding the core driver and hwif integration:

https://lore.kernel.org/netdev/20260402213629.1996133-2-jitendra.vegiraju@broadcom.com/
https://lore.kernel.org/netdev/20260402213629.1996133-3-jitendra.vegiraju@broadcom.com/

That series is expected to be revised. Before posting this patch, it
must be rebased onto the latest Broadcom revision and retested on
Qualcomm Nord hardware.

Keep this change downstream until those dependencies are satisfied,
then revise and post the remaining Qualcomm-specific delta.

Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
@qcomlnxci
qcomlnxci requested review from a team and qcom-sarohasa and removed request for a team September 25, 2026 09:55
Merged
shawngsc
shawngsc approved these changes Sep 25, 2026
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Looks good for Nord support!

@ayaan-anwar
Mohd Ayaan Anwar (ayaan-anwar) merged commit 7151807 into qualcomm-linux:tech/net/eth Sep 25, 2026
5 of 7 checks passed
@ayaan-anwar

Mohd Ayaan Anwar (ayaan-anwar) commented Sep 25, 2026

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These changes have been tested via sbanerjeeqc/meta-qcom#1

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@Komal-Bajaj Komal Bajaj (Komal-Bajaj) Komal-Bajaj approved these changes
@qcom-sarohasa qcom-sarohasa qcom-sarohasa approved these changes
@shawngsc shawngsc shawngsc approved these changes
@idlethread Amit Kucheria (idlethread) Awaiting requested review from idlethread
@shashim-quic Shiraz Hashim (shashim-quic) Awaiting requested review from shashim-quic

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@ayaan-anwar @Komal-Bajaj @qcom-sarohasa @shawngsc